1 // Copyright (C) 2022 Beken Corporation
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15
16 #pragma once
17
18 #ifdef __cplusplus
19 extern "C" {
20 #endif
21
22 #include <soc/soc.h>
23
24 #define PSRAM_LL_REG_BASE (SOC_PSRAM_REG_BASE)
25 /* REG_0x00 */
26 #define PSRAM_REG0 (PSRAM_LL_REG_BASE + 0x0 * 4)
27
psram_ll_get_reg0_value(void)28 static inline uint32_t psram_ll_get_reg0_value(void)
29 {
30 return REG_READ(PSRAM_REG0);
31 }
32
psram_ll_set_reg0_value(uint32_t value)33 static inline void psram_ll_set_reg0_value(uint32_t value)
34 {
35 REG_WRITE(PSRAM_REG0, value);
36 }
37
38 /* REG_0x01 */
39 #define PSRAM_REG1 (PSRAM_LL_REG_BASE + 0x1 * 4)
40
psram_ll_get_reg1_value(void)41 static inline uint32_t psram_ll_get_reg1_value(void)
42 {
43 return REG_READ(PSRAM_REG1);
44 }
45
psram_ll_set_reg1_value(uint32_t value)46 static inline void psram_ll_set_reg1_value(uint32_t value)
47 {
48 REG_WRITE(PSRAM_REG1, value);
49 }
50
51 /* REG_0x02 */
52 #define PSRAM_REG2 (PSRAM_LL_REG_BASE + 0x2 * 4)
53 #define PSRAM_SF_RESET_POS (0)
54 #define PSRAM_SF_RESET_MASK (0x1)
55
psram_ll_get_reg2_value(void)56 static inline uint32_t psram_ll_get_reg2_value(void)
57 {
58 return REG_READ(PSRAM_REG2);
59 }
60
psram_ll_set_reg2_value(uint32_t value)61 static inline void psram_ll_set_reg2_value(uint32_t value)
62 {
63 REG_WRITE(PSRAM_REG2, value);
64 }
65
psram_ll_get_sf_reset_value(void)66 static inline uint32_t psram_ll_get_sf_reset_value(void)
67 {
68 uint32_t reg_value;
69 reg_value = REG_READ(PSRAM_REG2);
70 reg_value = ((reg_value >> PSRAM_SF_RESET_POS) & PSRAM_SF_RESET_MASK);
71 return reg_value;
72 }
73
psram_ll_set_sf_reset_value(uint32_t value)74 static inline void psram_ll_set_sf_reset_value(uint32_t value)
75 {
76 uint32_t reg_value;
77 reg_value = REG_READ(PSRAM_REG2);
78 reg_value &= ~(PSRAM_SF_RESET_MASK << PSRAM_SF_RESET_POS);
79 reg_value |= ((value & PSRAM_SF_RESET_MASK) << PSRAM_SF_RESET_POS);
80 REG_WRITE(PSRAM_REG2, reg_value);
81 }
82
83
84 /* REG_0x03 */
85 #define PSRAM_REG3 (PSRAM_LL_REG_BASE + 0x3 * 4)
86
psram_ll_get_reg3_value(void)87 static inline uint32_t psram_ll_get_reg3_value(void)
88 {
89 return REG_READ(PSRAM_REG3);
90 }
91
psram_ll_set_reg3_value(uint32_t value)92 static inline void psram_ll_set_reg3_value(uint32_t value)
93 {
94 REG_WRITE(PSRAM_REG3, value);
95 }
96
97
98 /* REG_0x04 */
99 #define PSRAM_REG4 (PSRAM_LL_REG_BASE + 0x4 * 4)
100
psram_ll_get_mode_value(void)101 static inline uint32_t psram_ll_get_mode_value(void)
102 {
103 return REG_READ(PSRAM_REG4);
104 }
105
psram_ll_set_mode_value(uint32_t value)106 static inline void psram_ll_set_mode_value(uint32_t value)
107 {
108 REG_WRITE(PSRAM_REG4, value);
109 }
110
111 /* REG_0x05 */
112 #define PSRAM_REG5 (PSRAM_LL_REG_BASE + 0x5 * 4)
113
psram_ll_get_reg5_value(void)114 static inline uint32_t psram_ll_get_reg5_value(void)
115 {
116 return REG_READ(PSRAM_REG5);
117 }
118
psram_ll_set_reg5_value(uint32_t value)119 static inline void psram_ll_set_reg5_value(uint32_t value)
120 {
121 REG_WRITE(PSRAM_REG5, value);
122 }
123
124 /* REG_0x06 */
125 #define PSRAM_REG6 (PSRAM_LL_REG_BASE + 0x6 * 4)
126
psram_ll_get_reg6_value(void)127 static inline uint32_t psram_ll_get_reg6_value(void)
128 {
129 return REG_READ(PSRAM_REG6);
130 }
131
psram_ll_set_reg6_value(uint32_t value)132 static inline void psram_ll_set_reg6_value(uint32_t value)
133 {
134 REG_WRITE(PSRAM_REG6, value);
135 }
136
137 /* REG_0x07 */
138 #define PSRAM_REG7 (PSRAM_LL_REG_BASE + 0x7 * 4)
139
psram_ll_get_reg7_value(void)140 static inline uint32_t psram_ll_get_reg7_value(void)
141 {
142 return REG_READ(PSRAM_REG7);
143 }
144
psram_ll_set_reg7_value(uint32_t value)145 static inline void psram_ll_set_reg7_value(uint32_t value)
146 {
147 REG_WRITE(PSRAM_REG7, value);
148 }
149
150 /* REG_0x08 */
151 #define PSRAM_REG8 (PSRAM_LL_REG_BASE + 0x8 * 4)
152
psram_ll_get_reg8_value(void)153 static inline uint32_t psram_ll_get_reg8_value(void)
154 {
155 return REG_READ(PSRAM_REG8);
156 }
157
psram_ll_set_reg8_value(uint32_t value)158 static inline void psram_ll_set_reg8_value(uint32_t value)
159 {
160 REG_WRITE(PSRAM_REG8, value);
161 }
162
163 /* REG_0x09 */
164 #define PSRAM_REG9 (PSRAM_LL_REG_BASE + 0x9 * 4)
165
psram_ll_get_write_address(void)166 static inline uint32_t psram_ll_get_write_address(void)
167 {
168 return REG_READ(PSRAM_REG9);
169 }
170
psram_ll_set_write_address(uint32_t value)171 static inline void psram_ll_set_write_address(uint32_t value)
172 {
173 REG_WRITE(PSRAM_REG9, value);
174 }
175
176 /* REG_0x0a */
177 #define PSRAM_REGa (PSRAM_LL_REG_BASE + 0xa * 4)
178
psram_ll_get_write_data(void)179 static inline uint32_t psram_ll_get_write_data(void)
180 {
181 return REG_READ(PSRAM_REGa);
182 }
183
psram_ll_set_write_data(uint32_t value)184 static inline void psram_ll_set_write_data(uint32_t value)
185 {
186 REG_WRITE(PSRAM_REGa, value);
187 }
188
189 /* REG_0x0b */
190 #define PSRAM_REGb (PSRAM_LL_REG_BASE + 0xb * 4)
191
psram_ll_get_regb_value(void)192 static inline uint32_t psram_ll_get_regb_value(void)
193 {
194 return REG_READ(PSRAM_REGb);
195 }
196
psram_ll_set_regb_value(uint32_t value)197 static inline void psram_ll_set_regb_value(uint32_t value)
198 {
199 REG_WRITE(PSRAM_REGb, value);
200 }
201
202
203 #ifdef __cplusplus
204 }
205 #endif
206