1 // Copyright (C) 2022 Beken Corporation
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 // Notes:
16 // This file only contain OS-independent components initialization code,
17 // For OS-dependently initialization, put them to OSK or bk_system.
18
19 #include <common/bk_include.h>
20 #include "bk_sys_ctrl.h"
21 #include "bk_drv_model.h"
22 #include <components/ate.h>
23 #include <driver/wdt.h>
24 #include "bk_wdt.h"
25 #include <common/sys_config.h>
26 #include "release.h"
27 #include "sys_driver.h"
28 #include "bk_pm_model.h"
29 #if CONFIG_SOC_BK7256XX
30 #include "BK7256_RegList.h"
31 #endif
32 #if CONFIG_FULLY_HOSTED
33 #include "mmgmt.h"
34 #endif
35
36 #include "reset_reason.h"
37
38 #if CONFIG_EASY_FLASH && (!CONFIG_RTT)
39 #include "easyflash.h"
40 #include "bk_ef.h"
41 #endif
42
43 #include <components/log.h>
44 #include "bk_pm_control.h"
45 #include <driver/trng.h>
46
47 #include "bk_arch.h"
48 #include "bk_private/bk_driver.h"
49
50 #include "mb_ipc_cmd.h"
51
52 #if (CONFIG_PSRAM)
53 #include <driver/psram.h>
54 #endif
55
56 #define TAG "init"
57
58 //TODO move to better place
59 #if CONFIG_MEM_DEBUG
60 /* memory leak timer at 1sec */
61 static beken_timer_t memleak_timer = {0};
62 int bmsg_memleak_check_sender();
63
memleak_timer_cb(void * arg)64 void memleak_timer_cb(void *arg)
65 {
66 bmsg_memleak_check_sender();
67 }
68
mem_debug_start_timer(void)69 void mem_debug_start_timer(void)
70 {
71 bk_err_t err;
72
73 err = rtos_init_timer(&memleak_timer,
74 1000,
75 memleak_timer_cb,
76 (void *)0);
77 BK_ASSERT(kNoErr == err);
78 err = rtos_start_timer(&memleak_timer);
79 BK_ASSERT(kNoErr == err);
80 }
81 #endif
82
random_init(void)83 int random_init(void)
84 {
85 #if (CONFIG_TRNG_SUPPORT)
86 BK_LOGI(TAG, "trng enable\r\n");
87 bk_trng_start();
88 #endif
89 return BK_OK;
90 }
91
wdt_init(void)92 int wdt_init(void)
93 {
94 #if (CONFIG_FREERTOS)
95 #if CONFIG_INT_WDT
96 BK_LOGD(TAG, "int watchdog enabled, period=%u\r\n", CONFIG_INT_WDT_PERIOD_MS);
97 bk_wdt_start(CONFIG_INT_WDT_PERIOD_MS);
98 #else
99 #if (CONFIG_SOC_BK7271)
100 BK_LOGI(TAG, "watchdog disabled\r\n");
101 bk_wdt_start(CONFIG_INT_WDT_PERIOD_MS);
102 bk_wdt_feed();
103 bk_wdt_stop();
104 #endif
105 #endif //CONFIG_INT_WDT
106 #endif //CONFIG_FREERTOS
107
108 #if !(CONFIG_ALIOS)
109 #if CONFIG_TASK_WDT
110 bk_task_wdt_start();
111 BK_LOGD(TAG, "task watchdog enabled, period=%u\r\n", CONFIG_TASK_WDT_PERIOD_MS);
112 #endif
113 #endif
114 return BK_OK;
115 }
116
memory_debug_todo(void)117 int memory_debug_todo(void)
118 {
119 #if CONFIG_MEM_DEBUG
120 mem_debug_start_timer();
121 #endif
122 return BK_OK;
123 }
124 //TODO put it to better place, check with XB/HT
pm_init_todo(void)125 static int pm_init_todo(void)
126 {
127 #if CONFIG_SOC_BK7256XX
128
129 #else
130 #if CONFIG_DEEP_PS
131 bk_init_deep_wakeup_gpio_status();
132 #endif
133 #endif
134
135 #if CONFIG_POWER_CLOCK_RF
136 extern void rf_ps_pm_init(void);
137 rf_ps_pm_init();
138 #else
139 #if CONFIG_SLAVE_CORE
140
141 #else
142 dev_pm_init();
143 #endif
144 #endif
145
146 return BK_OK;
147 }
148
show_sdk_version(void)149 static inline void show_sdk_version(void)
150 {
151 #if (CONFIG_CMAKE)
152 //BK_LOGI(TAG, "armino rev: %s\r\n", ARMINO_VER);
153 BK_LOGI(TAG, "armino rev: %s\r\n", "");
154 #else
155 //BK_LOGI(TAG, "armino rev: %s\r\n", BEKEN_SDK_REV);
156 BK_LOGI(TAG, "armino rev: %s\r\n", "");
157 #endif
158 }
159
show_chip_id(void)160 static inline void show_chip_id(void)
161 {
162 // BK_LOGI(TAG, "armino soc id:%x_%x\r\n",sddev_control(DD_DEV_TYPE_SCTRL,CMD_GET_DEVICE_ID, NULL),
163 // sddev_control(DD_DEV_TYPE_SCTRL,CMD_GET_CHIP_ID, NULL));
164 BK_LOGI(TAG, "armino soc id:%x_%x\r\n", sys_drv_get_device_id(), sys_drv_get_chip_id());
165 }
166
show_sdk_lib_version(void)167 static inline void show_sdk_lib_version(void)
168 {
169 #if (!CONFIG_SLAVE_CORE)
170 extern char* bk_get_internal_lib_version(void);
171 char* ver = bk_get_internal_lib_version();
172 BK_LOGI(TAG, "armino internal lib rev: %s\n", ver);
173 #endif
174 }
175
show_armino_version(void)176 static void show_armino_version(void)
177 {
178 show_sdk_version();
179 show_sdk_lib_version();
180 show_chip_id();
181 }
182
show_init_info(void)183 static void show_init_info(void)
184 {
185 #if CONFIG_SOC_BK7256XX
186 show_armino_version();
187 #else
188 show_reset_reason();
189 show_armino_version();
190 #endif
191 }
192 #if CONFIG_SOC_BK7256XX
193 #define NCV_SIM 0x1
194 #define TEST_ID_MAX 100
195 #if (NCV_SIM == 0)
196 #define UART_BAUD_RATE1 115200
197 #else
198 #define UART_BAUD_RATE1 115200
199 #endif
200
201 #define UART_CLK_FREQ 26
print_str(char * st)202 int print_str(char * st)
203 {
204 while (*st) {
205 addUART0_Reg0x3 = *st;
206 st++;
207 }
208 return 1;
209 }
UartDbgInit()210 void UartDbgInit()
211 {
212 unsigned int uart_clk_div;
213
214 // clrf_SYS_Reg0x3_uart0_pwd ; //open periph
215 //*((volatile unsigned long *) (0x44010000+0xc*4)) = 0x4;
216 setf_SYSTEM_Reg0xc_uart0_cken ; //uart0 enable
217
218
219 //*((volatile unsigned long *) (0x44000400+10*4)) = 0x40 ; //second_func
220 //*((volatile unsigned long *) (0x44000400+11*4)) = 0x40 ; //second_func
221 addAON_GPIO_Reg0xa = 0x40 ; //second_func
222 addAON_GPIO_Reg0xb = 0x40 ; //second_func
223
224
225 uart_clk_div = (UART_CLK_FREQ*1000000)/UART_BAUD_RATE1 - 1;
226
227
228
229
230 addUART0_Reg0x0 = (uart_clk_div << posUART0_Reg0x0_UART_CLK_DIVID) |
231 (0x0 << posUART0_Reg0x0_UART_STOP_LEN ) |
232 #if (NCV_SIM == 0)
233 (0x0 << posUART0_Reg0x0_UART_PAR_MODE ) |
234 (0x0 << posUART0_Reg0x0_UART_PAR_EN ) |
235 #else
236 (0x0 << posUART0_Reg0x0_UART_PAR_MODE ) |
237 (0x0 << posUART0_Reg0x0_UART_PAR_EN ) |
238 #endif
239 (0x3 << posUART0_Reg0x0_UART_LEN ) |
240 (0x0 << posUART0_Reg0x0_UART_IRDA ) |
241 (0x1 << posUART0_Reg0x0_UART_RX_ENABLE) |
242 (0x1 << posUART0_Reg0x0_UART_TX_ENABLE) ;
243
244 addUART0_Reg0x1 = 0x00004010;
245 addUART0_Reg0x4 = 0x42;
246 addUART0_Reg0x6 = 0x0;
247 addUART0_Reg0x7 = 0x0;
248
249 // setf_SYS_Reg0x10_int_uart0_en; //enable uart_int irq
250 // *((volatile unsigned long *) (0x44010000+0x20*4)) = 0x10; //enable uart_int
251 addSYSTEM_Reg0x20 = 0x10 ; //enable uart_int
252
253 }
254 #endif
255
components_init(void)256 int components_init(void)
257 {
258 /*for bringup test*/
259 #if CONFIG_SOC_BK7256XX
260 if(driver_init())
261 return BK_FAIL;
262
263 pm_init_todo();
264 show_init_info();
265 random_init();
266 #if (!CONFIG_SLAVE_CORE)
267 wdt_init();
268 #if (CONFIG_PSRAM_AS_SYS_MEMORY)
269 bk_psram_init();
270 #endif
271 #endif
272 ipc_init();
273
274 #else
275 driver_init();
276 pm_init_todo();
277 reset_reason_init();
278 random_init();
279 wdt_init();
280 show_init_info();
281 #endif
282 return BK_OK;
283 }
284