1 /*
2 * drivers/amlogic/amports/avs2.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/types.h>
20 #include <linux/errno.h>
21 #include <linux/interrupt.h>
22 #include <linux/semaphore.h>
23 #include <linux/delay.h>
24 #include <linux/timer.h>
25 #include <linux/kfifo.h>
26 #include <linux/kthread.h>
27 #include <linux/spinlock.h>
28 #include <linux/platform_device.h>
29 #include <linux/amlogic/media/vfm/vframe.h>
30 #include <linux/amlogic/media/utils/amstream.h>
31 #include <linux/amlogic/media/utils/vformat.h>
32 #include <linux/amlogic/media/frame_sync/ptsserv.h>
33 #include <linux/amlogic/media/frame_sync/tsync.h>
34 #include <linux/amlogic/media/canvas/canvas.h>
35 #include <linux/amlogic/media/vfm/vframe_provider.h>
36 #include <linux/amlogic/media/vfm/vframe_receiver.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/dma-map-ops.h>
39 #include <linux/sched/clock.h>
40 #include <linux/slab.h>
41 #include <linux/amlogic/tee.h>
42 #include "../../../stream_input/amports/amports_priv.h"
43 #include <linux/amlogic/media/codec_mm/codec_mm.h>
44 #include "../utils/decoder_mmu_box.h"
45 #include "../utils/decoder_bmmu_box.h"
46 #include "avs2_global.h"
47
48 #define MEM_NAME "codec_avs2"
49 /* #include <mach/am_regs.h> */
50 #include <linux/amlogic/media/utils/vdec_reg.h>
51 #include "../utils/vdec.h"
52 #include "../utils/amvdec.h"
53
54 #include <linux/amlogic/media/video_sink/video.h>
55 #include <linux/amlogic/media/codec_mm/configs.h>
56 #include "../utils/config_parser.h"
57 #include "../utils/firmware.h"
58 #include "../../../common/chips/decoder_cpu_ver_info.h"
59 #include <linux/amlogic/tee.h>
60
61
62 #define I_ONLY_SUPPORT
63 #define MIX_STREAM_SUPPORT
64 #define G12A_BRINGUP_DEBUG
65 #define CONSTRAIN_MAX_BUF_NUM
66
67 #include "vavs2.h"
68 #define HEVC_SHIFT_LENGTH_PROTECT 0x313a
69 #define HEVC_MPRED_CTRL9 0x325b
70 #define HEVC_DBLK_CFGD 0x350d
71
72
73 #define HEVC_CM_HEADER_START_ADDR 0x3628
74 #define HEVC_DBLK_CFGB 0x350b
75 #define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
76 #define HEVC_SAO_MMU_VH1_ADDR 0x363b
77 #define HEVC_SAO_MMU_VH0_ADDR 0x363a
78
79
80 /*
81 * AVS2_DEC_STATUS define
82 */
83 /*internal*/
84 #define AVS2_DEC_IDLE 0
85 #define AVS2_SEQUENCE 1
86 #define AVS2_I_PICTURE 2
87 #define AVS2_PB_PICTURE 3
88 #define AVS2_DISCARD_STARTCODE 4
89 #define AVS2_DISCARD_NAL 4
90
91 #define AVS2_SLICE_DECODING 6
92
93 #define SWAP_IN_CMD 0x10
94 #define SWAP_OUT_CMD 0x11
95 #define SWAP_OUTIN_CMD 0x12
96 #define SWAP_DONE 0x13
97 #define SWAP_POST_INIT 0x14
98
99 /*head*/
100 #define AVS2_HEAD_SEQ_READY 0x21
101 #define AVS2_HEAD_PIC_I_READY 0x22
102 #define AVS2_HEAD_PIC_PB_READY 0x23
103 #define AVS2_HEAD_SEQ_END_READY 0x24
104 #define AVS2_STARTCODE_SEARCH_DONE 0x25
105
106 /*pic done*/
107 #define HEVC_DECPIC_DATA_DONE 0x30
108 #define HEVC_DECPIC_DATA_ERROR 0x31
109 #define HEVC_NAL_DECODE_DONE 0x32
110 #define AVS2_DECODE_BUFEMPTY 0x33
111 #define AVS2_DECODE_TIMEOUT 0x34
112 #define AVS2_DECODE_OVER_SIZE 0x35
113 #define AVS2_EOS 0x36
114
115 /*cmd*/
116 #define AVS2_10B_DISCARD_NAL 0xf0
117 #define AVS2_SEARCH_NEW_PIC 0xf1
118 #define AVS2_ACTION_ERROR 0xfe
119 #define HEVC_ACTION_ERROR 0xfe
120 #define AVS2_ACTION_DONE 0xff
121 /*AVS2_DEC_STATUS end*/
122
123
124 #define VF_POOL_SIZE 32
125
126 #undef pr_info
127 #define pr_info printk
128
129 #define DECODE_MODE_SINGLE (0 | (0x80 << 24))
130 #define DECODE_MODE_MULTI_STREAMBASE (1 | (0x80 << 24))
131 #define DECODE_MODE_MULTI_FRAMEBASE (2 | (0x80 << 24))
132
133
134 #define VP9_TRIGGER_FRAME_DONE 0x100
135 #define VP9_TRIGGER_FRAME_ENABLE 0x200
136
137 /*#define MV_MEM_UNIT 0x240*/
138 #define MV_MEM_UNIT 0x200
139 /*---------------------------------------------------
140 Include "parser_cmd.h"
141 ---------------------------------------------------*/
142 #define PARSER_CMD_SKIP_CFG_0 0x0000090b
143
144 #define PARSER_CMD_SKIP_CFG_1 0x1b14140f
145
146 #define PARSER_CMD_SKIP_CFG_2 0x001b1910
147
148
149 #define PARSER_CMD_NUMBER 37
150
151 static unsigned short parser_cmd[PARSER_CMD_NUMBER] = {
152 0x0401,
153 0x8401,
154 0x0800,
155 0x0402,
156 0x9002,
157 0x1423,
158 0x8CC3,
159 0x1423,
160 0x8804,
161 0x9825,
162 0x0800,
163 0x04FE,
164 0x8406,
165 0x8411,
166 0x1800,
167 0x8408,
168 0x8409,
169 0x8C2A,
170 0x9C2B,
171 0x1C00,
172 0x840F,
173 0x8407,
174 0x8000,
175 0x8408,
176 0x2000,
177 0xA800,
178 0x8410,
179 0x04DE,
180 0x840C,
181 0x840D,
182 0xAC00,
183 0xA000,
184 0x08C0,
185 0x08E0,
186 0xA40E,
187 0xFC00,
188 0x7C00
189 };
190
191 static int32_t g_WqMDefault4x4[16] = {
192 64, 64, 64, 68,
193 64, 64, 68, 72,
194 64, 68, 76, 80,
195 72, 76, 84, 96
196 };
197
198
199 static int32_t g_WqMDefault8x8[64] = {
200 64, 64, 64, 64, 68, 68, 72, 76,
201 64, 64, 64, 68, 72, 76, 84, 92,
202 64, 64, 68, 72, 76, 80, 88, 100,
203 64, 68, 72, 80, 84, 92, 100, 112,
204 68, 72, 80, 84, 92, 104, 112, 128,
205 76, 80, 84, 92, 104, 116, 132, 152,
206 96, 100, 104, 116, 124, 140, 164, 188,
207 104, 108, 116, 128, 152, 172, 192, 216
208 };
209 /*#define HEVC_PIC_STRUCT_SUPPORT*/
210 /* to remove, fix build error */
211
212 /*#define CODEC_MM_FLAGS_FOR_VDECODER 0*/
213
214 #define MULTI_INSTANCE_SUPPORT
215 /* #define ERROR_HANDLE_DEBUG */
216
217 #ifndef STAT_KTHREAD
218 #define STAT_KTHREAD 0x40
219 #endif
220
221 #ifdef MULTI_INSTANCE_SUPPORT
222 #define MAX_DECODE_INSTANCE_NUM 12
223 #define MULTI_DRIVER_NAME "ammvdec_avs2"
224
225 #define lock_buffer(dec, flags) \
226 spin_lock_irqsave(&dec->buffer_lock, flags)
227
228 #define unlock_buffer(dec, flags) \
229 spin_unlock_irqrestore(&dec->buffer_lock, flags)
230
231 static unsigned int max_decode_instance_num
232 = MAX_DECODE_INSTANCE_NUM;
233 static unsigned int decode_frame_count[MAX_DECODE_INSTANCE_NUM];
234 static unsigned int display_frame_count[MAX_DECODE_INSTANCE_NUM];
235 static unsigned int max_process_time[MAX_DECODE_INSTANCE_NUM];
236 static unsigned int run_count[MAX_DECODE_INSTANCE_NUM];
237 static unsigned int input_empty[MAX_DECODE_INSTANCE_NUM];
238 static unsigned int not_run_ready[MAX_DECODE_INSTANCE_NUM];
239
240 #ifdef G12A_BRINGUP_DEBUG
241 static u32 decode_timeout_val = 200;
242 #else
243 static u32 decode_timeout_val = 200;
244 #endif
245 static int start_decode_buf_level = 0x8000;
246 #ifdef AVS2_10B_MMU
247 static u32 work_buf_size; /* = 24 * 1024 * 1024*/;
248 #else
249 static u32 work_buf_size = 32 * 1024 * 1024;
250 #endif
251
252 static u32 mv_buf_margin;
253 static int pre_decode_buf_level = 0x1000;
254 static u32 again_threshold;
255
256
257 /* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
258 /* double_write_mode:
259 * 0, no double write;
260 * 1, 1:1 ratio;
261 * 2, (1/4):(1/4) ratio;
262 * 3, (1/4):(1/4) ratio, with both compressed frame included
263 * 4, (1/2):(1/2) ratio;
264 * 0x10, double write only
265 * 0x100, if > 1080p,use mode 4,else use mode 1;
266 * 0x200, if > 1080p,use mode 2,else use mode 1;
267 * 0x300, if > 720p, use mode 4, else use mode 1;
268 */
269 static u32 double_write_mode;
270 static u32 without_display_mode;
271
272 #define DRIVER_NAME "amvdec_avs2"
273 #define MODULE_NAME "amvdec_avs2"
274 #define DRIVER_HEADER_NAME "amvdec_avs2_header"
275
276
277 #define PUT_INTERVAL (HZ/100)
278 #define ERROR_SYSTEM_RESET_COUNT 200
279
280 #define PTS_NORMAL 0
281 #define PTS_NONE_REF_USE_DURATION 1
282
283 #define PTS_MODE_SWITCHING_THRESHOLD 3
284 #define PTS_MODE_SWITCHING_RECOVERY_THREASHOLD 3
285
286 #define DUR2PTS(x) ((x)*90/96)
287
288 struct AVS2Decoder_s;
289 static int vavs2_vf_states(struct vframe_states *states, void *);
290 static struct vframe_s *vavs2_vf_peek(void *);
291 static struct vframe_s *vavs2_vf_get(void *);
292 static void vavs2_vf_put(struct vframe_s *, void *);
293 static int vavs2_event_cb(int type, void *data, void *private_data);
294 static void set_vframe(struct AVS2Decoder_s *dec,
295 struct vframe_s *vf, struct avs2_frame_s *pic, u8 dummy);
296
297 static int vavs2_stop(struct AVS2Decoder_s *dec);
298 static s32 vavs2_init(struct vdec_s *vdec);
299 static void vavs2_prot_init(struct AVS2Decoder_s *dec);
300 static int vavs2_local_init(struct AVS2Decoder_s *dec);
301 static void vavs2_put_timer_func(struct timer_list *timer);
302 static void dump_data(struct AVS2Decoder_s *dec, int size);
303 static unsigned char get_data_check_sum
304 (struct AVS2Decoder_s *dec, int size);
305 static void dump_pic_list(struct AVS2Decoder_s *dec);
306
307 static const char vavs2_dec_id[] = "vavs2-dev";
308
309 #define PROVIDER_NAME "decoder.avs2"
310 #define MULTI_INSTANCE_PROVIDER_NAME "vdec.avs2"
311
312 static const struct vframe_operations_s vavs2_vf_provider = {
313 .peek = vavs2_vf_peek,
314 .get = vavs2_vf_get,
315 .put = vavs2_vf_put,
316 .event_cb = vavs2_event_cb,
317 .vf_states = vavs2_vf_states,
318 };
319
320 static struct vframe_provider_s vavs2_vf_prov;
321
322 static u32 bit_depth_luma;
323 static u32 bit_depth_chroma;
324 static u32 frame_width;
325 static u32 frame_height;
326 static u32 video_signal_type;
327 static u32 pts_unstable;
328 static u32 on_no_keyframe_skiped;
329
330 static u32 force_video_signal_type;
331 static u32 enable_force_video_signal_type;
332 #define VIDEO_SIGNAL_TYPE_AVAILABLE_MASK 0x20000000
333
334 static const char * const video_format_names[] = {
335 "component", "PAL", "NTSC", "SECAM",
336 "MAC", "unspecified", "Reserved", "Reserved"
337 };
338
div_r32(int64_t m,int n)339 static inline int div_r32(int64_t m, int n)
340 {
341 /*
342 return (int)(m/n)
343 */
344 #ifndef CONFIG_ARM64
345 int64_t qu = 0;
346 qu = div_s64(m, n);
347 return (int)qu;
348 #else
349 return (int)(m/n);
350 #endif
351 }
352
353 enum vpx_bit_depth_t {
354 AVS2_BITS_8 = 8, /**< 8 bits */
355 AVS2_BITS_10 = 10, /**< 10 bits */
356 AVS2_BITS_12 = 12, /**< 12 bits */
357 };
358
359 /*USE_BUF_BLOCK*/
360 struct BUF_s {
361 int index;
362 unsigned int alloc_flag;
363 /*buffer */
364 unsigned int cma_page_count;
365 unsigned long alloc_addr;
366 unsigned long start_adr;
367 unsigned int size;
368
369 unsigned int free_start_adr;
370 } /*BUF_t */;
371
372 struct MVBUF_s {
373 unsigned long start_adr;
374 unsigned int size;
375 int used_flag;
376 } /*MVBUF_t */;
377
378 /* #undef BUFMGR_ONLY to enable hardware configuration */
379
380 /*#define TEST_WR_PTR_INC*/
381 #define WR_PTR_INC_NUM 128
382
383 #define SIMULATION
384 #define DOS_PROJECT
385 #undef MEMORY_MAP_IN_REAL_CHIP
386
387 /*#undef DOS_PROJECT*/
388 /*#define MEMORY_MAP_IN_REAL_CHIP*/
389
390 /*#define BUFFER_MGR_ONLY*/
391 /*#define CONFIG_HEVC_CLK_FORCED_ON*/
392 /*#define ENABLE_SWAP_TEST*/
393
394 #ifdef AVS2_10B_NV21
395 #define MEM_MAP_MODE 2 /* 0:linear 1:32x32 2:64x32*/
396 #else
397 #define MEM_MAP_MODE 0 /* 0:linear 1:32x32 2:64x32*/
398 #endif
399
400 #ifdef AVS2_10B_NV21
401 #else
402 #define LOSLESS_COMPRESS_MODE
403 #endif
404
405 #define DOUBLE_WRITE_YSTART_TEMP 0x02000000
406 #define DOUBLE_WRITE_CSTART_TEMP 0x02900000
407
408
409
410 typedef unsigned int u32;
411 typedef unsigned short u16;
412
413 #define AVS2_DBG_BUFMGR 0x01
414 #define AVS2_DBG_BUFMGR_MORE 0x02
415 #define AVS2_DBG_BUFMGR_DETAIL 0x04
416 #define AVS2_DBG_IRQ_EVENT 0x08
417 #define AVS2_DBG_OUT_PTS 0x10
418 #define AVS2_DBG_PRINT_SOURCE_LINE 0x20
419 #define AVS2_DBG_PRINT_PARAM 0x40
420 #define AVS2_DBG_PRINT_PIC_LIST 0x80
421 #define AVS2_DBG_SEND_PARAM_WITH_REG 0x100
422 #define AVS2_DBG_MERGE 0x200
423 #define AVS2_DBG_DBG_LF_PRINT 0x400
424 #define AVS2_DBG_REG 0x800
425 #define AVS2_DBG_PIC_LEAK 0x1000
426 #define AVS2_DBG_PIC_LEAK_WAIT 0x2000
427 #define AVS2_DBG_HDR_INFO 0x4000
428 #define AVS2_DBG_DIS_LOC_ERROR_PROC 0x10000
429 #define AVS2_DBG_DIS_SYS_ERROR_PROC 0x20000
430 #define AVS2_DBG_DUMP_PIC_LIST 0x40000
431 #define AVS2_DBG_TRIG_SLICE_SEGMENT_PROC 0x80000
432 #define AVS2_DBG_FORCE_UNCOMPRESS 0x100000
433 #define AVS2_DBG_LOAD_UCODE_FROM_FILE 0x200000
434 #define AVS2_DBG_FORCE_SEND_AGAIN 0x400000
435 #define AVS2_DBG_DUMP_DATA 0x800000
436 #define AVS2_DBG_DUMP_LMEM_BUF 0x1000000
437 #define AVS2_DBG_DUMP_RPM_BUF 0x2000000
438 #define AVS2_DBG_CACHE 0x4000000
439 #define IGNORE_PARAM_FROM_CONFIG 0x8000000
440 /*MULTI_INSTANCE_SUPPORT*/
441 #define PRINT_FLAG_ERROR 0
442 #define PRINT_FLAG_VDEC_STATUS 0x20000000
443 #define PRINT_FLAG_VDEC_DETAIL 0x40000000
444 #define PRINT_FLAG_VDEC_DATA 0x80000000
445
446 #define PRINT_LINE() \
447 do { \
448 if (debug & AVS2_DBG_PRINT_SOURCE_LINE)\
449 pr_info("%s line %d\n", __func__, __LINE__);\
450 } while (0)
451
452 static u32 debug;
453
454 static u32 debug_again;
455
is_avs2_print_param(void)456 bool is_avs2_print_param(void)
457 {
458 bool ret = false;
459 if (debug & AVS2_DBG_PRINT_PARAM)
460 ret = true;
461 return ret;
462 }
463
is_avs2_print_bufmgr_detail(void)464 bool is_avs2_print_bufmgr_detail(void)
465 {
466 bool ret = false;
467 if (debug & AVS2_DBG_BUFMGR_DETAIL)
468 ret = true;
469 return ret;
470 }
471 static bool is_reset;
472 /*for debug*/
473 /*
474 udebug_flag:
475 bit 0, enable ucode print
476 bit 1, enable ucode detail print
477 bit [31:16] not 0, pos to dump lmem
478 bit 2, pop bits to lmem
479 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
480 */
481 static u32 udebug_flag;
482 /*
483 when udebug_flag[1:0] is not 0
484 udebug_pause_pos not 0,
485 pause position
486 */
487 static u32 udebug_pause_pos;
488 /*
489 when udebug_flag[1:0] is not 0
490 and udebug_pause_pos is not 0,
491 pause only when DEBUG_REG2 is equal to this val
492 */
493 static u32 udebug_pause_val;
494
495 static u32 udebug_pause_decode_idx;
496
497 static u32 force_disp_pic_index;
498
499 #define DEBUG_REG
500 #ifdef DEBUG_REG
WRITE_VREG_DBG2(unsigned adr,unsigned val)501 static void WRITE_VREG_DBG2(unsigned adr, unsigned val)
502 {
503 if (debug & AVS2_DBG_REG)
504 pr_info("%s(%x, %x)\n", __func__, adr, val);
505 if (adr != 0)
506 WRITE_VREG(adr, val);
507 }
508
509 #undef WRITE_VREG
510 #define WRITE_VREG WRITE_VREG_DBG2
511 #endif
512
513
514 #ifdef AVS2_10B_MMU
515 #define MMU_COMPRESS_HEADER_SIZE 0x48000
516 #define MMU_COMPRESS_8K_HEADER_SIZE 0x48000*4
517 #endif
518
519 #define INVALID_IDX -1 /* Invalid buffer index.*/
520
521
522 #define FRAME_BUFFERS (AVS2_MAX_BUFFER_NUM)
523 #define HEADER_FRAME_BUFFERS (FRAME_BUFFERS)
524 #define MAX_BUF_NUM (FRAME_BUFFERS)
525
526 #define FRAME_CONTEXTS_LOG2 2
527 #define FRAME_CONTEXTS (1 << FRAME_CONTEXTS_LOG2)
528 /*buffer + header buffer + workspace*/
529 #ifdef MV_USE_FIXED_BUF
530 #define MAX_BMMU_BUFFER_NUM ((FRAME_BUFFERS + HEADER_FRAME_BUFFERS + 1)+1)
531 #define VF_BUFFER_IDX(n) (n)
532 #define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n+1)
533 #define WORK_SPACE_BUF_ID (FRAME_BUFFERS + HEADER_FRAME_BUFFERS+1)
534 #else
535 #define MAX_BMMU_BUFFER_NUM (((FRAME_BUFFERS*2)+HEADER_FRAME_BUFFERS+1)+1)
536 #define VF_BUFFER_IDX(n) (n)
537 #define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n+1)
538 #define MV_BUFFER_IDX(n) ((FRAME_BUFFERS * 2) + n+1)
539 #define WORK_SPACE_BUF_ID ((FRAME_BUFFERS * 2) + HEADER_FRAME_BUFFERS+1)
540 #endif
541 /*
542 static void set_canvas(struct AVS2Decoder_s *dec,
543 struct avs2_frame_s *pic);
544 int avs2_prepare_display_buf(struct AVS2Decoder_s *dec,
545 int pos);
546 */
547
548
549 struct buff_s {
550 u32 buf_start;
551 u32 buf_size;
552 u32 buf_end;
553 };
554
555 struct BuffInfo_s {
556 u32 max_width;
557 u32 max_height;
558 u32 start_adr;
559 u32 end_adr;
560 struct buff_s ipp;
561 struct buff_s sao_abv;
562 struct buff_s sao_vb;
563 struct buff_s short_term_rps;
564 struct buff_s rcs;
565 struct buff_s sps;
566 struct buff_s pps;
567 struct buff_s sao_up;
568 struct buff_s swap_buf;
569 struct buff_s swap_buf2;
570 struct buff_s scalelut;
571 struct buff_s dblk_para;
572 struct buff_s dblk_data;
573 struct buff_s dblk_data2;
574 #ifdef AVS2_10B_MMU
575 struct buff_s mmu_vbh;
576 struct buff_s cm_header;
577 #endif
578 struct buff_s mpred_above;
579 #ifdef MV_USE_FIXED_BUF
580 struct buff_s mpred_mv;
581 #endif
582 struct buff_s rpm;
583 struct buff_s lmem;
584 };
585
586 #define DEC_RESULT_NONE 0
587 #define DEC_RESULT_DONE 1
588 #define DEC_RESULT_AGAIN 2
589 #define DEC_RESULT_CONFIG_PARAM 3
590 #define DEC_RESULT_ERROR 4
591 #define DEC_INIT_PICLIST 5
592 #define DEC_UNINIT_PICLIST 6
593 #define DEC_RESULT_GET_DATA 7
594 #define DEC_RESULT_GET_DATA_RETRY 8
595 #define DEC_RESULT_EOS 9
596 #define DEC_RESULT_FORCE_EXIT 10
597
598 static void avs2_work(struct work_struct *work);
599 struct loop_filter_info_n;
600 struct loopfilter;
601 struct segmentation;
602
603 struct AVS2Decoder_s {
604 int pic_list_init_flag;
605 unsigned char index;
606 spinlock_t buffer_lock;
607 struct device *cma_dev;
608 struct platform_device *platform_dev;
609 void (*vdec_cb)(struct vdec_s *, void *);
610 void *vdec_cb_arg;
611 struct vframe_chunk_s *chunk;
612 int dec_result;
613 struct work_struct work;
614 u32 start_shift_bytes;
615
616 struct BuffInfo_s work_space_buf_store;
617 unsigned long buf_start;
618 u32 buf_size;
619 u32 cma_alloc_count;
620 unsigned long cma_alloc_addr;
621 uint8_t eos;
622 unsigned long int start_process_time;
623 unsigned last_lcu_idx;
624 int decode_timeout_count;
625 unsigned timeout_num;
626
627 int double_write_mode;
628
629 unsigned char m_ins_flag;
630 char *provider_name;
631 int frame_count;
632 u32 stat;
633 struct timer_list timer;
634 u32 frame_dur;
635 u32 frame_ar;
636 int fatal_error;
637 uint8_t init_flag;
638 uint8_t first_sc_checked;
639 uint8_t process_busy;
640 #define PROC_STATE_INIT 0
641 #define PROC_STATE_HEAD_DONE 1
642 #define PROC_STATE_DECODING 2
643 #define PROC_STATE_HEAD_AGAIN 3
644 #define PROC_STATE_DECODE_AGAIN 4
645 #define PROC_STATE_TEST1 5
646 uint8_t process_state;
647 u32 ucode_pause_pos;
648
649 int show_frame_num;
650 #ifndef AVS2_10B_MMU
651 struct buff_s mc_buf_spec;
652 #endif
653 struct dec_sysinfo vavs2_amstream_dec_info;
654 void *rpm_addr;
655 void *lmem_addr;
656 dma_addr_t rpm_phy_addr;
657 dma_addr_t lmem_phy_addr;
658 unsigned short *lmem_ptr;
659 unsigned short *debug_ptr;
660
661 #if 1
662 /*AVS2_10B_MMU*/
663 void *frame_mmu_map_addr;
664 dma_addr_t frame_mmu_map_phy_addr;
665 #endif
666 unsigned int use_cma_flag;
667
668 struct BUF_s m_BUF[MAX_BUF_NUM];
669 struct MVBUF_s m_mv_BUF[MAX_BUF_NUM];
670 u32 used_buf_num;
671 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
672 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
673 DECLARE_KFIFO(pending_q, struct vframe_s *, VF_POOL_SIZE);
674 struct vframe_s vfpool[VF_POOL_SIZE];
675 u32 vf_pre_count;
676 u32 vf_get_count;
677 u32 vf_put_count;
678 int buf_num;
679 unsigned int losless_comp_body_size;
680
681 u32 video_signal_type;
682 u32 video_ori_signal_type;
683
684 int pts_mode;
685 int last_lookup_pts;
686 int last_pts;
687 u64 last_lookup_pts_us64;
688 u64 last_pts_us64;
689 u64 shift_byte_count;
690 u32 shift_byte_count_lo;
691 u32 shift_byte_count_hi;
692 int pts_mode_switching_count;
693 int pts_mode_recovery_count;
694
695 bool get_frame_dur;
696 u32 saved_resolution;
697
698 /**/
699 int refresh_frame_flags;
700 uint8_t hold_ref_buf;
701 struct BuffInfo_s *work_space_buf;
702 #ifndef AVS2_10B_MMU
703 struct buff_s *mc_buf;
704 #endif
705 unsigned int frame_width;
706 unsigned int frame_height;
707
708 unsigned short *rpm_ptr;
709 int init_pic_w;
710 int init_pic_h;
711
712 int slice_type;
713
714 int decode_idx;
715 int slice_idx;
716 uint8_t wait_buf;
717 uint8_t error_flag;
718 unsigned int bufmgr_error_count;
719
720 /* bit 0, for decoding; bit 1, for displaying */
721 uint8_t ignore_bufmgr_error;
722 uint8_t skip_PB_before_I;
723 int PB_skip_mode;
724 int PB_skip_count_after_decoding;
725 /*hw*/
726
727 /**/
728 struct vdec_info *gvs;
729
730
731 unsigned int dec_status;
732 u32 last_put_idx;
733 int new_frame_displayed;
734 void *mmu_box;
735 void *bmmu_box;
736 struct vframe_master_display_colour_s vf_dp;
737 struct firmware_s *fw;
738 #ifdef AVS2_10B_MMU
739 int cur_fb_idx_mmu;
740 long used_4k_num;
741 #endif
742 struct avs2_decoder avs2_dec;
743 #define ALF_NUM_BIT_SHIFT 6
744 #define NO_VAR_BINS 16
745 int32_t m_filterCoeffSym[16][9];
746 int32_t m_varIndTab[NO_VAR_BINS];
747
748 struct vframe_s vframe_dummy;
749 /* start_decoding_flag,
750 bit 0, SEQ ready
751 bit 1, I ready
752 */
753 unsigned char start_decoding_flag;
754 uint32_t mpred_abv_start_addr;
755 uint32_t mpred_abv_start_addr_bak;
756 u8 next_again_flag;
757 u32 pre_parser_wr_ptr;
758 int need_cache_size;
759 u64 sc_start_time;
760 #ifdef I_ONLY_SUPPORT
761 u32 i_only;
762 #endif
763 int frameinfo_enable;
764 struct vframe_qos_s vframe_qos;
765 u32 dynamic_buf_margin;
766 int sidebind_type;
767 int sidebind_channel_id;
768 };
769
770 static int compute_losless_comp_body_size(
771 struct AVS2Decoder_s *dec, int width, int height,
772 uint8_t is_bit_depth_10);
773
avs2_print(struct AVS2Decoder_s * dec,int flag,const char * fmt,...)774 static int avs2_print(struct AVS2Decoder_s *dec,
775 int flag, const char *fmt, ...)
776 {
777 #define HEVC_PRINT_BUF 256
778 unsigned char buf[HEVC_PRINT_BUF];
779 int len = 0;
780 if (dec == NULL ||
781 (flag == 0) ||
782 (debug & flag)) {
783 va_list args;
784 va_start(args, fmt);
785 if (dec)
786 len = sprintf(buf, "[%d]", dec->index);
787 vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
788 pr_info("%s", buf);
789 va_end(args);
790 }
791 return 0;
792 }
793
avs2_print_cont(struct AVS2Decoder_s * dec,int flag,const char * fmt,...)794 static int avs2_print_cont(struct AVS2Decoder_s *dec,
795 int flag, const char *fmt, ...)
796 {
797 unsigned char buf[HEVC_PRINT_BUF];
798 int len = 0;
799 if (dec == NULL ||
800 (flag == 0) ||
801 (debug & flag)) {
802 va_list args;
803 va_start(args, fmt);
804 vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
805 pr_info("%s", buf);
806 va_end(args);
807 }
808 return 0;
809 }
810
811 #define PROB_SIZE (496 * 2 * 4)
812 #define PROB_BUF_SIZE (0x5000)
813 #define COUNT_BUF_SIZE (0x300 * 4 * 4)
814 /*compute_losless_comp_body_size(4096, 2304, 1) = 18874368(0x1200000)*/
815 #define MAX_FRAME_4K_NUM 0x1200
816 #define MAX_FRAME_8K_NUM 0x4800
817 #define MAX_SIZE_4K (4096 * 2304)
818 #define IS_8K_SIZE(w, h) (((w) * (h)) > MAX_SIZE_4K)
819
get_frame_mmu_map_size(struct AVS2Decoder_s * dec)820 static int get_frame_mmu_map_size(struct AVS2Decoder_s *dec)
821 {
822 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
823 (IS_8K_SIZE(dec->init_pic_w, dec->init_pic_h)))
824 return (MAX_FRAME_8K_NUM * 4);
825 return (MAX_FRAME_4K_NUM * 4);
826 }
827
get_compress_header_size(struct AVS2Decoder_s * dec)828 static int get_compress_header_size(struct AVS2Decoder_s *dec)
829 {
830 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
831 (IS_8K_SIZE(dec->init_pic_w, dec->init_pic_h)))
832 return MMU_COMPRESS_8K_HEADER_SIZE;
833 return MMU_COMPRESS_HEADER_SIZE;
834 }
835
reset_process_time(struct AVS2Decoder_s * dec)836 static void reset_process_time(struct AVS2Decoder_s *dec)
837 {
838 if (dec->start_process_time) {
839 unsigned process_time =
840 1000 * (jiffies - dec->start_process_time) / HZ;
841 dec->start_process_time = 0;
842 if (process_time > max_process_time[dec->index])
843 max_process_time[dec->index] = process_time;
844 }
845 }
846
start_process_time(struct AVS2Decoder_s * dec)847 static void start_process_time(struct AVS2Decoder_s *dec)
848 {
849 dec->start_process_time = jiffies;
850 dec->decode_timeout_count = 0;
851 dec->last_lcu_idx = 0;
852 }
853
854 static void update_decoded_pic(struct AVS2Decoder_s *dec);
855
timeout_process(struct AVS2Decoder_s * dec)856 static void timeout_process(struct AVS2Decoder_s *dec)
857 {
858 struct avs2_decoder *avs2_dec = &dec->avs2_dec;
859 struct avs2_frame_s *cur_pic = avs2_dec->hc.cur_pic;
860 dec->timeout_num++;
861 amhevc_stop();
862 avs2_print(dec,
863 0, "%s decoder timeout\n", __func__);
864 if (cur_pic)
865 cur_pic->error_mark = 1;
866 dec->dec_result = DEC_RESULT_DONE;
867 update_decoded_pic(dec);
868 reset_process_time(dec);
869 vdec_schedule_work(&dec->work);
870 }
871
get_valid_double_write_mode(struct AVS2Decoder_s * dec)872 static u32 get_valid_double_write_mode(struct AVS2Decoder_s *dec)
873 {
874 return (dec->m_ins_flag &&
875 ((double_write_mode & 0x80000000) == 0)) ?
876 dec->double_write_mode :
877 (double_write_mode & 0x7fffffff);
878 }
879
get_double_write_mode(struct AVS2Decoder_s * dec)880 static int get_double_write_mode(struct AVS2Decoder_s *dec)
881 {
882 u32 valid_dw_mode = get_valid_double_write_mode(dec);
883 int w = dec->avs2_dec.img.width;
884 int h = dec->avs2_dec.img.height;
885 u32 dw = 0x1; /*1:1*/
886 switch (valid_dw_mode) {
887 case 0x100:
888 if (w > 1920 && h > 1088)
889 dw = 0x4; /*1:2*/
890 break;
891 case 0x200:
892 if (w > 1920 && h > 1088)
893 dw = 0x2; /*1:4*/
894 break;
895 case 0x300:
896 if (w > 1280 && h > 720)
897 dw = 0x4; /*1:2*/
898 break;
899 default:
900 dw = valid_dw_mode;
901 break;
902 }
903 return dw;
904 }
905
906 /* for double write buf alloc */
get_double_write_mode_init(struct AVS2Decoder_s * dec)907 static int get_double_write_mode_init(struct AVS2Decoder_s *dec)
908 {
909 u32 valid_dw_mode = get_valid_double_write_mode(dec);
910 u32 dw;
911 int w = dec->init_pic_w;
912 int h = dec->init_pic_h;
913
914 dw = 0x1; /*1:1*/
915 switch (valid_dw_mode) {
916 case 0x100:
917 if (w > 1920 && h > 1088)
918 dw = 0x4; /*1:2*/
919 break;
920 case 0x200:
921 if (w > 1920 && h > 1088)
922 dw = 0x2; /*1:4*/
923 break;
924 case 0x300:
925 if (w > 1280 && h > 720)
926 dw = 0x4; /*1:2*/
927 break;
928 default:
929 dw = valid_dw_mode;
930 break;
931 }
932 return dw;
933 }
934
get_double_write_ratio(struct AVS2Decoder_s * dec,int dw_mode)935 static int get_double_write_ratio(struct AVS2Decoder_s *dec,
936 int dw_mode)
937 {
938 int ratio = 1;
939 if ((dw_mode == 2) ||
940 (dw_mode == 3))
941 ratio = 4;
942 else if (dw_mode == 4)
943 ratio = 2;
944 return ratio;
945 }
946
947 //#define MAX_4K_NUM 0x1200
948 #ifdef AVS2_10B_MMU
avs2_alloc_mmu(struct AVS2Decoder_s * dec,int cur_buf_idx,int pic_width,int pic_height,unsigned short bit_depth,unsigned int * mmu_index_adr)949 int avs2_alloc_mmu(
950 struct AVS2Decoder_s *dec,
951 int cur_buf_idx,
952 int pic_width,
953 int pic_height,
954 unsigned short bit_depth,
955 unsigned int *mmu_index_adr)
956 {
957 int bit_depth_10 = (bit_depth == AVS2_BITS_10);
958 int picture_size;
959 int cur_mmu_4k_number, max_frame_num;
960 #ifdef DYNAMIC_ALLOC_HEAD
961 unsigned long buf_addr;
962 struct avs2_frame_s *pic = dec->avs2_dec.hc.cur_pic;
963 if (pic->header_adr == 0) {
964 if (decoder_bmmu_box_alloc_buf_phy
965 (dec->bmmu_box,
966 HEADER_BUFFER_IDX(cur_buf_idx),
967 MMU_COMPRESS_HEADER_SIZE,
968 DRIVER_HEADER_NAME,
969 &buf_addr) < 0){
970 avs2_print(dec, 0,
971 "%s malloc compress header failed %d\n",
972 DRIVER_HEADER_NAME, cur_buf_idx);
973 dec->fatal_error |= DECODER_FATAL_ERROR_NO_MEM;
974 return -1;
975 } else
976 pic->header_adr = buf_addr;
977 }
978 #endif
979
980 picture_size = compute_losless_comp_body_size(
981 dec, pic_width, pic_height,
982 bit_depth_10);
983 cur_mmu_4k_number = ((picture_size + (1 << 12) - 1) >> 12);
984 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
985 max_frame_num = MAX_FRAME_8K_NUM;
986 else
987 max_frame_num = MAX_FRAME_4K_NUM;
988 if (cur_mmu_4k_number > max_frame_num) {
989 pr_err("over max !! cur_mmu_4k_number 0x%x width %d height %d\n",
990 cur_mmu_4k_number, pic_width, pic_height);
991 return -1;
992 }
993 return decoder_mmu_box_alloc_idx(
994 dec->mmu_box,
995 cur_buf_idx,
996 cur_mmu_4k_number,
997 mmu_index_adr);
998 }
999 #endif
1000
1001 #if 0
1002 /*ndef MV_USE_FIXED_BUF*/
1003 static void dealloc_mv_bufs(struct AVS2Decoder_s *dec)
1004 {
1005 int i;
1006 for (i = 0; i < FRAME_BUFFERS; i++) {
1007 if (dec->m_mv_BUF[i].start_adr) {
1008 if (debug)
1009 pr_info(
1010 "dealloc mv buf(%d) adr %ld size 0x%x used_flag %d\n",
1011 i, dec->m_mv_BUF[i].start_adr,
1012 dec->m_mv_BUF[i].size,
1013 dec->m_mv_BUF[i].used_flag);
1014 decoder_bmmu_box_free_idx(
1015 dec->bmmu_box,
1016 MV_BUFFER_IDX(i));
1017 dec->m_mv_BUF[i].start_adr = 0;
1018 dec->m_mv_BUF[i].size = 0;
1019 dec->m_mv_BUF[i].used_flag = 0;
1020 }
1021 }
1022 }
1023
1024 static int alloc_mv_buf(struct AVS2Decoder_s *dec,
1025 int i, int size)
1026 {
1027 int ret = 0;
1028 if (decoder_bmmu_box_alloc_buf_phy
1029 (dec->bmmu_box,
1030 MV_BUFFER_IDX(i), size,
1031 DRIVER_NAME,
1032 &dec->m_mv_BUF[i].start_adr) < 0) {
1033 dec->m_mv_BUF[i].start_adr = 0;
1034 ret = -1;
1035 } else {
1036 dec->m_mv_BUF[i].size = size;
1037 dec->m_mv_BUF[i].used_flag = 0;
1038 ret = 0;
1039 if (debug) {
1040 pr_info(
1041 "MV Buffer %d: start_adr %p size %x\n",
1042 i,
1043 (void *)dec->m_mv_BUF[i].start_adr,
1044 dec->m_mv_BUF[i].size);
1045 }
1046 }
1047 return ret;
1048 }
1049
1050 static int init_mv_buf_list(struct AVS2Decoder_s *dec)
1051 {
1052 int i;
1053 int ret = 0;
1054 int count = FRAME_BUFFERS;
1055 int pic_width = dec->init_pic_w;
1056 int pic_height = dec->init_pic_h;
1057 int lcu_size = 64; /*fixed 64*/
1058 int pic_width_64 = (pic_width + 63) & (~0x3f);
1059 int pic_height_32 = (pic_height + 31) & (~0x1f);
1060 int pic_width_lcu = (pic_width_64 % lcu_size) ?
1061 pic_width_64 / lcu_size + 1
1062 : pic_width_64 / lcu_size;
1063 int pic_height_lcu = (pic_height_32 % lcu_size) ?
1064 pic_height_32 / lcu_size + 1
1065 : pic_height_32 / lcu_size;
1066 int lcu_total = pic_width_lcu * pic_height_lcu;
1067 int size = ((lcu_total * MV_MEM_UNIT) + 0xffff) &
1068 (~0xffff);
1069 if (mv_buf_margin > 0)
1070 count = dec->avs2_dec.ref_maxbuffer + mv_buf_margin;
1071 for (i = 0; i < count; i++) {
1072 if (alloc_mv_buf(dec, i, size) < 0) {
1073 ret = -1;
1074 break;
1075 }
1076 }
1077 return ret;
1078 }
1079 #if 0
1080
1081 static int get_mv_buf(struct AVS2Decoder_s *dec,
1082 struct avs2_frame_s *pic)
1083 {
1084 int i;
1085 int ret = -1;
1086 for (i = 0; i < FRAME_BUFFERS; i++) {
1087 if (dec->m_mv_BUF[i].start_adr &&
1088 dec->m_mv_BUF[i].used_flag == 0) {
1089 dec->m_mv_BUF[i].used_flag = 1;
1090 ret = i;
1091 break;
1092 }
1093 }
1094
1095 if (ret >= 0) {
1096 pic->mv_buf_index = ret;
1097 pic->mpred_mv_wr_start_addr =
1098 (dec->m_mv_BUF[ret].start_adr + 0xffff) &
1099 (~0xffff);
1100 if (debug & AVS2_DBG_BUFMGR_MORE)
1101 pr_info(
1102 "%s => %d (%d) size 0x%x\n",
1103 __func__, ret,
1104 pic->mpred_mv_wr_start_addr,
1105 dec->m_mv_BUF[ret].size);
1106 } else {
1107 pr_info(
1108 "%s: Error, mv buf is not enough\n",
1109 __func__);
1110 }
1111 return ret;
1112 }
1113
1114 static void put_mv_buf(struct AVS2Decoder_s *dec,
1115 struct avs2_frame_s *pic)
1116 {
1117 int i = pic->mv_buf_index;
1118 if (i >= FRAME_BUFFERS) {
1119 if (debug & AVS2_DBG_BUFMGR_MORE)
1120 pr_info(
1121 "%s: index %d beyond range\n",
1122 __func__, i);
1123 return;
1124 }
1125 if (debug & AVS2_DBG_BUFMGR_MORE)
1126 pr_info(
1127 "%s(%d): used_flag(%d)\n",
1128 __func__, i,
1129 dec->m_mv_BUF[i].used_flag);
1130
1131 pic->mv_buf_index = -1;
1132 if (dec->m_mv_BUF[i].start_adr &&
1133 dec->m_mv_BUF[i].used_flag)
1134 dec->m_mv_BUF[i].used_flag = 0;
1135 }
1136
1137 static void put_un_used_mv_bufs(struct AVS2Decoder_s *dec)
1138 {
1139 struct VP9_Common_s *const cm = &dec->common;
1140 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
1141 int i;
1142 for (i = 0; i < dec->used_buf_num; ++i) {
1143 if ((frame_bufs[i].ref_count == 0) &&
1144 (frame_bufs[i].buf.index != -1) &&
1145 (frame_bufs[i].buf.mv_buf_index >= 0)
1146 )
1147 put_mv_buf(dec, &frame_bufs[i].buf);
1148 }
1149 }
1150 #endif
1151
1152 #endif
1153
get_free_buf_count(struct AVS2Decoder_s * dec)1154 static int get_free_buf_count(struct AVS2Decoder_s *dec)
1155 {
1156 struct avs2_decoder *avs2_dec = &dec->avs2_dec;
1157 int i;
1158 int count = 0;
1159 for (i = 0; i < avs2_dec->ref_maxbuffer; i++) {
1160 if ((avs2_dec->fref[i]->imgcoi_ref < -256
1161 #if 0
1162 || abs(avs2_dec->fref[i]->
1163 imgtr_fwRefDistance - img->tr) >= 128
1164 #endif
1165 ) && avs2_dec->fref[i]->is_output == -1
1166 && avs2_dec->fref[i]->bg_flag == 0
1167 #ifndef NO_DISPLAY
1168 && avs2_dec->fref[i]->vf_ref == 0
1169 && avs2_dec->fref[i]->to_prepare_disp == 0
1170 #endif
1171 ) {
1172 count++;
1173 }
1174 }
1175
1176 return count;
1177 }
1178
1179 #ifdef CONSTRAIN_MAX_BUF_NUM
get_vf_ref_only_buf_count(struct AVS2Decoder_s * dec)1180 static int get_vf_ref_only_buf_count(struct AVS2Decoder_s *dec)
1181 {
1182 struct avs2_decoder *avs2_dec = &dec->avs2_dec;
1183 int i;
1184 int count = 0;
1185 for (i = 0; i < avs2_dec->ref_maxbuffer; i++) {
1186 if ((avs2_dec->fref[i]->imgcoi_ref < -256
1187 #if 0
1188 || abs(avs2_dec->fref[i]->
1189 imgtr_fwRefDistance - img->tr) >= 128
1190 #endif
1191 ) && avs2_dec->fref[i]->is_output == -1
1192 && avs2_dec->fref[i]->bg_flag == 0
1193 #ifndef NO_DISPLAY
1194 && avs2_dec->fref[i]->vf_ref > 0
1195 && avs2_dec->fref[i]->to_prepare_disp == 0
1196 #endif
1197 ) {
1198 count++;
1199 }
1200 }
1201
1202 return count;
1203 }
1204
get_used_buf_count(struct AVS2Decoder_s * dec)1205 static int get_used_buf_count(struct AVS2Decoder_s *dec)
1206 {
1207 struct avs2_decoder *avs2_dec = &dec->avs2_dec;
1208 int i;
1209 int count = 0;
1210 for (i = 0; i < avs2_dec->ref_maxbuffer; i++) {
1211 if ((avs2_dec->fref[i]->imgcoi_ref >= -256
1212 #if 0
1213 || abs(avs2_dec->fref[i]->
1214 imgtr_fwRefDistance - img->tr) >= 128
1215 #endif
1216 ) || avs2_dec->fref[i]->is_output != -1
1217 || avs2_dec->fref[i]->bg_flag != 0
1218 #ifndef NO_DISPLAY
1219 || avs2_dec->fref[i]->vf_ref != 0
1220 || avs2_dec->fref[i]->to_prepare_disp != 0
1221 #endif
1222 ) {
1223 count++;
1224 }
1225 }
1226
1227 return count;
1228 }
1229 #endif
1230
avs2_bufmgr_init(struct AVS2Decoder_s * dec,struct BuffInfo_s * buf_spec_i,struct buff_s * mc_buf_i)1231 int avs2_bufmgr_init(struct AVS2Decoder_s *dec, struct BuffInfo_s *buf_spec_i,
1232 struct buff_s *mc_buf_i) {
1233
1234 dec->frame_count = 0;
1235 #ifdef AVS2_10B_MMU
1236 dec->used_4k_num = -1;
1237 dec->cur_fb_idx_mmu = INVALID_IDX;
1238 #endif
1239
1240
1241 /* private init */
1242 dec->work_space_buf = buf_spec_i;
1243 #ifndef AVS2_10B_MMU
1244 dec->mc_buf = mc_buf_i;
1245 #endif
1246 dec->rpm_addr = NULL;
1247 dec->lmem_addr = NULL;
1248
1249 dec->use_cma_flag = 0;
1250 dec->decode_idx = 0;
1251 dec->slice_idx = 0;
1252 /*int m_uiMaxCUWidth = 1<<7;*/
1253 /*int m_uiMaxCUHeight = 1<<7;*/
1254 dec->wait_buf = 0;
1255 dec->error_flag = 0;
1256 dec->skip_PB_before_I = 0;
1257
1258 dec->pts_mode = PTS_NORMAL;
1259 dec->last_pts = 0;
1260 dec->last_lookup_pts = 0;
1261 dec->last_pts_us64 = 0;
1262 dec->last_lookup_pts_us64 = 0;
1263 dec->shift_byte_count = 0;
1264 dec->shift_byte_count_lo = 0;
1265 dec->shift_byte_count_hi = 0;
1266 dec->pts_mode_switching_count = 0;
1267 dec->pts_mode_recovery_count = 0;
1268
1269 dec->buf_num = 0;
1270
1271 dec->bufmgr_error_count = 0;
1272 return 0;
1273 }
1274
1275
1276
1277 #define HEVC_CM_BODY_START_ADDR 0x3626
1278 #define HEVC_CM_BODY_LENGTH 0x3627
1279 #define HEVC_CM_HEADER_LENGTH 0x3629
1280 #define HEVC_CM_HEADER_OFFSET 0x362b
1281
1282 #define LOSLESS_COMPRESS_MODE
1283
1284 /*#define DECOMP_HEADR_SURGENT*/
1285
1286 static u32 mem_map_mode; /* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
1287 static u32 enable_mem_saving = 1;
1288 static u32 force_w_h;
1289
1290 static u32 force_fps;
1291
1292
1293 const u32 avs2_version = 201602101;
1294 static u32 debug;
1295 static u32 radr;
1296 static u32 rval;
1297 static u32 pop_shorts;
1298 static u32 dbg_cmd;
1299 static u32 dbg_skip_decode_index;
1300 static u32 endian = 0xff0;
1301 #ifdef ERROR_HANDLE_DEBUG
1302 static u32 dbg_nal_skip_flag;
1303 /* bit[0], skip vps; bit[1], skip sps; bit[2], skip pps */
1304 static u32 dbg_nal_skip_count;
1305 #endif
1306 /*for debug*/
1307 static u32 decode_pic_begin;
1308 static uint slice_parse_begin;
1309 static u32 step;
1310 #ifdef MIX_STREAM_SUPPORT
1311 static u32 buf_alloc_width = 4096;
1312 static u32 buf_alloc_height = 2304;
1313
1314 static u32 dynamic_buf_num_margin;
1315 #else
1316 static u32 buf_alloc_width;
1317 static u32 buf_alloc_height;
1318 static u32 dynamic_buf_num_margin = 7;
1319 #endif
1320 #ifdef CONSTRAIN_MAX_BUF_NUM
1321 static u32 run_ready_max_vf_only_num;
1322 static u32 run_ready_display_q_num;
1323 /*0: not check
1324 0xff: avs2_dec.ref_maxbuffer
1325 */
1326 static u32 run_ready_max_buf_num = 0xff;
1327 #endif
1328 static u32 buf_alloc_depth = 10;
1329 static u32 buf_alloc_size;
1330 /*
1331 bit[0]: 0,
1332 bit[1]: 0, always release cma buffer when stop
1333 bit[1]: 1, never release cma buffer when stop
1334 bit[0]: 1, when stop, release cma buffer if blackout is 1;
1335 do not release cma buffer is blackout is not 1
1336
1337 bit[2]: 0, when start decoding, check current displayed buffer
1338 (only for buffer decoded by vp9) if blackout is 0
1339 1, do not check current displayed buffer
1340
1341 bit[3]: 1, if blackout is not 1, do not release current
1342 displayed cma buffer always.
1343 */
1344 /* set to 1 for fast play;
1345 set to 8 for other case of "keep last frame"
1346 */
1347 static u32 buffer_mode = 1;
1348 /* buffer_mode_dbg: debug only*/
1349 static u32 buffer_mode_dbg = 0xffff0000;
1350 /**/
1351
1352 /*
1353 bit 0, 1: only display I picture;
1354 bit 1, 1: only decode I picture;
1355 */
1356 static u32 i_only_flag;
1357
1358
1359 static u32 max_decoding_time;
1360 /*
1361 error handling
1362 */
1363 /*error_handle_policy:
1364 bit 0: search seq again if buffer mgr error occur
1365 (buffer mgr error count need big than
1366 re_search_seq_threshold)
1367 bit 1: 1, display from I picture;
1368 0, display from any correct pic
1369 */
1370
1371 static u32 error_handle_policy = 1;
1372 /*
1373 re_search_seq_threshold:
1374 bit 7~0: buffer mgr error research seq count
1375 bit 15~8: frame count threshold
1376 */
1377 static u32 re_search_seq_threshold = 0x800; /*0x8;*/
1378 /*static u32 parser_sei_enable = 1;*/
1379
1380 static u32 max_buf_num = (REF_BUFFER + 1);
1381
1382 static u32 run_ready_min_buf_num = 2;
1383
1384 static DEFINE_MUTEX(vavs2_mutex);
1385
1386 #define HEVC_DEC_STATUS_REG HEVC_ASSIST_SCRATCH_0
1387 #define HEVC_RPM_BUFFER HEVC_ASSIST_SCRATCH_1
1388 #define AVS2_ALF_SWAP_BUFFER HEVC_ASSIST_SCRATCH_2
1389 #define HEVC_RCS_BUFFER HEVC_ASSIST_SCRATCH_3
1390 #define HEVC_SPS_BUFFER HEVC_ASSIST_SCRATCH_4
1391 #define HEVC_PPS_BUFFER HEVC_ASSIST_SCRATCH_5
1392 #define HEVC_SAO_UP HEVC_ASSIST_SCRATCH_6
1393 #ifdef AVS2_10B_MMU
1394 #define AVS2_MMU_MAP_BUFFER HEVC_ASSIST_SCRATCH_7
1395 #else
1396 #define HEVC_STREAM_SWAP_BUFFER HEVC_ASSIST_SCRATCH_7
1397 #endif
1398 #define HEVC_STREAM_SWAP_BUFFER2 HEVC_ASSIST_SCRATCH_8
1399 /*
1400 #define VP9_PROB_SWAP_BUFFER HEVC_ASSIST_SCRATCH_9
1401 #define VP9_COUNT_SWAP_BUFFER HEVC_ASSIST_SCRATCH_A
1402 #define VP9_SEG_MAP_BUFFER HEVC_ASSIST_SCRATCH_B
1403 */
1404 #define HEVC_SCALELUT HEVC_ASSIST_SCRATCH_D
1405 #define HEVC_WAIT_FLAG HEVC_ASSIST_SCRATCH_E
1406 #define RPM_CMD_REG HEVC_ASSIST_SCRATCH_F
1407 #define LMEM_DUMP_ADR HEVC_ASSIST_SCRATCH_9
1408 #define HEVC_STREAM_SWAP_TEST HEVC_ASSIST_SCRATCH_L
1409 /*!!!*/
1410 #define HEVC_DECODE_COUNT HEVC_ASSIST_SCRATCH_M
1411 #define HEVC_DECODE_SIZE HEVC_ASSIST_SCRATCH_N
1412 #define DEBUG_REG1 HEVC_ASSIST_SCRATCH_G
1413 #define DEBUG_REG2 HEVC_ASSIST_SCRATCH_H
1414
1415
1416 /*
1417 ucode parser/search control
1418 bit 0: 0, header auto parse; 1, header manual parse
1419 bit 1: 0, auto skip for noneseamless stream; 1, no skip
1420 bit [3:2]: valid when bit1==0;
1421 0, auto skip nal before first vps/sps/pps/idr;
1422 1, auto skip nal before first vps/sps/pps
1423 2, auto skip nal before first vps/sps/pps,
1424 and not decode until the first I slice (with slice address of 0)
1425
1426 3, auto skip before first I slice (nal_type >=16 && nal_type<=21)
1427 bit [15:4] nal skip count (valid when bit0 == 1 (manual mode) )
1428 bit [16]: for NAL_UNIT_EOS when bit0 is 0:
1429 0, send SEARCH_DONE to arm ; 1, do not send SEARCH_DONE to arm
1430 bit [17]: for NAL_SEI when bit0 is 0:
1431 0, do not parse SEI in ucode; 1, parse SEI in ucode
1432 bit [31:20]: used by ucode for debug purpose
1433 */
1434 #define NAL_SEARCH_CTL HEVC_ASSIST_SCRATCH_I
1435 /*DECODE_MODE: set before start decoder
1436 bit 7~0: decode mode
1437 bit 23~16: start_decoding_flag
1438 bit [0] - SEQ_ready
1439 bit [2:1] - I Picture Count
1440 bit 31~24: chip feature
1441 */
1442 #define DECODE_MODE HEVC_ASSIST_SCRATCH_J
1443 #define DECODE_STOP_POS HEVC_ASSIST_SCRATCH_K
1444 /*read only*/
1445 #define CUR_NAL_UNIT_TYPE HEVC_ASSIST_SCRATCH_J
1446
1447 #define RPM_BUF_SIZE (0x600 * 2)
1448 #define LMEM_BUF_SIZE (0x600 * 2)
1449
1450 #define WORK_BUF_SPEC_NUM 3
1451 static struct BuffInfo_s amvavs2_workbuff_spec[WORK_BUF_SPEC_NUM] = {
1452 {
1453 /* 8M bytes */
1454 .max_width = 1920,
1455 .max_height = 1088,
1456 .ipp = {
1457 /* IPP work space calculation :
1458 4096 * (Y+CbCr+Flags) = 12k, round to 16k */
1459 .buf_size = 0x4000,
1460 },
1461 .sao_abv = {
1462 .buf_size = 0x30000,
1463 },
1464 .sao_vb = {
1465 .buf_size = 0x30000,
1466 },
1467 .short_term_rps = {
1468 /* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
1469 total 64x16x2 = 2048 bytes (0x800) */
1470 .buf_size = 0x800,
1471 },
1472 .rcs = {
1473 /* RCS STORE AREA - Max 32 RCS, each has 32 bytes,
1474 total 0x0400 bytes */
1475 .buf_size = 0x400,
1476 },
1477 .sps = {
1478 /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
1479 total 0x0800 bytes*/
1480 .buf_size = 0x800,
1481 },
1482 .pps = {
1483 /*PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
1484 total 0x2000 bytes*/
1485 .buf_size = 0x2000,
1486 },
1487 .sao_up = {
1488 /* SAO UP STORE AREA - Max 640(10240/16) LCU,
1489 each has 16 bytes total 0x2800 bytes */
1490 .buf_size = 0x2800,
1491 },
1492 .swap_buf = {
1493 /* 256cyclex64bit = 2K bytes 0x800
1494 (only 144 cycles valid) */
1495 .buf_size = 0x800,
1496 },
1497 .swap_buf2 = {
1498 .buf_size = 0x800,
1499 },
1500 .scalelut = {
1501 /* support up to 32 SCALELUT 1024x32 =
1502 32Kbytes (0x8000) */
1503 .buf_size = 0x8000,
1504 },
1505 .dblk_para = {
1506 /* DBLK -> Max 256(4096/16) LCU,
1507 each para 1024bytes(total:0x40000),
1508 data 1024bytes(total:0x40000)*/
1509 .buf_size = 0x40000,
1510 },
1511 .dblk_data = {
1512 .buf_size = 0x40000,
1513 },
1514 .dblk_data2 = {
1515 .buf_size = 0x40000,
1516 },
1517 #ifdef AVS2_10B_MMU
1518 .mmu_vbh = {
1519 .buf_size = 0x5000, /*2*16*(more than 2304)/4, 4K*/
1520 },
1521 #if 0
1522 .cm_header = {
1523 /*add one for keeper.*/
1524 .buf_size = MMU_COMPRESS_HEADER_SIZE *
1525 (FRAME_BUFFERS + 1),
1526 /* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */
1527 },
1528 #endif
1529 #endif
1530 .mpred_above = {
1531 .buf_size = 0x8000, /* 2 * size of hevc*/
1532 },
1533 #ifdef MV_USE_FIXED_BUF
1534 .mpred_mv = {/* 1080p, 0x40000 per buffer */
1535 .buf_size = 0x40000 * FRAME_BUFFERS,
1536 },
1537 #endif
1538 .rpm = {
1539 .buf_size = RPM_BUF_SIZE,
1540 },
1541 .lmem = {
1542 .buf_size = 0x400 * 2,
1543 }
1544 },
1545 {
1546 .max_width = 4096,
1547 .max_height = 2304,
1548 .ipp = {
1549 /* IPP work space calculation :
1550 4096 * (Y+CbCr+Flags) = 12k, round to 16k */
1551 .buf_size = 0x4000,
1552 },
1553 .sao_abv = {
1554 .buf_size = 0x30000,
1555 },
1556 .sao_vb = {
1557 .buf_size = 0x30000,
1558 },
1559 .short_term_rps = {
1560 /* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
1561 total 64x16x2 = 2048 bytes (0x800) */
1562 .buf_size = 0x800,
1563 },
1564 .rcs = {
1565 /* RCS STORE AREA - Max 16 RCS, each has 32 bytes,
1566 total 0x0400 bytes */
1567 .buf_size = 0x400,
1568 },
1569 .sps = {
1570 /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
1571 total 0x0800 bytes */
1572 .buf_size = 0x800,
1573 },
1574 .pps = {
1575 /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
1576 total 0x2000 bytes */
1577 .buf_size = 0x2000,
1578 },
1579 .sao_up = {
1580 /* SAO UP STORE AREA - Max 640(10240/16) LCU,
1581 each has 16 bytes total 0x2800 bytes */
1582 .buf_size = 0x2800,
1583 },
1584 .swap_buf = {
1585 /* 256cyclex64bit = 2K bytes 0x800
1586 (only 144 cycles valid) */
1587 .buf_size = 0x800,
1588 },
1589 .swap_buf2 = {
1590 .buf_size = 0x800,
1591 },
1592 .scalelut = {
1593 /* support up to 32 SCALELUT 1024x32 = 32Kbytes
1594 (0x8000) */
1595 .buf_size = 0x8000,
1596 },
1597 .dblk_para = {
1598 /* DBLK -> Max 256(4096/16) LCU,
1599 each para 1024bytes(total:0x40000),
1600 data 1024bytes(total:0x40000)*/
1601 .buf_size = 0x80000,
1602 },
1603 .dblk_data = {
1604 /*DBLK -> Max 256(4096/16) LCU,
1605 each para 1024bytes(total:0x40000),
1606 data 1024bytes(total:0x40000)*/
1607 .buf_size = 0x80000,
1608 },
1609 .dblk_data2 = {
1610 .buf_size = 0x80000,
1611 },
1612 #ifdef AVS2_10B_MMU
1613 .mmu_vbh = {
1614 .buf_size = 0x5000,/*2*16*(more than 2304)/4, 4K*/
1615 },
1616 #if 0
1617 .cm_header = {
1618 /*add one for keeper.*/
1619 .buf_size = MMU_COMPRESS_HEADER_SIZE *
1620 (FRAME_BUFFERS + 1),
1621 /* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */
1622 },
1623 #endif
1624 #endif
1625 .mpred_above = {
1626 .buf_size = 0x10000, /* 2 * size of hevc*/
1627 },
1628 #ifdef MV_USE_FIXED_BUF
1629 .mpred_mv = {
1630 /* .buf_size = 0x100000*16,
1631 //4k2k , 0x100000 per buffer */
1632 /* 4096x2304 , 0x120000 per buffer */
1633 .buf_size = 0x120000 * FRAME_BUFFERS,
1634 },
1635 #endif
1636 .rpm = {
1637 .buf_size = RPM_BUF_SIZE,
1638 },
1639 .lmem = {
1640 .buf_size = 0x400 * 2,
1641 }
1642 },
1643 {
1644 .max_width = 4096 * 2,
1645 .max_height = 2304 * 2,
1646 .ipp = {
1647 /*IPP work space calculation : 4096 * (Y+CbCr+Flags) = 12k,
1648 round to 16k*/
1649 .buf_size = 0x4000 * 2,
1650 },
1651 .sao_abv = {
1652 .buf_size = 0x30000 * 2,
1653 },
1654 .sao_vb = {
1655 .buf_size = 0x30000 * 2,
1656 },
1657 .short_term_rps = {
1658 /*SHORT_TERM_RPS - Max 64 set, 16 entry every set,
1659 total 64x16x2 = 2048 bytes (0x800)*/
1660 .buf_size = 0x800,
1661 },
1662 .rcs = {
1663 /*RCS STORE AREA - Max 16 RCS, each has 32 bytes,
1664 total 0x0400 bytes*/
1665 .buf_size = 0x400,
1666 },
1667 .sps = {
1668 /*SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
1669 total 0x0800 bytes*/
1670 .buf_size = 0x800,
1671 },
1672 .pps = {
1673 /*PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, total
1674 0x2000 bytes*/
1675 .buf_size = 0x2000,
1676 },
1677 .sao_up = {
1678 /*SAO UP STORE AREA - Max 640(10240/16) LCU, each has 16 bytes i
1679 total 0x2800 bytes*/
1680 .buf_size = 0x2800 * 2,
1681 },
1682 .swap_buf = {
1683 /*256cyclex64bit = 2K bytes 0x800 (only 144 cycles valid)*/
1684 .buf_size = 0x800,
1685 },
1686 .swap_buf2 = {
1687 .buf_size = 0x800,
1688 },
1689 .scalelut = {
1690 /*support up to 32 SCALELUT 1024x32 = 32Kbytes (0x8000)*/
1691 .buf_size = 0x8000 * 2,
1692 },
1693 .dblk_para = {
1694 .buf_size = 0x40000 * 2,
1695 },
1696 .dblk_data = {
1697 .buf_size = 0x80000 * 2,
1698 },
1699 .dblk_data2 = {
1700 .buf_size = 0x80000 * 2,
1701 },
1702 #ifdef AVS2_10B_MMU
1703 .mmu_vbh = {
1704 .buf_size = 0x5000 * 2, /*2*16*2304/4, 4K*/
1705 },
1706 #if 0
1707 .cm_header = {
1708 /*0x44000 = ((1088*2*1024*4)/32/4)*(32/8)*/
1709 .buf_size = MMU_COMPRESS_8K_HEADER_SIZE * 17,
1710 },
1711 #endif
1712 #endif
1713 .mpred_above = {
1714 .buf_size = 0x8000 * 2,
1715 },
1716 #ifdef MV_USE_FIXED_BUF
1717 .mpred_mv = {
1718 /*4k2k , 0x100000 per buffer*/
1719 .buf_size = 0x120000 * FRAME_BUFFERS * 4,
1720 },
1721 #endif
1722 .rpm = {
1723 .buf_size = RPM_BUF_SIZE,
1724 },
1725 .lmem = {
1726 .buf_size = 0x400 * 2,
1727 }
1728 }
1729 };
1730
1731
1732 /*Losless compression body buffer size 4K per 64x32 (jt)*/
compute_losless_comp_body_size(struct AVS2Decoder_s * dec,int width,int height,uint8_t is_bit_depth_10)1733 static int compute_losless_comp_body_size(struct AVS2Decoder_s *dec,
1734 int width, int height,
1735 uint8_t is_bit_depth_10)
1736 {
1737 int width_x64;
1738 int height_x32;
1739 int bsize;
1740 width_x64 = width + 63;
1741 width_x64 >>= 6;
1742 height_x32 = height + 31;
1743 height_x32 >>= 5;
1744 #ifdef AVS2_10B_MMU
1745 bsize = (is_bit_depth_10 ? 4096 : 3200)
1746 * width_x64 * height_x32;
1747 #else
1748 bsize = (is_bit_depth_10 ? 4096 : 3072)
1749 * width_x64 * height_x32;
1750 #endif
1751 avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
1752 "%s(%d,%d,%d)=>%d\n",
1753 __func__, width, height,
1754 is_bit_depth_10, bsize);
1755
1756 return bsize;
1757 }
1758
1759 /* Losless compression header buffer size 32bytes per 128x64 (jt)*/
compute_losless_comp_header_size(struct AVS2Decoder_s * dec,int width,int height)1760 static int compute_losless_comp_header_size(struct AVS2Decoder_s *dec,
1761 int width, int height)
1762 {
1763 int width_x128;
1764 int height_x64;
1765 int hsize;
1766 width_x128 = width + 127;
1767 width_x128 >>= 7;
1768 height_x64 = height + 63;
1769 height_x64 >>= 6;
1770
1771 hsize = 32 * width_x128 * height_x64;
1772 avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
1773 "%s(%d,%d)=>%d\n",
1774 __func__, width, height,
1775 hsize);
1776
1777 return hsize;
1778 }
1779
init_buff_spec(struct AVS2Decoder_s * dec,struct BuffInfo_s * buf_spec)1780 static void init_buff_spec(struct AVS2Decoder_s *dec,
1781 struct BuffInfo_s *buf_spec)
1782 {
1783 void *mem_start_virt;
1784 buf_spec->ipp.buf_start = buf_spec->start_adr;
1785 buf_spec->sao_abv.buf_start =
1786 buf_spec->ipp.buf_start + buf_spec->ipp.buf_size;
1787
1788 buf_spec->sao_vb.buf_start =
1789 buf_spec->sao_abv.buf_start + buf_spec->sao_abv.buf_size;
1790 buf_spec->short_term_rps.buf_start =
1791 buf_spec->sao_vb.buf_start + buf_spec->sao_vb.buf_size;
1792 buf_spec->rcs.buf_start =
1793 buf_spec->short_term_rps.buf_start +
1794 buf_spec->short_term_rps.buf_size;
1795 buf_spec->sps.buf_start =
1796 buf_spec->rcs.buf_start + buf_spec->rcs.buf_size;
1797 buf_spec->pps.buf_start =
1798 buf_spec->sps.buf_start + buf_spec->sps.buf_size;
1799 buf_spec->sao_up.buf_start =
1800 buf_spec->pps.buf_start + buf_spec->pps.buf_size;
1801 buf_spec->swap_buf.buf_start =
1802 buf_spec->sao_up.buf_start + buf_spec->sao_up.buf_size;
1803 buf_spec->swap_buf2.buf_start =
1804 buf_spec->swap_buf.buf_start + buf_spec->swap_buf.buf_size;
1805 buf_spec->scalelut.buf_start =
1806 buf_spec->swap_buf2.buf_start + buf_spec->swap_buf2.buf_size;
1807 buf_spec->dblk_para.buf_start =
1808 buf_spec->scalelut.buf_start + buf_spec->scalelut.buf_size;
1809 buf_spec->dblk_data.buf_start =
1810 buf_spec->dblk_para.buf_start + buf_spec->dblk_para.buf_size;
1811 buf_spec->dblk_data2.buf_start =
1812 buf_spec->dblk_data.buf_start + buf_spec->dblk_data.buf_size;
1813 #ifdef AVS2_10B_MMU
1814 buf_spec->mmu_vbh.buf_start =
1815 buf_spec->dblk_data2.buf_start + buf_spec->dblk_data2.buf_size;
1816 buf_spec->mpred_above.buf_start =
1817 buf_spec->mmu_vbh.buf_start + buf_spec->mmu_vbh.buf_size;
1818 #else
1819 buf_spec->mpred_above.buf_start =
1820 buf_spec->dblk_data2.buf_start + buf_spec->dblk_data2.buf_size;
1821 #endif
1822 #ifdef MV_USE_FIXED_BUF
1823 buf_spec->mpred_mv.buf_start =
1824 buf_spec->mpred_above.buf_start +
1825 buf_spec->mpred_above.buf_size;
1826
1827 buf_spec->rpm.buf_start =
1828 buf_spec->mpred_mv.buf_start +
1829 buf_spec->mpred_mv.buf_size;
1830 #else
1831 buf_spec->rpm.buf_start =
1832 buf_spec->mpred_above.buf_start +
1833 buf_spec->mpred_above.buf_size;
1834
1835 #endif
1836 buf_spec->lmem.buf_start =
1837 buf_spec->rpm.buf_start +
1838 buf_spec->rpm.buf_size;
1839 buf_spec->end_adr =
1840 buf_spec->lmem.buf_start +
1841 buf_spec->lmem.buf_size;
1842
1843 if (dec) {
1844 mem_start_virt =
1845 codec_mm_phys_to_virt(buf_spec->dblk_para.buf_start);
1846 if (mem_start_virt) {
1847 memset(mem_start_virt, 0, buf_spec->dblk_para.buf_size);
1848 codec_mm_dma_flush(mem_start_virt,
1849 buf_spec->dblk_para.buf_size,
1850 DMA_TO_DEVICE);
1851 } else {
1852 /*not virt for tvp playing,
1853 may need clear on ucode.*/
1854 pr_err("mem_start_virt failed\n");
1855 }
1856 if (debug) {
1857 pr_info("%s workspace (%x %x) size = %x\n", __func__,
1858 buf_spec->start_adr, buf_spec->end_adr,
1859 buf_spec->end_adr - buf_spec->start_adr);
1860 }
1861 if (debug) {
1862 pr_info("ipp.buf_start :%x\n",
1863 buf_spec->ipp.buf_start);
1864 pr_info("sao_abv.buf_start :%x\n",
1865 buf_spec->sao_abv.buf_start);
1866 pr_info("sao_vb.buf_start :%x\n",
1867 buf_spec->sao_vb.buf_start);
1868 pr_info("short_term_rps.buf_start :%x\n",
1869 buf_spec->short_term_rps.buf_start);
1870 pr_info("rcs.buf_start :%x\n",
1871 buf_spec->rcs.buf_start);
1872 pr_info("sps.buf_start :%x\n",
1873 buf_spec->sps.buf_start);
1874 pr_info("pps.buf_start :%x\n",
1875 buf_spec->pps.buf_start);
1876 pr_info("sao_up.buf_start :%x\n",
1877 buf_spec->sao_up.buf_start);
1878 pr_info("swap_buf.buf_start :%x\n",
1879 buf_spec->swap_buf.buf_start);
1880 pr_info("swap_buf2.buf_start :%x\n",
1881 buf_spec->swap_buf2.buf_start);
1882 pr_info("scalelut.buf_start :%x\n",
1883 buf_spec->scalelut.buf_start);
1884 pr_info("dblk_para.buf_start :%x\n",
1885 buf_spec->dblk_para.buf_start);
1886 pr_info("dblk_data.buf_start :%x\n",
1887 buf_spec->dblk_data.buf_start);
1888 pr_info("dblk_data2.buf_start :%x\n",
1889 buf_spec->dblk_data2.buf_start);
1890 #ifdef AVS2_10B_MMU
1891 pr_info("mmu_vbh.buf_start :%x\n",
1892 buf_spec->mmu_vbh.buf_start);
1893 #endif
1894 pr_info("mpred_above.buf_start :%x\n",
1895 buf_spec->mpred_above.buf_start);
1896 #ifdef MV_USE_FIXED_BUF
1897 pr_info("mpred_mv.buf_start :%x\n",
1898 buf_spec->mpred_mv.buf_start);
1899 #endif
1900 if ((debug & AVS2_DBG_SEND_PARAM_WITH_REG) == 0) {
1901 pr_info("rpm.buf_start :%x\n",
1902 buf_spec->rpm.buf_start);
1903 }
1904 }
1905 }
1906
1907 }
1908
uninit_mmu_buffers(struct AVS2Decoder_s * dec)1909 static void uninit_mmu_buffers(struct AVS2Decoder_s *dec)
1910 {
1911 #if 0
1912 /*ndef MV_USE_FIXED_BUF*/
1913 dealloc_mv_bufs(dec);
1914 #endif
1915 decoder_mmu_box_free(dec->mmu_box);
1916 dec->mmu_box = NULL;
1917
1918 if (dec->bmmu_box)
1919 decoder_bmmu_box_free(dec->bmmu_box);
1920 dec->bmmu_box = NULL;
1921 }
1922
1923 #ifndef AVS2_10B_MMU
init_buf_list(struct AVS2Decoder_s * dec)1924 static void init_buf_list(struct AVS2Decoder_s *dec)
1925 {
1926 int i;
1927 int buf_size;
1928 int mc_buffer_end = dec->mc_buf->buf_start + dec->mc_buf->buf_size;
1929 dec->used_buf_num = max_buf_num;
1930
1931 if (dec->used_buf_num > MAX_BUF_NUM)
1932 dec->used_buf_num = MAX_BUF_NUM;
1933 if (buf_alloc_size > 0) {
1934 buf_size = buf_alloc_size;
1935 avs2_print(dec, AVS2_DBG_BUFMGR,
1936 "[Buffer Management] init_buf_list:\n");
1937 } else {
1938 int pic_width = dec->init_pic_w;
1939 int pic_height = dec->init_pic_h;
1940
1941 /*SUPPORT_10BIT*/
1942 int losless_comp_header_size = compute_losless_comp_header_size
1943 (dec, pic_width, pic_height);
1944 int losless_comp_body_size = compute_losless_comp_body_size
1945 (dec, pic_width, pic_height, buf_alloc_depth == 10);
1946 int mc_buffer_size = losless_comp_header_size
1947 + losless_comp_body_size;
1948 int mc_buffer_size_h = (mc_buffer_size + 0xffff)>>16;
1949
1950 int dw_mode = get_double_write_mode_init(dec);
1951
1952 if (dw_mode) {
1953 int pic_width_dw = pic_width /
1954 get_double_write_ratio(dec, dw_mode);
1955 int pic_height_dw = pic_height /
1956 get_double_write_ratio(dec, dw_mode);
1957 int lcu_size = 64; /*fixed 64*/
1958 int pic_width_64 = (pic_width_dw + 63) & (~0x3f);
1959 int pic_height_32 = (pic_height_dw + 31) & (~0x1f);
1960 int pic_width_lcu =
1961 (pic_width_64 % lcu_size) ? pic_width_64 / lcu_size
1962 + 1 : pic_width_64 / lcu_size;
1963 int pic_height_lcu =
1964 (pic_height_32 % lcu_size) ? pic_height_32 / lcu_size
1965 + 1 : pic_height_32 / lcu_size;
1966 int lcu_total = pic_width_lcu * pic_height_lcu;
1967 int mc_buffer_size_u_v = lcu_total * lcu_size * lcu_size / 2;
1968 int mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16;
1969 /*64k alignment*/
1970 buf_size = ((mc_buffer_size_u_v_h << 16) * 3);
1971 } else
1972 buf_size = 0;
1973
1974 if (mc_buffer_size & 0xffff) { /*64k alignment*/
1975 mc_buffer_size_h += 1;
1976 }
1977 if ((dw_mode & 0x10) == 0)
1978 buf_size += (mc_buffer_size_h << 16);
1979 avs2_print(dec, AVS2_DBG_BUFMGR,
1980 "init_buf_list num %d (width %d height %d):\n",
1981 dec->used_buf_num, pic_width, pic_height);
1982 }
1983
1984 for (i = 0; i < dec->used_buf_num; i++) {
1985 if (((i + 1) * buf_size) > dec->mc_buf->buf_size)
1986 dec->use_cma_flag = 1;
1987 #ifndef AVS2_10B_MMU
1988 dec->m_BUF[i].alloc_flag = 0;
1989 dec->m_BUF[i].index = i;
1990
1991 dec->use_cma_flag = 1;
1992 if (dec->use_cma_flag) {
1993 dec->m_BUF[i].cma_page_count =
1994 PAGE_ALIGN(buf_size) / PAGE_SIZE;
1995 if (decoder_bmmu_box_alloc_buf_phy(dec->bmmu_box,
1996 VF_BUFFER_IDX(i), buf_size, DRIVER_NAME,
1997 &dec->m_BUF[i].alloc_addr) < 0) {
1998 dec->m_BUF[i].cma_page_count = 0;
1999 if (i <= 5) {
2000 dec->fatal_error |=
2001 DECODER_FATAL_ERROR_NO_MEM;
2002 }
2003 break;
2004 }
2005 dec->m_BUF[i].start_adr = dec->m_BUF[i].alloc_addr;
2006 } else {
2007 dec->m_BUF[i].cma_page_count = 0;
2008 dec->m_BUF[i].alloc_addr = 0;
2009 dec->m_BUF[i].start_adr =
2010 dec->mc_buf->buf_start + i * buf_size;
2011 }
2012 dec->m_BUF[i].size = buf_size;
2013 dec->m_BUF[i].free_start_adr = dec->m_BUF[i].start_adr;
2014
2015 if (((dec->m_BUF[i].start_adr + buf_size) > mc_buffer_end)
2016 && (dec->m_BUF[i].alloc_addr == 0)) {
2017 if (debug) {
2018 avs2_print(dec, 0,
2019 "Max mc buffer or mpred_mv buffer is used\n");
2020 }
2021 break;
2022 }
2023
2024 avs2_print(dec, AVS2_DBG_BUFMGR,
2025 "Buffer %d: start_adr %p size %x\n", i,
2026 (void *)dec->m_BUF[i].start_adr,
2027 dec->m_BUF[i].size);
2028 #endif
2029 }
2030 dec->buf_num = i;
2031 }
2032 #endif
2033
config_pic(struct AVS2Decoder_s * dec,struct avs2_frame_s * pic,int32_t lcu_size_log2)2034 static int config_pic(struct AVS2Decoder_s *dec,
2035 struct avs2_frame_s *pic, int32_t lcu_size_log2)
2036 {
2037 int ret = -1;
2038 int i;
2039 int pic_width = dec->init_pic_w;
2040 int pic_height = dec->init_pic_h;
2041 /*struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2042 int32_t lcu_size_log2 = avs2_dec->lcu_size_log2;*/
2043 int32_t lcu_size = 1 << lcu_size_log2;
2044 int pic_width_64 = (pic_width + 63) & (~0x3f);
2045 int pic_height_32 = (pic_height + 31) & (~0x1f);
2046 int pic_width_lcu = (pic_width_64 % lcu_size) ?
2047 pic_width_64 / lcu_size + 1
2048 : pic_width_64 / lcu_size;
2049 int pic_height_lcu = (pic_height_32 % lcu_size) ?
2050 pic_height_32 / lcu_size + 1
2051 : pic_height_32 / lcu_size;
2052 int lcu_total = pic_width_lcu * pic_height_lcu;
2053 #if 0
2054 int32_t MV_MEM_UNIT =
2055 (lcu_size_log2 == 6) ? 0x200 :
2056 ((lcu_size_log2 == 5) ? 0x80 : 0x20);
2057 #endif
2058 #ifdef MV_USE_FIXED_BUF
2059 u32 mpred_mv_end = dec->work_space_buf->mpred_mv.buf_start +
2060 dec->work_space_buf->mpred_mv.buf_size;
2061 #endif
2062 u32 y_adr = 0;
2063 int buf_size = 0;
2064
2065 int losless_comp_header_size =
2066 compute_losless_comp_header_size(
2067 dec, pic_width, pic_height);
2068 int losless_comp_body_size = compute_losless_comp_body_size(
2069 dec, pic_width,
2070 pic_height, buf_alloc_depth == 10);
2071 int mc_buffer_size = losless_comp_header_size + losless_comp_body_size;
2072 int mc_buffer_size_h = (mc_buffer_size + 0xffff) >> 16;
2073 int mc_buffer_size_u_v = 0;
2074 int mc_buffer_size_u_v_h = 0;
2075 int dw_mode = get_double_write_mode_init(dec);
2076
2077 if (dw_mode) {
2078 int pic_width_dw = pic_width /
2079 get_double_write_ratio(dec, dw_mode);
2080 int pic_height_dw = pic_height /
2081 get_double_write_ratio(dec, dw_mode);
2082 int pic_width_64_dw = (pic_width_dw + 63) & (~0x3f);
2083 int pic_height_32_dw = (pic_height_dw + 31) & (~0x1f);
2084 int pic_width_lcu_dw = (pic_width_64_dw % lcu_size) ?
2085 pic_width_64_dw / lcu_size + 1
2086 : pic_width_64_dw / lcu_size;
2087 int pic_height_lcu_dw = (pic_height_32_dw % lcu_size) ?
2088 pic_height_32_dw / lcu_size + 1
2089 : pic_height_32_dw / lcu_size;
2090 int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
2091
2092 mc_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
2093 mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16;
2094 /*64k alignment*/
2095 buf_size = ((mc_buffer_size_u_v_h << 16) * 3);
2096 buf_size = ((buf_size + 0xffff) >> 16) << 16;
2097 }
2098 if (mc_buffer_size & 0xffff) /*64k alignment*/
2099 mc_buffer_size_h += 1;
2100 #ifndef AVS2_10B_MMU
2101 if ((dw_mode & 0x10) == 0)
2102 buf_size += (mc_buffer_size_h << 16);
2103 #endif
2104
2105 #ifdef AVS2_10B_MMU
2106 #ifndef DYNAMIC_ALLOC_HEAD
2107 pic->header_adr = decoder_bmmu_box_get_phy_addr(
2108 dec->bmmu_box, HEADER_BUFFER_IDX(pic->index));
2109
2110 avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
2111 "buf_size %d, MMU header_adr %d: %ld\n",
2112 buf_size, pic->index, pic->header_adr);
2113 #endif
2114 #endif
2115
2116 i = pic->index;
2117 #ifdef MV_USE_FIXED_BUF
2118 #ifdef G12A_BRINGUP_DEBUG
2119 if (1) {
2120 #else
2121 if ((dec->work_space_buf->mpred_mv.buf_start +
2122 (((i + 1) * lcu_total) * MV_MEM_UNIT))
2123 <= mpred_mv_end
2124 ) {
2125 #endif
2126 #endif
2127 #ifndef AVS2_10B_MMU
2128 if (debug) {
2129 pr_err("start %x .size=%d\n",
2130 dec->mc_buf_spec.buf_start + i * buf_size,
2131 buf_size);
2132 }
2133 #endif
2134 #ifndef AVS2_10B_MMU
2135 for (i = 0; i < dec->buf_num; i++) {
2136 y_adr = ((dec->m_BUF[i].free_start_adr
2137 + 0xffff) >> 16) << 16;
2138 /*64k alignment*/
2139 if ((y_adr+buf_size) <= (dec->m_BUF[i].start_adr+
2140 dec->m_BUF[i].size)) {
2141 dec->m_BUF[i].free_start_adr =
2142 y_adr + buf_size;
2143 break;
2144 }
2145 }
2146 if (i < dec->buf_num)
2147 #else
2148 /*if ((dec->mc_buf->buf_start + (i + 1) * buf_size) <
2149 dec->mc_buf->buf_end)
2150 y_adr = dec->mc_buf->buf_start + i * buf_size;
2151 else {*/
2152 if (buf_size > 0 && pic->cma_alloc_addr == 0) {
2153 ret = decoder_bmmu_box_alloc_buf_phy(dec->bmmu_box,
2154 VF_BUFFER_IDX(i),
2155 buf_size, DRIVER_NAME,
2156 &pic->cma_alloc_addr);
2157 if (ret < 0) {
2158 avs2_print(dec, 0,
2159 "decoder_bmmu_box_alloc_buf_phy idx %d size %d fail\n",
2160 VF_BUFFER_IDX(i),
2161 buf_size
2162 );
2163 return ret;
2164 }
2165
2166 if (pic->cma_alloc_addr)
2167 y_adr = pic->cma_alloc_addr;
2168 else {
2169 avs2_print(dec, 0,
2170 "decoder_bmmu_box_alloc_buf_phy idx %d size %d return null\n",
2171 VF_BUFFER_IDX(i),
2172 buf_size
2173 );
2174 return -1;
2175 }
2176 }
2177 #endif
2178 {
2179 /*ensure get_pic_by_POC()
2180 not get the buffer not decoded*/
2181 pic->BUF_index = i;
2182 pic->lcu_total = lcu_total;
2183
2184 pic->comp_body_size = losless_comp_body_size;
2185 pic->buf_size = buf_size;
2186 #ifndef AVS2_10B_MMU
2187 pic->mc_y_adr = y_adr;
2188 #endif
2189 pic->mc_canvas_y = pic->index;
2190 pic->mc_canvas_u_v = pic->index;
2191 #ifndef AVS2_10B_MMU
2192 if (dw_mode & 0x10) {
2193 pic->mc_u_v_adr = y_adr +
2194 ((mc_buffer_size_u_v_h << 16) << 1);
2195
2196 pic->mc_canvas_y =
2197 (pic->index << 1);
2198 pic->mc_canvas_u_v =
2199 (pic->index << 1) + 1;
2200
2201 pic->dw_y_adr = y_adr;
2202 pic->dw_u_v_adr = pic->mc_u_v_adr;
2203 } else
2204 #endif
2205 if (dw_mode) {
2206 pic->dw_y_adr = y_adr
2207 #ifndef AVS2_10B_MMU
2208 + (mc_buffer_size_h << 16)
2209 #endif
2210 ;
2211 pic->dw_u_v_adr = pic->dw_y_adr +
2212 ((mc_buffer_size_u_v_h << 16) << 1);
2213 #ifdef AVS2_10B_MMU
2214 pic->mc_y_adr = pic->dw_y_adr;
2215 pic->mc_u_v_adr = pic->dw_u_v_adr;
2216 #endif
2217 }
2218 #ifdef MV_USE_FIXED_BUF
2219 #ifdef G12A_BRINGUP_DEBUG
2220 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
2221 pic->mpred_mv_wr_start_addr =
2222 dec->work_space_buf->mpred_mv.buf_start +
2223 (pic->index * 0x120000 * 4);
2224 } else {
2225 pic->mpred_mv_wr_start_addr =
2226 dec->work_space_buf->mpred_mv.buf_start +
2227 (pic->index * 0x120000);
2228 }
2229 #else
2230 pic->mpred_mv_wr_start_addr =
2231 dec->work_space_buf->mpred_mv.buf_start +
2232 ((pic->index * lcu_total)
2233 * MV_MEM_UNIT);
2234 #endif
2235 #endif
2236 if (debug) {
2237 avs2_print(dec, AVS2_DBG_BUFMGR,
2238 "%s index %d BUF_index %d mc_y_adr %x ",
2239 __func__, pic->index,
2240 pic->BUF_index,
2241 pic->mc_y_adr);
2242 avs2_print_cont(dec, AVS2_DBG_BUFMGR,
2243 "comp_body_size %x comp_buf_size %x ",
2244 pic->comp_body_size,
2245 pic->buf_size);
2246 avs2_print_cont(dec, AVS2_DBG_BUFMGR,
2247 "mpred_mv_wr_start_adr %d\n",
2248 pic->mpred_mv_wr_start_addr);
2249 avs2_print_cont(dec, AVS2_DBG_BUFMGR,
2250 "dw_y_adr %d, pic->dw_u_v_adr =%d\n",
2251 pic->dw_y_adr,
2252 pic->dw_u_v_adr);
2253 }
2254 ret = 0;
2255 }
2256 #ifdef MV_USE_FIXED_BUF
2257 } else {
2258 avs2_print(dec, 0,
2259 "mv buffer alloc fail %x > %x\n",
2260 dec->work_space_buf->mpred_mv.buf_start +
2261 (((i + 1) * lcu_total) * MV_MEM_UNIT),
2262 mpred_mv_end);
2263 }
2264 #endif
2265 return ret;
2266 }
2267
2268 static void init_pic_list(struct AVS2Decoder_s *dec,
2269 int32_t lcu_size_log2)
2270 {
2271 int i;
2272 struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2273 struct avs2_frame_s *pic;
2274 #ifdef AVS2_10B_MMU
2275 unsigned long buf_addr1;
2276 /*alloc AVS2 compress header first*/
2277 if (decoder_bmmu_box_alloc_buf_phy
2278 (dec->bmmu_box,
2279 HEADER_BUFFER_IDX(-1), get_compress_header_size(dec),
2280 DRIVER_HEADER_NAME,
2281 &buf_addr1) < 0){
2282 avs2_print(dec, 0,
2283 "%s malloc compress header failed %d\n",
2284 DRIVER_HEADER_NAME, -1);
2285 dec->fatal_error |= DECODER_FATAL_ERROR_NO_MEM;
2286 return;
2287 }
2288 #ifndef DYNAMIC_ALLOC_HEAD
2289 for (i = 0; i < dec->used_buf_num; i++) {
2290 unsigned long buf_addr;
2291 if (decoder_bmmu_box_alloc_buf_phy
2292 (dec->bmmu_box,
2293 HEADER_BUFFER_IDX(i), get_compress_header_size(dec),
2294 DRIVER_HEADER_NAME,
2295 &buf_addr) < 0){
2296 avs2_print(dec, 0,
2297 "%s malloc compress header failed %d\n",
2298 DRIVER_HEADER_NAME, i);
2299 dec->fatal_error |= DECODER_FATAL_ERROR_NO_MEM;
2300 return;
2301 }
2302 }
2303 #endif
2304 #endif
2305 dec->frame_height = avs2_dec->img.height;
2306 dec->frame_width = avs2_dec->img.width;
2307
2308 for (i = 0; i < dec->used_buf_num; i++) {
2309 if (i == (dec->used_buf_num - 1))
2310 pic = avs2_dec->m_bg;
2311 else
2312 pic = avs2_dec->fref[i];
2313 pic->index = i;
2314 pic->BUF_index = -1;
2315 pic->mv_buf_index = -1;
2316 if (config_pic(dec, pic, lcu_size_log2) < 0) {
2317 if (debug)
2318 avs2_print(dec, 0,
2319 "Config_pic %d fail\n",
2320 pic->index);
2321 pic->index = -1;
2322 break;
2323 }
2324 pic->pic_w = avs2_dec->img.width;
2325 pic->pic_h = avs2_dec->img.height;
2326 }
2327 for (; i < dec->used_buf_num; i++) {
2328 if (i == (dec->used_buf_num - 1))
2329 pic = avs2_dec->m_bg;
2330 else
2331 pic = avs2_dec->fref[i];
2332 pic->index = -1;
2333 pic->BUF_index = -1;
2334 pic->mv_buf_index = -1;
2335 }
2336 avs2_print(dec, AVS2_DBG_BUFMGR,
2337 "%s ok, used_buf_num = %d\n",
2338 __func__, dec->used_buf_num);
2339 dec->pic_list_init_flag = 1;
2340 }
2341
2342
2343 static void init_pic_list_hw(struct AVS2Decoder_s *dec)
2344 {
2345 int i;
2346 struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2347 struct avs2_frame_s *pic;
2348 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x0);*/
2349 #if 0
2350 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
2351 (0x1 << 1) | (0x1 << 2));
2352
2353 #ifdef DUAL_CORE_64
2354 WRITE_VREG(HEVC2_HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
2355 (0x1 << 1) | (0x1 << 2));
2356 #endif
2357 #endif
2358 for (i = 0; i < dec->used_buf_num; i++) {
2359 if (i == (dec->used_buf_num - 1))
2360 pic = avs2_dec->m_bg;
2361 else
2362 pic = avs2_dec->fref[i];
2363 if (pic->index < 0)
2364 break;
2365 #ifdef AVS2_10B_MMU
2366 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
2367 pic->header_adr
2368 | (pic->mc_canvas_y << 8)|0x1);*/
2369 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
2370 (0x1 << 1) | (pic->index << 8));
2371
2372 #ifdef DUAL_CORE_64
2373 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXLX2)
2374 WRITE_VREG(HEVC2_MPP_ANC2AXI_TBL_CONF_ADDR,
2375 (0x1 << 1) | (pic->index << 8));
2376 else
2377 WRITE_VREG(HEVC2_HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
2378 (0x1 << 1) | (pic->index << 8));
2379 #endif
2380 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, pic->header_adr >> 5);
2381 #else
2382 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
2383 pic->mc_y_adr
2384 | (pic->mc_canvas_y << 8) | 0x1);*/
2385 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, pic->mc_y_adr >> 5);
2386 #endif
2387 #ifndef LOSLESS_COMPRESS_MODE
2388 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
2389 pic->mc_u_v_adr
2390 | (pic->mc_canvas_u_v << 8)| 0x1);*/
2391 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, pic->mc_u_v_adr >> 5);
2392 #endif
2393 #ifdef DUAL_CORE_64
2394 #ifdef AVS2_10B_MMU
2395 WRITE_VREG(HEVC2_HEVCD_MPP_ANC2AXI_TBL_DATA,
2396 pic->header_adr >> 5);
2397 #else
2398 WRITE_VREG(HEVC2_HEVCD_MPP_ANC2AXI_TBL_DATA,
2399 pic->mc_y_adr >> 5);
2400 #endif
2401 #ifndef LOSLESS_COMPRESS_MODE
2402 WRITE_VREG(HEVC2_HEVCD_MPP_ANC2AXI_TBL_DATA,
2403 pic->mc_u_v_adr >> 5);
2404 #endif
2405 /*DUAL_CORE_64*/
2406 #endif
2407 }
2408 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
2409 #ifdef DUAL_CORE_64
2410 WRITE_VREG(HEVC2_HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
2411 0x1);
2412 #endif
2413 /*Zero out canvas registers in IPP -- avoid simulation X*/
2414 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2415 (0 << 8) | (0 << 1) | 1);
2416 for (i = 0; i < 32; i++) {
2417 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
2418 #ifdef DUAL_CORE_64
2419 WRITE_VREG(HEVC2_HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
2420 #endif
2421 }
2422 }
2423
2424
2425 static void dump_pic_list(struct AVS2Decoder_s *dec)
2426 {
2427 int ii;
2428 struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2429 for (ii = 0; ii < avs2_dec->ref_maxbuffer; ii++) {
2430 avs2_print(dec, 0,
2431 "fref[%d]: index %d decode_id %d mvbuf %d imgcoi_ref %d imgtr_fwRefDistance %d refered %d, pre %d is_out %d, bg %d, vf_ref %d error %d lcu %d ref_pos(%d,%d,%d,%d,%d,%d,%d)\n",
2432 ii, avs2_dec->fref[ii]->index,
2433 avs2_dec->fref[ii]->decode_idx,
2434 avs2_dec->fref[ii]->mv_buf_index,
2435 avs2_dec->fref[ii]->imgcoi_ref,
2436 avs2_dec->fref[ii]->imgtr_fwRefDistance,
2437 avs2_dec->fref[ii]->refered_by_others,
2438 avs2_dec->fref[ii]->to_prepare_disp,
2439 avs2_dec->fref[ii]->is_output,
2440 avs2_dec->fref[ii]->bg_flag,
2441 avs2_dec->fref[ii]->vf_ref,
2442 avs2_dec->fref[ii]->error_mark,
2443 avs2_dec->fref[ii]->decoded_lcu,
2444 avs2_dec->fref[ii]->ref_poc[0],
2445 avs2_dec->fref[ii]->ref_poc[1],
2446 avs2_dec->fref[ii]->ref_poc[2],
2447 avs2_dec->fref[ii]->ref_poc[3],
2448 avs2_dec->fref[ii]->ref_poc[4],
2449 avs2_dec->fref[ii]->ref_poc[5],
2450 avs2_dec->fref[ii]->ref_poc[6]
2451 );
2452 }
2453 return;
2454 }
2455
2456 static int config_mc_buffer(struct AVS2Decoder_s *dec)
2457 {
2458 int32_t i;
2459 struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2460 struct avs2_frame_s *pic;
2461 struct avs2_frame_s *cur_pic = avs2_dec->hc.cur_pic;
2462
2463 /*if (avs2_dec->img.type == I_IMG)
2464 return 0;
2465 */
2466 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2467 "Entered config_mc_buffer....\n");
2468 if (avs2_dec->f_bg != NULL) {
2469 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2470 "config_mc_buffer for background (canvas_y %d, canvas_u_v %d)\n",
2471 avs2_dec->f_bg->mc_canvas_y, avs2_dec->f_bg->mc_canvas_u_v);
2472 /*WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2473 (7 << 8) | (0<<1) | 1); L0:BG */
2474 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2475 (15 << 8) | (0<<1) | 1); /* L0:BG*/
2476 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
2477 (avs2_dec->f_bg->mc_canvas_u_v << 16) |
2478 (avs2_dec->f_bg->mc_canvas_u_v << 8) |
2479 avs2_dec->f_bg->mc_canvas_y);
2480 /*WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2481 (23 << 8) | (0<<1) | 1); L1:BG*/
2482 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2483 (31 << 8) | (0<<1) | 1); /* L1:BG*/
2484 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
2485 (avs2_dec->f_bg->mc_canvas_u_v << 16) |
2486 (avs2_dec->f_bg->mc_canvas_u_v << 8) |
2487 avs2_dec->f_bg->mc_canvas_y);
2488 }
2489
2490 if (avs2_dec->img.type == I_IMG)
2491 return 0;
2492
2493 if (avs2_dec->img.type == P_IMG) {
2494 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2495 "config_mc_buffer for P_IMG, img type %d\n",
2496 avs2_dec->img.type);
2497 /*refer to prepare_RefInfo()*/
2498 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2499 (0 << 8) | (0<<1) | 1);
2500 for (i = 0; i < avs2_dec->img.num_of_references; i++) {
2501 pic = avs2_dec->fref[i];
2502 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
2503 (pic->mc_canvas_u_v << 16) |
2504 (pic->mc_canvas_u_v << 8) |
2505 pic->mc_canvas_y);
2506
2507 if (pic->error_mark)
2508 cur_pic->error_mark = 1;
2509
2510 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2511 "refid %x mc_canvas_u_v %x mc_canvas_y %x error_mark %x\n",
2512 i, pic->mc_canvas_u_v, pic->mc_canvas_y,
2513 pic->error_mark);
2514 }
2515 } else if (avs2_dec->img.type == F_IMG) {
2516 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2517 "config_mc_buffer for F_IMG, img type %d\n",
2518 avs2_dec->img.type);
2519 /*refer to prepare_RefInfo()*/
2520 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2521 (0 << 8) | (0<<1) | 1);
2522 for (i = 0; i < avs2_dec->img.num_of_references; i++) {
2523 pic = avs2_dec->fref[i];
2524 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
2525 (pic->mc_canvas_u_v << 16) |
2526 (pic->mc_canvas_u_v << 8) |
2527 pic->mc_canvas_y);
2528
2529 if (pic->error_mark)
2530 cur_pic->error_mark = 1;
2531
2532 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2533 "refid %x mc_canvas_u_v %x mc_canvas_y %x error_mark %x\n",
2534 i, pic->mc_canvas_u_v, pic->mc_canvas_y,
2535 pic->error_mark);
2536 }
2537 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2538 (16 << 8) | (0<<1) | 1);
2539 for (i = 0; i < avs2_dec->img.num_of_references; i++) {
2540 pic = avs2_dec->fref[i];
2541 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
2542 (pic->mc_canvas_u_v << 16) |
2543 (pic->mc_canvas_u_v << 8) |
2544 pic->mc_canvas_y);
2545 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2546 "refid %x mc_canvas_u_v %x mc_canvas_y %x\n",
2547 i, pic->mc_canvas_u_v, pic->mc_canvas_y);
2548 }
2549 } else {
2550 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2551 "config_mc_buffer for B_IMG\n");
2552 /*refer to prepare_RefInfo()*/
2553 pic = avs2_dec->fref[1];
2554 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2555 (0 << 8) | (0<<1) | 1);
2556 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
2557 (pic->mc_canvas_u_v << 16) |
2558 (pic->mc_canvas_u_v << 8) |
2559 pic->mc_canvas_y);
2560
2561 if (pic->error_mark)
2562 cur_pic->error_mark = 1;
2563
2564 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2565 "refid %x mc_canvas_u_v %x mc_canvas_y %x error_mark %x\n",
2566 1, pic->mc_canvas_u_v, pic->mc_canvas_y,
2567 pic->error_mark);
2568
2569 pic = avs2_dec->fref[0];
2570 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2571 (16 << 8) | (0<<1) | 1);
2572 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
2573 (pic->mc_canvas_u_v<<16) |
2574 (pic->mc_canvas_u_v<<8) |
2575 pic->mc_canvas_y);
2576
2577 if (pic->error_mark)
2578 cur_pic->error_mark = 1;
2579
2580 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2581 "refid %x mc_canvas_u_v %x mc_canvas_y %x error_mark %x\n",
2582 0, pic->mc_canvas_u_v, pic->mc_canvas_y,
2583 pic->error_mark);
2584 }
2585 return 0;
2586 }
2587 #if 0
2588 static void mcrcc_get_hitrate(void)
2589 {
2590 u32 tmp;
2591 u32 raw_mcr_cnt;
2592 u32 hit_mcr_cnt;
2593 u32 byp_mcr_cnt_nchoutwin;
2594 u32 byp_mcr_cnt_nchcanv;
2595 int hitrate;
2596
2597 if (debug & AVS2_DBG_CACHE)
2598 pr_info("[cache_util.c] Entered mcrcc_get_hitrate...\n");
2599 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x0<<1));
2600 raw_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
2601 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x1<<1));
2602 hit_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
2603 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x2<<1));
2604 byp_mcr_cnt_nchoutwin = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
2605 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x3<<1));
2606 byp_mcr_cnt_nchcanv = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
2607
2608 if (debug & AVS2_DBG_CACHE) {
2609 pr_info("raw_mcr_cnt_total: %d\n",raw_mcr_cnt);
2610 pr_info("hit_mcr_cnt_total: %d\n",hit_mcr_cnt);
2611 pr_info("byp_mcr_cnt_nchoutwin_total: %d\n",byp_mcr_cnt_nchoutwin);
2612 pr_info("byp_mcr_cnt_nchcanv_total: %d\n",byp_mcr_cnt_nchcanv);
2613 }
2614 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x4<<1));
2615 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
2616 if (debug & AVS2_DBG_CACHE)
2617 pr_info("miss_mcr_0_cnt_total: %d\n", tmp);
2618
2619 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x5<<1));
2620 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
2621 if (debug & AVS2_DBG_CACHE)
2622 pr_info("miss_mcr_1_cnt_total: %d\n", tmp);
2623
2624 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x6<<1));
2625 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
2626 if (debug & AVS2_DBG_CACHE)
2627 pr_info("hit_mcr_0_cnt_total: %d\n",tmp);
2628
2629 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x7<<1));
2630 tmp= READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
2631 if (debug & AVS2_DBG_CACHE)
2632 pr_info("hit_mcr_1_cnt_total: %d\n",tmp);
2633
2634 if (raw_mcr_cnt != 0) {
2635 hitrate = (hit_mcr_cnt / raw_mcr_cnt) * 100;
2636 if (debug & AVS2_DBG_CACHE)
2637 pr_info("MCRCC_HIT_RATE : %d\n", hitrate);
2638 hitrate = ((byp_mcr_cnt_nchoutwin + byp_mcr_cnt_nchcanv)
2639 /raw_mcr_cnt) * 100;
2640 if (debug & AVS2_DBG_CACHE)
2641 pr_info("MCRCC_BYP_RATE : %d\n", hitrate);
2642 } else if (debug & AVS2_DBG_CACHE) {
2643 pr_info("MCRCC_HIT_RATE : na\n");
2644 pr_info("MCRCC_BYP_RATE : na\n");
2645 }
2646 return;
2647 }
2648
2649
2650 static void decomp_get_hitrate(void)
2651 {
2652 u32 raw_mcr_cnt;
2653 u32 hit_mcr_cnt;
2654 int hitrate;
2655
2656 if (debug & AVS2_DBG_CACHE)
2657 pr_info("[cache_util.c] Entered decomp_get_hitrate...\n");
2658 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x0<<1));
2659 raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
2660 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x1<<1));
2661 hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
2662
2663 if (debug & AVS2_DBG_CACHE) {
2664 pr_info("hcache_raw_cnt_total: %d\n",raw_mcr_cnt);
2665 pr_info("hcache_hit_cnt_total: %d\n",hit_mcr_cnt);
2666 }
2667 if (raw_mcr_cnt != 0) {
2668 hitrate = (hit_mcr_cnt / raw_mcr_cnt) * 100;
2669 if (debug & AVS2_DBG_CACHE)
2670 pr_info("DECOMP_HCACHE_HIT_RATE : %d\n", hitrate);
2671 } else {
2672 if (debug & AVS2_DBG_CACHE)
2673 pr_info("DECOMP_HCACHE_HIT_RATE : na\n");
2674 }
2675 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x2<<1));
2676 raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
2677 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x3<<1));
2678 hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
2679
2680 if (debug & AVS2_DBG_CACHE) {
2681 pr_info("dcache_raw_cnt_total: %d\n", raw_mcr_cnt);
2682 pr_info("dcache_hit_cnt_total: %d\n", hit_mcr_cnt);
2683 }
2684 if (raw_mcr_cnt != 0) {
2685 hitrate = (hit_mcr_cnt / raw_mcr_cnt) * 100;
2686 if (debug & AVS2_DBG_CACHE)
2687 pr_info("DECOMP_DCACHE_HIT_RATE : %d\n", hitrate);
2688 } else if (debug & AVS2_DBG_CACHE) {
2689 pr_info("DECOMP_DCACHE_HIT_RATE : na\n");
2690 }
2691 return;
2692 }
2693
2694 static void decomp_get_comprate(void)
2695 {
2696 u32 raw_ucomp_cnt;
2697 u32 fast_comp_cnt;
2698 u32 slow_comp_cnt;
2699 int comprate;
2700
2701 if (debug & AVS2_DBG_CACHE)
2702 pr_info("[cache_util.c] Entered decomp_get_comprate...\n");
2703 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x4<<1));
2704 fast_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
2705 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x5<<1));
2706 slow_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
2707 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x6<<1));
2708 raw_ucomp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
2709 if (debug & AVS2_DBG_CACHE) {
2710 pr_info("decomp_fast_comp_total: %d\n", fast_comp_cnt);
2711 pr_info("decomp_slow_comp_total: %d\n", slow_comp_cnt);
2712 pr_info("decomp_raw_uncomp_total: %d\n", raw_ucomp_cnt);
2713 }
2714
2715 if (raw_ucomp_cnt != 0) {
2716 comprate = ((fast_comp_cnt + slow_comp_cnt)
2717 / raw_ucomp_cnt) * 100;
2718 if (debug & AVS2_DBG_CACHE)
2719 pr_info("DECOMP_COMP_RATIO : %d\n", comprate);
2720 } else if (debug & AVS2_DBG_CACHE) {
2721 pr_info("DECOMP_COMP_RATIO : na\n");
2722 }
2723 return;
2724 }
2725 #endif
2726
2727 static void config_mcrcc_axi_hw(struct AVS2Decoder_s *dec)
2728 {
2729 uint32_t rdata32;
2730 uint32_t rdata32_2;
2731 struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2732
2733 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2); /* reset mcrcc*/
2734
2735 if (avs2_dec->img.type == I_IMG) { /* I-PIC*/
2736 /* remove reset -- disables clock */
2737 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
2738 return;
2739 }
2740 /*
2741 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
2742 mcrcc_get_hitrate();
2743 decomp_get_hitrate();
2744 decomp_get_comprate();
2745 }
2746 */
2747 if ((avs2_dec->img.type == B_IMG) ||
2748 (avs2_dec->img.type == F_IMG)) { /*B-PIC or F_PIC*/
2749 /*Programme canvas0 */
2750 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2751 (0 << 8) | (0 << 1) | 0);
2752 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
2753 rdata32 = rdata32 & 0xffff;
2754 rdata32 = rdata32 | (rdata32 << 16);
2755 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
2756
2757 /*Programme canvas1 */
2758 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2759 (16 << 8) | (1 << 1) | 0);
2760 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
2761 rdata32_2 = rdata32_2 & 0xffff;
2762 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
2763 if (rdata32 == rdata32_2) {
2764 rdata32_2 =
2765 READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
2766 rdata32_2 = rdata32_2 & 0xffff;
2767 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
2768 }
2769 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32_2);
2770 } else { /* P-PIC */
2771 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2772 (0 << 8) | (1 << 1) | 0);
2773 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
2774 rdata32 = rdata32 & 0xffff;
2775 rdata32 = rdata32 | (rdata32 << 16);
2776 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
2777
2778 /*Programme canvas1*/
2779 rdata32 =
2780 READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
2781 rdata32 = rdata32 & 0xffff;
2782 rdata32 = rdata32 | (rdata32 << 16);
2783 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
2784 }
2785 /*enable mcrcc progressive-mode */
2786 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
2787 return;
2788 }
2789
2790 static void config_mpred_hw(struct AVS2Decoder_s *dec)
2791 {
2792 uint32_t data32;
2793 struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2794 struct avs2_frame_s *cur_pic = avs2_dec->hc.cur_pic;
2795 struct avs2_frame_s *col_pic = avs2_dec->fref[0];
2796 int32_t mpred_mv_rd_start_addr;
2797 int32_t mpred_curr_lcu_x;
2798 int32_t mpred_curr_lcu_y;
2799 int32_t mpred_mv_rd_end_addr;
2800 int32_t above_en;
2801 int32_t mv_wr_en;
2802 int32_t mv_rd_en;
2803 int32_t col_isIntra;
2804 int mv_mem_unit;
2805 if (avs2_dec->img.type != I_IMG) {
2806 above_en = 1;
2807 mv_wr_en = 1;
2808 mv_rd_en = 1;
2809 col_isIntra = 0;
2810 } else {
2811 above_en = 1;
2812 mv_wr_en = 1;
2813 mv_rd_en = 0;
2814 col_isIntra = 0;
2815 }
2816
2817 mpred_mv_rd_start_addr =
2818 col_pic->mpred_mv_wr_start_addr;
2819 data32 = READ_VREG(HEVC_MPRED_CURR_LCU);
2820 mpred_curr_lcu_x = data32 & 0xffff;
2821 mpred_curr_lcu_y = (data32 >> 16) & 0xffff;
2822
2823 mv_mem_unit = avs2_dec->lcu_size_log2 == 6 ?
2824 0x200 : (avs2_dec->lcu_size_log2 == 5 ?
2825 0x80 : 0x20);
2826
2827 mpred_mv_rd_end_addr =
2828 mpred_mv_rd_start_addr +
2829 ((avs2_dec->lcu_x_num *
2830 avs2_dec->lcu_y_num) * mv_mem_unit);
2831
2832 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2833 "cur pic index %d col pic index %d\n",
2834 cur_pic->index, col_pic->index);
2835
2836
2837 WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR,
2838 cur_pic->mpred_mv_wr_start_addr);
2839 WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR,
2840 col_pic->mpred_mv_wr_start_addr);
2841 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2842 "[MPRED CO_MV] write 0x%x read 0x%x\n",
2843 cur_pic->mpred_mv_wr_start_addr,
2844 col_pic->mpred_mv_wr_start_addr);
2845
2846 data32 =
2847 ((avs2_dec->bk_img_is_top_field) << 13) |
2848 ((avs2_dec->hd.background_picture_enable & 1) << 12) |
2849 ((avs2_dec->hd.curr_RPS.num_of_ref & 7) << 8) |
2850 ((avs2_dec->hd.b_pmvr_enabled & 1) << 6) |
2851 ((avs2_dec->img.is_top_field & 1) << 5) |
2852 ((avs2_dec->img.is_field_sequence & 1) << 4) |
2853 ((avs2_dec->img.typeb & 7) << 1) |
2854 (avs2_dec->hd.background_reference_enable & 0x1);
2855 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2856 "HEVC_MPRED_CTRL9 <= 0x%x(num of ref %d)\n",
2857 data32, avs2_dec->hd.curr_RPS.num_of_ref);
2858 WRITE_VREG(HEVC_MPRED_CTRL9, data32);
2859
2860 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2861 "%s: dis %d %d %d %d %d %d %d fref0_ref_poc %d %d %d %d %d %d %d\n",
2862 __func__,
2863 avs2_dec->fref[0]->imgtr_fwRefDistance,
2864 avs2_dec->fref[1]->imgtr_fwRefDistance,
2865 avs2_dec->fref[2]->imgtr_fwRefDistance,
2866 avs2_dec->fref[3]->imgtr_fwRefDistance,
2867 avs2_dec->fref[4]->imgtr_fwRefDistance,
2868 avs2_dec->fref[5]->imgtr_fwRefDistance,
2869 avs2_dec->fref[6]->imgtr_fwRefDistance,
2870 avs2_dec->fref[0]->ref_poc[0],
2871 avs2_dec->fref[0]->ref_poc[1],
2872 avs2_dec->fref[0]->ref_poc[2],
2873 avs2_dec->fref[0]->ref_poc[3],
2874 avs2_dec->fref[0]->ref_poc[4],
2875 avs2_dec->fref[0]->ref_poc[5],
2876 avs2_dec->fref[0]->ref_poc[6]
2877 );
2878 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2879 "pic_distance %d, imgtr_next_P %d\n",
2880 avs2_dec->img.pic_distance, avs2_dec->img.imgtr_next_P);
2881
2882
2883 WRITE_VREG(HEVC_MPRED_CUR_POC, avs2_dec->img.pic_distance);
2884 WRITE_VREG(HEVC_MPRED_COL_POC, avs2_dec->img.imgtr_next_P);
2885
2886 /*below MPRED Ref_POC_xx_Lx registers
2887 must follow Ref_POC_xx_L0 ->
2888 Ref_POC_xx_L1 in pair write order!!!*/
2889 WRITE_VREG(HEVC_MPRED_L0_REF00_POC,
2890 avs2_dec->fref[0]->imgtr_fwRefDistance);
2891 WRITE_VREG(HEVC_MPRED_L1_REF00_POC,
2892 avs2_dec->fref[0]->ref_poc[0]);
2893
2894 WRITE_VREG(HEVC_MPRED_L0_REF01_POC,
2895 avs2_dec->fref[1]->imgtr_fwRefDistance);
2896 WRITE_VREG(HEVC_MPRED_L1_REF01_POC,
2897 avs2_dec->fref[0]->ref_poc[1]);
2898
2899 WRITE_VREG(HEVC_MPRED_L0_REF02_POC,
2900 avs2_dec->fref[2]->imgtr_fwRefDistance);
2901 WRITE_VREG(HEVC_MPRED_L1_REF02_POC,
2902 avs2_dec->fref[0]->ref_poc[2]);
2903
2904 WRITE_VREG(HEVC_MPRED_L0_REF03_POC,
2905 avs2_dec->fref[3]->imgtr_fwRefDistance);
2906 WRITE_VREG(HEVC_MPRED_L1_REF03_POC,
2907 avs2_dec->fref[0]->ref_poc[3]);
2908
2909 WRITE_VREG(HEVC_MPRED_L0_REF04_POC,
2910 avs2_dec->fref[4]->imgtr_fwRefDistance);
2911 WRITE_VREG(HEVC_MPRED_L1_REF04_POC,
2912 avs2_dec->fref[0]->ref_poc[4]);
2913
2914 WRITE_VREG(HEVC_MPRED_L0_REF05_POC,
2915 avs2_dec->fref[5]->imgtr_fwRefDistance);
2916 WRITE_VREG(HEVC_MPRED_L1_REF05_POC,
2917 avs2_dec->fref[0]->ref_poc[5]);
2918
2919 WRITE_VREG(HEVC_MPRED_L0_REF06_POC,
2920 avs2_dec->fref[6]->imgtr_fwRefDistance);
2921 WRITE_VREG(HEVC_MPRED_L1_REF06_POC,
2922 avs2_dec->fref[0]->ref_poc[6]);
2923
2924
2925 WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR,
2926 mpred_mv_rd_end_addr);
2927 }
2928
2929 static void config_dblk_hw(struct AVS2Decoder_s *dec)
2930 {
2931 /*
2932 * Picture level de-block parameter configuration here
2933 */
2934 struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2935 union param_u *rpm_param = &avs2_dec->param;
2936 uint32_t data32;
2937
2938 data32 = READ_VREG(HEVC_DBLK_CFG1);
2939 data32 = (((data32 >> 20) & 0xfff) << 20) |
2940 (((avs2_dec->input.sample_bit_depth == 10)
2941 ? 0xa : 0x0) << 16) | /*[16 +: 4]: {luma_bd[1:0],
2942 chroma_bd[1:0]}*/
2943 (((data32 >> 2) & 0x3fff) << 2) |
2944 (((rpm_param->p.lcu_size == 6)
2945 ? 0 : (rpm_param->p.lcu_size == 5)
2946 ? 1 : 2) << 0);/*[ 0 +: 2]: lcu_size*/
2947 WRITE_VREG(HEVC_DBLK_CFG1, data32);
2948
2949 data32 = (avs2_dec->img.height << 16) |
2950 avs2_dec->img.width;
2951 WRITE_VREG(HEVC_DBLK_CFG2, data32);
2952 /*
2953 [27 +: 1]: cross_slice_loopfilter_enable_flag
2954 [26 +: 1]: loop_filter_disable
2955 [25 +: 1]: useNSQT
2956 [22 +: 3]: imgtype
2957 [17 +: 5]: alpha_c_offset (-8~8)
2958 [12 +: 5]: beta_offset (-8~8)
2959 [ 6 +: 6]: chroma_quant_param_delta_u (-16~16)
2960 [ 0 +: 6]: chroma_quant_param_delta_v (-16~16)
2961 */
2962 data32 = ((avs2_dec->input.crossSliceLoopFilter
2963 & 0x1) << 27) |
2964 ((rpm_param->p.loop_filter_disable & 0x1) << 26) |
2965 ((avs2_dec->input.useNSQT & 0x1) << 25) |
2966 ((avs2_dec->img.type & 0x7) << 22) |
2967 ((rpm_param->p.alpha_c_offset & 0x1f) << 17) |
2968 ((rpm_param->p.beta_offset & 0x1f) << 12) |
2969 ((rpm_param->p.chroma_quant_param_delta_cb & 0x3f) << 6) |
2970 ((rpm_param->p.chroma_quant_param_delta_cr & 0x3f) << 0);
2971
2972 WRITE_VREG(HEVC_DBLK_CFG9, data32);
2973 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2974 "[c] cfgDBLK: crossslice(%d),lfdisable(%d),bitDepth(%d),lcuSize(%d),NSQT(%d)\n",
2975 avs2_dec->input.crossSliceLoopFilter,
2976 rpm_param->p.loop_filter_disable,
2977 avs2_dec->input.sample_bit_depth,
2978 avs2_dec->lcu_size,
2979 avs2_dec->input.useNSQT);
2980 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2981 "[c] cfgDBLK: alphaCOffset(%d),betaOffset(%d),quantDeltaCb(%d),quantDeltaCr(%d)\n",
2982 rpm_param->p.alpha_c_offset,
2983 rpm_param->p.beta_offset,
2984 rpm_param->p.chroma_quant_param_delta_cb,
2985 rpm_param->p.chroma_quant_param_delta_cr);
2986 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2987 "[c] cfgDBLK: .done.\n");
2988 }
2989
2990 static void config_sao_hw(struct AVS2Decoder_s *dec)
2991 {
2992 uint32_t data32;
2993 struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2994 struct avs2_frame_s *cur_pic = avs2_dec->hc.cur_pic;
2995
2996 int lcu_size = 64;
2997 int mc_buffer_size_u_v =
2998 cur_pic->lcu_total * lcu_size*lcu_size/2;
2999 int mc_buffer_size_u_v_h =
3000 (mc_buffer_size_u_v + 0xffff) >> 16;/*64k alignment*/
3001
3002 data32 = READ_VREG(HEVC_SAO_CTRL0);
3003 data32 &= (~0xf);
3004 data32 |= avs2_dec->lcu_size_log2;
3005 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
3006 "%s, lcu_size_log2 = %d, config HEVC_SAO_CTRL0 0x%x\n",
3007 __func__,
3008 avs2_dec->lcu_size_log2,
3009 data32);
3010
3011 WRITE_VREG(HEVC_SAO_CTRL0, data32);
3012
3013 #ifndef AVS2_10B_MMU
3014 if ((get_double_write_mode(dec) & 0x10) == 0)
3015 WRITE_VREG(HEVC_CM_BODY_START_ADDR, cur_pic->mc_y_adr);
3016 #endif
3017 if (get_double_write_mode(dec)) {
3018 WRITE_VREG(HEVC_SAO_Y_START_ADDR, cur_pic->dw_y_adr);
3019 WRITE_VREG(HEVC_SAO_C_START_ADDR, cur_pic->dw_u_v_adr);
3020 WRITE_VREG(HEVC_SAO_Y_WPTR, cur_pic->dw_y_adr);
3021 WRITE_VREG(HEVC_SAO_C_WPTR, cur_pic->dw_u_v_adr);
3022 } else {
3023 WRITE_VREG(HEVC_SAO_Y_START_ADDR, 0xffffffff);
3024 WRITE_VREG(HEVC_SAO_C_START_ADDR, 0xffffffff);
3025 }
3026 #ifdef AVS2_10B_MMU
3027 WRITE_VREG(HEVC_CM_HEADER_START_ADDR, cur_pic->header_adr);
3028 #endif
3029 data32 = (mc_buffer_size_u_v_h << 16) << 1;
3030 /*pr_info("data32=%x,mc_buffer_size_u_v_h=%x,lcu_total=%x\n",
3031 data32, mc_buffer_size_u_v_h, cur_pic->lcu_total);*/
3032 WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
3033
3034 data32 = (mc_buffer_size_u_v_h << 16);
3035 WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
3036
3037 #ifdef AVS2_10B_NV21
3038 #ifdef DOS_PROJECT
3039 data32 = READ_VREG(HEVC_SAO_CTRL1);
3040 data32 &= (~0x3000);
3041 /*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/
3042 data32 |= (MEM_MAP_MODE << 12);
3043 data32 &= (~0x3);
3044 data32 |= 0x1; /* [1]:dw_disable [0]:cm_disable*/
3045 WRITE_VREG(HEVC_SAO_CTRL1, data32);
3046 /*[23:22] dw_v1_ctrl [21:20] dw_v0_ctrl [19:18] dw_h1_ctrl
3047 [17:16] dw_h0_ctrl*/
3048 data32 = READ_VREG(HEVC_SAO_CTRL5);
3049 /*set them all 0 for H265_NV21 (no down-scale)*/
3050 data32 &= ~(0xff << 16);
3051 WRITE_VREG(HEVC_SAO_CTRL5, data32);
3052 ata32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
3053 data32 &= (~0x30);
3054 /*[5:4] address_format 00:linear 01:32x32 10:64x32*/
3055 data32 |= (MEM_MAP_MODE << 4);
3056 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
3057 #else
3058 /*m8baby test1902*/
3059 data32 = READ_VREG(HEVC_SAO_CTRL1);
3060 data32 &= (~0x3000);
3061 /*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/
3062 data32 |= (MEM_MAP_MODE << 12);
3063 data32 &= (~0xff0);
3064 /*data32 |= 0x670;*/ /*Big-Endian per 64-bit*/
3065 data32 |= 0x880; /*.Big-Endian per 64-bit */
3066 data32 &= (~0x3);
3067 data32 |= 0x1; /*[1]:dw_disable [0]:cm_disable*/
3068 WRITE_VREG(HEVC_SAO_CTRL1, data32);
3069 /* [23:22] dw_v1_ctrl [21:20] dw_v0_ctrl
3070 [19:18] dw_h1_ctrl [17:16] dw_h0_ctrl*/
3071 data32 = READ_VREG(HEVC_SAO_CTRL5);
3072 /* set them all 0 for H265_NV21 (no down-scale)*/
3073 data32 &= ~(0xff << 16);
3074 WRITE_VREG(HEVC_SAO_CTRL5, data32);
3075
3076 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
3077 data32 &= (~0x30);
3078 /*[5:4] address_format 00:linear 01:32x32 10:64x32*/
3079 data32 |= (MEM_MAP_MODE << 4);
3080 data32 &= (~0xF);
3081 data32 |= 0x8; /*Big-Endian per 64-bit*/
3082 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
3083 #endif
3084 #else
3085 data32 = READ_VREG(HEVC_SAO_CTRL1);
3086 data32 &= (~0x3000);
3087 data32 |= (MEM_MAP_MODE <<
3088 12); /* [13:12] axi_aformat, 0-Linear,
3089 1-32x32, 2-64x32 */
3090 data32 &= (~0xff0);
3091 /* data32 |= 0x670; // Big-Endian per 64-bit */
3092 data32 |= endian; /* Big-Endian per 64-bit */
3093 data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/
3094 #if 0
3095 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
3096 if (get_double_write_mode(dec) == 0)
3097 data32 |= 0x2; /*disable double write*/
3098 #ifndef AVS2_10B_MMU
3099 else
3100 if (get_double_write_mode(dec) & 0x10)
3101 data32 |= 0x1; /*disable cm*/
3102 #endif
3103 }
3104 #endif
3105 if (get_double_write_mode(dec) == 0)
3106 data32 |= 0x2; /*disable double write*/
3107 else if (get_double_write_mode(dec) & 0x10)
3108 data32 |= 0x1; /*disable cm*/
3109
3110 WRITE_VREG(HEVC_SAO_CTRL1, data32);
3111
3112 if (get_double_write_mode(dec) & 0x10) {
3113 /* [23:22] dw_v1_ctrl
3114 [21:20] dw_v0_ctrl
3115 [19:18] dw_h1_ctrl
3116 [17:16] dw_h0_ctrl
3117 */
3118 data32 = READ_VREG(HEVC_SAO_CTRL5);
3119 /*set them all 0 for H265_NV21 (no down-scale)*/
3120 data32 &= ~(0xff << 16);
3121 WRITE_VREG(HEVC_SAO_CTRL5, data32);
3122 } else {
3123 data32 = READ_VREG(HEVC_SAO_CTRL5);
3124 data32 &= (~(0xff << 16));
3125 if (get_double_write_mode(dec) == 2 ||
3126 get_double_write_mode(dec) == 3)
3127 data32 |= (0xff<<16);
3128 else if (get_double_write_mode(dec) == 4)
3129 data32 |= (0x33<<16);
3130 WRITE_VREG(HEVC_SAO_CTRL5, data32);
3131 }
3132
3133 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
3134 data32 &= (~0x30);
3135 /* [5:4] -- address_format 00:linear 01:32x32 10:64x32 */
3136 data32 |= (mem_map_mode <<
3137 4);
3138 data32 &= (~0xF);
3139 data32 |= 0xf; /* valid only when double write only */
3140 /*data32 |= 0x8;*/ /* Big-Endian per 64-bit */
3141 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
3142 #endif
3143 }
3144
3145 static void reconstructCoefficients(struct AVS2Decoder_s *dec,
3146 struct ALFParam_s *alfParam)
3147 {
3148 int32_t g, sum, i, coeffPred;
3149 for (g = 0; g < alfParam->filters_per_group; g++) {
3150 sum = 0;
3151 for (i = 0; i < alfParam->num_coeff - 1; i++) {
3152 sum += (2 * alfParam->coeffmulti[g][i]);
3153 dec->m_filterCoeffSym[g][i] =
3154 alfParam->coeffmulti[g][i];
3155 /*pr_info("[t] dec->m_filterCoeffSym[%d][%d]=0x%x\n",
3156 g, i, dec->m_filterCoeffSym[g][i]);*/
3157 }
3158 coeffPred = (1 << ALF_NUM_BIT_SHIFT) - sum;
3159 dec->m_filterCoeffSym[g][alfParam->num_coeff - 1]
3160 = coeffPred +
3161 alfParam->coeffmulti[g][alfParam->num_coeff - 1];
3162 /*pr_info("[t] dec->m_filterCoeffSym[%d][%d]=0x%x\n",
3163 g, (alfParam->num_coeff - 1),
3164 dec->m_filterCoeffSym[g][alfParam->num_coeff - 1]);*/
3165 }
3166 }
3167
3168 static void reconstructCoefInfo(struct AVS2Decoder_s *dec,
3169 int32_t compIdx, struct ALFParam_s *alfParam)
3170 {
3171 int32_t i;
3172 if (compIdx == ALF_Y) {
3173 if (alfParam->filters_per_group > 1) {
3174 for (i = 1; i < NO_VAR_BINS; ++i) {
3175 if (alfParam->filterPattern[i])
3176 dec->m_varIndTab[i] =
3177 dec->m_varIndTab[i - 1] + 1;
3178 else
3179 dec->m_varIndTab[i] =
3180 dec->m_varIndTab[i - 1];
3181 }
3182 }
3183 }
3184 reconstructCoefficients(dec, alfParam);
3185 }
3186
3187 static void config_alf_hw(struct AVS2Decoder_s *dec)
3188 {
3189 /*
3190 * Picture level ALF parameter configuration here
3191 */
3192 uint32_t data32;
3193 int32_t i, j;
3194 int32_t m_filters_per_group;
3195 struct avs2_decoder *avs2_dec = &dec->avs2_dec;
3196 struct ALFParam_s *m_alfPictureParam_y =
3197 &avs2_dec->m_alfPictureParam[0];
3198 struct ALFParam_s *m_alfPictureParam_cb =
3199 &avs2_dec->m_alfPictureParam[1];
3200 struct ALFParam_s *m_alfPictureParam_cr =
3201 &avs2_dec->m_alfPictureParam[2];
3202
3203 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
3204 "[t]alfy,cidx(%d),flag(%d),filters_per_group(%d),filterPattern[0]=0x%x,[15]=0x%x\n",
3205 m_alfPictureParam_y->componentID,
3206 m_alfPictureParam_y->alf_flag,
3207 m_alfPictureParam_y->filters_per_group,
3208 m_alfPictureParam_y->filterPattern[0],
3209 m_alfPictureParam_y->filterPattern[15]);
3210 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
3211 "[t]alfy,num_coeff(%d),coeffmulti[0][0]=0x%x,[0][1]=0x%x,[1][0]=0x%x,[1][1]=0x%x\n",
3212 m_alfPictureParam_y->num_coeff,
3213 m_alfPictureParam_y->coeffmulti[0][0],
3214 m_alfPictureParam_y->coeffmulti[0][1],
3215 m_alfPictureParam_y->coeffmulti[1][0],
3216 m_alfPictureParam_y->coeffmulti[1][1]);
3217
3218 /*Cr*/
3219 for (i = 0; i < 16; i++)
3220 dec->m_varIndTab[i] = 0;
3221 for (j = 0; j < 16; j++)
3222 for (i = 0; i < 9; i++)
3223 dec->m_filterCoeffSym[j][i] = 0;
3224 reconstructCoefInfo(dec, 2, m_alfPictureParam_cr);
3225 data32 =
3226 ((dec->m_filterCoeffSym[0][4] & 0xf) << 28) |
3227 ((dec->m_filterCoeffSym[0][3] & 0x7f) << 21) |
3228 ((dec->m_filterCoeffSym[0][2] & 0x7f) << 14) |
3229 ((dec->m_filterCoeffSym[0][1] & 0x7f) << 7) |
3230 ((dec->m_filterCoeffSym[0][0] & 0x7f) << 0);
3231 WRITE_VREG(HEVC_DBLK_CFGD, data32);
3232 data32 =
3233 ((dec->m_filterCoeffSym[0][8] & 0x7f) << 24) |
3234 ((dec->m_filterCoeffSym[0][7] & 0x7f) << 17) |
3235 ((dec->m_filterCoeffSym[0][6] & 0x7f) << 10) |
3236 ((dec->m_filterCoeffSym[0][5] & 0x7f) << 3) |
3237 (((dec->m_filterCoeffSym[0][4] >> 4) & 0x7) << 0);
3238 WRITE_VREG(HEVC_DBLK_CFGD, data32);
3239 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
3240 "[c] pic_alf_on_cr(%d), alf_cr_coef(%d %d %d %d %d %d %d %d %d)\n",
3241 m_alfPictureParam_cr->alf_flag,
3242 dec->m_filterCoeffSym[0][0],
3243 dec->m_filterCoeffSym[0][1],
3244 dec->m_filterCoeffSym[0][2],
3245 dec->m_filterCoeffSym[0][3],
3246 dec->m_filterCoeffSym[0][4],
3247 dec->m_filterCoeffSym[0][5],
3248 dec->m_filterCoeffSym[0][6],
3249 dec->m_filterCoeffSym[0][7],
3250 dec->m_filterCoeffSym[0][8]);
3251
3252 /* Cb*/
3253 for (j = 0; j < 16; j++)
3254 for (i = 0; i < 9; i++)
3255 dec->m_filterCoeffSym[j][i] = 0;
3256 reconstructCoefInfo(dec, 1, m_alfPictureParam_cb);
3257 data32 =
3258 ((dec->m_filterCoeffSym[0][4] & 0xf) << 28) |
3259 ((dec->m_filterCoeffSym[0][3] & 0x7f) << 21) |
3260 ((dec->m_filterCoeffSym[0][2] & 0x7f) << 14) |
3261 ((dec->m_filterCoeffSym[0][1] & 0x7f) << 7) |
3262 ((dec->m_filterCoeffSym[0][0] & 0x7f) << 0);
3263 WRITE_VREG(HEVC_DBLK_CFGD, data32);
3264 data32 =
3265 ((dec->m_filterCoeffSym[0][8] & 0x7f) << 24) |
3266 ((dec->m_filterCoeffSym[0][7] & 0x7f) << 17) |
3267 ((dec->m_filterCoeffSym[0][6] & 0x7f) << 10) |
3268 ((dec->m_filterCoeffSym[0][5] & 0x7f) << 3) |
3269 (((dec->m_filterCoeffSym[0][4] >> 4) & 0x7) << 0);
3270 WRITE_VREG(HEVC_DBLK_CFGD, data32);
3271 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
3272 "[c] pic_alf_on_cb(%d), alf_cb_coef(%d %d %d %d %d %d %d %d %d)\n",
3273 m_alfPictureParam_cb->alf_flag,
3274 dec->m_filterCoeffSym[0][0],
3275 dec->m_filterCoeffSym[0][1],
3276 dec->m_filterCoeffSym[0][2],
3277 dec->m_filterCoeffSym[0][3],
3278 dec->m_filterCoeffSym[0][4],
3279 dec->m_filterCoeffSym[0][5],
3280 dec->m_filterCoeffSym[0][6],
3281 dec->m_filterCoeffSym[0][7],
3282 dec->m_filterCoeffSym[0][8]);
3283
3284 /* Y*/
3285 for (j = 0; j < 16; j++)
3286 for (i = 0; i < 9; i++)
3287 dec->m_filterCoeffSym[j][i] = 0;
3288 reconstructCoefInfo(dec, 0, m_alfPictureParam_y);
3289 data32 =
3290 ((dec->m_varIndTab[7] & 0xf) << 28) |
3291 ((dec->m_varIndTab[6] & 0xf) << 24) |
3292 ((dec->m_varIndTab[5] & 0xf) << 20) |
3293 ((dec->m_varIndTab[4] & 0xf) << 16) |
3294 ((dec->m_varIndTab[3] & 0xf) << 12) |
3295 ((dec->m_varIndTab[2] & 0xf) << 8) |
3296 ((dec->m_varIndTab[1] & 0xf) << 4) |
3297 ((dec->m_varIndTab[0] & 0xf) << 0);
3298 WRITE_VREG(HEVC_DBLK_CFGD, data32);
3299 data32 = ((dec->m_varIndTab[15] & 0xf) << 28) |
3300 ((dec->m_varIndTab[14] & 0xf) << 24) |
3301 ((dec->m_varIndTab[13] & 0xf) << 20) |
3302 ((dec->m_varIndTab[12] & 0xf) << 16) |
3303 ((dec->m_varIndTab[11] & 0xf) << 12) |
3304 ((dec->m_varIndTab[10] & 0xf) << 8) |
3305 ((dec->m_varIndTab[9] & 0xf) << 4) |
3306 ((dec->m_varIndTab[8] & 0xf) << 0);
3307 WRITE_VREG(HEVC_DBLK_CFGD, data32);
3308 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
3309 "[c] pic_alf_on_y(%d), alf_y_tab(%d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d)\n",
3310 m_alfPictureParam_y->alf_flag,
3311 dec->m_varIndTab[0],
3312 dec->m_varIndTab[1],
3313 dec->m_varIndTab[2],
3314 dec->m_varIndTab[3],
3315 dec->m_varIndTab[4],
3316 dec->m_varIndTab[5],
3317 dec->m_varIndTab[6],
3318 dec->m_varIndTab[7],
3319 dec->m_varIndTab[8],
3320 dec->m_varIndTab[9],
3321 dec->m_varIndTab[10],
3322 dec->m_varIndTab[11],
3323 dec->m_varIndTab[12],
3324 dec->m_varIndTab[13],
3325 dec->m_varIndTab[14],
3326 dec->m_varIndTab[15]);
3327
3328 m_filters_per_group =
3329 (m_alfPictureParam_y->alf_flag == 0) ?
3330 1 : m_alfPictureParam_y->filters_per_group;
3331 for (i = 0; i < m_filters_per_group; i++) {
3332 data32 =
3333 ((dec->m_filterCoeffSym[i][4] & 0xf) << 28) |
3334 ((dec->m_filterCoeffSym[i][3] & 0x7f) << 21) |
3335 ((dec->m_filterCoeffSym[i][2] & 0x7f) << 14) |
3336 ((dec->m_filterCoeffSym[i][1] & 0x7f) << 7) |
3337 ((dec->m_filterCoeffSym[i][0] & 0x7f) << 0);
3338 WRITE_VREG(HEVC_DBLK_CFGD, data32);
3339 data32 =
3340 /*[31] last indication*/
3341 ((i == m_filters_per_group-1) << 31) |
3342 ((dec->m_filterCoeffSym[i][8] & 0x7f) << 24) |
3343 ((dec->m_filterCoeffSym[i][7] & 0x7f) << 17) |
3344 ((dec->m_filterCoeffSym[i][6] & 0x7f) << 10) |
3345 ((dec->m_filterCoeffSym[i][5] & 0x7f) << 3) |
3346 (((dec->m_filterCoeffSym[i][4] >> 4) & 0x7) << 0);
3347 WRITE_VREG(HEVC_DBLK_CFGD, data32);
3348 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
3349 "[c] alf_y_coef[%d](%d %d %d %d %d %d %d %d %d)\n",
3350 i, dec->m_filterCoeffSym[i][0],
3351 dec->m_filterCoeffSym[i][1],
3352 dec->m_filterCoeffSym[i][2],
3353 dec->m_filterCoeffSym[i][3],
3354 dec->m_filterCoeffSym[i][4],
3355 dec->m_filterCoeffSym[i][5],
3356 dec->m_filterCoeffSym[i][6],
3357 dec->m_filterCoeffSym[i][7],
3358 dec->m_filterCoeffSym[i][8]);
3359 }
3360 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
3361 "[c] cfgALF .done.\n");
3362 }
3363
3364 static void config_other_hw(struct AVS2Decoder_s *dec)
3365 {
3366 uint32_t data32;
3367 struct avs2_decoder *avs2_dec = &dec->avs2_dec;
3368 struct avs2_frame_s *cur_pic = avs2_dec->hc.cur_pic;
3369 int bit_depth = cur_pic->bit_depth;
3370 int losless_comp_header_size =
3371 compute_losless_comp_header_size(
3372 dec, cur_pic->pic_w,
3373 cur_pic->pic_h);
3374 int losless_comp_body_size =
3375 compute_losless_comp_body_size(
3376 dec, cur_pic->pic_w,
3377 cur_pic->pic_h, (bit_depth == AVS2_BITS_10));
3378 cur_pic->comp_body_size = losless_comp_body_size;
3379
3380 #ifdef LOSLESS_COMPRESS_MODE
3381 data32 = READ_VREG(HEVC_SAO_CTRL5);
3382 if (bit_depth == AVS2_BITS_10)
3383 data32 &= ~(1 << 9);
3384 else
3385 data32 |= (1 << 9);
3386
3387 WRITE_VREG(HEVC_SAO_CTRL5, data32);
3388
3389 #ifdef AVS2_10B_MMU
3390 /*bit[4] : paged_mem_mode*/
3391 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
3392 #else
3393 /*bit[3] smem mdoe*/
3394 if (bit_depth == AVS2_BITS_10)
3395 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0 << 3));
3396 else
3397 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (1 << 3));
3398 #endif
3399 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, (losless_comp_body_size >> 5));
3400 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,(0xff<<20) | (0xff<<10) | 0xff);*/
3401 WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
3402 WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
3403 WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
3404 #else
3405 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
3406 #endif
3407 }
3408
3409 static void avs2_config_work_space_hw(struct AVS2Decoder_s *dec)
3410 {
3411 struct BuffInfo_s *buf_spec = dec->work_space_buf;
3412 #ifdef LOSLESS_COMPRESS_MODE
3413 int losless_comp_header_size =
3414 compute_losless_comp_header_size(
3415 dec, dec->init_pic_w,
3416 dec->init_pic_h);
3417 int losless_comp_body_size =
3418 compute_losless_comp_body_size(dec,
3419 dec->init_pic_w,
3420 dec->init_pic_h, buf_alloc_depth == 10);
3421 #endif
3422 #ifdef AVS2_10B_MMU
3423 unsigned int data32;
3424 #endif
3425 if (debug && dec->init_flag == 0)
3426 avs2_print(dec, 0,
3427 "%s %x %x %x %x %x %x %x %x %x %x %x %x %x\n",
3428 __func__,
3429 buf_spec->ipp.buf_start,
3430 buf_spec->start_adr,
3431 buf_spec->short_term_rps.buf_start,
3432 buf_spec->rcs.buf_start,
3433 buf_spec->sps.buf_start,
3434 buf_spec->pps.buf_start,
3435 buf_spec->sao_up.buf_start,
3436 buf_spec->swap_buf.buf_start,
3437 buf_spec->swap_buf2.buf_start,
3438 buf_spec->scalelut.buf_start,
3439 buf_spec->dblk_para.buf_start,
3440 buf_spec->dblk_data.buf_start,
3441 buf_spec->dblk_data2.buf_start);
3442 WRITE_VREG(HEVCD_IPP_LINEBUFF_BASE, buf_spec->ipp.buf_start);
3443 if ((debug & AVS2_DBG_SEND_PARAM_WITH_REG) == 0)
3444 WRITE_VREG(HEVC_RPM_BUFFER, (u32)dec->rpm_phy_addr);
3445 WRITE_VREG(AVS2_ALF_SWAP_BUFFER, buf_spec->short_term_rps.buf_start);
3446 WRITE_VREG(HEVC_RCS_BUFFER, buf_spec->rcs.buf_start);
3447 WRITE_VREG(HEVC_SPS_BUFFER, buf_spec->sps.buf_start);
3448 WRITE_VREG(HEVC_PPS_BUFFER, buf_spec->pps.buf_start);
3449 WRITE_VREG(HEVC_SAO_UP, buf_spec->sao_up.buf_start);
3450 #ifdef AVS2_10B_MMU
3451 WRITE_VREG(AVS2_MMU_MAP_BUFFER, dec->frame_mmu_map_phy_addr);
3452 #else
3453 WRITE_VREG(HEVC_STREAM_SWAP_BUFFER, buf_spec->swap_buf.buf_start);
3454 #endif
3455 WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2, buf_spec->swap_buf2.buf_start);
3456 WRITE_VREG(HEVC_SCALELUT, buf_spec->scalelut.buf_start);
3457
3458 /* cfg_p_addr */
3459 WRITE_VREG(HEVC_DBLK_CFG4, buf_spec->dblk_para.buf_start);
3460 /* cfg_d_addr */
3461 WRITE_VREG(HEVC_DBLK_CFG5, buf_spec->dblk_data.buf_start);
3462
3463 WRITE_VREG(HEVC_DBLK_CFGE, buf_spec->dblk_data2.buf_start);
3464
3465 #ifdef LOSLESS_COMPRESS_MODE
3466 data32 = READ_VREG(HEVC_SAO_CTRL5);
3467 #if 1
3468 data32 &= ~(1<<9);
3469 #else
3470 if (params->p.bit_depth != 0x00)
3471 data32 &= ~(1<<9);
3472 else
3473 data32 |= (1<<9);
3474 #endif
3475 WRITE_VREG(HEVC_SAO_CTRL5, data32);
3476 #ifdef AVS2_10B_MMU
3477 /*bit[4] : paged_mem_mode*/
3478 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
3479 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0);
3480 #else
3481 /* bit[3] smem mode*/
3482 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0<<3));
3483
3484 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, (losless_comp_body_size >> 5));
3485 #endif
3486 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,(losless_comp_body_size >> 5));*/
3487 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,(0xff<<20) | (0xff<<10) | 0xff);*/
3488 /*8-bit mode */
3489 WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
3490 WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
3491 WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
3492 #else
3493 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
3494 #endif
3495
3496 #ifdef AVS2_10B_MMU
3497 WRITE_VREG(HEVC_SAO_MMU_VH0_ADDR, buf_spec->mmu_vbh.buf_start);
3498 WRITE_VREG(HEVC_SAO_MMU_VH1_ADDR, buf_spec->mmu_vbh.buf_start
3499 + buf_spec->mmu_vbh.buf_size/2);
3500 /*data32 = READ_VREG(HEVC_SAO_CTRL9);*/
3501 /*data32 |= 0x1;*/
3502 /*WRITE_VREG(HEVC_SAO_CTRL9, data32);*/
3503
3504 /* use HEVC_CM_HEADER_START_ADDR */
3505 data32 = READ_VREG(HEVC_SAO_CTRL5);
3506 data32 |= (1<<10);
3507 #if 1
3508 if (debug & AVS2_DBG_FORCE_UNCOMPRESS)
3509 data32 |= 0x80;
3510 #endif
3511 WRITE_VREG(HEVC_SAO_CTRL5, data32);
3512
3513 #endif
3514
3515 WRITE_VREG(LMEM_DUMP_ADR, (u32)dec->lmem_phy_addr);
3516 #if 1
3517 /*MULTI_INSTANCE_SUPPORT*/
3518 /*new added in simulation???*/
3519 WRITE_VREG(HEVC_MPRED_ABV_START_ADDR, buf_spec->mpred_above.buf_start);
3520 #endif
3521 }
3522
3523 static void decomp_perfcount_reset(void)
3524 {
3525 if (debug & AVS2_DBG_CACHE)
3526 pr_info("[cache_util.c] Entered decomp_perfcount_reset...\n");
3527 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x1);
3528 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x0);
3529 return;
3530 }
3531
3532 static void mcrcc_perfcount_reset(void)
3533 {
3534 if (debug & AVS2_DBG_CACHE)
3535 pr_info("[cache_util.c] Entered mcrcc_perfcount_reset...\n");
3536 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x1);
3537 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x0);
3538 return;
3539 }
3540
3541 static void avs2_init_decoder_hw(struct AVS2Decoder_s *dec)
3542 {
3543 unsigned int data32;
3544 unsigned int decode_mode;
3545 int i;
3546
3547 /*if (debug & AVS2_DBG_BUFMGR_MORE)
3548 pr_info("%s\n", __func__);*/
3549 data32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
3550 #if 1
3551 /* set bit 31~29 to 3 if HEVC_STREAM_FIFO_CTL[29] is 1 */
3552 data32 &= ~(7 << 29);
3553 data32 |= (3 << 29);
3554 #endif
3555 data32 = data32 |
3556 (1 << 24) |/*stream_buffer_empty_int_amrisc_enable*/
3557 (1 << 22) |/*stream_fifo_empty_int_amrisc_enable*/
3558 (1 << 7) |/*dec_done_int_cpu_enable*/
3559 (1 << 4) |/*startcode_found_int_cpu_enable*/
3560 (0 << 3) |/*startcode_found_int_amrisc_enable*/
3561 (1 << 0) /*parser_int_enable*/
3562 ;
3563 WRITE_VREG(HEVC_PARSER_INT_CONTROL, data32);
3564
3565 data32 = READ_VREG(HEVC_SHIFT_STATUS);
3566 data32 = data32 |
3567 (0 << 1) |/*emulation_check_off VP9
3568 do not have emulation*/
3569 (1 << 0)/*startcode_check_on*/
3570 ;
3571 WRITE_VREG(HEVC_SHIFT_STATUS, data32);
3572 WRITE_VREG(HEVC_SHIFT_CONTROL,
3573 (6 << 20) | /* emu_push_bits (6-bits for AVS2)*/
3574 (0 << 19) | /* emu_3_enable, maybe turned on in microcode*/
3575 (0 << 18) | /* emu_2_enable, maybe turned on in microcode*/
3576 (0 << 17) | /* emu_1_enable, maybe turned on in microcode*/
3577 (0 << 16) | /* emu_0_enable, maybe turned on in microcode*/
3578 (0 << 14) | /*disable_start_code_protect*/
3579 (3 << 6) | /* sft_valid_wr_position*/
3580 (2 << 4) | /* emulate_code_length_sub_1*/
3581 (2 << 1) | /* start_code_length_sub_1*/
3582 (1 << 0) /* stream_shift_enable*/
3583 );
3584
3585 WRITE_VREG(HEVC_SHIFT_LENGTH_PROTECT,
3586 (0 << 30) | /*data_protect_fill_00_enable*/
3587 (1 << 29) /*data_protect_fill_ff_enable*/
3588 );
3589 WRITE_VREG(HEVC_CABAC_CONTROL,
3590 (1 << 0)/*cabac_enable*/
3591 );
3592
3593 WRITE_VREG(HEVC_PARSER_CORE_CONTROL,
3594 (1 << 0)/* hevc_parser_core_clk_en*/
3595 );
3596
3597
3598 WRITE_VREG(HEVC_DEC_STATUS_REG, 0);
3599
3600 /*Initial IQIT_SCALELUT memory -- just to avoid X in simulation*/
3601
3602 WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0);/*cfg_p_addr*/
3603 for (i = 0; i < 1024; i++)
3604 WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, 0);
3605
3606
3607 #ifdef ENABLE_SWAP_TEST
3608 WRITE_VREG(HEVC_STREAM_SWAP_TEST, 100);
3609 #else
3610 WRITE_VREG(HEVC_STREAM_SWAP_TEST, 0);
3611 #endif
3612 if (!dec->m_ins_flag)
3613 decode_mode = DECODE_MODE_SINGLE;
3614 else if (vdec_frame_based(hw_to_vdec(dec)))
3615 decode_mode = DECODE_MODE_MULTI_FRAMEBASE;
3616 else
3617 decode_mode = DECODE_MODE_MULTI_STREAMBASE;
3618 if (dec->avs2_dec.bufmgr_error_flag &&
3619 (error_handle_policy & 0x1)) {
3620 dec->bufmgr_error_count++;
3621 dec->avs2_dec.bufmgr_error_flag = 0;
3622 if (dec->bufmgr_error_count >
3623 (re_search_seq_threshold & 0xff)
3624 && dec->frame_count >
3625 ((re_search_seq_threshold >> 8) & 0xff)) {
3626 struct avs2_decoder *avs2_dec = &dec->avs2_dec;
3627 dec->start_decoding_flag = 0;
3628 avs2_dec->hd.vec_flag = 1;
3629 dec->skip_PB_before_I = 1;
3630 avs2_print(dec, 0,
3631 "!!Bufmgr error, search seq again (0x%x %d %d)\n",
3632 error_handle_policy,
3633 dec->frame_count,
3634 dec->bufmgr_error_count);
3635 dec->bufmgr_error_count = 0;
3636 }
3637 }
3638 decode_mode |= (dec->start_decoding_flag << 16);
3639
3640 WRITE_VREG(DECODE_MODE, decode_mode);
3641 WRITE_VREG(HEVC_DECODE_SIZE, 0);
3642 WRITE_VREG(HEVC_DECODE_COUNT, 0);
3643
3644 /*Send parser_cmd*/
3645 WRITE_VREG(HEVC_PARSER_CMD_WRITE, (1 << 16) | (0 << 0));
3646 for (i = 0; i < PARSER_CMD_NUMBER; i++)
3647 WRITE_VREG(HEVC_PARSER_CMD_WRITE, parser_cmd[i]);
3648 WRITE_VREG(HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0);
3649 WRITE_VREG(HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1);
3650 WRITE_VREG(HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2);
3651
3652
3653 WRITE_VREG(HEVC_PARSER_IF_CONTROL,
3654 (1 << 9) | /* parser_alf_if_en*/
3655 /* (1 << 8) |*/ /*sao_sw_pred_enable*/
3656 (1 << 5) | /*parser_sao_if_en*/
3657 (1 << 2) | /*parser_mpred_if_en*/
3658 (1 << 0) /*parser_scaler_if_en*/
3659 );
3660
3661 #ifdef MULTI_INSTANCE_SUPPORT
3662 WRITE_VREG(HEVC_MPRED_INT_STATUS, (1<<31));
3663
3664 WRITE_VREG(HEVC_PARSER_RESULT_3, 0xffffffff);
3665
3666 for (i = 0; i < 8; i++)
3667 data32 = READ_VREG(HEVC_MPRED_ABV_START_ADDR);
3668
3669 WRITE_VREG(DOS_SW_RESET3, (1<<18)); /* reset mpred */
3670 WRITE_VREG(DOS_SW_RESET3, 0);
3671 WRITE_VREG(HEVC_MPRED_ABV_START_ADDR, data32);
3672 WRITE_VREG(HEVC_MPRED_ABV_START_ADDR, data32);
3673 WRITE_VREG(HEVC_MPRED_ABV_START_ADDR, data32);
3674 #endif
3675 /*End of Multi-instance*/
3676 /*Changed to Start MPRED in microcode*/
3677 /*
3678 pr_info("[test.c] Start MPRED\n");
3679 WRITE_VREG(HEVC_MPRED_INT_STATUS,
3680 (1<<31)
3681 );
3682 */
3683
3684 /*AVS2 default seq_wq_matrix config*/
3685
3686 avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
3687 "Config AVS2 default seq_wq_matrix ...\n");
3688 /*4x4*/
3689 /* default seq_wq_matrix_4x4 begin address*/
3690 WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 64);
3691 for (i = 0; i < 16; i++)
3692 WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, g_WqMDefault4x4[i]);
3693
3694 /*8x8*/
3695 /*default seq_wq_matrix_8x8 begin address*/
3696 WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0);
3697 for (i = 0; i < 64; i++)
3698 WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, g_WqMDefault8x8[i]);
3699
3700
3701 WRITE_VREG(HEVCD_IPP_TOP_CNTL,
3702 (0 << 1) | /*enable ipp*/
3703 (1 << 0) /*software reset ipp and mpp*/
3704 );
3705 WRITE_VREG(HEVCD_IPP_TOP_CNTL,
3706 (1 << 1) | /*enable ipp*/
3707 (0 << 0) /*software reset ipp and mpp*/
3708 );
3709 #if 0
3710 /*AVS2_10B_NV21*/
3711 /*Enable NV21 reference read mode for MC*/
3712 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
3713 #endif
3714 /* Init dblk*/
3715 data32 = READ_VREG(HEVC_DBLK_CFGB);
3716 data32 |= (2 << 0);
3717 /* [3:0] cfg_video_type -> AVS2*/
3718
3719 data32 &= (~0x300); /*[8]:first write enable (compress)
3720 [9]:double write enable (uncompress)*/
3721 if (get_double_write_mode(dec) == 0)
3722 data32 |= (0x1 << 8); /*enable first write*/
3723 else if (get_double_write_mode(dec) == 0x10)
3724 data32 |= (0x1 << 9); /*double write only*/
3725 else
3726 data32 |= ((0x1 << 8) | (0x1 << 9));
3727 WRITE_VREG(HEVC_DBLK_CFGB, data32);
3728
3729 WRITE_VREG(HEVC_DBLK_CFG0, (1 << 0)); /* [0] rst_sync*/
3730 avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
3731 "Bitstream level Init for DBLK .Done.\n");
3732
3733 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
3734 mcrcc_perfcount_reset();
3735 decomp_perfcount_reset();
3736 }
3737
3738 return;
3739 }
3740
3741
3742 #ifdef CONFIG_HEVC_CLK_FORCED_ON
3743 static void config_avs2_clk_forced_on(void)
3744 {
3745 unsigned int rdata32;
3746 /*IQIT*/
3747 rdata32 = READ_VREG(HEVC_IQIT_CLK_RST_CTRL);
3748 WRITE_VREG(HEVC_IQIT_CLK_RST_CTRL, rdata32 | (0x1 << 2));
3749
3750 /* DBLK*/
3751 rdata32 = READ_VREG(HEVC_DBLK_CFG0);
3752 WRITE_VREG(HEVC_DBLK_CFG0, rdata32 | (0x1 << 2));
3753
3754 /* SAO*/
3755 rdata32 = READ_VREG(HEVC_SAO_CTRL1);
3756 WRITE_VREG(HEVC_SAO_CTRL1, rdata32 | (0x1 << 2));
3757
3758 /*MPRED*/
3759 rdata32 = READ_VREG(HEVC_MPRED_CTRL1);
3760 WRITE_VREG(HEVC_MPRED_CTRL1, rdata32 | (0x1 << 24));
3761
3762 /* PARSER*/
3763 rdata32 = READ_VREG(HEVC_STREAM_CONTROL);
3764 WRITE_VREG(HEVC_STREAM_CONTROL, rdata32 | (0x1 << 15));
3765 rdata32 = READ_VREG(HEVC_SHIFT_CONTROL);
3766 WRITE_VREG(HEVC_SHIFT_CONTROL, rdata32 | (0x1 << 15));
3767 rdata32 = READ_VREG(HEVC_CABAC_CONTROL);
3768 WRITE_VREG(HEVC_CABAC_CONTROL, rdata32 | (0x1 << 13));
3769 rdata32 = READ_VREG(HEVC_PARSER_CORE_CONTROL);
3770 WRITE_VREG(HEVC_PARSER_CORE_CONTROL, rdata32 | (0x1 << 15));
3771 rdata32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
3772 WRITE_VREG(HEVC_PARSER_INT_CONTROL, rdata32 | (0x1 << 15));
3773 rdata32 = READ_VREG(HEVC_PARSER_IF_CONTROL);
3774 WRITE_VREG(HEVC_PARSER_IF_CONTROL,
3775 rdata32 | (0x1 << 6) | (0x1 << 3) | (0x1 << 1));
3776
3777 /*IPP*/
3778 rdata32 = READ_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG);
3779 WRITE_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG, rdata32 | 0xffffffff);
3780
3781 /* MCRCC*/
3782 rdata32 = READ_VREG(HEVCD_MCRCC_CTL1);
3783 WRITE_VREG(HEVCD_MCRCC_CTL1, rdata32 | (0x1 << 3));
3784 }
3785 #endif
3786
3787
3788
3789
3790
3791 static struct AVS2Decoder_s gAVS2Decoder;
3792
3793 static void avs2_local_uninit(struct AVS2Decoder_s *dec)
3794 {
3795 dec->rpm_ptr = NULL;
3796 dec->lmem_ptr = NULL;
3797 if (dec->rpm_addr) {
3798 dma_free_coherent(amports_get_dma_device(),
3799 RPM_BUF_SIZE, dec->rpm_addr,
3800 dec->rpm_phy_addr);
3801 dec->rpm_addr = NULL;
3802 }
3803 if (dec->lmem_addr) {
3804 if (dec->lmem_phy_addr)
3805 dma_free_coherent(amports_get_dma_device(),
3806 LMEM_BUF_SIZE, dec->lmem_addr,
3807 dec->lmem_phy_addr);
3808 dec->lmem_addr = NULL;
3809 }
3810
3811 #ifdef AVS2_10B_MMU
3812 if (dec->frame_mmu_map_addr) {
3813 if (dec->frame_mmu_map_phy_addr)
3814 dma_free_coherent(amports_get_dma_device(),
3815 get_frame_mmu_map_size(dec), dec->frame_mmu_map_addr,
3816 dec->frame_mmu_map_phy_addr);
3817 dec->frame_mmu_map_addr = NULL;
3818 }
3819 #endif
3820 if (dec->gvs)
3821 vfree(dec->gvs);
3822 dec->gvs = NULL;
3823 }
3824
3825 static int avs2_local_init(struct AVS2Decoder_s *dec)
3826 {
3827 int ret = -1;
3828 /*int losless_comp_header_size, losless_comp_body_size;*/
3829
3830 struct BuffInfo_s *cur_buf_info = NULL;
3831
3832 cur_buf_info = &dec->work_space_buf_store;
3833
3834 if (vdec_is_support_4k()) {
3835 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
3836 memcpy(cur_buf_info, &amvavs2_workbuff_spec[2], /* 8k */
3837 sizeof(struct BuffInfo_s));
3838 else
3839 memcpy(cur_buf_info, &amvavs2_workbuff_spec[1], /* 4k */
3840 sizeof(struct BuffInfo_s));
3841 } else
3842 memcpy(cur_buf_info, &amvavs2_workbuff_spec[0],/* 1080p */
3843 sizeof(struct BuffInfo_s));
3844
3845 cur_buf_info->start_adr = dec->buf_start;
3846 #ifndef AVS2_10B_MMU
3847 dec->mc_buf_spec.buf_end = dec->buf_start + dec->buf_size;
3848 #endif
3849
3850 init_buff_spec(dec, cur_buf_info);
3851
3852 init_avs2_decoder(&dec->avs2_dec);
3853
3854 #ifdef AVS2_10B_MMU
3855 avs2_bufmgr_init(dec, cur_buf_info, NULL);
3856 #else
3857 dec->mc_buf_spec.buf_start = (cur_buf_info->end_adr + 0xffff)
3858 & (~0xffff);
3859 dec->mc_buf_spec.buf_size = (dec->mc_buf_spec.buf_end
3860 - dec->mc_buf_spec.buf_start);
3861 if (debug) {
3862 pr_err("dec->mc_buf_spec.buf_start %x-%x\n",
3863 dec->mc_buf_spec.buf_start,
3864 dec->mc_buf_spec.buf_start +
3865 dec->mc_buf_spec.buf_size);
3866 }
3867 avs2_bufmgr_init(dec, cur_buf_info, &dec->mc_buf_spec);
3868 #endif
3869
3870 if (!vdec_is_support_4k()
3871 && (buf_alloc_width > 1920 && buf_alloc_height > 1088)) {
3872 buf_alloc_width = 1920;
3873 buf_alloc_height = 1088;
3874 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
3875 buf_alloc_width = 8192;
3876 buf_alloc_height = 4608;
3877 }
3878 dec->init_pic_w = buf_alloc_width ? buf_alloc_width :
3879 (dec->vavs2_amstream_dec_info.width ?
3880 dec->vavs2_amstream_dec_info.width :
3881 dec->work_space_buf->max_width);
3882 dec->init_pic_h = buf_alloc_height ? buf_alloc_height :
3883 (dec->vavs2_amstream_dec_info.height ?
3884 dec->vavs2_amstream_dec_info.height :
3885 dec->work_space_buf->max_height);
3886 #if 0
3887 /*ndef MV_USE_FIXED_BUF*/
3888 if (init_mv_buf_list(dec) < 0) {
3889 pr_err("%s: init_mv_buf_list fail\n", __func__);
3890 return -1;
3891 }
3892 #endif
3893
3894 #ifndef AVS2_10B_MMU
3895 init_buf_list(dec);
3896 #else
3897 dec->used_buf_num = max_buf_num + dec->dynamic_buf_margin;
3898 if (dec->used_buf_num > MAX_BUF_NUM)
3899 dec->used_buf_num = MAX_BUF_NUM;
3900 if (dec->used_buf_num > FRAME_BUFFERS)
3901 dec->used_buf_num = FRAME_BUFFERS;
3902 #endif
3903 dec->avs2_dec.ref_maxbuffer = dec->used_buf_num - 1;
3904 /*init_pic_list(dec);*/
3905
3906 pts_unstable = ((unsigned long)(dec->vavs2_amstream_dec_info.param)
3907 & 0x40) >> 6;
3908
3909 if ((debug & AVS2_DBG_SEND_PARAM_WITH_REG) == 0) {
3910 dec->rpm_addr = dma_alloc_coherent(amports_get_dma_device(),
3911 RPM_BUF_SIZE,
3912 &dec->rpm_phy_addr, GFP_KERNEL);
3913 if (dec->rpm_addr == NULL) {
3914 pr_err("%s: failed to alloc rpm buffer\n", __func__);
3915 return -1;
3916 }
3917 avs2_print(dec, AVS2_DBG_BUFMGR,
3918 "rpm_phy_addr %x\n", (u32) dec->rpm_phy_addr);
3919 dec->rpm_ptr = dec->rpm_addr;
3920 }
3921
3922 dec->lmem_addr = dma_alloc_coherent(amports_get_dma_device(),
3923 LMEM_BUF_SIZE,
3924 &dec->lmem_phy_addr, GFP_KERNEL);
3925 if (dec->lmem_addr == NULL) {
3926 pr_err("%s: failed to alloc lmem buffer\n", __func__);
3927 return -1;
3928 } else
3929 avs2_print(dec, AVS2_DBG_BUFMGR,
3930 "%s, lmem_phy_addr %x\n",
3931 __func__, (u32)dec->lmem_phy_addr);
3932
3933 dec->lmem_ptr = dec->lmem_addr;
3934
3935
3936 #ifdef AVS2_10B_MMU
3937 dec->frame_mmu_map_addr = dma_alloc_coherent(amports_get_dma_device(),
3938 get_frame_mmu_map_size(dec),
3939 &dec->frame_mmu_map_phy_addr, GFP_KERNEL);
3940 if (dec->frame_mmu_map_addr == NULL) {
3941 pr_err("%s: failed to alloc count_buffer\n", __func__);
3942 return -1;
3943 }
3944 memset(dec->frame_mmu_map_addr, 0, get_frame_mmu_map_size(dec));
3945 #endif
3946
3947 ret = 0;
3948 return ret;
3949 }
3950
3951 /********************************************
3952 * Mailbox command
3953 ********************************************/
3954 #define CMD_FINISHED 0
3955 #define CMD_ALLOC_VIEW 1
3956 #define CMD_FRAME_DISPLAY 3
3957 #define CMD_DEBUG 10
3958
3959
3960 #define DECODE_BUFFER_NUM_MAX 32
3961 #define DISPLAY_BUFFER_NUM 6
3962
3963 #define video_domain_addr(adr) (adr&0x7fffffff)
3964 #define DECODER_WORK_SPACE_SIZE 0x800000
3965
3966 #define spec2canvas(x) \
3967 (((x)->uv_canvas_index << 16) | \
3968 ((x)->uv_canvas_index << 8) | \
3969 ((x)->y_canvas_index << 0))
3970
3971
3972 static void set_canvas(struct AVS2Decoder_s *dec,
3973 struct avs2_frame_s *pic)
3974 {
3975 int canvas_w = ALIGN(pic->pic_w, 64)/4;
3976 int canvas_h = ALIGN(pic->pic_h, 32)/4;
3977 int blkmode = mem_map_mode;
3978 struct vdec_s *vdec = hw_to_vdec(dec);
3979 /*CANVAS_BLKMODE_64X32*/
3980 if (pic->double_write_mode) {
3981 canvas_w = pic->pic_w /
3982 get_double_write_ratio(dec,
3983 pic->double_write_mode);
3984 canvas_h = pic->pic_h /
3985 get_double_write_ratio(dec,
3986 pic->double_write_mode);
3987
3988 if (mem_map_mode == 0)
3989 canvas_w = ALIGN(canvas_w, 32);
3990 else
3991 canvas_w = ALIGN(canvas_w, 64);
3992 canvas_h = ALIGN(canvas_h, 32);
3993
3994 if (vdec->parallel_dec == 1) {
3995 if (pic->y_canvas_index == -1)
3996 pic->y_canvas_index = vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
3997 if (pic->uv_canvas_index == -1)
3998 pic->uv_canvas_index = vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
3999 } else {
4000 pic->y_canvas_index = 128 + pic->index * 2;
4001 pic->uv_canvas_index = 128 + pic->index * 2 + 1;
4002 }
4003
4004 canvas_config_ex(pic->y_canvas_index,
4005 pic->dw_y_adr, canvas_w, canvas_h,
4006 CANVAS_ADDR_NOWRAP, blkmode, 0x7);
4007 canvas_config_ex(pic->uv_canvas_index,
4008 pic->dw_u_v_adr, canvas_w, canvas_h,
4009 CANVAS_ADDR_NOWRAP, blkmode, 0x7);
4010 #ifdef MULTI_INSTANCE_SUPPORT
4011 pic->canvas_config[0].phy_addr =
4012 pic->dw_y_adr;
4013 pic->canvas_config[0].width =
4014 canvas_w;
4015 pic->canvas_config[0].height =
4016 canvas_h;
4017 pic->canvas_config[0].block_mode =
4018 blkmode;
4019 pic->canvas_config[0].endian = 7;
4020
4021 pic->canvas_config[1].phy_addr =
4022 pic->dw_u_v_adr;
4023 pic->canvas_config[1].width =
4024 canvas_w;
4025 pic->canvas_config[1].height =
4026 canvas_h;
4027 pic->canvas_config[1].block_mode =
4028 blkmode;
4029 pic->canvas_config[1].endian = 7;
4030 #endif
4031 } else {
4032 #ifndef AVS2_10B_MMU
4033 if (vdec->parallel_dec == 1) {
4034 if (pic->y_canvas_index == -1)
4035 pic->y_canvas_index = vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
4036 if (pic->uv_canvas_index == -1)
4037 pic->uv_canvas_index = vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
4038 } else {
4039 pic->y_canvas_index = 128 + pic->index;
4040 pic->uv_canvas_index = 128 + pic->index;
4041 }
4042
4043 canvas_config_ex(pic->y_canvas_index,
4044 pic->mc_y_adr, canvas_w, canvas_h,
4045 CANVAS_ADDR_NOWRAP, blkmode, 0x7);
4046 canvas_config_ex(pic->uv_canvas_index,
4047 pic->mc_u_v_adr, canvas_w, canvas_h,
4048 CANVAS_ADDR_NOWRAP, blkmode, 0x7);
4049 #endif
4050 }
4051 }
4052
4053 static void set_frame_info(struct AVS2Decoder_s *dec, struct vframe_s *vf)
4054 {
4055 unsigned int ar;
4056
4057 vf->duration = dec->frame_dur;
4058 vf->duration_pulldown = 0;
4059 vf->flag = 0;
4060 vf->prop.master_display_colour = dec->vf_dp;
4061 vf->signal_type = dec->video_signal_type;
4062
4063 ar = min_t(u32, dec->frame_ar, DISP_RATIO_ASPECT_RATIO_MAX);
4064 vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT);
4065
4066 vf->sidebind_type = dec->sidebind_type;
4067 vf->sidebind_channel_id = dec->sidebind_channel_id;
4068
4069 return;
4070 }
4071
4072 static int vavs2_vf_states(struct vframe_states *states, void *op_arg)
4073 {
4074 struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)op_arg;
4075
4076 states->vf_pool_size = VF_POOL_SIZE;
4077 states->buf_free_num = kfifo_len(&dec->newframe_q);
4078 states->buf_avail_num = kfifo_len(&dec->display_q);
4079
4080 if (step == 2)
4081 states->buf_avail_num = 0;
4082 return 0;
4083 }
4084
4085 static struct vframe_s *vavs2_vf_peek(void *op_arg)
4086 {
4087 struct vframe_s *vf;
4088 struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)op_arg;
4089 if (step == 2)
4090 return NULL;
4091
4092 if (force_disp_pic_index & 0x100) {
4093 if (force_disp_pic_index & 0x200)
4094 return NULL;
4095 return &dec->vframe_dummy;
4096 }
4097
4098 if (kfifo_peek(&dec->display_q, &vf))
4099 return vf;
4100
4101 return NULL;
4102 }
4103
4104 static struct avs2_frame_s *get_pic_by_index(
4105 struct AVS2Decoder_s *dec, int index)
4106 {
4107 int i;
4108 struct avs2_frame_s *pic = NULL;
4109 if (index == (dec->used_buf_num - 1))
4110 pic = dec->avs2_dec.m_bg;
4111 else if (index >= 0 && index < dec->used_buf_num) {
4112 for (i = 0; i < dec->used_buf_num; i++) {
4113 if (dec->avs2_dec.fref[i]->index == index)
4114 pic = dec->avs2_dec.fref[i];
4115 }
4116 }
4117 return pic;
4118 }
4119
4120 static struct vframe_s *vavs2_vf_get(void *op_arg)
4121 {
4122 struct vframe_s *vf;
4123 struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)op_arg;
4124 if (step == 2)
4125 return NULL;
4126 else if (step == 1)
4127 step = 2;
4128
4129 if (force_disp_pic_index & 0x100) {
4130 int idx = force_disp_pic_index & 0xff;
4131 struct avs2_frame_s *pic = NULL;
4132 if (idx >= 0
4133 && idx < dec->avs2_dec.ref_maxbuffer)
4134 pic = get_pic_by_index(dec, idx);
4135 if (pic == NULL)
4136 return NULL;
4137 if (force_disp_pic_index & 0x200)
4138 return NULL;
4139
4140 vf = &dec->vframe_dummy;
4141
4142 set_vframe(dec, vf, pic, 1);
4143
4144 force_disp_pic_index |= 0x200;
4145 return vf;
4146 }
4147
4148 if (kfifo_get(&dec->display_q, &vf)) {
4149 uint8_t index = vf->index & 0xff;
4150 if (index < dec->used_buf_num) {
4151 struct avs2_frame_s *pic = get_pic_by_index(dec, index);
4152 if (pic == NULL &&
4153 (debug & AVS2_DBG_PIC_LEAK)) {
4154 int i;
4155 avs2_print(dec, 0,
4156 "%s error index 0x%x pic not exist\n",
4157 __func__, index);
4158 dump_pic_list(dec);
4159 for (i = 0; i < 10; i++) {
4160 pic = get_pic_by_index(dec, index);
4161 pr_info("pic = %p\n", pic);
4162 }
4163
4164 if (debug & AVS2_DBG_PIC_LEAK)
4165 debug |= AVS2_DBG_PIC_LEAK_WAIT;
4166 return NULL;
4167 }
4168 dec->vf_get_count++;
4169 if (pic)
4170 avs2_print(dec, AVS2_DBG_BUFMGR,
4171 "%s index 0x%x pos %d getcount %d type 0x%x w/h %d/%d, pts %d, %lld\n",
4172 __func__, index,
4173 pic->imgtr_fwRefDistance_bak,
4174 dec->vf_get_count,
4175 vf->type,
4176 vf->width, vf->height,
4177 vf->pts,
4178 vf->pts_us64);
4179 return vf;
4180 }
4181 }
4182 return NULL;
4183 }
4184
4185 static void vavs2_vf_put(struct vframe_s *vf, void *op_arg)
4186 {
4187 struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)op_arg;
4188 uint8_t index = vf->index & 0xff;
4189
4190 if (vf == (&dec->vframe_dummy))
4191 return;
4192
4193 kfifo_put(&dec->newframe_q, (const struct vframe_s *)vf);
4194 dec->vf_put_count++;
4195 avs2_print(dec, AVS2_DBG_BUFMGR,
4196 "%s index putcount 0x%x %d\n",
4197 __func__, vf->index,
4198 dec->vf_put_count);
4199
4200 if (index < dec->used_buf_num) {
4201 unsigned long flags;
4202 struct avs2_frame_s *pic;
4203
4204 lock_buffer(dec, flags);
4205 pic = get_pic_by_index(dec, index);
4206 if (pic && pic->vf_ref > 0)
4207 pic->vf_ref--;
4208 else {
4209 if (pic)
4210 avs2_print(dec, 0,
4211 "%s, error pic (index %d) vf_ref is %d\n",
4212 __func__, index, pic->vf_ref);
4213 else
4214 avs2_print(dec, 0,
4215 "%s, error pic (index %d) is NULL\n",
4216 __func__, index);
4217 }
4218 if (dec->wait_buf)
4219 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG,
4220 0x1);
4221 dec->last_put_idx = index;
4222 dec->new_frame_displayed++;
4223 unlock_buffer(dec, flags);
4224 }
4225
4226 }
4227
4228 static int vavs2_event_cb(int type, void *data, void *private_data)
4229 {
4230 return 0;
4231 }
4232
4233 static struct avs2_frame_s *get_disp_pic(struct AVS2Decoder_s *dec)
4234 {
4235 struct avs2_decoder *avs2_dec = &dec->avs2_dec;
4236 struct avs2_frame_s *pic = NULL;
4237 int32_t j;
4238 int32_t pre_disp_count_min = 0x7fffffff;
4239 for (j = 0; j < avs2_dec->ref_maxbuffer; j++) {
4240 if (avs2_dec->fref[j]->to_prepare_disp &&
4241 avs2_dec->fref[j]->to_prepare_disp <
4242 pre_disp_count_min) {
4243 pre_disp_count_min =
4244 avs2_dec->fref[j]->to_prepare_disp;
4245 pic = avs2_dec->fref[j];
4246 }
4247 }
4248 if (pic)
4249 pic->to_prepare_disp = 0;
4250
4251 return pic;
4252
4253 }
4254
4255
4256
4257 static void fill_frame_info(struct AVS2Decoder_s *dec,
4258 struct avs2_frame_s *pic, unsigned int framesize, unsigned int pts)
4259 {
4260 struct vframe_qos_s *vframe_qos = &dec->vframe_qos;
4261
4262 if (pic->slice_type == I_IMG)
4263 vframe_qos->type = 1;
4264 else if (pic->slice_type == P_IMG)
4265 vframe_qos->type = 2;
4266 else if (pic->slice_type == B_IMG)
4267 vframe_qos->type = 3;
4268 /*
4269 #define SHOW_QOS_INFO
4270 */
4271 if (input_frame_based(hw_to_vdec(dec)))
4272 vframe_qos->size = pic->frame_size;
4273 else
4274 vframe_qos->size = framesize;
4275 vframe_qos->pts = pts;
4276 #ifdef SHOW_QOS_INFO
4277 avs2_print(dec, 0, "slice:%d\n", pic->slice_type);
4278 #endif
4279
4280
4281 vframe_qos->max_mv = pic->max_mv;
4282 vframe_qos->avg_mv = pic->avg_mv;
4283 vframe_qos->min_mv = pic->min_mv;
4284 #ifdef SHOW_QOS_INFO
4285 avs2_print(dec, 0, "mv: max:%d, avg:%d, min:%d\n",
4286 vframe_qos->max_mv,
4287 vframe_qos->avg_mv,
4288 vframe_qos->min_mv);
4289 #endif
4290
4291 vframe_qos->max_qp = pic->max_qp;
4292 vframe_qos->avg_qp = pic->avg_qp;
4293 vframe_qos->min_qp = pic->min_qp;
4294 #ifdef SHOW_QOS_INFO
4295 avs2_print(dec, 0, "qp: max:%d, avg:%d, min:%d\n",
4296 vframe_qos->max_qp,
4297 vframe_qos->avg_qp,
4298 vframe_qos->min_qp);
4299 #endif
4300
4301 vframe_qos->max_skip = pic->max_skip;
4302 vframe_qos->avg_skip = pic->avg_skip;
4303 vframe_qos->min_skip = pic->min_skip;
4304 #ifdef SHOW_QOS_INFO
4305 avs2_print(dec, 0, "skip: max:%d, avg:%d, min:%d\n",
4306 vframe_qos->max_skip,
4307 vframe_qos->avg_skip,
4308 vframe_qos->min_skip);
4309 #endif
4310
4311 vframe_qos->num++;
4312
4313 }
4314
4315 static void set_vframe(struct AVS2Decoder_s *dec,
4316 struct vframe_s *vf, struct avs2_frame_s *pic, u8 dummy)
4317 {
4318 unsigned long flags;
4319 int stream_offset;
4320 unsigned int frame_size = 0;
4321 int pts_discontinue;
4322 stream_offset = pic->stream_offset;
4323 avs2_print(dec, AVS2_DBG_BUFMGR,
4324 "%s index = %d pos = %d\r\n",
4325 __func__, pic->index,
4326 pic->imgtr_fwRefDistance);
4327
4328 if (pic->double_write_mode)
4329 set_canvas(dec, pic);
4330
4331 display_frame_count[dec->index]++;
4332
4333 if (!dummy) {
4334 #ifdef MULTI_INSTANCE_SUPPORT
4335 if (vdec_frame_based(hw_to_vdec(dec))) {
4336 vf->pts = pic->pts;
4337 vf->pts_us64 = pic->pts64;
4338 } else
4339 #endif
4340 /* if (pts_lookup_offset(PTS_TYPE_VIDEO,
4341 stream_offset, &vf->pts, 0) != 0) { */
4342 if (pts_lookup_offset_us64
4343 (PTS_TYPE_VIDEO, stream_offset,
4344 &vf->pts, &frame_size, 0,
4345 &vf->pts_us64) != 0) {
4346 #ifdef DEBUG_PTS
4347 dec->pts_missed++;
4348 #endif
4349 vf->pts = 0;
4350 vf->pts_us64 = 0;
4351 }
4352 #ifdef DEBUG_PTS
4353 else
4354 dec->pts_hit++;
4355 #endif
4356 if (pts_unstable)
4357 dec->pts_mode = PTS_NONE_REF_USE_DURATION;
4358
4359 fill_frame_info(dec, pic, frame_size, vf->pts);
4360
4361 if ((dec->pts_mode == PTS_NORMAL) && (vf->pts != 0)
4362 && dec->get_frame_dur) {
4363 int pts_diff = (int)vf->pts - dec->last_lookup_pts;
4364
4365 if (pts_diff < 0) {
4366 dec->pts_mode_switching_count++;
4367 dec->pts_mode_recovery_count = 0;
4368
4369 if (dec->pts_mode_switching_count >=
4370 PTS_MODE_SWITCHING_THRESHOLD) {
4371 dec->pts_mode =
4372 PTS_NONE_REF_USE_DURATION;
4373 pr_info
4374 ("HEVC: switch to n_d mode.\n");
4375 }
4376
4377 } else {
4378 int p = PTS_MODE_SWITCHING_RECOVERY_THREASHOLD;
4379 dec->pts_mode_recovery_count++;
4380 if (dec->pts_mode_recovery_count > p) {
4381 dec->pts_mode_switching_count = 0;
4382 dec->pts_mode_recovery_count = 0;
4383 }
4384 }
4385 }
4386
4387 pts_discontinue =
4388 (abs(dec->last_pts - vf->pts) >=
4389 tsync_vpts_discontinuity_margin());
4390
4391 if (vf->pts != 0)
4392 dec->last_lookup_pts = vf->pts;
4393 #if 1
4394 if ((dec->pts_mode == PTS_NONE_REF_USE_DURATION)
4395 && ((pic->slice_type != I_IMG) || (!pts_discontinue &&
4396 !first_pts_checkin_complete(PTS_TYPE_AUDIO))))
4397 vf->pts = dec->last_pts + DUR2PTS(dec->frame_dur);
4398 #endif
4399 dec->last_pts = vf->pts;
4400
4401 if (vf->pts_us64 != 0)
4402 dec->last_lookup_pts_us64 = vf->pts_us64;
4403
4404 #if 1
4405 if ((dec->pts_mode == PTS_NONE_REF_USE_DURATION)
4406 && ((pic->slice_type != I_IMG) || (!pts_discontinue &&
4407 !first_pts_checkin_complete(PTS_TYPE_AUDIO)))) {
4408 vf->pts_us64 =
4409 dec->last_pts_us64 +
4410 (DUR2PTS(dec->frame_dur) * 100 / 9);
4411 }
4412 #endif
4413 dec->last_pts_us64 = vf->pts_us64;
4414 avs2_print(dec, AVS2_DBG_OUT_PTS,
4415 "avs2 dec out pts: vf->pts=%d, vf->pts_us64 = %lld\n",
4416 vf->pts, vf->pts_us64);
4417 }
4418
4419 vf->index = 0xff00 | pic->index;
4420
4421 if (pic->double_write_mode & 0x10) {
4422 /* double write only */
4423 vf->compBodyAddr = 0;
4424 vf->compHeadAddr = 0;
4425 } else {
4426 #ifdef AVS2_10B_MMU
4427 vf->compBodyAddr = 0;
4428 vf->compHeadAddr = pic->header_adr;
4429 #else
4430 vf->compBodyAddr = pic->mc_y_adr; /*body adr*/
4431 vf->compHeadAddr = pic->mc_y_adr +
4432 pic->comp_body_size;
4433 /*head adr*/
4434 #endif
4435 }
4436 if (pic->double_write_mode) {
4437 vf->type = VIDTYPE_PROGRESSIVE |
4438 VIDTYPE_VIU_FIELD;
4439 vf->type |= VIDTYPE_VIU_NV21;
4440 if (pic->double_write_mode == 3) {
4441 vf->type |= VIDTYPE_COMPRESS;
4442 #ifdef AVS2_10B_MMU
4443 vf->type |= VIDTYPE_SCATTER;
4444 #endif
4445 }
4446 #ifdef MULTI_INSTANCE_SUPPORT
4447 if (dec->m_ins_flag) {
4448 vf->canvas0Addr = vf->canvas1Addr = -1;
4449 vf->plane_num = 2;
4450 vf->canvas0_config[0] =
4451 pic->canvas_config[0];
4452 vf->canvas0_config[1] =
4453 pic->canvas_config[1];
4454
4455 vf->canvas1_config[0] =
4456 pic->canvas_config[0];
4457 vf->canvas1_config[1] =
4458 pic->canvas_config[1];
4459
4460 } else
4461 #endif
4462 vf->canvas0Addr = vf->canvas1Addr =
4463 spec2canvas(pic);
4464 } else {
4465 vf->canvas0Addr = vf->canvas1Addr = 0;
4466 vf->type = VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
4467 #ifdef AVS2_10B_MMU
4468 vf->type |= VIDTYPE_SCATTER;
4469 #endif
4470 }
4471
4472 switch (pic->bit_depth) {
4473 case AVS2_BITS_8:
4474 vf->bitdepth = BITDEPTH_Y8 |
4475 BITDEPTH_U8 | BITDEPTH_V8;
4476 break;
4477 case AVS2_BITS_10:
4478 case AVS2_BITS_12:
4479 vf->bitdepth = BITDEPTH_Y10 |
4480 BITDEPTH_U10 | BITDEPTH_V10;
4481 break;
4482 default:
4483 vf->bitdepth = BITDEPTH_Y10 |
4484 BITDEPTH_U10 | BITDEPTH_V10;
4485 break;
4486 }
4487 if ((vf->type & VIDTYPE_COMPRESS) == 0)
4488 vf->bitdepth =
4489 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
4490 if (pic->bit_depth == AVS2_BITS_8)
4491 vf->bitdepth |= BITDEPTH_SAVING_MODE;
4492
4493 set_frame_info(dec, vf);
4494 /* if((vf->width!=pic->width)|
4495 (vf->height!=pic->height)) */
4496 /* pr_info("aaa: %d/%d, %d/%d\n",
4497 vf->width,vf->height, pic->width,
4498 pic->height); */
4499 vf->width = pic->pic_w /
4500 get_double_write_ratio(dec,
4501 pic->double_write_mode);
4502 vf->height = pic->pic_h /
4503 get_double_write_ratio(dec,
4504 pic->double_write_mode);
4505 if (force_w_h != 0) {
4506 vf->width = (force_w_h >> 16) & 0xffff;
4507 vf->height = force_w_h & 0xffff;
4508 }
4509 vf->compWidth = pic->pic_w;
4510 vf->compHeight = pic->pic_h;
4511 if (force_fps & 0x100) {
4512 u32 rate = force_fps & 0xff;
4513 if (rate)
4514 vf->duration = 96000/rate;
4515 else
4516 vf->duration = 0;
4517 }
4518 #ifdef AVS2_10B_MMU
4519 if (vf->type & VIDTYPE_SCATTER) {
4520 vf->mem_handle = decoder_mmu_box_get_mem_handle(
4521 dec->mmu_box,
4522 pic->index);
4523 vf->mem_head_handle = decoder_bmmu_box_get_mem_handle(
4524 dec->bmmu_box,
4525 HEADER_BUFFER_IDX(pic->index));
4526 } else {
4527 vf->mem_handle = decoder_bmmu_box_get_mem_handle(
4528 dec->bmmu_box,
4529 VF_BUFFER_IDX(pic->index));
4530 vf->mem_head_handle = decoder_bmmu_box_get_mem_handle(
4531 dec->bmmu_box,
4532 HEADER_BUFFER_IDX(pic->index));
4533 }
4534 #else
4535 vf->mem_handle = decoder_bmmu_box_get_mem_handle(
4536 dec->bmmu_box,
4537 VF_BUFFER_IDX(pic->index));
4538 #endif
4539
4540 if (!dummy) {
4541 lock_buffer(dec, flags);
4542 pic->vf_ref = 1;
4543 unlock_buffer(dec, flags);
4544 }
4545 dec->vf_pre_count++;
4546 }
4547
4548 static inline void dec_update_gvs(struct AVS2Decoder_s *dec)
4549 {
4550 if (dec->gvs->frame_height != dec->frame_height) {
4551 dec->gvs->frame_width = dec->frame_width;
4552 dec->gvs->frame_height = dec->frame_height;
4553 }
4554 if (dec->gvs->frame_dur != dec->frame_dur) {
4555 dec->gvs->frame_dur = dec->frame_dur;
4556 if (dec->frame_dur != 0)
4557 dec->gvs->frame_rate = 96000 / dec->frame_dur;
4558 else
4559 dec->gvs->frame_rate = -1;
4560 }
4561 dec->gvs->status = dec->stat | dec->fatal_error;
4562 }
4563
4564
4565 static int avs2_prepare_display_buf(struct AVS2Decoder_s *dec)
4566 {
4567 #ifndef NO_DISPLAY
4568 struct vframe_s *vf = NULL;
4569 /*unsigned short slice_type;*/
4570 struct avs2_frame_s *pic;
4571 struct vdec_s *pvdec = hw_to_vdec(dec);
4572 while (1) {
4573 pic = get_disp_pic(dec);
4574 if (pic == NULL)
4575 break;
4576
4577 if (force_disp_pic_index & 0x100) {
4578 /*recycle directly*/
4579 continue;
4580 }
4581
4582 if (pic->error_mark) {
4583 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
4584 "!!!error pic, skip\n",
4585 0);
4586 continue;
4587 }
4588
4589 if (dec->start_decoding_flag != 0) {
4590 if (dec->skip_PB_before_I &&
4591 pic->slice_type != I_IMG) {
4592 avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
4593 "!!!slice type %d (not I) skip\n",
4594 0, pic->slice_type);
4595 continue;
4596 }
4597 dec->skip_PB_before_I = 0;
4598 }
4599
4600 if (kfifo_get(&dec->newframe_q, &vf) == 0) {
4601 pr_info("fatal error, no available buffer slot.");
4602 return -1;
4603 }
4604
4605 if (vf) {
4606 struct vdec_info tmp4x;
4607 int stream_offset = pic->stream_offset;
4608 set_vframe(dec, vf, pic, 0);
4609 decoder_do_frame_check(pvdec, vf);
4610 kfifo_put(&dec->display_q, (const struct vframe_s *)vf);
4611 ATRACE_COUNTER(MODULE_NAME, vf->pts);
4612
4613 dec_update_gvs(dec);
4614 /*count info*/
4615 vdec_count_info(dec->gvs, 0, stream_offset);
4616 memcpy(&tmp4x, dec->gvs, sizeof(struct vdec_info));
4617 tmp4x.bit_depth_luma = bit_depth_luma;
4618 tmp4x.bit_depth_chroma = bit_depth_chroma;
4619 tmp4x.double_write_mode = get_double_write_mode(dec);
4620 vdec_fill_vdec_frame(pvdec, &dec->vframe_qos, &tmp4x, vf, pic->hw_decode_time);
4621 pvdec->vdec_fps_detec(pvdec->id);
4622 if (without_display_mode == 0) {
4623 vf_notify_receiver(dec->provider_name,
4624 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
4625 } else
4626 vavs2_vf_put(vavs2_vf_get(dec), dec);
4627 }
4628 }
4629 /*!NO_DISPLAY*/
4630 #endif
4631 return 0;
4632 }
4633
4634 static void get_rpm_param(union param_u *params)
4635 {
4636 int i;
4637 unsigned int data32;
4638 if (debug & AVS2_DBG_BUFMGR)
4639 pr_info("enter %s\r\n", __func__);
4640 for (i = 0; i < (RPM_END - RPM_BEGIN); i++) {
4641 do {
4642 data32 = READ_VREG(RPM_CMD_REG);
4643 /*pr_info("%x\n", data32);*/
4644 } while ((data32 & 0x10000) == 0);
4645 params->l.data[i] = data32&0xffff;
4646 /*pr_info("%x\n", data32);*/
4647 WRITE_VREG(RPM_CMD_REG, 0);
4648 }
4649 if (debug & AVS2_DBG_BUFMGR)
4650 pr_info("leave %s\r\n", __func__);
4651 }
4652 static void debug_buffer_mgr_more(struct AVS2Decoder_s *dec)
4653 {
4654 int i;
4655 if (!(debug & AVS2_DBG_BUFMGR_MORE))
4656 return;
4657 pr_info("avs2_param: (%d)\n", dec->avs2_dec.img.number);
4658 for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
4659 pr_info("%04x ", dec->avs2_dec.param.l.data[i]);
4660 if (((i + 1) & 0xf) == 0)
4661 pr_info("\n");
4662 }
4663 }
4664
4665 #ifdef AVS2_10B_MMU
4666 static void avs2_recycle_mmu_buf_tail(struct AVS2Decoder_s *dec)
4667 {
4668 if (dec->cur_fb_idx_mmu != INVALID_IDX) {
4669 if (dec->used_4k_num == -1) {
4670 dec->used_4k_num =
4671 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
4672 if (dec->m_ins_flag)
4673 hevc_mmu_dma_check(hw_to_vdec(dec));
4674 decoder_mmu_box_free_idx_tail(dec->mmu_box,
4675 dec->cur_fb_idx_mmu, dec->used_4k_num);
4676 }
4677 dec->cur_fb_idx_mmu = INVALID_IDX;
4678 dec->used_4k_num = -1;
4679 }
4680 }
4681
4682 static void avs2_recycle_mmu_buf(struct AVS2Decoder_s *dec)
4683 {
4684 if (dec->cur_fb_idx_mmu != INVALID_IDX) {
4685 decoder_mmu_box_free_idx(dec->mmu_box,
4686 dec->cur_fb_idx_mmu);
4687
4688 dec->cur_fb_idx_mmu = INVALID_IDX;
4689 dec->used_4k_num = -1;
4690 }
4691 }
4692 #endif
4693
4694 static void dec_again_process(struct AVS2Decoder_s *dec)
4695 {
4696 amhevc_stop();
4697 dec->dec_result = DEC_RESULT_AGAIN;
4698 if (dec->process_state ==
4699 PROC_STATE_DECODING) {
4700 dec->process_state =
4701 PROC_STATE_DECODE_AGAIN;
4702 } else if (dec->process_state ==
4703 PROC_STATE_HEAD_DONE) {
4704 dec->process_state =
4705 PROC_STATE_HEAD_AGAIN;
4706 }
4707 dec->next_again_flag = 1;
4708 reset_process_time(dec);
4709 vdec_schedule_work(&dec->work);
4710 }
4711
4712 static uint32_t log2i(uint32_t val)
4713 {
4714 uint32_t ret = -1;
4715 while (val != 0) {
4716 val >>= 1;
4717 ret++;
4718 }
4719 return ret;
4720 }
4721
4722 static void check_pic_error(struct AVS2Decoder_s *dec,
4723 struct avs2_frame_s *pic)
4724 {
4725 if (pic->decoded_lcu == 0) {
4726 pic->decoded_lcu =
4727 (READ_VREG(HEVC_PARSER_LCU_START)
4728 & 0xffffff) + 1;
4729 }
4730 if (pic->decoded_lcu != dec->avs2_dec.lcu_total) {
4731 avs2_print(dec, AVS2_DBG_BUFMGR,
4732 "%s error pic(index %d imgtr_fwRefDistance %d) decoded lcu %d (total %d)\n",
4733 __func__, pic->index, pic->imgtr_fwRefDistance,
4734 pic->decoded_lcu, dec->avs2_dec.lcu_total);
4735 pic->error_mark = 1;
4736 } else {
4737 avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
4738 "%s pic(index %d imgtr_fwRefDistance %d) decoded lcu %d (total %d)\n",
4739 __func__, pic->index, pic->imgtr_fwRefDistance,
4740 pic->decoded_lcu, dec->avs2_dec.lcu_total);
4741
4742 }
4743 }
4744 static void update_decoded_pic(struct AVS2Decoder_s *dec)
4745 {
4746 struct avs2_frame_s *pic = dec->avs2_dec.hc.cur_pic;
4747 if (pic) {
4748 dec->avs2_dec.hc.cur_pic->decoded_lcu =
4749 (READ_VREG(HEVC_PARSER_LCU_START)
4750 & 0xffffff) + 1;
4751 avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
4752 "%s pic(index %d imgtr_fwRefDistance %d) decoded lcu %d (total %d)\n",
4753 __func__, pic->index, pic->imgtr_fwRefDistance,
4754 pic->decoded_lcu, dec->avs2_dec.lcu_total);
4755 }
4756 }
4757 /* +[SE] [BUG][BUG-171463][chuanqi.wang]: get frame rate by video sequeue*/
4758 static int get_frame_rate(union param_u *params, struct AVS2Decoder_s *dec)
4759 {
4760 int tmp = 0;
4761
4762 switch (params->p.frame_rate_code) {
4763 case 1:
4764 case 2:
4765 tmp = 24;
4766 break;
4767 case 3:
4768 tmp = 25;
4769 break;
4770 case 4:
4771 case 5:
4772 tmp = 30;
4773 break;
4774 case 6:
4775 tmp = 50;
4776 break;
4777 case 7:
4778 case 8:
4779 tmp = 60;
4780 break;
4781 case 9:
4782 tmp = 100;
4783 break;
4784 case 10:
4785 tmp = 120;
4786 break;
4787 default:
4788 tmp = 25;
4789 break;
4790 }
4791
4792 if (!params->p.progressive_sequence)
4793 tmp = tmp / 2;
4794 dec->frame_dur = div_u64(96000ULL, tmp);
4795 dec->get_frame_dur = true;
4796 /*avs2_print(dec, 0, "avs2 frame_dur:%d,progressive:%d\n", dec->frame_dur, params->p.progressive_sequence);*/
4797 return 0;
4798 }
4799
4800
4801 #define HEVC_MV_INFO 0x310d
4802 #define HEVC_QP_INFO 0x3137
4803 #define HEVC_SKIP_INFO 0x3136
4804
4805 /* only when we decoded one field or one frame,
4806 we can call this function to get qos info*/
4807 static void get_picture_qos_info(struct AVS2Decoder_s *dec)
4808 {
4809 struct avs2_frame_s *picture = dec->avs2_dec.hc.cur_pic;
4810 struct vdec_s *vdec = hw_to_vdec(dec);
4811 if (!picture) {
4812 avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
4813 "%s decode picture is none exist\n");
4814
4815 return;
4816 }
4817 if (vdec->mvfrm) {
4818 picture->frame_size = vdec->mvfrm->frame_size;
4819 picture->hw_decode_time =
4820 local_clock() - vdec->mvfrm->hw_decode_start;
4821 }
4822
4823 /*
4824 #define DEBUG_QOS
4825 */
4826
4827 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
4828 unsigned char a[3];
4829 unsigned char i, j, t;
4830 unsigned long data;
4831
4832 data = READ_VREG(HEVC_MV_INFO);
4833 if (picture->slice_type == I_IMG)
4834 data = 0;
4835 a[0] = data & 0xff;
4836 a[1] = (data >> 8) & 0xff;
4837 a[2] = (data >> 16) & 0xff;
4838
4839 for (i = 0; i < 3; i++)
4840 for (j = i+1; j < 3; j++) {
4841 if (a[j] < a[i]) {
4842 t = a[j];
4843 a[j] = a[i];
4844 a[i] = t;
4845 } else if (a[j] == a[i]) {
4846 a[i]++;
4847 t = a[j];
4848 a[j] = a[i];
4849 a[i] = t;
4850 }
4851 }
4852 picture->max_mv = a[2];
4853 picture->avg_mv = a[1];
4854 picture->min_mv = a[0];
4855 #ifdef DEBUG_QOS
4856 avs2_print(dec, 0, "mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
4857 data, a[0], a[1], a[2]);
4858 #endif
4859
4860 data = READ_VREG(HEVC_QP_INFO);
4861 a[0] = data & 0x1f;
4862 a[1] = (data >> 8) & 0x3f;
4863 a[2] = (data >> 16) & 0x7f;
4864
4865 for (i = 0; i < 3; i++)
4866 for (j = i+1; j < 3; j++) {
4867 if (a[j] < a[i]) {
4868 t = a[j];
4869 a[j] = a[i];
4870 a[i] = t;
4871 } else if (a[j] == a[i]) {
4872 a[i]++;
4873 t = a[j];
4874 a[j] = a[i];
4875 a[i] = t;
4876 }
4877 }
4878 picture->max_qp = a[2];
4879 picture->avg_qp = a[1];
4880 picture->min_qp = a[0];
4881 #ifdef DEBUG_QOS
4882 avs2_print(dec, 0, "qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
4883 data, a[0], a[1], a[2]);
4884 #endif
4885
4886 data = READ_VREG(HEVC_SKIP_INFO);
4887 a[0] = data & 0x1f;
4888 a[1] = (data >> 8) & 0x3f;
4889 a[2] = (data >> 16) & 0x7f;
4890
4891 for (i = 0; i < 3; i++)
4892 for (j = i+1; j < 3; j++) {
4893 if (a[j] < a[i]) {
4894 t = a[j];
4895 a[j] = a[i];
4896 a[i] = t;
4897 } else if (a[j] == a[i]) {
4898 a[i]++;
4899 t = a[j];
4900 a[j] = a[i];
4901 a[i] = t;
4902 }
4903 }
4904 picture->max_skip = a[2];
4905 picture->avg_skip = a[1];
4906 picture->min_skip = a[0];
4907
4908 #ifdef DEBUG_QOS
4909 avs2_print(dec, 0,
4910 "skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
4911 data, a[0], a[1], a[2]);
4912 #endif
4913 } else {
4914 uint32_t blk88_y_count;
4915 uint32_t blk88_c_count;
4916 uint32_t blk22_mv_count;
4917 uint32_t rdata32;
4918 int32_t mv_hi;
4919 int32_t mv_lo;
4920 uint32_t rdata32_l;
4921 uint32_t mvx_L0_hi;
4922 uint32_t mvy_L0_hi;
4923 uint32_t mvx_L1_hi;
4924 uint32_t mvy_L1_hi;
4925 int64_t value;
4926 uint64_t temp_value;
4927 #ifdef DEBUG_QOS
4928 int pic_number = 0;
4929 #endif
4930
4931 picture->max_mv = 0;
4932 picture->avg_mv = 0;
4933 picture->min_mv = 0;
4934
4935 picture->max_skip = 0;
4936 picture->avg_skip = 0;
4937 picture->min_skip = 0;
4938
4939 picture->max_qp = 0;
4940 picture->avg_qp = 0;
4941 picture->min_qp = 0;
4942
4943
4944
4945 #ifdef DEBUG_QOS
4946 avs2_print(dec, 0, "slice_type:%d, poc:%d\n",
4947 picture->slice_type,
4948 pic_number);
4949 #endif
4950 /* set rd_idx to 0 */
4951 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, 0);
4952
4953 blk88_y_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
4954 if (blk88_y_count == 0) {
4955 #ifdef DEBUG_QOS
4956 avs2_print(dec, 0,
4957 "[Picture %d Quality] NO Data yet.\n",
4958 pic_number);
4959 #endif
4960 /* reset all counts */
4961 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
4962 return;
4963 }
4964 /* qp_y_sum */
4965 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
4966 #ifdef DEBUG_QOS
4967 avs2_print(dec, 0,
4968 "[Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
4969 pic_number, rdata32/blk88_y_count,
4970 rdata32, blk88_y_count);
4971 #endif
4972 picture->avg_qp = rdata32/blk88_y_count;
4973 /* intra_y_count */
4974 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
4975 #ifdef DEBUG_QOS
4976 avs2_print(dec, 0,
4977 "[Picture %d Quality] Y intra rate : %d%c (%d)\n",
4978 pic_number, rdata32*100/blk88_y_count,
4979 '%', rdata32);
4980 #endif
4981 /* skipped_y_count */
4982 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
4983 #ifdef DEBUG_QOS
4984 avs2_print(dec, 0,
4985 "[Picture %d Quality] Y skipped rate : %d%c (%d)\n",
4986 pic_number, rdata32*100/blk88_y_count,
4987 '%', rdata32);
4988 #endif
4989 picture->avg_skip = rdata32*100/blk88_y_count;
4990 /* coeff_non_zero_y_count */
4991 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
4992 #ifdef DEBUG_QOS
4993 avs2_print(dec, 0,
4994 "[Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
4995 pic_number, (100 - rdata32*100/(blk88_y_count*1)),
4996 '%', rdata32);
4997 #endif
4998 /* blk66_c_count */
4999 blk88_c_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
5000 if (blk88_c_count == 0) {
5001 #ifdef DEBUG_QOS
5002 avs2_print(dec, 0,
5003 "[Picture %d Quality] NO Data yet.\n",
5004 pic_number);
5005 #endif
5006 /* reset all counts */
5007 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
5008 return;
5009 }
5010 /* qp_c_sum */
5011 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
5012 #ifdef DEBUG_QOS
5013 avs2_print(dec, 0,
5014 "[Picture %d Quality] C QP AVG : %d (%d/%d)\n",
5015 pic_number, rdata32/blk88_c_count,
5016 rdata32, blk88_c_count);
5017 #endif
5018 /* intra_c_count */
5019 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
5020 #ifdef DEBUG_QOS
5021 avs2_print(dec, 0,
5022 "[Picture %d Quality] C intra rate : %d%c (%d)\n",
5023 pic_number, rdata32*100/blk88_c_count,
5024 '%', rdata32);
5025 #endif
5026 /* skipped_cu_c_count */
5027 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
5028 #ifdef DEBUG_QOS
5029 avs2_print(dec, 0,
5030 "[Picture %d Quality] C skipped rate : %d%c (%d)\n",
5031 pic_number, rdata32*100/blk88_c_count,
5032 '%', rdata32);
5033 #endif
5034 /* coeff_non_zero_c_count */
5035 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
5036 #ifdef DEBUG_QOS
5037 avs2_print(dec, 0,
5038 "[Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
5039 pic_number, (100 - rdata32*100/(blk88_c_count*1)),
5040 '%', rdata32);
5041 #endif
5042
5043 /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
5044 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
5045 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
5046 #ifdef DEBUG_QOS
5047 avs2_print(dec, 0, "[Picture %d Quality] Y QP min : %d\n",
5048 pic_number, (rdata32>>0)&0xff);
5049 #endif
5050 picture->min_qp = (rdata32>>0)&0xff;
5051
5052 #ifdef DEBUG_QOS
5053 avs2_print(dec, 0, "[Picture %d Quality] Y QP max : %d\n",
5054 pic_number, (rdata32>>8)&0xff);
5055 #endif
5056 picture->max_qp = (rdata32>>8)&0xff;
5057
5058 #ifdef DEBUG_QOS
5059 avs2_print(dec, 0, "[Picture %d Quality] C QP min : %d\n",
5060 pic_number, (rdata32>>16)&0xff);
5061 avs2_print(dec, 0, "[Picture %d Quality] C QP max : %d\n",
5062 pic_number, (rdata32>>24)&0xff);
5063 #endif
5064
5065 /* blk22_mv_count */
5066 blk22_mv_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
5067 if (blk22_mv_count == 0) {
5068 #ifdef DEBUG_QOS
5069 avs2_print(dec, 0,
5070 "[Picture %d Quality] NO MV Data yet.\n",
5071 pic_number);
5072 #endif
5073 /* reset all counts */
5074 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
5075 return;
5076 }
5077 /* mvy_L1_count[39:32], mvx_L1_count[39:32],
5078 mvy_L0_count[39:32], mvx_L0_count[39:32] */
5079 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
5080 /* should all be 0x00 or 0xff */
5081 #ifdef DEBUG_QOS
5082 avs2_print(dec, 0,
5083 "[Picture %d Quality] MV AVG High Bits: 0x%X\n",
5084 pic_number, rdata32);
5085 #endif
5086 mvx_L0_hi = ((rdata32>>0)&0xff);
5087 mvy_L0_hi = ((rdata32>>8)&0xff);
5088 mvx_L1_hi = ((rdata32>>16)&0xff);
5089 mvy_L1_hi = ((rdata32>>24)&0xff);
5090
5091 /* mvx_L0_count[31:0] */
5092 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
5093 temp_value = mvx_L0_hi;
5094 temp_value = (temp_value << 32) | rdata32_l;
5095
5096 if (mvx_L0_hi & 0x80)
5097 value = 0xFFFFFFF000000000 | temp_value;
5098 else
5099 value = temp_value;
5100 value = div_s64(value, blk22_mv_count);
5101 #ifdef DEBUG_QOS
5102 avs2_print(dec, 0,
5103 "[Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
5104 pic_number, (int)value,
5105 value, blk22_mv_count);
5106 #endif
5107 picture->avg_mv = value;
5108
5109 /* mvy_L0_count[31:0] */
5110 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
5111 temp_value = mvy_L0_hi;
5112 temp_value = (temp_value << 32) | rdata32_l;
5113
5114 if (mvy_L0_hi & 0x80)
5115 value = 0xFFFFFFF000000000 | temp_value;
5116 else
5117 value = temp_value;
5118 #ifdef DEBUG_QOS
5119 avs2_print(dec, 0,
5120 "[Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
5121 pic_number, rdata32_l/blk22_mv_count,
5122 value, blk22_mv_count);
5123 #endif
5124
5125 /* mvx_L1_count[31:0] */
5126 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
5127 temp_value = mvx_L1_hi;
5128 temp_value = (temp_value << 32) | rdata32_l;
5129 if (mvx_L1_hi & 0x80)
5130 value = 0xFFFFFFF000000000 | temp_value;
5131 else
5132 value = temp_value;
5133 #ifdef DEBUG_QOS
5134 avs2_print(dec, 0,
5135 "[Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
5136 pic_number, rdata32_l/blk22_mv_count,
5137 value, blk22_mv_count);
5138 #endif
5139
5140 /* mvy_L1_count[31:0] */
5141 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
5142 temp_value = mvy_L1_hi;
5143 temp_value = (temp_value << 32) | rdata32_l;
5144 if (mvy_L1_hi & 0x80)
5145 value = 0xFFFFFFF000000000 | temp_value;
5146 else
5147 value = temp_value;
5148 #ifdef DEBUG_QOS
5149 avs2_print(dec, 0,
5150 "[Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
5151 pic_number, rdata32_l/blk22_mv_count,
5152 value, blk22_mv_count);
5153 #endif
5154
5155 /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
5156 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
5157 mv_hi = (rdata32>>16)&0xffff;
5158 if (mv_hi & 0x8000)
5159 mv_hi = 0x8000 - mv_hi;
5160 #ifdef DEBUG_QOS
5161 avs2_print(dec, 0, "[Picture %d Quality] MVX_L0 MAX : %d\n",
5162 pic_number, mv_hi);
5163 #endif
5164 picture->max_mv = mv_hi;
5165
5166 mv_lo = (rdata32>>0)&0xffff;
5167 if (mv_lo & 0x8000)
5168 mv_lo = 0x8000 - mv_lo;
5169 #ifdef DEBUG_QOS
5170 avs2_print(dec, 0, "[Picture %d Quality] MVX_L0 MIN : %d\n",
5171 pic_number, mv_lo);
5172 #endif
5173 picture->min_mv = mv_lo;
5174
5175 #ifdef DEBUG_QOS
5176 /* {mvy_L0_max, mvy_L0_min} */
5177 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
5178 mv_hi = (rdata32>>16)&0xffff;
5179 if (mv_hi & 0x8000)
5180 mv_hi = 0x8000 - mv_hi;
5181 avs2_print(dec, 0, "[Picture %d Quality] MVY_L0 MAX : %d\n",
5182 pic_number, mv_hi);
5183
5184
5185 mv_lo = (rdata32>>0)&0xffff;
5186 if (mv_lo & 0x8000)
5187 mv_lo = 0x8000 - mv_lo;
5188
5189 avs2_print(dec, 0, "[Picture %d Quality] MVY_L0 MIN : %d\n",
5190 pic_number, mv_lo);
5191
5192
5193 /* {mvx_L1_max, mvx_L1_min} */
5194 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
5195 mv_hi = (rdata32>>16)&0xffff;
5196 if (mv_hi & 0x8000)
5197 mv_hi = 0x8000 - mv_hi;
5198
5199 avs2_print(dec, 0, "[Picture %d Quality] MVX_L1 MAX : %d\n",
5200 pic_number, mv_hi);
5201
5202
5203 mv_lo = (rdata32>>0)&0xffff;
5204 if (mv_lo & 0x8000)
5205 mv_lo = 0x8000 - mv_lo;
5206
5207 avs2_print(dec, 0, "[Picture %d Quality] MVX_L1 MIN : %d\n",
5208 pic_number, mv_lo);
5209
5210
5211 /* {mvy_L1_max, mvy_L1_min} */
5212 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
5213 mv_hi = (rdata32>>16)&0xffff;
5214 if (mv_hi & 0x8000)
5215 mv_hi = 0x8000 - mv_hi;
5216
5217 avs2_print(dec, 0, "[Picture %d Quality] MVY_L1 MAX : %d\n",
5218 pic_number, mv_hi);
5219
5220 mv_lo = (rdata32>>0)&0xffff;
5221 if (mv_lo & 0x8000)
5222 mv_lo = 0x8000 - mv_lo;
5223
5224 avs2_print(dec, 0, "[Picture %d Quality] MVY_L1 MIN : %d\n",
5225 pic_number, mv_lo);
5226 #endif
5227
5228 rdata32 = READ_VREG(HEVC_PIC_QUALITY_CTRL);
5229 #ifdef DEBUG_QOS
5230 avs2_print(dec, 0,
5231 "[Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
5232 pic_number, rdata32);
5233 #endif
5234 /* reset all counts */
5235 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
5236 }
5237 }
5238
5239 static irqreturn_t vavs2_isr_thread_fn(int irq, void *data)
5240 {
5241 struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)data;
5242 unsigned int dec_status = dec->dec_status;
5243 int i, ret;
5244 int32_t start_code = 0;
5245
5246 /*if (dec->wait_buf)
5247 pr_info("set wait_buf to 0\r\n");
5248 */
5249
5250 avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
5251 "%s decode_status 0x%x process_state %d lcu 0x%x\n",
5252 __func__, dec_status, dec->process_state,
5253 READ_VREG(HEVC_PARSER_LCU_START));
5254
5255 #ifndef G12A_BRINGUP_DEBUG
5256 if (dec->eos) {
5257 PRINT_LINE();
5258 goto irq_handled_exit;
5259 }
5260 #endif
5261 dec->wait_buf = 0;
5262 if (dec_status == AVS2_DECODE_BUFEMPTY) {
5263 PRINT_LINE();
5264 if (dec->m_ins_flag) {
5265 reset_process_time(dec);
5266 if (!vdec_frame_based(hw_to_vdec(dec)))
5267 dec_again_process(dec);
5268 else {
5269 dec->dec_result = DEC_RESULT_DONE;
5270 reset_process_time(dec);
5271 amhevc_stop();
5272 vdec_schedule_work(&dec->work);
5273 }
5274 }
5275 goto irq_handled_exit;
5276 } else if (dec_status == HEVC_DECPIC_DATA_DONE) {
5277 PRINT_LINE();
5278 dec->start_decoding_flag |= 0x3;
5279 if (dec->m_ins_flag) {
5280 update_decoded_pic(dec);
5281 get_picture_qos_info(dec);
5282 reset_process_time(dec);
5283 dec->dec_result = DEC_RESULT_DONE;
5284 amhevc_stop();
5285 #if 0 /*def AVS2_10B_MMU*/
5286 if (dec->m_ins_flag) {
5287 /*avs2_recycle_mmu_buf_tail(dec);*/
5288 dec->used_4k_num =
5289 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
5290 }
5291 #endif
5292
5293 #if 0
5294 /*keep hardware state*/
5295 WRITE_VREG(HEVC_MPRED_INT_STATUS, (1<<31));
5296 WRITE_VREG(HEVC_PARSER_RESULT_3, 0xffffffff);
5297 dec->mpred_abv_start_addr =
5298 READ_VREG(HEVC_MPRED_ABV_START_ADDR);
5299 /**/
5300 #endif
5301 vdec_schedule_work(&dec->work);
5302 }
5303 goto irq_handled_exit;
5304 }
5305 PRINT_LINE();
5306 #if 0
5307 if (dec_status == AVS2_EOS) {
5308 if (dec->m_ins_flag)
5309 reset_process_time(dec);
5310
5311 avs2_print(dec, AVS2_DBG_BUFMGR,
5312 "AVS2_EOS, flush buffer\r\n");
5313
5314 avs2_post_process(&dec->avs2_dec);
5315 avs2_prepare_display_buf(dec);
5316
5317 avs2_print(dec, AVS2_DBG_BUFMGR,
5318 "send AVS2_10B_DISCARD_NAL\r\n");
5319 WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_10B_DISCARD_NAL);
5320 if (dec->m_ins_flag) {
5321 update_decoded_pic(dec);
5322 dec->dec_result = DEC_RESULT_DONE;
5323 amhevc_stop();
5324 vdec_schedule_work(&dec->work);
5325 }
5326 goto irq_handled_exit;
5327 } else
5328 #endif
5329 if (dec_status == AVS2_DECODE_OVER_SIZE) {
5330 avs2_print(dec, 0,
5331 "avs2 decode oversize !!\n");
5332 debug |= (AVS2_DBG_DIS_LOC_ERROR_PROC |
5333 AVS2_DBG_DIS_SYS_ERROR_PROC);
5334 dec->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
5335 if (dec->m_ins_flag)
5336 reset_process_time(dec);
5337 goto irq_handled_exit;
5338 }
5339 PRINT_LINE();
5340
5341 if (dec->m_ins_flag)
5342 reset_process_time(dec);
5343
5344 if (dec_status == AVS2_HEAD_SEQ_READY)
5345 start_code = SEQUENCE_HEADER_CODE;
5346 else if (dec_status == AVS2_HEAD_PIC_I_READY)
5347 start_code = I_PICTURE_START_CODE;
5348 else if (dec_status == AVS2_HEAD_PIC_PB_READY)
5349 start_code = PB_PICTURE_START_CODE;
5350 else if (dec_status == AVS2_STARTCODE_SEARCH_DONE)
5351 /*SEQUENCE_END_CODE, VIDEO_EDIT_CODE*/
5352 start_code = READ_VREG(CUR_NAL_UNIT_TYPE);
5353
5354 if (dec->process_state ==
5355 PROC_STATE_HEAD_AGAIN
5356 ) {
5357 if ((start_code == I_PICTURE_START_CODE)
5358 || (start_code == PB_PICTURE_START_CODE)) {
5359 avs2_print(dec, 0,
5360 "PROC_STATE_HEAD_AGAIN error, start_code 0x%x!!!\r\n",
5361 start_code);
5362 goto irq_handled_exit;
5363 } else {
5364 avs2_print(dec, AVS2_DBG_BUFMGR,
5365 "PROC_STATE_HEAD_AGAIN, start_code 0x%x\r\n",
5366 start_code);
5367 dec->process_state = PROC_STATE_HEAD_DONE;
5368 WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_ACTION_DONE);
5369 goto irq_handled_exit;
5370 }
5371 } else if (dec->process_state ==
5372 PROC_STATE_DECODE_AGAIN) {
5373 if ((start_code == I_PICTURE_START_CODE)
5374 || (start_code == PB_PICTURE_START_CODE)) {
5375 avs2_print(dec, AVS2_DBG_BUFMGR,
5376 "PROC_STATE_DECODE_AGAIN=> decode_slice, start_code 0x%x\r\n",
5377 start_code);
5378 goto decode_slice;
5379 } else {
5380 avs2_print(dec, 0,
5381 "PROC_STATE_DECODE_AGAIN, start_code 0x%x!!!\r\n",
5382 start_code);
5383 WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_ACTION_DONE);
5384 goto irq_handled_exit;
5385 }
5386 }
5387
5388 if ((start_code == I_PICTURE_START_CODE)
5389 || (start_code == PB_PICTURE_START_CODE)
5390 || (start_code == SEQUENCE_END_CODE)
5391 || (start_code == VIDEO_EDIT_CODE)) {
5392 PRINT_LINE();
5393
5394 if (dec->avs2_dec.hc.cur_pic != NULL) {
5395 int32_t ii;
5396 #ifdef AVS2_10B_MMU
5397 avs2_recycle_mmu_buf_tail(dec);
5398 #endif
5399 check_pic_error(dec, dec->avs2_dec.hc.cur_pic);
5400 avs2_post_process(&dec->avs2_dec);
5401
5402 if (debug & AVS2_DBG_PRINT_PIC_LIST)
5403 dump_pic_list(dec);
5404
5405 avs2_prepare_display_buf(dec);
5406 dec->avs2_dec.hc.cur_pic = NULL;
5407 for (ii = 0; ii < dec->avs2_dec.ref_maxbuffer;
5408 ii++) {
5409 if (dec->avs2_dec.fref[ii]->
5410 bg_flag == 0 &&
5411 dec->avs2_dec.fref[ii]->
5412 is_output == -1 &&
5413 dec->avs2_dec.fref[ii]->
5414 mmu_alloc_flag &&
5415 dec->avs2_dec.fref[ii]->
5416 vf_ref == 0) {
5417 struct avs2_frame_s *pic =
5418 dec->avs2_dec.fref[ii];
5419 if (dec->avs2_dec.fref[ii]->
5420 refered_by_others == 0) {
5421 #ifdef AVS2_10B_MMU
5422 dec->avs2_dec.fref[ii]->
5423 mmu_alloc_flag = 0;
5424 /*release_buffer_4k(
5425 dec->avs2_dec.fref[ii]->index);*/
5426 decoder_mmu_box_free_idx(dec->mmu_box,
5427 dec->avs2_dec.fref[ii]->index);
5428 #ifdef DYNAMIC_ALLOC_HEAD
5429 decoder_bmmu_box_free_idx(
5430 dec->bmmu_box,
5431 HEADER_BUFFER_IDX(pic->index));
5432 pic->header_adr = 0;
5433 #endif
5434 #endif
5435 #ifndef MV_USE_FIXED_BUF
5436 decoder_bmmu_box_free_idx(
5437 dec->bmmu_box,
5438 MV_BUFFER_IDX(pic->index));
5439 pic->mpred_mv_wr_start_addr = 0;
5440 #endif
5441 }
5442 decoder_bmmu_box_free_idx(
5443 dec->bmmu_box,
5444 VF_BUFFER_IDX(pic->index));
5445 dec->cma_alloc_addr = 0;
5446 }
5447 }
5448 }
5449 }
5450
5451 if ((dec_status == AVS2_HEAD_PIC_I_READY)
5452 || (dec_status == AVS2_HEAD_PIC_PB_READY)) {
5453 PRINT_LINE();
5454
5455 if (debug & AVS2_DBG_SEND_PARAM_WITH_REG) {
5456 get_rpm_param(
5457 &dec->avs2_dec.param);
5458 } else {
5459
5460 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
5461 int ii;
5462 for (ii = 0; ii < 4; ii++)
5463 dec->avs2_dec.param.l.data[i + ii] =
5464 dec->rpm_ptr[i + 3 - ii];
5465 }
5466 }
5467 #ifdef SANITY_CHECK
5468 if (dec->avs2_dec.param.p.num_of_ref_cur >
5469 dec->avs2_dec.ref_maxbuffer) {
5470 pr_info("Warning: Wrong num_of_ref_cur %d, force to %d\n",
5471 dec->avs2_dec.param.p.num_of_ref_cur,
5472 dec->avs2_dec.ref_maxbuffer);
5473 dec->avs2_dec.param.p.num_of_ref_cur =
5474 dec->avs2_dec.ref_maxbuffer;
5475 }
5476 #endif
5477 PRINT_LINE();
5478
5479 debug_buffer_mgr_more(dec);
5480 get_frame_rate(&dec->avs2_dec.param, dec);
5481
5482 #if 0 // The video_signal_type is type of uint16_t and result false, so comment it out.
5483 if (dec->avs2_dec.param.p.video_signal_type
5484 & (1<<30)) {
5485 union param_u *pPara;
5486
5487 avs2_print(dec, 0,
5488 "avs2 HDR meta data present\n");
5489 pPara = &dec->avs2_dec.param;
5490
5491 /*clean this flag*/
5492 pPara->p.video_signal_type
5493 &= ~(1<<30);
5494
5495 dec->vf_dp.present_flag = 1;
5496
5497 dec->vf_dp.white_point[0]
5498 = pPara->p.white_point_x;
5499 avs2_print(dec, AVS2_DBG_HDR_INFO,
5500 "white_point[0]:0x%x\n",
5501 dec->vf_dp.white_point[0]);
5502
5503 dec->vf_dp.white_point[1]
5504 = pPara->p.white_point_y;
5505 avs2_print(dec, AVS2_DBG_HDR_INFO,
5506 "white_point[1]:0x%x\n",
5507 dec->vf_dp.white_point[1]);
5508
5509 for (i = 0; i < 3; i++) {
5510 dec->vf_dp.primaries[i][0]
5511 = pPara->p.display_primaries_x[i];
5512 avs2_print(dec, AVS2_DBG_HDR_INFO,
5513 "primaries[%d][0]:0x%x\n",
5514 i,
5515 dec->vf_dp.primaries[i][0]);
5516 }
5517
5518 for (i = 0; i < 3; i++) {
5519 dec->vf_dp.primaries[i][1]
5520 = pPara->p.display_primaries_y[i];
5521 avs2_print(dec, AVS2_DBG_HDR_INFO,
5522 "primaries[%d][1]:0x%x\n",
5523 i,
5524 dec->vf_dp.primaries[i][1]);
5525 }
5526
5527 dec->vf_dp.luminance[0]
5528 = pPara->p.max_display_mastering_luminance;
5529 avs2_print(dec, AVS2_DBG_HDR_INFO,
5530 "luminance[0]:0x%x\n",
5531 dec->vf_dp.luminance[0]);
5532
5533 dec->vf_dp.luminance[1]
5534 = pPara->p.min_display_mastering_luminance;
5535 avs2_print(dec, AVS2_DBG_HDR_INFO,
5536 "luminance[1]:0x%x\n",
5537 dec->vf_dp.luminance[1]);
5538
5539
5540 dec->vf_dp.content_light_level.present_flag
5541 = 1;
5542 dec->vf_dp.content_light_level.max_content
5543 = pPara->p.max_content_light_level;
5544 avs2_print(dec, AVS2_DBG_HDR_INFO,
5545 "max_content:0x%x\n",
5546 dec->vf_dp.content_light_level.max_content);
5547
5548 dec->vf_dp.content_light_level.max_pic_average
5549 = pPara->p.max_picture_average_light_level;
5550
5551 avs2_print(dec, AVS2_DBG_HDR_INFO,
5552 "max_pic_average:0x%x\n",
5553 dec->vf_dp.content_light_level.max_pic_average);
5554 }
5555 #endif
5556
5557
5558 if (dec->video_ori_signal_type !=
5559 ((dec->avs2_dec.param.p.video_signal_type << 16)
5560 | dec->avs2_dec.param.p.color_description)) {
5561 u32 v = dec->avs2_dec.param.p.video_signal_type;
5562 u32 c = dec->avs2_dec.param.p.color_description;
5563 u32 convert_c = c;
5564
5565 if (v & 0x2000) {
5566 avs2_print(dec, 0,
5567 "video_signal_type present:\n");
5568 avs2_print(dec, 0,
5569 " %s %s\n",
5570 video_format_names[(v >> 10) & 7],
5571 ((v >> 9) & 1) ?
5572 "full_range" : "limited");
5573 if (v & 0x100) {
5574 u32 transfer;
5575 u32 maxtrix;
5576
5577 avs2_print(dec, 0,
5578 "color_description present:\n");
5579 avs2_print(dec, 0,
5580 "color_primarie = %d\n",
5581 v & 0xff);
5582 avs2_print(dec, 0,
5583 "transfer_characteristic = %d\n",
5584 (c >> 8) & 0xff);
5585 avs2_print(dec, 0,
5586 " matrix_coefficient = %d\n",
5587 c & 0xff);
5588
5589 transfer = (c >> 8) & 0xFF;
5590 if (transfer >= 15)
5591 avs2_print(dec, 0,
5592 "unsupport transfer_characteristic\n");
5593 else if (transfer == 14)
5594 transfer = 18; /* HLG */
5595 else if (transfer == 13)
5596 transfer = 32;
5597 else if (transfer == 12)
5598 transfer = 16;
5599 else if (transfer == 11)
5600 transfer = 15;
5601
5602 maxtrix = c & 0xFF;
5603 if (maxtrix >= 10)
5604 avs2_print(dec, 0,
5605 "unsupport matrix_coefficient\n");
5606 else if (maxtrix == 9)
5607 maxtrix = 10;
5608 else if (maxtrix == 8)
5609 maxtrix = 9;
5610
5611 convert_c = (transfer << 8) | (maxtrix);
5612
5613 avs2_print(dec, 0,
5614 " convered c:0x%x\n",
5615 convert_c);
5616 }
5617 }
5618
5619 if (enable_force_video_signal_type)
5620 dec->video_signal_type
5621 = force_video_signal_type;
5622 else {
5623 dec->video_signal_type
5624 = (v << 16) | convert_c;
5625
5626 dec->video_ori_signal_type
5627 = (v << 16) | c;
5628 }
5629
5630 video_signal_type = dec->video_signal_type;
5631 }
5632 }
5633 #if 0
5634 if ((debug_again & 0x4) &&
5635 dec->process_state ==
5636 PROC_STATE_INIT) {
5637 if (start_code == PB_PICTURE_START_CODE) {
5638 dec->process_state = PROC_STATE_TEST1;
5639 dec_again_process(dec);
5640 goto irq_handled_exit;
5641 }
5642 }
5643 #endif
5644 PRINT_LINE();
5645 avs2_prepare_header(&dec->avs2_dec, start_code);
5646
5647 if (start_code == SEQUENCE_HEADER_CODE ||
5648 start_code == VIDEO_EDIT_CODE ||
5649 start_code == SEQUENCE_END_CODE) {
5650 if (dec->m_ins_flag &&
5651 vdec_frame_based(hw_to_vdec(dec)))
5652 dec->start_decoding_flag |= 0x1;
5653 dec->process_state = PROC_STATE_HEAD_DONE;
5654 WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_ACTION_DONE);
5655 } else if (start_code == I_PICTURE_START_CODE ||
5656 start_code == PB_PICTURE_START_CODE) {
5657 ret = 0;
5658 if (dec->pic_list_init_flag == 0) {
5659 int32_t lcu_size_log2 =
5660 log2i(dec->avs2_dec.param.p.lcu_size);
5661
5662 avs2_init_global_buffers(&dec->avs2_dec);
5663 /*avs2_dec->m_bg->index is
5664 set to dec->used_buf_num - 1*/
5665 init_pic_list(dec, lcu_size_log2);
5666 init_pic_list_hw(dec);
5667 }
5668 ret = avs2_process_header(&dec->avs2_dec);
5669 if (!dec->m_ins_flag)
5670 dec->slice_idx++;
5671
5672 PRINT_LINE();
5673 #ifdef I_ONLY_SUPPORT
5674 if ((start_code == PB_PICTURE_START_CODE) &&
5675 (dec->i_only & 0x2))
5676 ret = -2;
5677 #endif
5678 #ifdef AVS2_10B_MMU
5679 if (ret >= 0) {
5680 ret = avs2_alloc_mmu(dec,
5681 dec->avs2_dec.hc.cur_pic->index,
5682 dec->avs2_dec.img.width,
5683 dec->avs2_dec.img.height,
5684 dec->avs2_dec.input.sample_bit_depth,
5685 dec->frame_mmu_map_addr);
5686 if (ret >= 0) {
5687 dec->cur_fb_idx_mmu =
5688 dec->avs2_dec.hc.cur_pic->index;
5689 dec->avs2_dec.hc.cur_pic->mmu_alloc_flag = 1;
5690 } else
5691 pr_err("can't alloc need mmu1,idx %d ret =%d\n",
5692 dec->avs2_dec.hc.cur_pic->index,
5693 ret);
5694 }
5695 #endif
5696
5697 #ifndef MV_USE_FIXED_BUF
5698 if (ret >= 0 &&
5699 dec->avs2_dec.hc.cur_pic->
5700 mpred_mv_wr_start_addr == 0) {
5701 unsigned long buf_addr;
5702 unsigned mv_buf_size = 0x120000;
5703 int i = dec->avs2_dec.hc.cur_pic->index;
5704 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
5705 mv_buf_size = 0x120000 * 4;
5706 if (decoder_bmmu_box_alloc_buf_phy
5707 (dec->bmmu_box,
5708 MV_BUFFER_IDX(i),
5709 mv_buf_size,
5710 DRIVER_NAME,
5711 &buf_addr) < 0)
5712 ret = -1;
5713 else
5714 dec->avs2_dec.hc.cur_pic->
5715 mpred_mv_wr_start_addr
5716 = buf_addr;
5717 }
5718 #endif
5719 if (ret < 0) {
5720 avs2_print(dec, AVS2_DBG_BUFMGR,
5721 "avs2_bufmgr_process=> %d, AVS2_10B_DISCARD_NAL\r\n",
5722 ret);
5723 WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_10B_DISCARD_NAL);
5724 #ifdef AVS2_10B_MMU
5725 avs2_recycle_mmu_buf(dec);
5726 #endif
5727 if (dec->m_ins_flag) {
5728 dec->dec_result = DEC_RESULT_DONE;
5729 amhevc_stop();
5730 vdec_schedule_work(&dec->work);
5731 }
5732
5733 goto irq_handled_exit;
5734 } else {
5735 PRINT_LINE();
5736 dec->avs2_dec.hc.cur_pic->stream_offset =
5737 READ_VREG(HEVC_SHIFT_BYTE_COUNT);
5738 /*
5739 struct PIC_BUFFER_CONFIG_s *cur_pic
5740 = &cm->cur_frame->buf;
5741 cur_pic->decode_idx = dec->frame_count;
5742 */
5743 if (!dec->m_ins_flag) {
5744 dec->frame_count++;
5745 decode_frame_count[dec->index]
5746 = dec->frame_count;
5747 }
5748 /*MULTI_INSTANCE_SUPPORT*/
5749 if (dec->chunk) {
5750 dec->avs2_dec.hc.cur_pic->pts =
5751 dec->chunk->pts;
5752 dec->avs2_dec.hc.cur_pic->pts64 =
5753 dec->chunk->pts64;
5754 }
5755 /**/
5756 dec->avs2_dec.hc.cur_pic->bit_depth
5757 = dec->avs2_dec.input.sample_bit_depth;
5758 dec->avs2_dec.hc.cur_pic->double_write_mode
5759 = get_double_write_mode(dec);
5760 decode_slice:
5761 PRINT_LINE();
5762
5763 config_mc_buffer(dec);
5764 config_mcrcc_axi_hw(dec);
5765 config_mpred_hw(dec);
5766 config_dblk_hw(dec);
5767 config_sao_hw(dec);
5768 config_alf_hw(dec);
5769 config_other_hw(dec);
5770
5771 avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
5772 "=>fref0 imgtr_fwRefDistance %d, fref1 imgtr_fwRefDistance %d, dis2/dis3/dis4 %d %d %d img->tr %d\n",
5773 dec->avs2_dec.fref[0]->imgtr_fwRefDistance,
5774 dec->avs2_dec.fref[1]->imgtr_fwRefDistance,
5775 dec->avs2_dec.fref[2]->imgtr_fwRefDistance,
5776 dec->avs2_dec.fref[3]->imgtr_fwRefDistance,
5777 dec->avs2_dec.fref[4]->imgtr_fwRefDistance,
5778 dec->avs2_dec.img.tr);
5779
5780 if ((debug_again & 0x2) &&
5781 dec->process_state ==
5782 PROC_STATE_INIT) {
5783 dec->process_state = PROC_STATE_DECODING;
5784 dec_again_process(dec);
5785 goto irq_handled_exit;
5786 }
5787
5788 dec->process_state = PROC_STATE_DECODING;
5789
5790 WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_ACTION_DONE);
5791
5792 }
5793
5794 if (dec->m_ins_flag)
5795 start_process_time(dec);
5796 }
5797 irq_handled_exit:
5798 PRINT_LINE();
5799 dec->process_busy = 0;
5800 return IRQ_HANDLED;
5801 }
5802
5803 static irqreturn_t vavs2_isr(int irq, void *data)
5804 {
5805 int i;
5806 unsigned int dec_status;
5807 struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)data;
5808 uint debug_tag;
5809
5810 WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
5811
5812 dec_status = READ_VREG(HEVC_DEC_STATUS_REG);
5813
5814 if (!dec)
5815 return IRQ_HANDLED;
5816 if (dec->init_flag == 0)
5817 return IRQ_HANDLED;
5818 if (dec->process_busy)/*on process.*/
5819 return IRQ_HANDLED;
5820 dec->dec_status = dec_status;
5821 dec->process_busy = 1;
5822 if (debug & AVS2_DBG_IRQ_EVENT)
5823 avs2_print(dec, 0,
5824 "avs2 isr dec status = 0x%x, lcu 0x%x shiftbyte 0x%x (%x %x lev %x, wr %x, rd %x)\n",
5825 dec_status, READ_VREG(HEVC_PARSER_LCU_START),
5826 READ_VREG(HEVC_SHIFT_BYTE_COUNT),
5827 READ_VREG(HEVC_STREAM_START_ADDR),
5828 READ_VREG(HEVC_STREAM_END_ADDR),
5829 READ_VREG(HEVC_STREAM_LEVEL),
5830 READ_VREG(HEVC_STREAM_WR_PTR),
5831 READ_VREG(HEVC_STREAM_RD_PTR)
5832 );
5833
5834 debug_tag = READ_HREG(DEBUG_REG1);
5835 if (debug_tag & 0x10000) {
5836 dma_sync_single_for_cpu(
5837 amports_get_dma_device(),
5838 dec->lmem_phy_addr,
5839 LMEM_BUF_SIZE,
5840 DMA_FROM_DEVICE);
5841
5842 pr_info("LMEM<tag %x>:\n", READ_HREG(DEBUG_REG1));
5843 for (i = 0; i < 0x400; i += 4) {
5844 int ii;
5845 if ((i & 0xf) == 0)
5846 pr_info("%03x: ", i);
5847 for (ii = 0; ii < 4; ii++) {
5848 pr_info("%04x ",
5849 dec->lmem_ptr[i + 3 - ii]);
5850 }
5851 if (((i + ii) & 0xf) == 0)
5852 pr_info("\n");
5853 }
5854
5855 if (((udebug_pause_pos & 0xffff)
5856 == (debug_tag & 0xffff)) &&
5857 (udebug_pause_decode_idx == 0 ||
5858 udebug_pause_decode_idx == dec->decode_idx) &&
5859 (udebug_pause_val == 0 ||
5860 udebug_pause_val == READ_HREG(DEBUG_REG2))) {
5861 udebug_pause_pos &= 0xffff;
5862 dec->ucode_pause_pos = udebug_pause_pos;
5863 } else if (debug_tag & 0x20000)
5864 dec->ucode_pause_pos = 0xffffffff;
5865 if (dec->ucode_pause_pos)
5866 reset_process_time(dec);
5867 else
5868 WRITE_HREG(DEBUG_REG1, 0);
5869 } else if (debug_tag != 0) {
5870 pr_info(
5871 "dbg%x: %x lcu %x\n", READ_HREG(DEBUG_REG1),
5872 READ_HREG(DEBUG_REG2),
5873 READ_VREG(HEVC_PARSER_LCU_START));
5874 if (((udebug_pause_pos & 0xffff)
5875 == (debug_tag & 0xffff)) &&
5876 (udebug_pause_decode_idx == 0 ||
5877 udebug_pause_decode_idx == dec->decode_idx) &&
5878 (udebug_pause_val == 0 ||
5879 udebug_pause_val == READ_HREG(DEBUG_REG2))) {
5880 udebug_pause_pos &= 0xffff;
5881 dec->ucode_pause_pos = udebug_pause_pos;
5882 }
5883 if (dec->ucode_pause_pos)
5884 reset_process_time(dec);
5885 else
5886 WRITE_HREG(DEBUG_REG1, 0);
5887 dec->process_busy = 0;
5888 return IRQ_HANDLED;
5889 }
5890
5891 if (!dec->m_ins_flag) {
5892 if (dec->error_flag == 1) {
5893 dec->error_flag = 2;
5894 dec->process_busy = 0;
5895 return IRQ_HANDLED;
5896 } else if (dec->error_flag == 3) {
5897 dec->process_busy = 0;
5898 return IRQ_HANDLED;
5899 }
5900
5901 if ((dec->pic_list_init_flag) &&
5902 get_free_buf_count(dec) <= 0) {
5903 /*
5904 if (dec->wait_buf == 0)
5905 pr_info("set wait_buf to 1\r\n");
5906 */
5907 dec->wait_buf = 1;
5908 dec->process_busy = 0;
5909 if (debug & AVS2_DBG_IRQ_EVENT)
5910 avs2_print(dec, 0, "wait_buf\n");
5911 return IRQ_HANDLED;
5912 } else if (force_disp_pic_index) {
5913 dec->process_busy = 0;
5914 return IRQ_HANDLED;
5915 }
5916 }
5917 return IRQ_WAKE_THREAD;
5918 }
5919
5920 static void vavs2_put_timer_func(struct timer_list *timer)
5921 {
5922 struct AVS2Decoder_s *dec = container_of(timer, struct AVS2Decoder_s, timer);
5923 uint8_t empty_flag;
5924 unsigned int buf_level;
5925
5926 enum receviver_start_e state = RECEIVER_INACTIVE;
5927 if (dec->m_ins_flag) {
5928 if (hw_to_vdec(dec)->next_status
5929 == VDEC_STATUS_DISCONNECTED) {
5930 dec->dec_result = DEC_RESULT_FORCE_EXIT;
5931 vdec_schedule_work(&dec->work);
5932 avs2_print(dec, AVS2_DBG_BUFMGR,
5933 "vdec requested to be disconnected\n");
5934 return;
5935 }
5936 }
5937 if (dec->init_flag == 0) {
5938 if (dec->stat & STAT_TIMER_ARM) {
5939 timer->expires = jiffies + PUT_INTERVAL;
5940 add_timer(&dec->timer);
5941 }
5942 return;
5943 }
5944 if (dec->m_ins_flag == 0) {
5945 if (vf_get_receiver(dec->provider_name)) {
5946 state =
5947 vf_notify_receiver(dec->provider_name,
5948 VFRAME_EVENT_PROVIDER_QUREY_STATE,
5949 NULL);
5950 if ((state == RECEIVER_STATE_NULL)
5951 || (state == RECEIVER_STATE_NONE))
5952 state = RECEIVER_INACTIVE;
5953 } else
5954 state = RECEIVER_INACTIVE;
5955
5956 empty_flag = (READ_VREG(HEVC_PARSER_INT_STATUS) >> 6) & 0x1;
5957 /* error watchdog */
5958 if (empty_flag == 0) {
5959 /* decoder has input */
5960 if ((debug & AVS2_DBG_DIS_LOC_ERROR_PROC) == 0) {
5961
5962 buf_level = READ_VREG(HEVC_STREAM_LEVEL);
5963 /* receiver has no buffer to recycle */
5964 if ((state == RECEIVER_INACTIVE) &&
5965 (kfifo_is_empty(&dec->display_q) &&
5966 buf_level > 0x200)
5967 ) {
5968 WRITE_VREG
5969 (HEVC_ASSIST_MBOX0_IRQ_REG,
5970 0x1);
5971 }
5972 }
5973
5974 if ((debug & AVS2_DBG_DIS_SYS_ERROR_PROC) == 0) {
5975 /* receiver has no buffer to recycle */
5976 /*if ((state == RECEIVER_INACTIVE) &&
5977 (kfifo_is_empty(&dec->display_q))) {
5978 pr_info("avs2 something error,need reset\n");
5979 }*/
5980 }
5981 }
5982 } else {
5983 if (
5984 (decode_timeout_val > 0) &&
5985 (dec->start_process_time > 0) &&
5986 ((1000 * (jiffies - dec->start_process_time) / HZ)
5987 > decode_timeout_val)
5988 ) {
5989 int current_lcu_idx =
5990 READ_VREG(HEVC_PARSER_LCU_START)
5991 & 0xffffff;
5992 if (dec->last_lcu_idx == current_lcu_idx) {
5993 if (dec->decode_timeout_count > 0)
5994 dec->decode_timeout_count--;
5995 if (dec->decode_timeout_count == 0) {
5996 if (input_frame_based(
5997 hw_to_vdec(dec)) ||
5998 (READ_VREG(HEVC_STREAM_LEVEL) > 0x200))
5999 timeout_process(dec);
6000 else {
6001 avs2_print(dec, 0,
6002 "timeout & empty, again\n");
6003 dec_again_process(dec);
6004 }
6005 }
6006 } else {
6007 start_process_time(dec);
6008 dec->last_lcu_idx = current_lcu_idx;
6009 }
6010 }
6011 }
6012
6013 if ((dec->ucode_pause_pos != 0) &&
6014 (dec->ucode_pause_pos != 0xffffffff) &&
6015 udebug_pause_pos != dec->ucode_pause_pos) {
6016 dec->ucode_pause_pos = 0;
6017 WRITE_HREG(DEBUG_REG1, 0);
6018 }
6019 if (debug & AVS2_DBG_DUMP_DATA) {
6020 debug &= ~AVS2_DBG_DUMP_DATA;
6021 avs2_print(dec, 0,
6022 "%s: chunk size 0x%x off 0x%x sum 0x%x\n",
6023 __func__,
6024 dec->chunk->size,
6025 dec->chunk->offset,
6026 get_data_check_sum(dec, dec->chunk->size)
6027 );
6028 dump_data(dec, dec->chunk->size);
6029 }
6030 if (debug & AVS2_DBG_DUMP_PIC_LIST) {
6031 dump_pic_list(dec);
6032 debug &= ~AVS2_DBG_DUMP_PIC_LIST;
6033 }
6034 if (debug & AVS2_DBG_TRIG_SLICE_SEGMENT_PROC) {
6035 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
6036 debug &= ~AVS2_DBG_TRIG_SLICE_SEGMENT_PROC;
6037 }
6038 if (debug & AVS2_DBG_DUMP_RPM_BUF) {
6039 int i;
6040 pr_info("RPM:\n");
6041 for (i = 0; i < RPM_BUF_SIZE; i += 4) {
6042 int ii;
6043 if ((i & 0xf) == 0)
6044 pr_info("%03x: ", i);
6045 for (ii = 0; ii < 4; ii++) {
6046 pr_info("%04x ",
6047 dec->lmem_ptr[i + 3 - ii]);
6048 }
6049 if (((i + ii) & 0xf) == 0)
6050 pr_info("\n");
6051 }
6052 debug &= ~AVS2_DBG_DUMP_RPM_BUF;
6053 }
6054 if (debug & AVS2_DBG_DUMP_LMEM_BUF) {
6055 int i;
6056 pr_info("LMEM:\n");
6057 for (i = 0; i < LMEM_BUF_SIZE; i += 4) {
6058 int ii;
6059 if ((i & 0xf) == 0)
6060 pr_info("%03x: ", i);
6061 for (ii = 0; ii < 4; ii++) {
6062 pr_info("%04x ",
6063 dec->lmem_ptr[i + 3 - ii]);
6064 }
6065 if (((i + ii) & 0xf) == 0)
6066 pr_info("\n");
6067 }
6068 debug &= ~AVS2_DBG_DUMP_LMEM_BUF;
6069 }
6070 /*if (debug & AVS2_DBG_HW_RESET) {
6071 }*/
6072
6073 if (radr != 0) {
6074 if (rval != 0) {
6075 WRITE_VREG(radr, rval);
6076 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
6077 } else
6078 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
6079 rval = 0;
6080 radr = 0;
6081 }
6082 if (pop_shorts != 0) {
6083 int i;
6084 u32 sum = 0;
6085 pr_info("pop stream 0x%x shorts\r\n", pop_shorts);
6086 for (i = 0; i < pop_shorts; i++) {
6087 u32 data =
6088 (READ_HREG(HEVC_SHIFTED_DATA) >> 16);
6089 WRITE_HREG(HEVC_SHIFT_COMMAND,
6090 (1<<7)|16);
6091 if ((i & 0xf) == 0)
6092 pr_info("%04x:", i);
6093 pr_info("%04x ", data);
6094 if (((i + 1) & 0xf) == 0)
6095 pr_info("\r\n");
6096 sum += data;
6097 }
6098 pr_info("\r\nsum = %x\r\n", sum);
6099 pop_shorts = 0;
6100 }
6101 if (dbg_cmd != 0) {
6102 if (dbg_cmd == 1) {
6103 u32 disp_laddr;
6104 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXBB &&
6105 get_double_write_mode(dec) == 0) {
6106 disp_laddr =
6107 READ_VCBUS_REG(AFBC_BODY_BADDR) << 4;
6108 } else {
6109 struct canvas_s cur_canvas;
6110 canvas_read((READ_VCBUS_REG(VD1_IF0_CANVAS0)
6111 & 0xff), &cur_canvas);
6112 disp_laddr = cur_canvas.addr;
6113 }
6114 pr_info("current displayed buffer address %x\r\n",
6115 disp_laddr);
6116 }
6117 dbg_cmd = 0;
6118 }
6119 /*don't changed at start.*/
6120 if (dec->get_frame_dur && dec->show_frame_num > 60 &&
6121 dec->frame_dur > 0 && dec->saved_resolution !=
6122 frame_width * frame_height *
6123 (96000 / dec->frame_dur)) {
6124 int fps = 96000 / dec->frame_dur;
6125 if (hevc_source_changed(VFORMAT_AVS2,
6126 frame_width, frame_height, fps) > 0)
6127 dec->saved_resolution = frame_width *
6128 frame_height * fps;
6129 }
6130
6131 timer->expires = jiffies + PUT_INTERVAL;
6132 add_timer(timer);
6133 }
6134
6135
6136 int vavs2_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
6137 {
6138 struct AVS2Decoder_s *dec =
6139 (struct AVS2Decoder_s *)vdec->private;
6140
6141 if (!dec)
6142 return -1;
6143
6144 vstatus->frame_width = dec->frame_width;
6145 vstatus->frame_height = dec->frame_height;
6146
6147 if (dec->frame_dur != 0)
6148 vstatus->frame_rate = 96000 / dec->frame_dur;
6149 else
6150 vstatus->frame_rate = -1;
6151 vstatus->error_count = 0;
6152 vstatus->status = dec->stat | dec->fatal_error;
6153 vstatus->frame_dur = dec->frame_dur;
6154 vstatus->bit_rate = dec->gvs->bit_rate;
6155 vstatus->frame_data = dec->gvs->frame_data;
6156 vstatus->total_data = dec->gvs->total_data;
6157 vstatus->frame_count = dec->gvs->frame_count;
6158 vstatus->error_frame_count = dec->gvs->error_frame_count;
6159 vstatus->drop_frame_count = dec->gvs->drop_frame_count;
6160 vstatus->total_data = dec->gvs->total_data;
6161 vstatus->samp_cnt = dec->gvs->samp_cnt;
6162 vstatus->offset = dec->gvs->offset;
6163 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
6164 "%s", DRIVER_NAME);
6165 return 0;
6166 }
6167
6168 int vavs2_set_isreset(struct vdec_s *vdec, int isreset)
6169 {
6170 is_reset = isreset;
6171 return 0;
6172 }
6173
6174 static void vavs2_prot_init(struct AVS2Decoder_s *dec)
6175 {
6176 unsigned int data32;
6177
6178 avs2_config_work_space_hw(dec);
6179 if (dec->pic_list_init_flag)
6180 init_pic_list_hw(dec);
6181
6182 avs2_init_decoder_hw(dec);
6183
6184 #if 1
6185 avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
6186 "%s\n", __func__);
6187 data32 = READ_VREG(HEVC_STREAM_CONTROL);
6188 data32 = data32 |
6189 (1 << 0)/*stream_fetch_enable*/
6190 ;
6191 WRITE_VREG(HEVC_STREAM_CONTROL, data32);
6192 #if 0
6193 data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
6194 if (data32 != 0x00000100) {
6195 pr_info("avs2 prot init error %d\n", __LINE__);
6196 return;
6197 }
6198 data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
6199 if (data32 != 0x00000300) {
6200 pr_info("avs2 prot init error %d\n", __LINE__);
6201 return;
6202 }
6203 WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x12345678);
6204 WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x9abcdef0);
6205 data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
6206 if (data32 != 0x12345678) {
6207 pr_info("avs2 prot init error %d\n", __LINE__);
6208 return;
6209 }
6210 data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
6211 if (data32 != 0x9abcdef0) {
6212 pr_info("avs2 prot init error %d\n", __LINE__);
6213 return;
6214 }
6215 #endif
6216 WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x00000100);
6217 WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x00000000);
6218 #endif
6219
6220
6221
6222 WRITE_VREG(HEVC_WAIT_FLAG, 1);
6223
6224 /* WRITE_VREG(HEVC_MPSR, 1); */
6225
6226 /* clear mailbox interrupt */
6227 WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
6228
6229 /* enable mailbox interrupt */
6230 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 1);
6231
6232 /* disable PSCALE for hardware sharing */
6233 WRITE_VREG(HEVC_PSCALE_CTRL, 0);
6234
6235 WRITE_VREG(DEBUG_REG1, 0x0);
6236 /*check vps/sps/pps/i-slice in ucode*/
6237 WRITE_VREG(NAL_SEARCH_CTL, 0x8);
6238
6239 WRITE_VREG(DECODE_STOP_POS, udebug_flag);
6240
6241 }
6242
6243 #ifdef I_ONLY_SUPPORT
6244 static int vavs2_set_trickmode(struct vdec_s *vdec, unsigned long trickmode)
6245 {
6246 struct AVS2Decoder_s *dec =
6247 (struct AVS2Decoder_s *)vdec->private;
6248 if (i_only_flag & 0x100)
6249 return 0;
6250 if (trickmode == TRICKMODE_I || trickmode == TRICKMODE_I_HEVC)
6251 dec->i_only = 0x3;
6252 else if (trickmode == TRICKMODE_NONE)
6253 dec->i_only = 0x0;
6254 return 0;
6255 }
6256 #endif
6257
6258 static int vavs2_local_init(struct AVS2Decoder_s *dec)
6259 {
6260 int i;
6261 int ret;
6262 int width, height;
6263
6264 dec->gvs = vzalloc(sizeof(struct vdec_info));
6265 if (NULL == dec->gvs) {
6266 avs2_print(dec, 0,
6267 "the struct of vdec status malloc failed.\n");
6268 return -1;
6269 }
6270 #ifdef DEBUG_PTS
6271 dec->pts_missed = 0;
6272 dec->pts_hit = 0;
6273 #endif
6274 dec->new_frame_displayed = 0;
6275 dec->last_put_idx = -1;
6276 dec->saved_resolution = 0;
6277 dec->get_frame_dur = false;
6278 on_no_keyframe_skiped = 0;
6279 width = dec->vavs2_amstream_dec_info.width;
6280 height = dec->vavs2_amstream_dec_info.height;
6281 dec->frame_dur =
6282 (dec->vavs2_amstream_dec_info.rate ==
6283 0) ? 3600 : dec->vavs2_amstream_dec_info.rate;
6284 if (width && height)
6285 dec->frame_ar = height * 0x100 / width;
6286 /*
6287 TODO:FOR VERSION
6288 */
6289 avs2_print(dec, AVS2_DBG_BUFMGR,
6290 "avs2: ver (%d,%d) decinfo: %dx%d rate=%d\n", avs2_version,
6291 0, width, height, dec->frame_dur);
6292
6293 if (dec->frame_dur == 0)
6294 dec->frame_dur = 96000 / 24;
6295 #ifdef I_ONLY_SUPPORT
6296 if (i_only_flag & 0x100)
6297 dec->i_only = i_only_flag & 0xff;
6298 else if ((unsigned long) dec->vavs2_amstream_dec_info.param
6299 & 0x08)
6300 dec->i_only = 0x7;
6301 else
6302 dec->i_only = 0x0;
6303 #endif
6304 INIT_KFIFO(dec->display_q);
6305 INIT_KFIFO(dec->newframe_q);
6306
6307
6308 for (i = 0; i < VF_POOL_SIZE; i++) {
6309 const struct vframe_s *vf = &dec->vfpool[i];
6310 dec->vfpool[i].index = -1;
6311 kfifo_put(&dec->newframe_q, vf);
6312 }
6313
6314
6315 ret = avs2_local_init(dec);
6316
6317 return ret;
6318 }
6319
6320
6321 static s32 vavs2_init(struct vdec_s *vdec)
6322 {
6323 int ret = -1, size = -1;
6324 int fw_size = 0x1000 * 16;
6325 struct firmware_s *fw = NULL;
6326 struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)vdec->private;
6327 timer_setup(&dec->timer, NULL, 0);
6328
6329 dec->stat |= STAT_TIMER_INIT;
6330 if (vavs2_local_init(dec) < 0)
6331 return -EBUSY;
6332
6333 vdec_set_vframe_comm(vdec, DRIVER_NAME);
6334
6335 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
6336 if (IS_ERR_OR_NULL(fw))
6337 return -ENOMEM;
6338
6339 size = get_firmware_data(VIDEO_DEC_AVS2_MMU, fw->data);
6340 if (size < 0) {
6341 pr_err("get firmware fail.\n");
6342 vfree(fw);
6343 return -1;
6344 }
6345
6346 fw->len = fw_size;
6347
6348 if (dec->m_ins_flag) {
6349 //dec->timer.data = (ulong) dec;
6350 dec->timer.function = vavs2_put_timer_func;
6351 dec->timer.expires = jiffies + PUT_INTERVAL;
6352
6353 /*add_timer(&dec->timer);
6354
6355 dec->stat |= STAT_TIMER_ARM;
6356 dec->stat |= STAT_ISR_REG;*/
6357
6358 INIT_WORK(&dec->work, avs2_work);
6359 dec->fw = fw;
6360
6361 return 0;
6362 }
6363 amhevc_enable();
6364 ret = amhevc_loadmc_ex(VFORMAT_AVS2, NULL, fw->data);
6365 if (ret < 0) {
6366 amhevc_disable();
6367 vfree(fw);
6368 pr_err("AVS2: the %s fw loading failed, err: %x\n",
6369 tee_enabled() ? "TEE" : "local", ret);
6370 return -EBUSY;
6371 }
6372
6373 vfree(fw);
6374
6375 dec->stat |= STAT_MC_LOAD;
6376
6377 /* enable AMRISC side protocol */
6378 vavs2_prot_init(dec);
6379
6380 if (vdec_request_threaded_irq(VDEC_IRQ_0,
6381 vavs2_isr,
6382 vavs2_isr_thread_fn,
6383 IRQF_ONESHOT,/*run thread on this irq disabled*/
6384 "vavs2-irq", (void *)dec)) {
6385 pr_info("vavs2 irq register error.\n");
6386 amhevc_disable();
6387 return -ENOENT;
6388 }
6389
6390 dec->stat |= STAT_ISR_REG;
6391
6392 dec->provider_name = PROVIDER_NAME;
6393 vf_provider_init(&vavs2_vf_prov, PROVIDER_NAME,
6394 &vavs2_vf_provider, dec);
6395 vf_reg_provider(&vavs2_vf_prov);
6396 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
6397 if (dec->frame_dur != 0) {
6398 if (!is_reset)
6399 vf_notify_receiver(dec->provider_name,
6400 VFRAME_EVENT_PROVIDER_FR_HINT,
6401 (void *)
6402 ((unsigned long)dec->frame_dur));
6403 }
6404 dec->stat |= STAT_VF_HOOK;
6405
6406 //dec->timer.data = (ulong)dec;
6407 dec->timer.function = vavs2_put_timer_func;
6408 dec->timer.expires = jiffies + PUT_INTERVAL;
6409
6410
6411 add_timer(&dec->timer);
6412
6413 dec->stat |= STAT_TIMER_ARM;
6414
6415 /* dec->stat |= STAT_KTHREAD; */
6416 dec->process_busy = 0;
6417 avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
6418 "%d, vavs2_init, RP=0x%x\n",
6419 __LINE__, READ_VREG(HEVC_STREAM_RD_PTR));
6420 return 0;
6421 }
6422
6423 static int vmavs2_stop(struct AVS2Decoder_s *dec)
6424 {
6425 dec->init_flag = 0;
6426 dec->first_sc_checked = 0;
6427 if (dec->stat & STAT_TIMER_ARM) {
6428 del_timer_sync(&dec->timer);
6429 dec->stat &= ~STAT_TIMER_ARM;
6430 }
6431
6432 if (dec->stat & STAT_VF_HOOK) {
6433 if (!is_reset)
6434 vf_notify_receiver(dec->provider_name,
6435 VFRAME_EVENT_PROVIDER_FR_END_HINT,
6436 NULL);
6437
6438 vf_unreg_provider(&vavs2_vf_prov);
6439 dec->stat &= ~STAT_VF_HOOK;
6440 }
6441 avs2_local_uninit(dec);
6442 reset_process_time(dec);
6443 cancel_work_sync(&dec->work);
6444 uninit_mmu_buffers(dec);
6445 if (dec->fw) {
6446 vfree(dec->fw);
6447 dec->fw = NULL;
6448 }
6449
6450 return 0;
6451 }
6452
6453
6454 static int vavs2_stop(struct AVS2Decoder_s *dec)
6455 {
6456
6457 dec->init_flag = 0;
6458 dec->first_sc_checked = 0;
6459 if (dec->stat & STAT_VDEC_RUN) {
6460 amhevc_stop();
6461 dec->stat &= ~STAT_VDEC_RUN;
6462 }
6463
6464 if (dec->stat & STAT_ISR_REG) {
6465 if (!dec->m_ins_flag)
6466 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
6467 vdec_free_irq(VDEC_IRQ_0, (void *)dec);
6468 dec->stat &= ~STAT_ISR_REG;
6469 }
6470
6471 if (dec->stat & STAT_TIMER_ARM) {
6472 del_timer_sync(&dec->timer);
6473 dec->stat &= ~STAT_TIMER_ARM;
6474 }
6475
6476 if (dec->stat & STAT_VF_HOOK) {
6477 if (!is_reset)
6478 vf_notify_receiver(dec->provider_name,
6479 VFRAME_EVENT_PROVIDER_FR_END_HINT,
6480 NULL);
6481
6482 vf_unreg_provider(&vavs2_vf_prov);
6483 dec->stat &= ~STAT_VF_HOOK;
6484 }
6485 avs2_local_uninit(dec);
6486
6487 if (dec->m_ins_flag)
6488 cancel_work_sync(&dec->work);
6489 else
6490 amhevc_disable();
6491 uninit_mmu_buffers(dec);
6492
6493 return 0;
6494 }
6495
6496 static int amvdec_avs2_mmu_init(struct AVS2Decoder_s *dec)
6497 {
6498 int tvp_flag = vdec_secure(hw_to_vdec(dec)) ?
6499 CODEC_MM_FLAGS_TVP : 0;
6500 int buf_size = 48;
6501
6502 #ifdef AVS2_10B_MMU
6503 dec->need_cache_size = buf_size * SZ_1M;
6504 dec->sc_start_time = get_jiffies_64();
6505 dec->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
6506 dec->index, FRAME_BUFFERS,
6507 dec->need_cache_size,
6508 tvp_flag
6509 );
6510 if (!dec->mmu_box) {
6511 pr_err("avs2 alloc mmu box failed!!\n");
6512 return -1;
6513 }
6514 #endif
6515 dec->bmmu_box = decoder_bmmu_box_alloc_box(
6516 DRIVER_NAME,
6517 dec->index,
6518 MAX_BMMU_BUFFER_NUM,
6519 4 + PAGE_SHIFT,
6520 CODEC_MM_FLAGS_CMA_CLEAR |
6521 CODEC_MM_FLAGS_FOR_VDECODER |
6522 tvp_flag);
6523 if (!dec->bmmu_box) {
6524 pr_err("avs2 alloc bmmu box failed!!\n");
6525 return -1;
6526 }
6527 return 0;
6528 }
6529
6530 static int amvdec_avs2_probe(struct platform_device *pdev)
6531 {
6532 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
6533 struct BUF_s BUF[MAX_BUF_NUM];
6534 struct AVS2Decoder_s *dec = &gAVS2Decoder;
6535 int ret;
6536 pr_info("%s\n", __func__);
6537 mutex_lock(&vavs2_mutex);
6538
6539 memcpy(&BUF[0], &dec->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
6540 memset(dec, 0, sizeof(struct AVS2Decoder_s));
6541 memcpy(&dec->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
6542
6543 dec->init_flag = 0;
6544 dec->first_sc_checked = 0;
6545 dec->eos = 0;
6546 dec->start_process_time = 0;
6547 dec->timeout_num = 0;
6548 dec->fatal_error = 0;
6549 dec->show_frame_num = 0;
6550 if (pdata == NULL) {
6551 avs2_print(dec, 0,
6552 "\namvdec_avs2 memory resource undefined.\n");
6553 mutex_unlock(&vavs2_mutex);
6554 return -EFAULT;
6555 }
6556 dec->m_ins_flag = 0;
6557 dec->platform_dev = pdev;
6558 platform_set_drvdata(pdev, pdata);
6559
6560 if (amvdec_avs2_mmu_init(dec) < 0) {
6561 mutex_unlock(&vavs2_mutex);
6562 pr_err("avs2 alloc bmmu box failed!!\n");
6563 return -1;
6564 }
6565
6566 ret = decoder_bmmu_box_alloc_buf_phy(dec->bmmu_box, WORK_SPACE_BUF_ID,
6567 work_buf_size, DRIVER_NAME, &pdata->mem_start);
6568 if (ret < 0) {
6569 uninit_mmu_buffers(dec);
6570 mutex_unlock(&vavs2_mutex);
6571 return ret;
6572 }
6573 dec->buf_size = work_buf_size;
6574
6575 dec->buf_start = pdata->mem_start;
6576
6577
6578 if (debug) {
6579 avs2_print(dec, 0,
6580 "===AVS2 decoder mem resource 0x%lx size 0x%x\n",
6581 pdata->mem_start, dec->buf_size);
6582 }
6583
6584 if (pdata->sys_info) {
6585 dec->vavs2_amstream_dec_info = *pdata->sys_info;
6586 dec->frame_width = dec->vavs2_amstream_dec_info.width;
6587 dec->frame_height = dec->vavs2_amstream_dec_info.height;
6588 } else {
6589 dec->vavs2_amstream_dec_info.width = 0;
6590 dec->vavs2_amstream_dec_info.height = 0;
6591 dec->vavs2_amstream_dec_info.rate = 30;
6592 }
6593 dec->cma_dev = pdata->cma_dev;
6594
6595 pdata->private = dec;
6596 pdata->dec_status = vavs2_dec_status;
6597 /*pdata->set_isreset = vavs2_set_isreset;*/
6598 is_reset = 0;
6599 if (vavs2_init(pdata) < 0) {
6600 pr_info("\namvdec_avs2 init failed.\n");
6601 avs2_local_uninit(dec);
6602 uninit_mmu_buffers(dec);
6603 pdata->dec_status = NULL;
6604 mutex_unlock(&vavs2_mutex);
6605 return -ENODEV;
6606 }
6607 /*set the max clk for smooth playing...*/
6608 hevc_source_changed(VFORMAT_AVS2,
6609 4096, 2048, 60);
6610 mutex_unlock(&vavs2_mutex);
6611
6612 return 0;
6613 }
6614
6615 static int amvdec_avs2_remove(struct platform_device *pdev)
6616 {
6617 struct AVS2Decoder_s *dec = &gAVS2Decoder;
6618 if (debug)
6619 pr_info("amvdec_avs2_remove\n");
6620
6621 mutex_lock(&vavs2_mutex);
6622
6623 vavs2_stop(dec);
6624
6625
6626 hevc_source_changed(VFORMAT_AVS2, 0, 0, 0);
6627
6628
6629 #ifdef DEBUG_PTS
6630 pr_info("pts missed %ld, pts hit %ld, duration %d\n",
6631 dec->pts_missed, dec->pts_hit, dec->frame_dur);
6632 #endif
6633
6634 mutex_unlock(&vavs2_mutex);
6635
6636 return 0;
6637 }
6638
6639 /****************************************/
6640 #ifdef CONFIG_PM
6641 static int avs2_suspend(struct device *dev)
6642 {
6643 amhevc_suspend(to_platform_device(dev), dev->power.power_state);
6644 return 0;
6645 }
6646
6647 static int avs2_resume(struct device *dev)
6648 {
6649 amhevc_resume(to_platform_device(dev));
6650 return 0;
6651 }
6652
6653 static const struct dev_pm_ops avs2_pm_ops = {
6654 SET_SYSTEM_SLEEP_PM_OPS(avs2_suspend, avs2_resume)
6655 };
6656 #endif
6657
6658 static struct platform_driver amvdec_avs2_driver = {
6659 .probe = amvdec_avs2_probe,
6660 .remove = amvdec_avs2_remove,
6661 .driver = {
6662 .name = DRIVER_NAME,
6663 #ifdef CONFIG_PM
6664 .pm = &avs2_pm_ops,
6665 #endif
6666 }
6667 };
6668
6669 static struct codec_profile_t amvdec_avs2_profile = {
6670 .name = "avs2",
6671 .profile = ""
6672 };
6673
6674 static struct codec_profile_t amvdec_avs2_profile_mult;
6675
6676 static unsigned char get_data_check_sum
6677 (struct AVS2Decoder_s *dec, int size)
6678 {
6679 int jj;
6680 int sum = 0;
6681 u8 *data = NULL;
6682
6683 if (!dec->chunk->block->is_mapped)
6684 data = codec_mm_vmap(dec->chunk->block->start +
6685 dec->chunk->offset, size);
6686 else
6687 data = ((u8 *)dec->chunk->block->start_virt) +
6688 dec->chunk->offset;
6689
6690 for (jj = 0; jj < size; jj++)
6691 sum += data[jj];
6692
6693 if (!dec->chunk->block->is_mapped)
6694 codec_mm_unmap_phyaddr(data);
6695 return sum;
6696 }
6697
6698 static void dump_data(struct AVS2Decoder_s *dec, int size)
6699 {
6700 int jj;
6701 u8 *data = NULL;
6702 int padding_size = dec->chunk->offset &
6703 (VDEC_FIFO_ALIGN - 1);
6704
6705 if (!dec->chunk->block->is_mapped)
6706 data = codec_mm_vmap(dec->chunk->block->start +
6707 dec->chunk->offset, size);
6708 else
6709 data = ((u8 *)dec->chunk->block->start_virt) +
6710 dec->chunk->offset;
6711
6712 avs2_print(dec, 0, "padding: ");
6713 for (jj = padding_size; jj > 0; jj--)
6714 avs2_print_cont(dec,
6715 0,
6716 "%02x ", *(data - jj));
6717 avs2_print_cont(dec, 0, "data adr %p\n",
6718 data);
6719
6720 for (jj = 0; jj < size; jj++) {
6721 if ((jj & 0xf) == 0)
6722 avs2_print(dec,
6723 0,
6724 "%06x:", jj);
6725 avs2_print_cont(dec,
6726 0,
6727 "%02x ", data[jj]);
6728 if (((jj + 1) & 0xf) == 0)
6729 avs2_print(dec,
6730 0,
6731 "\n");
6732 }
6733 avs2_print(dec,
6734 0,
6735 "\n");
6736
6737 if (!dec->chunk->block->is_mapped)
6738 codec_mm_unmap_phyaddr(data);
6739 }
6740
6741 static void avs2_work(struct work_struct *work)
6742 {
6743 struct AVS2Decoder_s *dec = container_of(work,
6744 struct AVS2Decoder_s, work);
6745 struct vdec_s *vdec = hw_to_vdec(dec);
6746 /* finished decoding one frame or error,
6747 * notify vdec core to switch context
6748 */
6749 avs2_print(dec, PRINT_FLAG_VDEC_DETAIL,
6750 "%s dec_result %d %x %x %x\n",
6751 __func__,
6752 dec->dec_result,
6753 READ_VREG(HEVC_STREAM_LEVEL),
6754 READ_VREG(HEVC_STREAM_WR_PTR),
6755 READ_VREG(HEVC_STREAM_RD_PTR));
6756
6757 if (((dec->dec_result == DEC_RESULT_GET_DATA) ||
6758 (dec->dec_result == DEC_RESULT_GET_DATA_RETRY))
6759 && (hw_to_vdec(dec)->next_status !=
6760 VDEC_STATUS_DISCONNECTED)) {
6761 if (!vdec_has_more_input(vdec)) {
6762 dec->dec_result = DEC_RESULT_EOS;
6763 vdec_schedule_work(&dec->work);
6764 return;
6765 }
6766
6767 if (dec->dec_result == DEC_RESULT_GET_DATA) {
6768 avs2_print(dec, PRINT_FLAG_VDEC_STATUS,
6769 "%s DEC_RESULT_GET_DATA %x %x %x\n",
6770 __func__,
6771 READ_VREG(HEVC_STREAM_LEVEL),
6772 READ_VREG(HEVC_STREAM_WR_PTR),
6773 READ_VREG(HEVC_STREAM_RD_PTR));
6774 vdec_vframe_dirty(vdec, dec->chunk);
6775 vdec_clean_input(vdec);
6776 }
6777
6778 if (get_free_buf_count(dec) >=
6779 run_ready_min_buf_num) {
6780 int r;
6781 int decode_size;
6782 r = vdec_prepare_input(vdec, &dec->chunk);
6783 if (r < 0) {
6784 dec->dec_result = DEC_RESULT_GET_DATA_RETRY;
6785
6786 avs2_print(dec,
6787 PRINT_FLAG_VDEC_DETAIL,
6788 "amvdec_vh265: Insufficient data\n");
6789
6790 vdec_schedule_work(&dec->work);
6791 return;
6792 }
6793 dec->dec_result = DEC_RESULT_NONE;
6794 avs2_print(dec, PRINT_FLAG_VDEC_STATUS,
6795 "%s: chunk size 0x%x sum 0x%x\n",
6796 __func__, r,
6797 (debug & PRINT_FLAG_VDEC_STATUS) ?
6798 get_data_check_sum(dec, r) : 0
6799 );
6800 if (debug & PRINT_FLAG_VDEC_DATA)
6801 dump_data(dec, dec->chunk->size);
6802
6803 decode_size = dec->chunk->size +
6804 (dec->chunk->offset & (VDEC_FIFO_ALIGN - 1));
6805
6806 WRITE_VREG(HEVC_DECODE_SIZE,
6807 READ_VREG(HEVC_DECODE_SIZE) + decode_size);
6808
6809 vdec_enable_input(vdec);
6810
6811 WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_ACTION_DONE);
6812
6813 start_process_time(dec);
6814
6815 } else{
6816 dec->dec_result = DEC_RESULT_GET_DATA_RETRY;
6817
6818 avs2_print(dec, PRINT_FLAG_VDEC_DETAIL,
6819 "amvdec_vh265: Insufficient data\n");
6820
6821 vdec_schedule_work(&dec->work);
6822 }
6823 return;
6824 } else if (dec->dec_result == DEC_RESULT_DONE) {
6825 /* if (!dec->ctx_valid)
6826 dec->ctx_valid = 1; */
6827 dec->slice_idx++;
6828 dec->frame_count++;
6829 dec->process_state = PROC_STATE_INIT;
6830 decode_frame_count[dec->index] = dec->frame_count;
6831
6832 #ifdef AVS2_10B_MMU
6833 dec->used_4k_num =
6834 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
6835 #endif
6836 avs2_print(dec, PRINT_FLAG_VDEC_STATUS,
6837 "%s (===> %d) dec_result %d %x %x %x shiftbytes 0x%x decbytes 0x%x\n",
6838 __func__,
6839 dec->frame_count,
6840 dec->dec_result,
6841 READ_VREG(HEVC_STREAM_LEVEL),
6842 READ_VREG(HEVC_STREAM_WR_PTR),
6843 READ_VREG(HEVC_STREAM_RD_PTR),
6844 READ_VREG(HEVC_SHIFT_BYTE_COUNT),
6845 READ_VREG(HEVC_SHIFT_BYTE_COUNT) -
6846 dec->start_shift_bytes
6847 );
6848 vdec_vframe_dirty(hw_to_vdec(dec), dec->chunk);
6849 } else if (dec->dec_result == DEC_RESULT_AGAIN) {
6850 /*
6851 stream base: stream buf empty or timeout
6852 frame base: vdec_prepare_input fail
6853 */
6854 if (!vdec_has_more_input(vdec)) {
6855 dec->dec_result = DEC_RESULT_EOS;
6856 vdec_schedule_work(&dec->work);
6857 return;
6858 }
6859 } else if (dec->dec_result == DEC_RESULT_EOS) {
6860 avs2_print(dec, 0,
6861 "%s: end of stream\n",
6862 __func__);
6863 dec->eos = 1;
6864 if ( dec->avs2_dec.hc.cur_pic != NULL) {
6865 check_pic_error(dec, dec->avs2_dec.hc.cur_pic);
6866 avs2_post_process(&dec->avs2_dec);
6867 avs2_prepare_display_buf(dec);
6868 }
6869 vdec_vframe_dirty(hw_to_vdec(dec), dec->chunk);
6870 } else if (dec->dec_result == DEC_RESULT_FORCE_EXIT) {
6871 avs2_print(dec, PRINT_FLAG_VDEC_STATUS,
6872 "%s: force exit\n",
6873 __func__);
6874 if (dec->stat & STAT_VDEC_RUN) {
6875 amhevc_stop();
6876 dec->stat &= ~STAT_VDEC_RUN;
6877 }
6878
6879 if (dec->stat & STAT_ISR_REG) {
6880 if (!dec->m_ins_flag)
6881 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
6882 vdec_free_irq(VDEC_IRQ_0, (void *)dec);
6883 dec->stat &= ~STAT_ISR_REG;
6884 }
6885 }
6886
6887 if (dec->stat & STAT_TIMER_ARM) {
6888 del_timer_sync(&dec->timer);
6889 dec->stat &= ~STAT_TIMER_ARM;
6890 }
6891 /* mark itself has all HW resource released and input released */
6892 if (vdec->parallel_dec ==1)
6893 vdec_core_finish_run(vdec, CORE_MASK_HEVC);
6894 else
6895 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
6896
6897 if (dec->vdec_cb)
6898 dec->vdec_cb(hw_to_vdec(dec), dec->vdec_cb_arg);
6899 }
6900
6901 static int avs2_hw_ctx_restore(struct AVS2Decoder_s *dec)
6902 {
6903 /* new to do ... */
6904 vavs2_prot_init(dec);
6905 return 0;
6906 }
6907
6908 static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
6909 {
6910 struct AVS2Decoder_s *dec =
6911 (struct AVS2Decoder_s *)vdec->private;
6912 int tvp = vdec_secure(hw_to_vdec(dec)) ?
6913 CODEC_MM_FLAGS_TVP : 0;
6914 unsigned long ret = 0;
6915 avs2_print(dec,
6916 PRINT_FLAG_VDEC_DETAIL, "%s\r\n", __func__);
6917 if (debug & AVS2_DBG_PIC_LEAK_WAIT)
6918 return ret;
6919
6920 if (dec->eos)
6921 return ret;
6922 if (!dec->first_sc_checked) {
6923 int size = decoder_mmu_box_sc_check(dec->mmu_box, tvp);
6924 dec->first_sc_checked = 1;
6925 avs2_print(dec, 0, "vavs2 cached=%d need_size=%d speed= %d ms\n",
6926 size, (dec->need_cache_size >> PAGE_SHIFT),
6927 (int)(get_jiffies_64() - dec->sc_start_time) * 1000/HZ);
6928 }
6929
6930 if (dec->next_again_flag &&
6931 (!vdec_frame_based(vdec))) {
6932 u32 parser_wr_ptr =
6933 STBUF_READ(&vdec->vbuf, get_wp);
6934 if (parser_wr_ptr >= dec->pre_parser_wr_ptr &&
6935 (parser_wr_ptr - dec->pre_parser_wr_ptr) <
6936 again_threshold) {
6937 int r = vdec_sync_input(vdec);
6938 avs2_print(dec,
6939 PRINT_FLAG_VDEC_DETAIL, "%s buf lelvel:%x\n", __func__, r);
6940 return 0;
6941 }
6942 }
6943 /*
6944 if (vdec_stream_based(vdec) && (dec->pic_list_init_flag == 0)
6945 && pre_decode_buf_level != 0) {
6946 u32 rp, wp, level;
6947
6948 rp = STBUF_READ(&vdec->vbuf, get_rp);
6949 wp = STBUF_READ(&vdec->vbuf, get_wp);
6950 if (wp < rp)
6951 level = vdec->input.size + wp - rp;
6952 else
6953 level = wp - rp;
6954
6955 if (level < pre_decode_buf_level)
6956 return 0;
6957 }
6958 */
6959
6960 if ((dec->pic_list_init_flag == 0) ||
6961 get_free_buf_count(dec) >=
6962 run_ready_min_buf_num)
6963 ret = 1;
6964 #ifdef CONSTRAIN_MAX_BUF_NUM
6965 if (dec->pic_list_init_flag) {
6966 if (run_ready_max_vf_only_num > 0 &&
6967 get_vf_ref_only_buf_count(dec) >=
6968 run_ready_max_vf_only_num
6969 )
6970 ret = 0;
6971 if (run_ready_display_q_num > 0 &&
6972 kfifo_len(&dec->display_q) >=
6973 run_ready_display_q_num)
6974 ret = 0;
6975
6976 if (run_ready_max_buf_num == 0xff &&
6977 get_used_buf_count(dec) >=
6978 dec->avs2_dec.ref_maxbuffer)
6979 ret = 0;
6980 else if (run_ready_max_buf_num &&
6981 get_used_buf_count(dec) >=
6982 run_ready_max_buf_num)
6983 ret = 0;
6984 }
6985 #endif
6986 if (ret)
6987 not_run_ready[dec->index] = 0;
6988 else
6989 not_run_ready[dec->index]++;
6990
6991 if (vdec->parallel_dec == 1)
6992 return ret ? CORE_MASK_HEVC : 0;
6993 else
6994 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
6995 }
6996
6997 static void run(struct vdec_s *vdec, unsigned long mask,
6998 void (*callback)(struct vdec_s *, void *), void *arg)
6999 {
7000 struct AVS2Decoder_s *dec =
7001 (struct AVS2Decoder_s *)vdec->private;
7002 int r;
7003
7004 run_count[dec->index]++;
7005 dec->vdec_cb_arg = arg;
7006 dec->vdec_cb = callback;
7007 /* dec->chunk = vdec_prepare_input(vdec); */
7008 hevc_reset_core(vdec);
7009
7010 if (vdec_stream_based(vdec)) {
7011 dec->pre_parser_wr_ptr =
7012 STBUF_READ(&vdec->vbuf, get_wp);
7013 dec->next_again_flag = 0;
7014 }
7015
7016 r = vdec_prepare_input(vdec, &dec->chunk);
7017 if (r < 0) {
7018 input_empty[dec->index]++;
7019
7020 dec->dec_result = DEC_RESULT_AGAIN;
7021
7022 avs2_print(dec, PRINT_FLAG_VDEC_DETAIL,
7023 "ammvdec_vh265: Insufficient data\n");
7024
7025 vdec_schedule_work(&dec->work);
7026 return;
7027 }
7028 input_empty[dec->index] = 0;
7029 dec->dec_result = DEC_RESULT_NONE;
7030 dec->start_shift_bytes = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
7031
7032 if (debug & PRINT_FLAG_VDEC_STATUS) {
7033 int ii;
7034 avs2_print(dec, 0,
7035 "%s (%d): size 0x%x (0x%x 0x%x) sum 0x%x (%x %x %x %x %x) bytes 0x%x",
7036 __func__,
7037 dec->frame_count, r,
7038 dec->chunk ? dec->chunk->size : 0,
7039 dec->chunk ? dec->chunk->offset : 0,
7040 dec->chunk ? ((vdec_frame_based(vdec) &&
7041 (debug & PRINT_FLAG_VDEC_STATUS)) ?
7042 get_data_check_sum(dec, r) : 0) : 0,
7043 READ_VREG(HEVC_STREAM_START_ADDR),
7044 READ_VREG(HEVC_STREAM_END_ADDR),
7045 READ_VREG(HEVC_STREAM_LEVEL),
7046 READ_VREG(HEVC_STREAM_WR_PTR),
7047 READ_VREG(HEVC_STREAM_RD_PTR),
7048 dec->start_shift_bytes);
7049 if (vdec_frame_based(vdec) && dec->chunk) {
7050 u8 *data = NULL;
7051 if (!dec->chunk->block->is_mapped)
7052 data = codec_mm_vmap(dec->chunk->block->start +
7053 dec->chunk->offset, 8);
7054 else
7055 data = ((u8 *)dec->chunk->block->start_virt) +
7056 dec->chunk->offset;
7057
7058 avs2_print_cont(dec, 0, "data adr %p:",
7059 data);
7060 for (ii = 0; ii < 8; ii++)
7061 avs2_print_cont(dec, 0, "%02x ",
7062 data[ii]);
7063 if (!dec->chunk->block->is_mapped)
7064 codec_mm_unmap_phyaddr(data);
7065 }
7066 avs2_print_cont(dec, 0, "\r\n");
7067 }
7068 if (vdec->mc_loaded) {
7069 /*firmware have load before,
7070 and not changes to another.
7071 ignore reload.
7072 */
7073 } else if (amhevc_loadmc_ex(VFORMAT_AVS2, NULL, dec->fw->data) < 0) {
7074 vdec->mc_loaded = 0;
7075 amhevc_disable();
7076 avs2_print(dec, 0,
7077 "%s: Error amvdec_loadmc fail\n", __func__);
7078 dec->dec_result = DEC_RESULT_FORCE_EXIT;
7079 vdec_schedule_work(&dec->work);
7080 return;
7081 } else {
7082 vdec->mc_loaded = 1;
7083 vdec->mc_type = VFORMAT_AVS2;
7084 }
7085
7086
7087 if (avs2_hw_ctx_restore(dec) < 0) {
7088 vdec_schedule_work(&dec->work);
7089 return;
7090 }
7091
7092 vdec_enable_input(vdec);
7093
7094 WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_SEARCH_NEW_PIC);
7095
7096 if (vdec_frame_based(vdec) && dec->chunk) {
7097 if (debug & PRINT_FLAG_VDEC_DATA)
7098 dump_data(dec, dec->chunk->size);
7099
7100 WRITE_VREG(HEVC_SHIFT_BYTE_COUNT, 0);
7101 r = dec->chunk->size +
7102 (dec->chunk->offset & (VDEC_FIFO_ALIGN - 1));
7103 if (vdec->mvfrm)
7104 vdec->mvfrm->frame_size = dec->chunk->size;
7105 }
7106
7107 WRITE_VREG(HEVC_DECODE_SIZE, r);
7108 WRITE_VREG(HEVC_DECODE_COUNT, dec->slice_idx);
7109 dec->init_flag = 1;
7110
7111 avs2_print(dec, PRINT_FLAG_VDEC_DETAIL,
7112 "%s: start hevc (%x %x %x)\n",
7113 __func__,
7114 READ_VREG(HEVC_DEC_STATUS_REG),
7115 READ_VREG(HEVC_MPC_E),
7116 READ_VREG(HEVC_MPSR));
7117
7118 start_process_time(dec);
7119 mod_timer(&dec->timer, jiffies);
7120 dec->stat |= STAT_TIMER_ARM;
7121 dec->stat |= STAT_ISR_REG;
7122 if (vdec->mvfrm)
7123 vdec->mvfrm->hw_decode_start = local_clock();
7124 amhevc_start();
7125 dec->stat |= STAT_VDEC_RUN;
7126 }
7127
7128 static void reset(struct vdec_s *vdec)
7129 {
7130
7131 struct AVS2Decoder_s *dec =
7132 (struct AVS2Decoder_s *)vdec->private;
7133
7134 avs2_print(dec,
7135 PRINT_FLAG_VDEC_DETAIL, "%s\r\n", __func__);
7136
7137 }
7138
7139 static irqreturn_t avs2_irq_cb(struct vdec_s *vdec, int irq)
7140 {
7141 struct AVS2Decoder_s *dec =
7142 (struct AVS2Decoder_s *)vdec->private;
7143 return vavs2_isr(0, dec);
7144 }
7145
7146 static irqreturn_t avs2_threaded_irq_cb(struct vdec_s *vdec, int irq)
7147 {
7148 struct AVS2Decoder_s *dec =
7149 (struct AVS2Decoder_s *)vdec->private;
7150 return vavs2_isr_thread_fn(0, dec);
7151 }
7152
7153 static void avs2_dump_state(struct vdec_s *vdec)
7154 {
7155 struct AVS2Decoder_s *dec =
7156 (struct AVS2Decoder_s *)vdec->private;
7157 int i;
7158 avs2_print(dec, 0, "====== %s\n", __func__);
7159
7160 avs2_print(dec, 0,
7161 "width/height (%d/%d), used_buf_num %d\n",
7162 dec->avs2_dec.img.width,
7163 dec->avs2_dec.img.height,
7164 dec->used_buf_num
7165 );
7166
7167 avs2_print(dec, 0,
7168 "is_framebase(%d), eos %d, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d\n",
7169 input_frame_based(vdec),
7170 dec->eos,
7171 dec->dec_result,
7172 decode_frame_count[dec->index],
7173 display_frame_count[dec->index],
7174 run_count[dec->index],
7175 not_run_ready[dec->index],
7176 input_empty[dec->index]
7177 );
7178
7179 if (vf_get_receiver(vdec->vf_provider_name)) {
7180 enum receviver_start_e state =
7181 vf_notify_receiver(vdec->vf_provider_name,
7182 VFRAME_EVENT_PROVIDER_QUREY_STATE,
7183 NULL);
7184 avs2_print(dec, 0,
7185 "\nreceiver(%s) state %d\n",
7186 vdec->vf_provider_name,
7187 state);
7188 }
7189
7190 avs2_print(dec, 0,
7191 "%s, newq(%d/%d), dispq(%d/%d), vf prepare/get/put (%d/%d/%d), free_buf_count %d (min %d for run_ready)\n",
7192 __func__,
7193 kfifo_len(&dec->newframe_q),
7194 VF_POOL_SIZE,
7195 kfifo_len(&dec->display_q),
7196 VF_POOL_SIZE,
7197 dec->vf_pre_count,
7198 dec->vf_get_count,
7199 dec->vf_put_count,
7200 get_free_buf_count(dec),
7201 run_ready_min_buf_num
7202 );
7203
7204 dump_pic_list(dec);
7205
7206 for (i = 0; i < MAX_BUF_NUM; i++) {
7207 avs2_print(dec, 0,
7208 "mv_Buf(%d) start_adr 0x%x size 0x%x used %d\n",
7209 i,
7210 dec->m_mv_BUF[i].start_adr,
7211 dec->m_mv_BUF[i].size,
7212 dec->m_mv_BUF[i].used_flag);
7213 }
7214
7215 avs2_print(dec, 0,
7216 "HEVC_DEC_STATUS_REG=0x%x\n",
7217 READ_VREG(HEVC_DEC_STATUS_REG));
7218 avs2_print(dec, 0,
7219 "HEVC_MPC_E=0x%x\n",
7220 READ_VREG(HEVC_MPC_E));
7221 avs2_print(dec, 0,
7222 "DECODE_MODE=0x%x\n",
7223 READ_VREG(DECODE_MODE));
7224 avs2_print(dec, 0,
7225 "NAL_SEARCH_CTL=0x%x\n",
7226 READ_VREG(NAL_SEARCH_CTL));
7227 avs2_print(dec, 0,
7228 "HEVC_PARSER_LCU_START=0x%x\n",
7229 READ_VREG(HEVC_PARSER_LCU_START));
7230 avs2_print(dec, 0,
7231 "HEVC_DECODE_SIZE=0x%x\n",
7232 READ_VREG(HEVC_DECODE_SIZE));
7233 avs2_print(dec, 0,
7234 "HEVC_SHIFT_BYTE_COUNT=0x%x\n",
7235 READ_VREG(HEVC_SHIFT_BYTE_COUNT));
7236 avs2_print(dec, 0,
7237 "HEVC_STREAM_START_ADDR=0x%x\n",
7238 READ_VREG(HEVC_STREAM_START_ADDR));
7239 avs2_print(dec, 0,
7240 "HEVC_STREAM_END_ADDR=0x%x\n",
7241 READ_VREG(HEVC_STREAM_END_ADDR));
7242 avs2_print(dec, 0,
7243 "HEVC_STREAM_LEVEL=0x%x\n",
7244 READ_VREG(HEVC_STREAM_LEVEL));
7245 avs2_print(dec, 0,
7246 "HEVC_STREAM_WR_PTR=0x%x\n",
7247 READ_VREG(HEVC_STREAM_WR_PTR));
7248 avs2_print(dec, 0,
7249 "HEVC_STREAM_RD_PTR=0x%x\n",
7250 READ_VREG(HEVC_STREAM_RD_PTR));
7251 avs2_print(dec, 0,
7252 "PARSER_VIDEO_RP=0x%x\n",
7253 STBUF_READ(&vdec->vbuf, get_rp));
7254 avs2_print(dec, 0,
7255 "PARSER_VIDEO_WP=0x%x\n",
7256 STBUF_READ(&vdec->vbuf, get_wp));
7257
7258 if (input_frame_based(vdec) &&
7259 (debug & PRINT_FLAG_VDEC_DATA)
7260 ) {
7261 int jj;
7262 if (dec->chunk && dec->chunk->block &&
7263 dec->chunk->size > 0) {
7264 u8 *data = NULL;
7265 if (!dec->chunk->block->is_mapped)
7266 data = codec_mm_vmap(dec->chunk->block->start +
7267 dec->chunk->offset, dec->chunk->size);
7268 else
7269 data = ((u8 *)dec->chunk->block->start_virt) +
7270 dec->chunk->offset;
7271 avs2_print(dec, 0,
7272 "frame data size 0x%x\n",
7273 dec->chunk->size);
7274 for (jj = 0; jj < dec->chunk->size; jj++) {
7275 if ((jj & 0xf) == 0)
7276 avs2_print(dec, 0,
7277 "%06x:", jj);
7278 avs2_print_cont(dec, 0,
7279 "%02x ", data[jj]);
7280 if (((jj + 1) & 0xf) == 0)
7281 avs2_print_cont(dec, 0,
7282 "\n");
7283 }
7284
7285 if (!dec->chunk->block->is_mapped)
7286 codec_mm_unmap_phyaddr(data);
7287 }
7288 }
7289
7290 }
7291
7292 static int ammvdec_avs2_probe(struct platform_device *pdev)
7293 {
7294 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
7295 int ret;
7296 int config_val;
7297 struct vframe_content_light_level_s content_light_level;
7298 struct vframe_master_display_colour_s vf_dp;
7299
7300 struct BUF_s BUF[MAX_BUF_NUM];
7301 struct AVS2Decoder_s *dec = NULL;
7302 pr_info("%s\n", __func__);
7303 if (pdata == NULL) {
7304 pr_info("\nammvdec_avs2 memory resource undefined.\n");
7305 return -EFAULT;
7306 }
7307 /*dec = (struct AVS2Decoder_s *)devm_kzalloc(&pdev->dev,
7308 sizeof(struct AVS2Decoder_s), GFP_KERNEL);*/
7309 memset(&vf_dp, 0, sizeof(struct vframe_master_display_colour_s));
7310 dec = vmalloc(sizeof(struct AVS2Decoder_s));
7311 memset(dec, 0, sizeof(struct AVS2Decoder_s));
7312 if (dec == NULL) {
7313 pr_info("\nammvdec_avs2 device data allocation failed\n");
7314 return -ENOMEM;
7315 }
7316 if (pdata->parallel_dec == 1) {
7317 int i;
7318 for (i = 0; i < AVS2_MAX_BUFFER_NUM; i++) {
7319 dec->avs2_dec.frm_pool[i].y_canvas_index = -1;
7320 dec->avs2_dec.frm_pool[i].uv_canvas_index = -1;
7321 }
7322 }
7323 pdata->private = dec;
7324 pdata->dec_status = vavs2_dec_status;
7325 #ifdef I_ONLY_SUPPORT
7326 pdata->set_trickmode = vavs2_set_trickmode;
7327 #endif
7328 pdata->run_ready = run_ready;
7329 pdata->run = run;
7330 pdata->reset = reset;
7331 pdata->irq_handler = avs2_irq_cb;
7332 pdata->threaded_irq_handler = avs2_threaded_irq_cb;
7333 pdata->dump_state = avs2_dump_state;
7334
7335 memcpy(&BUF[0], &dec->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
7336 memset(dec, 0, sizeof(struct AVS2Decoder_s));
7337 memcpy(&dec->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
7338
7339 dec->index = pdev->id;
7340 dec->m_ins_flag = 1;
7341
7342 if (pdata->use_vfm_path) {
7343 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
7344 VFM_DEC_PROVIDER_NAME);
7345 dec->frameinfo_enable = 1;
7346 } else
7347 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
7348 MULTI_INSTANCE_PROVIDER_NAME ".%02x", pdev->id & 0xff);
7349
7350 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
7351 &vavs2_vf_provider, dec);
7352
7353 dec->provider_name = pdata->vf_provider_name;
7354 platform_set_drvdata(pdev, pdata);
7355
7356 dec->platform_dev = pdev;
7357 dec->video_signal_type = 0;
7358 dec->video_ori_signal_type = 0;
7359 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX)
7360 dec->stat |= VP9_TRIGGER_FRAME_ENABLE;
7361 #if 1
7362 if ((debug & IGNORE_PARAM_FROM_CONFIG) == 0 &&
7363 pdata->config_len) {
7364 /*use ptr config for doubel_write_mode, etc*/
7365 avs2_print(dec, 0, "pdata->config=%s\n", pdata->config);
7366 if (get_config_int(pdata->config, "avs2_double_write_mode",
7367 &config_val) == 0)
7368 dec->double_write_mode = config_val;
7369 else
7370 dec->double_write_mode = double_write_mode;
7371
7372 if (get_config_int(pdata->config, "parm_v4l_buffer_margin",
7373 &config_val) == 0)
7374 dec->dynamic_buf_margin = config_val;
7375 else
7376 dec->dynamic_buf_margin = 0;
7377
7378 if (get_config_int(pdata->config, "sidebind_type",
7379 &config_val) == 0)
7380 dec->sidebind_type = config_val;
7381
7382 if (get_config_int(pdata->config, "sidebind_channel_id",
7383 &config_val) == 0)
7384 dec->sidebind_channel_id = config_val;
7385
7386 if (get_config_int(pdata->config, "HDRStaticInfo",
7387 &vf_dp.present_flag) == 0
7388 && vf_dp.present_flag == 1) {
7389 get_config_int(pdata->config, "mG.x",
7390 &vf_dp.primaries[0][0]);
7391 get_config_int(pdata->config, "mG.y",
7392 &vf_dp.primaries[0][1]);
7393 get_config_int(pdata->config, "mB.x",
7394 &vf_dp.primaries[1][0]);
7395 get_config_int(pdata->config, "mB.y",
7396 &vf_dp.primaries[1][1]);
7397 get_config_int(pdata->config, "mR.x",
7398 &vf_dp.primaries[2][0]);
7399 get_config_int(pdata->config, "mR.y",
7400 &vf_dp.primaries[2][1]);
7401 get_config_int(pdata->config, "mW.x",
7402 &vf_dp.white_point[0]);
7403 get_config_int(pdata->config, "mW.y",
7404 &vf_dp.white_point[1]);
7405 get_config_int(pdata->config, "mMaxDL",
7406 &vf_dp.luminance[0]);
7407 get_config_int(pdata->config, "mMinDL",
7408 &vf_dp.luminance[1]);
7409 vf_dp.content_light_level.present_flag = 1;
7410 get_config_int(pdata->config, "mMaxCLL",
7411 &content_light_level.max_content);
7412 get_config_int(pdata->config, "mMaxFALL",
7413 &content_light_level.max_pic_average);
7414 vf_dp.content_light_level = content_light_level;
7415 dec->video_signal_type = (1 << 29)
7416 | (5 << 26) /* unspecified */
7417 | (0 << 25) /* limit */
7418 | (1 << 24) /* color available */
7419 | (9 << 16) /* 2020 */
7420 | (16 << 8) /* 2084 */
7421 | (9 << 0); /* 2020 */
7422 }
7423 dec->vf_dp = vf_dp;
7424 } else
7425 #endif
7426 {
7427 /*dec->vavs2_amstream_dec_info.width = 0;
7428 dec->vavs2_amstream_dec_info.height = 0;
7429 dec->vavs2_amstream_dec_info.rate = 30;*/
7430 dec->double_write_mode = double_write_mode;
7431 dec->dynamic_buf_margin = dynamic_buf_num_margin;
7432 }
7433 video_signal_type = dec->video_signal_type;
7434
7435 #if 0
7436 dec->buf_start = pdata->mem_start;
7437 dec->buf_size = pdata->mem_end - pdata->mem_start + 1;
7438 #else
7439 if (amvdec_avs2_mmu_init(dec) < 0) {
7440 pr_err("avs2 alloc bmmu box failed!!\n");
7441 /* devm_kfree(&pdev->dev, (void *)dec); */
7442 vfree((void *)dec);
7443 return -1;
7444 }
7445 dec->cma_alloc_count = PAGE_ALIGN(work_buf_size) / PAGE_SIZE;
7446 ret = decoder_bmmu_box_alloc_buf_phy(dec->bmmu_box, WORK_SPACE_BUF_ID,
7447 dec->cma_alloc_count * PAGE_SIZE, DRIVER_NAME,
7448 &dec->cma_alloc_addr);
7449 if (ret < 0) {
7450 uninit_mmu_buffers(dec);
7451 /* devm_kfree(&pdev->dev, (void *)dec); */
7452 vfree((void *)dec);
7453 return ret;
7454 }
7455 dec->buf_start = dec->cma_alloc_addr;
7456 dec->buf_size = work_buf_size;
7457 #endif
7458 dec->init_flag = 0;
7459 dec->first_sc_checked = 0;
7460 dec->fatal_error = 0;
7461 dec->show_frame_num = 0;
7462
7463 if (debug) {
7464 pr_info("===AVS2 decoder mem resource 0x%lx size 0x%x\n",
7465 dec->buf_start,
7466 dec->buf_size);
7467 }
7468
7469 if (pdata->sys_info) {
7470 dec->vavs2_amstream_dec_info = *pdata->sys_info;
7471 dec->frame_width = dec->vavs2_amstream_dec_info.width;
7472 dec->frame_height = dec->vavs2_amstream_dec_info.height;
7473 } else {
7474 dec->vavs2_amstream_dec_info.width = 0;
7475 dec->vavs2_amstream_dec_info.height = 0;
7476 dec->vavs2_amstream_dec_info.rate = 30;
7477 }
7478
7479 dec->cma_dev = pdata->cma_dev;
7480 if (vavs2_init(pdata) < 0) {
7481 pr_info("\namvdec_avs2 init failed.\n");
7482 avs2_local_uninit(dec);
7483 uninit_mmu_buffers(dec);
7484 /* devm_kfree(&pdev->dev, (void *)dec); */
7485 vfree((void *)dec);
7486 pdata->dec_status = NULL;
7487 return -ENODEV;
7488 }
7489 vdec_set_prepare_level(pdata, start_decode_buf_level);
7490 hevc_source_changed(VFORMAT_AVS2,
7491 4096, 2048, 60);
7492 if (pdata->parallel_dec == 1)
7493 vdec_core_request(pdata, CORE_MASK_HEVC);
7494 else {
7495 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
7496 | CORE_MASK_COMBINE);
7497 }
7498
7499 return 0;
7500 }
7501
7502 static int ammvdec_avs2_remove(struct platform_device *pdev)
7503 {
7504 struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)
7505 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
7506 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
7507 int i;
7508
7509 if (debug)
7510 pr_info("amvdec_avs2_remove\n");
7511
7512 vmavs2_stop(dec);
7513
7514 if (pdata->parallel_dec == 1)
7515 vdec_core_release(hw_to_vdec(dec), CORE_MASK_HEVC);
7516 else
7517 vdec_core_release(hw_to_vdec(dec), CORE_MASK_HEVC);
7518
7519 vdec_set_status(hw_to_vdec(dec), VDEC_STATUS_DISCONNECTED);
7520 if (pdata->parallel_dec == 1) {
7521 for (i = 0; i < AVS2_MAX_BUFFER_NUM; i++) {
7522 pdata->free_canvas_ex(dec->avs2_dec.frm_pool[i].y_canvas_index, pdata->id);
7523 pdata->free_canvas_ex(dec->avs2_dec.frm_pool[i].uv_canvas_index, pdata->id);
7524 }
7525 }
7526
7527
7528 #ifdef DEBUG_PTS
7529 pr_info("pts missed %ld, pts hit %ld, duration %d\n",
7530 dec->pts_missed, dec->pts_hit, dec->frame_dur);
7531 #endif
7532 /* devm_kfree(&pdev->dev, (void *)dec); */
7533 vfree((void *)dec);
7534 return 0;
7535 }
7536
7537 static struct platform_driver ammvdec_avs2_driver = {
7538 .probe = ammvdec_avs2_probe,
7539 .remove = ammvdec_avs2_remove,
7540 .driver = {
7541 .name = MULTI_DRIVER_NAME,
7542 #ifdef CONFIG_PM
7543 .pm = &avs2_pm_ops,
7544 #endif
7545 }
7546 };
7547 #endif
7548 static struct mconfig avs2_configs[] = {
7549 MC_PU32("bit_depth_luma", &bit_depth_luma),
7550 MC_PU32("bit_depth_chroma", &bit_depth_chroma),
7551 MC_PU32("frame_width", &frame_width),
7552 MC_PU32("frame_height", &frame_height),
7553 MC_PU32("debug", &debug),
7554 MC_PU32("radr", &radr),
7555 MC_PU32("rval", &rval),
7556 MC_PU32("pop_shorts", &pop_shorts),
7557 MC_PU32("dbg_cmd", &dbg_cmd),
7558 MC_PU32("dbg_skip_decode_index", &dbg_skip_decode_index),
7559 MC_PU32("endian", &endian),
7560 MC_PU32("step", &step),
7561 MC_PU32("udebug_flag", &udebug_flag),
7562 MC_PU32("decode_pic_begin", &decode_pic_begin),
7563 MC_PU32("slice_parse_begin", &slice_parse_begin),
7564 MC_PU32("i_only_flag", &i_only_flag),
7565 MC_PU32("error_handle_policy", &error_handle_policy),
7566 MC_PU32("buf_alloc_width", &buf_alloc_width),
7567 MC_PU32("buf_alloc_height", &buf_alloc_height),
7568 MC_PU32("buf_alloc_depth", &buf_alloc_depth),
7569 MC_PU32("buf_alloc_size", &buf_alloc_size),
7570 MC_PU32("buffer_mode", &buffer_mode),
7571 MC_PU32("buffer_mode_dbg", &buffer_mode_dbg),
7572 MC_PU32("max_buf_num", &max_buf_num),
7573 MC_PU32("dynamic_buf_num_margin", &dynamic_buf_num_margin),
7574 MC_PU32("mem_map_mode", &mem_map_mode),
7575 MC_PU32("double_write_mode", &double_write_mode),
7576 MC_PU32("enable_mem_saving", &enable_mem_saving),
7577 MC_PU32("force_w_h", &force_w_h),
7578 MC_PU32("force_fps", &force_fps),
7579 MC_PU32("max_decoding_time", &max_decoding_time),
7580 MC_PU32("on_no_keyframe_skiped", &on_no_keyframe_skiped),
7581 MC_PU32("start_decode_buf_level", &start_decode_buf_level),
7582 MC_PU32("decode_timeout_val", &decode_timeout_val),
7583 };
7584 static struct mconfig_node avs2_node;
7585
7586 static int __init amvdec_avs2_driver_init_module(void)
7587 {
7588
7589 #ifdef AVS2_10B_MMU
7590
7591 struct BuffInfo_s *p_buf_info;
7592
7593 if (vdec_is_support_4k()) {
7594 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
7595 p_buf_info = &amvavs2_workbuff_spec[2];
7596 else
7597 p_buf_info = &amvavs2_workbuff_spec[1];
7598 } else
7599 p_buf_info = &amvavs2_workbuff_spec[0];
7600
7601 init_buff_spec(NULL, p_buf_info);
7602 work_buf_size =
7603 (p_buf_info->end_adr - p_buf_info->start_adr
7604 + 0xffff) & (~0xffff);
7605
7606 #endif
7607 pr_debug("amvdec_avs2 module init\n");
7608
7609 #ifdef ERROR_HANDLE_DEBUG
7610 dbg_nal_skip_flag = 0;
7611 dbg_nal_skip_count = 0;
7612 #endif
7613 udebug_flag = 0;
7614 decode_pic_begin = 0;
7615 slice_parse_begin = 0;
7616 step = 0;
7617 buf_alloc_size = 0;
7618 if (platform_driver_register(&ammvdec_avs2_driver))
7619 pr_err("failed to register ammvdec_avs2 driver\n");
7620
7621 if (platform_driver_register(&amvdec_avs2_driver)) {
7622 pr_err("failed to register amvdec_avs2 driver\n");
7623 return -ENODEV;
7624 }
7625
7626 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
7627 amvdec_avs2_profile.profile =
7628 "8k, 10bit, dwrite, compressed";
7629 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
7630 if (vdec_is_support_4k())
7631 amvdec_avs2_profile.profile =
7632 "4k, 10bit, dwrite, compressed";
7633 else
7634 amvdec_avs2_profile.profile =
7635 "10bit, dwrite, compressed";
7636 } else {
7637 amvdec_avs2_profile.name = "avs2_unsupport";
7638 }
7639
7640 vcodec_profile_register(&amvdec_avs2_profile);
7641 amvdec_avs2_profile_mult = amvdec_avs2_profile;
7642 amvdec_avs2_profile_mult.name = "mavs2";
7643 vcodec_profile_register(&amvdec_avs2_profile_mult);
7644
7645 INIT_REG_NODE_CONFIGS("media.decoder", &avs2_node,
7646 "avs2", avs2_configs, CONFIG_FOR_RW);
7647
7648 return 0;
7649 }
7650
7651 static void __exit amvdec_avs2_driver_remove_module(void)
7652 {
7653 pr_debug("amvdec_avs2 module remove.\n");
7654 platform_driver_unregister(&ammvdec_avs2_driver);
7655 platform_driver_unregister(&amvdec_avs2_driver);
7656 }
7657
7658 /****************************************/
7659
7660 module_param(bit_depth_luma, uint, 0664);
7661 MODULE_PARM_DESC(bit_depth_luma, "\n amvdec_avs2 bit_depth_luma\n");
7662
7663 module_param(bit_depth_chroma, uint, 0664);
7664 MODULE_PARM_DESC(bit_depth_chroma, "\n amvdec_avs2 bit_depth_chroma\n");
7665
7666 module_param(frame_width, uint, 0664);
7667 MODULE_PARM_DESC(frame_width, "\n amvdec_avs2 frame_width\n");
7668
7669 module_param(frame_height, uint, 0664);
7670 MODULE_PARM_DESC(frame_height, "\n amvdec_avs2 frame_height\n");
7671
7672 module_param(debug, uint, 0664);
7673 MODULE_PARM_DESC(debug, "\n amvdec_avs2 debug\n");
7674
7675 module_param(debug_again, uint, 0664);
7676 MODULE_PARM_DESC(debug_again, "\n amvdec_avs2 debug_again\n");
7677
7678 module_param(radr, uint, 0664);
7679 MODULE_PARM_DESC(radr, "\nradr\n");
7680
7681 module_param(rval, uint, 0664);
7682 MODULE_PARM_DESC(rval, "\nrval\n");
7683
7684 module_param(pop_shorts, uint, 0664);
7685 MODULE_PARM_DESC(pop_shorts, "\nrval\n");
7686
7687 module_param(dbg_cmd, uint, 0664);
7688 MODULE_PARM_DESC(dbg_cmd, "\ndbg_cmd\n");
7689
7690 module_param(dbg_skip_decode_index, uint, 0664);
7691 MODULE_PARM_DESC(dbg_skip_decode_index, "\ndbg_skip_decode_index\n");
7692
7693 module_param(endian, uint, 0664);
7694 MODULE_PARM_DESC(endian, "\nrval\n");
7695
7696 module_param(step, uint, 0664);
7697 MODULE_PARM_DESC(step, "\n amvdec_avs2 step\n");
7698
7699 module_param(decode_pic_begin, uint, 0664);
7700 MODULE_PARM_DESC(decode_pic_begin, "\n amvdec_avs2 decode_pic_begin\n");
7701
7702 module_param(slice_parse_begin, uint, 0664);
7703 MODULE_PARM_DESC(slice_parse_begin, "\n amvdec_avs2 slice_parse_begin\n");
7704
7705 module_param(i_only_flag, uint, 0664);
7706 MODULE_PARM_DESC(i_only_flag, "\n amvdec_avs2 i_only_flag\n");
7707
7708 module_param(error_handle_policy, uint, 0664);
7709 MODULE_PARM_DESC(error_handle_policy, "\n amvdec_avs2 error_handle_policy\n");
7710
7711 module_param(re_search_seq_threshold, uint, 0664);
7712 MODULE_PARM_DESC(re_search_seq_threshold, "\n amvdec_avs2 re_search_seq_threshold\n");
7713
7714 module_param(buf_alloc_width, uint, 0664);
7715 MODULE_PARM_DESC(buf_alloc_width, "\n buf_alloc_width\n");
7716
7717 module_param(buf_alloc_height, uint, 0664);
7718 MODULE_PARM_DESC(buf_alloc_height, "\n buf_alloc_height\n");
7719
7720 module_param(buf_alloc_depth, uint, 0664);
7721 MODULE_PARM_DESC(buf_alloc_depth, "\n buf_alloc_depth\n");
7722
7723 module_param(buf_alloc_size, uint, 0664);
7724 MODULE_PARM_DESC(buf_alloc_size, "\n buf_alloc_size\n");
7725
7726 module_param(buffer_mode, uint, 0664);
7727 MODULE_PARM_DESC(buffer_mode, "\n buffer_mode\n");
7728
7729 module_param(buffer_mode_dbg, uint, 0664);
7730 MODULE_PARM_DESC(buffer_mode_dbg, "\n buffer_mode_dbg\n");
7731 /*USE_BUF_BLOCK*/
7732 module_param(max_buf_num, uint, 0664);
7733 MODULE_PARM_DESC(max_buf_num, "\n max_buf_num\n");
7734
7735 module_param(dynamic_buf_num_margin, uint, 0664);
7736 MODULE_PARM_DESC(dynamic_buf_num_margin, "\n dynamic_buf_num_margin\n");
7737
7738 #ifdef CONSTRAIN_MAX_BUF_NUM
7739 module_param(run_ready_max_vf_only_num, uint, 0664);
7740 MODULE_PARM_DESC(run_ready_max_vf_only_num, "\n run_ready_max_vf_only_num\n");
7741
7742 module_param(run_ready_display_q_num, uint, 0664);
7743 MODULE_PARM_DESC(run_ready_display_q_num, "\n run_ready_display_q_num\n");
7744
7745 module_param(run_ready_max_buf_num, uint, 0664);
7746 MODULE_PARM_DESC(run_ready_max_buf_num, "\n run_ready_max_buf_num\n");
7747 #endif
7748
7749 module_param(mv_buf_margin, uint, 0664);
7750 MODULE_PARM_DESC(mv_buf_margin, "\n mv_buf_margin\n");
7751
7752 module_param(run_ready_min_buf_num, uint, 0664);
7753 MODULE_PARM_DESC(run_ready_min_buf_num, "\n run_ready_min_buf_num\n");
7754
7755 /**/
7756
7757 module_param(mem_map_mode, uint, 0664);
7758 MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
7759
7760 module_param(double_write_mode, uint, 0664);
7761 MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
7762
7763 module_param(enable_mem_saving, uint, 0664);
7764 MODULE_PARM_DESC(enable_mem_saving, "\n enable_mem_saving\n");
7765
7766 module_param(force_w_h, uint, 0664);
7767 MODULE_PARM_DESC(force_w_h, "\n force_w_h\n");
7768
7769 module_param(force_fps, uint, 0664);
7770 MODULE_PARM_DESC(force_fps, "\n force_fps\n");
7771
7772 module_param(max_decoding_time, uint, 0664);
7773 MODULE_PARM_DESC(max_decoding_time, "\n max_decoding_time\n");
7774
7775 module_param(on_no_keyframe_skiped, uint, 0664);
7776 MODULE_PARM_DESC(on_no_keyframe_skiped, "\n on_no_keyframe_skiped\n");
7777
7778
7779 module_param(start_decode_buf_level, int, 0664);
7780 MODULE_PARM_DESC(start_decode_buf_level,
7781 "\n avs2 start_decode_buf_level\n");
7782
7783 module_param(decode_timeout_val, uint, 0664);
7784 MODULE_PARM_DESC(decode_timeout_val,
7785 "\n avs2 decode_timeout_val\n");
7786
7787 module_param_array(decode_frame_count, uint,
7788 &max_decode_instance_num, 0664);
7789
7790 module_param_array(display_frame_count, uint,
7791 &max_decode_instance_num, 0664);
7792
7793 module_param_array(max_process_time, uint,
7794 &max_decode_instance_num, 0664);
7795
7796 module_param_array(run_count, uint,
7797 &max_decode_instance_num, 0664);
7798
7799 module_param_array(input_empty, uint,
7800 &max_decode_instance_num, 0664);
7801
7802 module_param_array(not_run_ready, uint,
7803 &max_decode_instance_num, 0664);
7804
7805 module_param(video_signal_type, uint, 0664);
7806 MODULE_PARM_DESC(video_signal_type, "\n amvdec_avs2 video_signal_type\n");
7807
7808 module_param(force_video_signal_type, uint, 0664);
7809 MODULE_PARM_DESC(force_video_signal_type, "\n amvdec_avs2 force_video_signal_type\n");
7810
7811 module_param(enable_force_video_signal_type, uint, 0664);
7812 MODULE_PARM_DESC(enable_force_video_signal_type, "\n amvdec_avs2 enable_force_video_signal_type\n");
7813
7814
7815 module_param(udebug_flag, uint, 0664);
7816 MODULE_PARM_DESC(udebug_flag, "\n amvdec_h265 udebug_flag\n");
7817
7818 module_param(udebug_pause_pos, uint, 0664);
7819 MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
7820
7821 module_param(udebug_pause_val, uint, 0664);
7822 MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
7823
7824 module_param(udebug_pause_decode_idx, uint, 0664);
7825 MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
7826
7827 module_param(pre_decode_buf_level, int, 0664);
7828 MODULE_PARM_DESC(pre_decode_buf_level,
7829 "\n amvdec_avs2 pre_decode_buf_level\n");
7830
7831 module_param(again_threshold, uint, 0664);
7832 MODULE_PARM_DESC(again_threshold, "\n again_threshold\n");
7833
7834
7835 module_param(force_disp_pic_index, int, 0664);
7836 MODULE_PARM_DESC(force_disp_pic_index,
7837 "\n amvdec_h265 force_disp_pic_index\n");
7838
7839 module_param(without_display_mode, uint, 0664);
7840 MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
7841
7842 module_init(amvdec_avs2_driver_init_module);
7843 module_exit(amvdec_avs2_driver_remove_module);
7844
7845 MODULE_DESCRIPTION("AMLOGIC avs2 Video Decoder Driver");
7846 MODULE_LICENSE("GPL");
7847 MODULE_AUTHOR("Tim Yao <tim.yao@amlogic.com>");
7848