1 /*
2 * Linux DHD Bus Module for PCIE
3 *
4 * Copyright (C) 2020, Broadcom.
5 *
6 * Unless you and Broadcom execute a separate written software license
7 * agreement governing use of this software, this software is licensed to you
8 * under the terms of the GNU General Public License version 2 (the "GPL"),
9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
10 * following added to such license:
11 *
12 * As a special exception, the copyright holders of this software give you
13 * permission to link this software with independent modules, and to copy and
14 * distribute the resulting executable under terms of your choice, provided that
15 * you also meet, for each linked independent module, the terms and conditions of
16 * the license of that module. An independent module is a module which is not
17 * derived from this software. The special exception does not apply to any
18 * modifications of the software.
19 *
20 *
21 * <<Broadcom-WL-IPTag/Open:>>
22 *
23 * $Id$
24 */
25
26 #ifndef dhd_pcie_h
27 #define dhd_pcie_h
28
29 #include <bcmpcie.h>
30 #include <hnd_cons.h>
31 #include <dhd_linux.h>
32 #ifdef SUPPORT_LINKDOWN_RECOVERY
33 #ifdef CONFIG_ARCH_MSM
34 #ifdef CONFIG_PCI_MSM
35 #include <linux/msm_pcie.h>
36 #else
37 #include <mach/msm_pcie.h>
38 #endif /* CONFIG_PCI_MSM */
39 #endif /* CONFIG_ARCH_MSM */
40 #ifdef CONFIG_ARCH_EXYNOS
41 #ifndef SUPPORT_EXYNOS7420
42 #include <linux/exynos-pci-noti.h>
43 extern int exynos_pcie_register_event(struct exynos_pcie_register_event *reg);
44 extern int exynos_pcie_deregister_event(struct exynos_pcie_register_event *reg);
45 #endif /* !SUPPORT_EXYNOS7420 */
46 #endif /* CONFIG_ARCH_EXYNOS */
47 #endif /* SUPPORT_LINKDOWN_RECOVERY */
48
49 #ifdef DHD_PCIE_RUNTIMEPM
50 #include <linux/mutex.h>
51 #include <linux/wait.h>
52 #endif /* DHD_PCIE_RUNTIMEPM */
53
54 /* defines */
55 #define PCIE_SHARED_VERSION PCIE_SHARED_VERSION_7
56
57 #define PCMSGBUF_HDRLEN 0
58 #define DONGLE_REG_MAP_SIZE (32 * 1024)
59 #define DONGLE_TCM_MAP_SIZE (4096 * 1024)
60 #define DONGLE_MIN_MEMSIZE (128 *1024)
61 #ifdef DHD_DEBUG
62 #define DHD_PCIE_SUCCESS 0
63 #define DHD_PCIE_FAILURE 1
64 #endif /* DHD_DEBUG */
65 #define REMAP_ENAB(bus) ((bus)->remap)
66 #define REMAP_ISADDR(bus, a) (((a) >= ((bus)->orig_ramsize)) && ((a) < ((bus)->ramsize)))
67
68 #ifdef SUPPORT_LINKDOWN_RECOVERY
69 #ifdef CONFIG_ARCH_MSM
70 #define struct_pcie_notify struct msm_pcie_notify
71 #define struct_pcie_register_event struct msm_pcie_register_event
72 #endif /* CONFIG_ARCH_MSM */
73 #ifdef CONFIG_ARCH_EXYNOS
74 #ifndef SUPPORT_EXYNOS7420
75 #define struct_pcie_notify struct exynos_pcie_notify
76 #define struct_pcie_register_event struct exynos_pcie_register_event
77 #endif /* !SUPPORT_EXYNOS7420 */
78 #endif /* CONFIG_ARCH_EXYNOS */
79 #endif /* SUPPORT_LINKDOWN_RECOVERY */
80
81 #define MAX_DHD_TX_FLOWS 320
82
83 /* user defined data structures */
84 /* Device console log buffer state */
85 #define CONSOLE_LINE_MAX 192u
86 #define CONSOLE_BUFFER_MAX (8 * 1024)
87
88 #ifdef IDLE_TX_FLOW_MGMT
89 #define IDLE_FLOW_LIST_TIMEOUT 5000
90 #define IDLE_FLOW_RING_TIMEOUT 5000
91 #endif /* IDLE_TX_FLOW_MGMT */
92
93 #ifdef DEVICE_TX_STUCK_DETECT
94 #define DEVICE_TX_STUCK_CKECK_TIMEOUT 1000 /* 1 sec */
95 #define DEVICE_TX_STUCK_TIMEOUT 10000 /* 10 secs */
96 #define DEVICE_TX_STUCK_WARN_DURATION (DEVICE_TX_STUCK_TIMEOUT / DEVICE_TX_STUCK_CKECK_TIMEOUT)
97 #define DEVICE_TX_STUCK_DURATION (DEVICE_TX_STUCK_WARN_DURATION * 2)
98 #endif /* DEVICE_TX_STUCK_DETECT */
99
100 /* implicit DMA for h2d wr and d2h rd indice from Host memory to TCM */
101 #define IDMA_ENAB(dhd) ((dhd) && (dhd)->idma_enable)
102 #define IDMA_ACTIVE(dhd) ((dhd) && ((dhd)->idma_enable) && ((dhd)->idma_inited))
103
104 #define IDMA_CAPABLE(bus) (((bus)->sih->buscorerev == 19) || ((bus)->sih->buscorerev >= 23))
105
106 /* IFRM (Implicit Flow Ring Manager enable and inited */
107 #define IFRM_ENAB(dhd) ((dhd) && (dhd)->ifrm_enable)
108 #define IFRM_ACTIVE(dhd) ((dhd) && ((dhd)->ifrm_enable) && ((dhd)->ifrm_inited))
109
110 /* DAR registers use for h2d doorbell */
111 #define DAR_ENAB(dhd) ((dhd) && (dhd)->dar_enable)
112 #define DAR_ACTIVE(dhd) ((dhd) && ((dhd)->dar_enable) && ((dhd)->dar_inited))
113
114 /* DAR WAR for revs < 64 */
115 #define DAR_PWRREQ(bus) (((bus)->_dar_war) && DAR_ACTIVE((bus)->dhd))
116
117 /* PCIE CTO Prevention and Recovery */
118 #define PCIECTO_ENAB(bus) ((bus)->cto_enable)
119
120 /* Implicit DMA index usage :
121 * Index 0 for h2d write index transfer
122 * Index 1 for d2h read index transfer
123 */
124 #define IDMA_IDX0 0
125 #define IDMA_IDX1 1
126 #define IDMA_IDX2 2
127 #define IDMA_IDX3 3
128 #define DMA_TYPE_SHIFT 4
129 #define DMA_TYPE_IDMA 1
130
131 #define DHDPCIE_CONFIG_HDR_SIZE 16
132 #define DHDPCIE_CONFIG_CHECK_DELAY_MS 10 /* 10ms */
133 #define DHDPCIE_CONFIG_CHECK_RETRY_COUNT 20
134 #define DHDPCIE_DONGLE_PWR_TOGGLE_DELAY 1000 /* 1ms in units of us */
135 #define DHDPCIE_PM_D3_DELAY 200000 /* 200ms in units of us */
136 #define DHDPCIE_PM_D2_DELAY 200 /* 200us */
137
138 typedef struct dhd_console {
139 uint count; /* Poll interval msec counter */
140 uint log_addr; /* Log struct address (fixed) */
141 hnd_log_t log; /* Log struct (host copy) */
142 uint bufsize; /* Size of log buffer */
143 uint8 *buf; /* Log buffer (host copy) */
144 uint last; /* Last buffer read index */
145 } dhd_console_t;
146
147 typedef struct ring_sh_info {
148 uint32 ring_mem_addr;
149 uint32 ring_state_w;
150 uint32 ring_state_r;
151 pcie_hwa_db_index_t ring_hwa_db_idx; /* HWA DB index value per ring */
152 } ring_sh_info_t;
153 #define MAX_DS_TRACE_SIZE 50
154 #ifdef DHD_MMIO_TRACE
155 #define MAX_MMIO_TRACE_SIZE 256
156 /* Minimum of 250us should be elapsed to add new entry */
157 #define MIN_MMIO_TRACE_TIME 250
158 #define DHD_RING_IDX 0x00FF0000
159 typedef struct _dhd_mmio_trace_t {
160 uint64 timestamp;
161 uint32 addr;
162 uint32 value;
163 bool set;
164 } dhd_mmio_trace_t;
165 #endif /* defined(DHD_MMIO_TRACE) */
166 typedef struct _dhd_ds_trace_t {
167 uint64 timestamp;
168 bool d2h;
169 uint32 dsval;
170 #ifdef PCIE_INB_DW
171 enum dhd_bus_ds_state inbstate;
172 #endif /* PCIE_INB_DW */
173 } dhd_ds_trace_t;
174
175 #define DEVICE_WAKE_NONE 0
176 #define DEVICE_WAKE_OOB 1
177 #define DEVICE_WAKE_INB 2
178
179 #define INBAND_DW_ENAB(bus) ((bus)->dw_option == DEVICE_WAKE_INB)
180 #define OOB_DW_ENAB(bus) ((bus)->dw_option == DEVICE_WAKE_OOB)
181 #define NO_DW_ENAB(bus) ((bus)->dw_option == DEVICE_WAKE_NONE)
182
183 #define PCIE_PWR_REQ_RELOAD_WAR_ENAB(buscorerev) \
184 ((buscorerev == 66) || (buscorerev == 67) || (buscorerev == 68) || \
185 (buscorerev == 70) || (buscorerev == 72))
186
187 #define PCIE_FASTLPO_ENABLED(buscorerev) \
188 ((buscorerev == 66) || (buscorerev == 67) || (buscorerev == 68) || \
189 (buscorerev == 70) || (buscorerev == 72))
190
191 /*
192 * HW JIRA - CRWLPCIEGEN2-672
193 * Producer Index Feature which is used by F1 gets reset on F0 FLR
194 * fixed in REV68
195 */
196 #define PCIE_ENUM_RESET_WAR_ENAB(buscorerev) \
197 ((buscorerev == 66) || (buscorerev == 67))
198
199 struct dhd_bus;
200
201 struct dhd_pcie_rev {
202 uint8 fw_rev;
203 void (*handle_mb_data)(struct dhd_bus *);
204 };
205
206 typedef struct dhdpcie_config_save
207 {
208 uint32 header[DHDPCIE_CONFIG_HDR_SIZE];
209 /* pmcsr save */
210 uint32 pmcsr;
211 /* express save */
212 uint32 exp_dev_ctrl_stat;
213 uint32 exp_link_ctrl_stat;
214 uint32 exp_dev_ctrl_stat2;
215 uint32 exp_link_ctrl_stat2;
216 /* msi save */
217 uint32 msi_cap;
218 uint32 msi_addr0;
219 uint32 msi_addr1;
220 uint32 msi_data;
221 /* l1pm save */
222 uint32 l1pm0;
223 uint32 l1pm1;
224 /* ltr save */
225 uint32 ltr;
226 /* aer save */
227 uint32 aer_caps_ctrl; /* 0x18 */
228 uint32 aer_severity; /* 0x0C */
229 uint32 aer_umask; /* 0x08 */
230 uint32 aer_cmask; /* 0x14 */
231 uint32 aer_root_cmd; /* 0x2c */
232 /* BAR0 and BAR1 windows */
233 uint32 bar0_win;
234 uint32 bar1_win;
235 } dhdpcie_config_save_t;
236
237 /* The level of bus communication with the dongle */
238 enum dhd_bus_low_power_state {
239 DHD_BUS_NO_LOW_POWER_STATE, /* Not in low power state */
240 DHD_BUS_D3_INFORM_SENT, /* D3 INFORM sent */
241 DHD_BUS_D3_ACK_RECIEVED, /* D3 ACK recieved */
242 };
243
244 #ifdef DHD_FLOW_RING_STATUS_TRACE
245 #define FRS_TRACE_SIZE 32 /* frs - flow_ring_status */
246 typedef struct _dhd_flow_ring_status_trace_t {
247 uint64 timestamp;
248 uint16 h2d_ctrl_post_drd;
249 uint16 h2d_ctrl_post_dwr;
250 uint16 d2h_ctrl_cpln_drd;
251 uint16 d2h_ctrl_cpln_dwr;
252 uint16 h2d_rx_post_drd;
253 uint16 h2d_rx_post_dwr;
254 uint16 d2h_rx_cpln_drd;
255 uint16 d2h_rx_cpln_dwr;
256 uint16 d2h_tx_cpln_drd;
257 uint16 d2h_tx_cpln_dwr;
258 uint16 h2d_info_post_drd;
259 uint16 h2d_info_post_dwr;
260 uint16 d2h_info_cpln_drd;
261 uint16 d2h_info_cpln_dwr;
262 uint16 d2h_ring_edl_drd;
263 uint16 d2h_ring_edl_dwr;
264 } dhd_frs_trace_t;
265 #endif /* DHD_FLOW_RING_STATUS_TRACE */
266
267 /** Instantiated once for each hardware (dongle) instance that this DHD manages */
268 typedef struct dhd_bus {
269 dhd_pub_t *dhd; /**< pointer to per hardware (dongle) unique instance */
270 #if !defined(NDIS)
271 struct pci_dev *rc_dev; /* pci RC device handle */
272 struct pci_dev *dev; /* pci device handle */
273 #endif /* !defined(NDIS) */
274 #ifdef DHD_EFI
275 void *pcie_dev;
276 #endif
277 dll_t flowring_active_list; /* constructed list of tx flowring queues */
278 #ifdef IDLE_TX_FLOW_MGMT
279 uint64 active_list_last_process_ts;
280 /* stores the timestamp of active list processing */
281 #endif /* IDLE_TX_FLOW_MGMT */
282
283 #ifdef DEVICE_TX_STUCK_DETECT
284 /* Flag to enable/disable device tx stuck monitor by DHD IOVAR dev_tx_stuck_monitor */
285 uint32 dev_tx_stuck_monitor;
286 /* Stores the timestamp (msec) of the last device Tx stuck check */
287 uint32 device_tx_stuck_check;
288 #endif /* DEVICE_TX_STUCK_DETECT */
289
290 si_t *sih; /* Handle for SI calls */
291 char *vars; /* Variables (from CIS and/or other) */
292 uint varsz; /* Size of variables buffer */
293 uint32 sbaddr; /* Current SB window pointer (-1, invalid) */
294 sbpcieregs_t *reg; /* Registers for PCIE core */
295
296 uint armrev; /* CPU core revision */
297 uint coreid; /* CPU core id */
298 uint ramrev; /* SOCRAM core revision */
299 uint32 ramsize; /* Size of RAM in SOCRAM (bytes) */
300 uint32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
301 uint32 srmemsize; /* Size of SRMEM */
302
303 uint32 bus; /* gSPI or SDIO bus */
304 uint32 bus_num; /* bus number */
305 uint32 slot_num; /* slot ID */
306 uint32 intstatus; /* Intstatus bits (events) pending */
307 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
308 bool fcstate; /* State of dongle flow-control */
309
310 uint16 cl_devid; /* cached devid for dhdsdio_probe_attach() */
311 char *fw_path; /* module_param: path to firmware image */
312 char *nv_path; /* module_param: path to nvram vars file */
313 #ifdef CACHE_FW_IMAGES
314 int processed_nvram_params_len; /* Modified len of NVRAM info */
315 #endif
316
317 #ifdef BCM_ROUTER_DHD
318 char *nvram_params; /* user specified nvram params. */
319 int nvram_params_len;
320 #endif /* BCM_ROUTER_DHD */
321
322 struct pktq txq; /* Queue length used for flow-control */
323
324 bool intr; /* Use interrupts */
325 bool poll; /* Use polling */
326 bool ipend; /* Device interrupt is pending */
327 bool intdis; /* Interrupts disabled by isr */
328 uint intrcount; /* Count of device interrupt callbacks */
329 uint lastintrs; /* Count as of last watchdog timer */
330
331 dhd_console_t console; /* Console output polling support */
332 uint console_addr; /* Console address from shared struct */
333
334 bool alp_only; /* Don't use HT clock (ALP only) */
335
336 bool remap; /* Contiguous 1MB RAM: 512K socram + 512K devram
337 * Available with socram rev 16
338 * Remap region not DMA-able
339 */
340 uint32 resetinstr;
341 uint32 dongle_ram_base;
342 uint32 next_tlv; /* Holds location of next available TLV */
343 ulong shared_addr;
344 pciedev_shared_t *pcie_sh;
345 uint32 dma_rxoffset;
346 volatile char *regs; /* pci device memory va */
347 volatile char *tcm; /* pci device memory va */
348 uint32 bar1_size; /* pci device memory size */
349 uint32 curr_bar1_win; /* current PCIEBar1Window setting */
350 osl_t *osh;
351 uint32 nvram_csm; /* Nvram checksum */
352 #ifdef BCMINTERNAL
353 bool msi_sim;
354 uchar *msi_sim_addr;
355 dmaaddr_t msi_sim_phys;
356 dhd_dma_buf_t hostfw_buf; /* Host offload firmware buffer */
357 uint32 hostfw_base; /* FW assumed base of host offload mem */
358 uint32 bp_base; /* adjusted bp base of host offload mem */
359 #endif /* BCMINTERNAL */
360 uint16 pollrate;
361 uint16 polltick;
362
363 volatile uint32 *pcie_mb_intr_addr;
364 volatile uint32 *pcie_mb_intr_2_addr;
365 void *pcie_mb_intr_osh;
366 bool sleep_allowed;
367
368 wake_counts_t wake_counts;
369
370 /* version 3 shared struct related info start */
371 ring_sh_info_t ring_sh[BCMPCIE_COMMON_MSGRINGS + MAX_DHD_TX_FLOWS];
372
373 uint8 h2d_ring_count;
374 uint8 d2h_ring_count;
375 uint32 ringmem_ptr;
376 uint32 ring_state_ptr;
377
378 uint32 d2h_dma_scratch_buffer_mem_addr;
379
380 uint32 h2d_mb_data_ptr_addr;
381 uint32 d2h_mb_data_ptr_addr;
382 /* version 3 shared struct related info end */
383
384 uint32 def_intmask;
385 uint32 d2h_mb_mask;
386 uint32 pcie_mailbox_mask;
387 uint32 pcie_mailbox_int;
388 bool ltrsleep_on_unload;
389 uint wait_for_d3_ack;
390 uint16 max_tx_flowrings;
391 uint16 max_submission_rings;
392 uint16 max_completion_rings;
393 uint16 max_cmn_rings;
394 uint32 rw_index_sz;
395 uint32 hwa_db_index_sz;
396 bool db1_for_mb;
397
398 dhd_timeout_t doorbell_timer;
399 bool device_wake_state;
400 #ifdef PCIE_OOB
401 bool oob_enabled;
402 #endif /* PCIE_OOB */
403 bool irq_registered;
404 bool d2h_intr_method;
405 #ifdef SUPPORT_LINKDOWN_RECOVERY
406 #if defined(CONFIG_ARCH_MSM) || (defined(CONFIG_ARCH_EXYNOS) && \
407 !defined(SUPPORT_EXYNOS7420))
408 #ifdef CONFIG_ARCH_MSM
409 uint8 no_cfg_restore;
410 #endif /* CONFIG_ARCH_MSM */
411 struct_pcie_register_event pcie_event;
412 #endif /* CONFIG_ARCH_MSM || CONFIG_ARCH_EXYNOS && !SUPPORT_EXYNOS7420 */
413 bool read_shm_fail;
414 #endif /* SUPPORT_LINKDOWN_RECOVERY */
415 int32 idletime; /* Control for activity timeout */
416 bool rpm_enabled;
417 #ifdef DHD_PCIE_RUNTIMEPM
418 int32 idlecount; /* Activity timeout counter */
419 int32 bus_wake; /* For wake up the bus */
420 bool runtime_resume_done; /* For check runtime suspend end */
421 struct mutex pm_lock; /* Synchronize for system PM & runtime PM */
422 wait_queue_head_t rpm_queue; /* wait-queue for bus wake up */
423 #endif /* DHD_PCIE_RUNTIMEPM */
424 uint32 d3_inform_cnt;
425 uint32 d0_inform_cnt;
426 uint32 d0_inform_in_use_cnt;
427 uint8 force_suspend;
428 uint8 is_linkdown;
429 uint8 no_bus_init;
430 #ifdef IDLE_TX_FLOW_MGMT
431 bool enable_idle_flowring_mgmt;
432 #endif /* IDLE_TX_FLOW_MGMT */
433 struct dhd_pcie_rev api;
434 bool use_mailbox;
435 bool use_d0_inform;
436 void *bus_lp_state_lock;
437 void *pwr_req_lock;
438 bool dongle_in_deepsleep;
439 void *dongle_ds_lock;
440 bool bar1_switch_enab;
441 void *bar1_switch_lock;
442 void *backplane_access_lock;
443 enum dhd_bus_low_power_state bus_low_power_state;
444 #ifdef DHD_FLOW_RING_STATUS_TRACE
445 dhd_frs_trace_t frs_isr_trace[FRS_TRACE_SIZE]; /* frs - flow_ring_status */
446 dhd_frs_trace_t frs_dpc_trace[FRS_TRACE_SIZE]; /* frs - flow_ring_status */
447 uint32 frs_isr_count;
448 uint32 frs_dpc_count;
449 #endif /* DHD_FLOW_RING_STATUS_TRACE */
450 #ifdef DHD_MMIO_TRACE
451 dhd_mmio_trace_t mmio_trace[MAX_MMIO_TRACE_SIZE];
452 uint32 mmio_trace_count;
453 #endif /* defined(DHD_MMIO_TRACE) */
454 dhd_ds_trace_t ds_trace[MAX_DS_TRACE_SIZE];
455 uint32 ds_trace_count;
456 uint32 hostready_count; /* Number of hostready issued */
457 #if defined(PCIE_OOB) || defined (BCMPCIE_OOB_HOST_WAKE)
458 bool oob_presuspend;
459 #endif /* PCIE_OOB || BCMPCIE_OOB_HOST_WAKE */
460 dhdpcie_config_save_t saved_config;
461 ulong resume_intr_enable_count;
462 ulong dpc_intr_enable_count;
463 ulong isr_intr_disable_count;
464 ulong suspend_intr_disable_count;
465 ulong dpc_return_busdown_count;
466 ulong non_ours_irq_count;
467 #ifdef BCMPCIE_OOB_HOST_WAKE
468 ulong oob_intr_count;
469 ulong oob_intr_enable_count;
470 ulong oob_intr_disable_count;
471 uint64 last_oob_irq_isr_time;
472 uint64 last_oob_irq_thr_time;
473 uint64 last_oob_irq_enable_time;
474 uint64 last_oob_irq_disable_time;
475 #endif /* BCMPCIE_OOB_HOST_WAKE */
476 uint64 isr_entry_time;
477 uint64 isr_exit_time;
478 uint64 isr_sched_dpc_time;
479 uint64 rpm_sched_dpc_time;
480 uint64 dpc_entry_time;
481 uint64 dpc_exit_time;
482 uint64 resched_dpc_time;
483 uint64 last_d3_inform_time;
484 uint64 last_process_ctrlbuf_time;
485 uint64 last_process_flowring_time;
486 uint64 last_process_txcpl_time;
487 uint64 last_process_rxcpl_time;
488 uint64 last_process_infocpl_time;
489 uint64 last_process_edl_time;
490 uint64 last_suspend_start_time;
491 uint64 last_suspend_end_time;
492 uint64 last_resume_start_time;
493 uint64 last_resume_end_time;
494 uint64 last_non_ours_irq_time;
495 bool hwa_enabled;
496 bool idma_enabled;
497 bool ifrm_enabled;
498 bool dar_enabled;
499 uint32 dmaxfer_complete;
500 uint8 dw_option;
501 #ifdef PCIE_INB_DW
502 bool inb_enabled;
503 uint32 ds_exit_timeout;
504 uint32 host_sleep_exit_timeout;
505 uint wait_for_ds_exit;
506 uint32 inband_dw_assert_cnt; /* # of inband device_wake assert */
507 uint32 inband_dw_deassert_cnt; /* # of inband device_wake deassert */
508 uint32 inband_ds_exit_host_cnt; /* # of DS-EXIT , host initiated */
509 uint32 inband_ds_exit_device_cnt; /* # of DS-EXIT , device initiated */
510 uint32 inband_ds_exit_to_cnt; /* # of DS-EXIT timeout */
511 uint32 inband_host_sleep_exit_to_cnt; /* # of Host_Sleep exit timeout */
512 void *inb_lock; /* Lock to serialize in band device wake activity */
513 /* # of contexts in the host which currently want a FW transaction */
514 uint32 host_active_cnt;
515 bool skip_ds_ack; /* Skip DS-ACK during suspend in progress */
516 #endif /* PCIE_INB_DW */
517 #if defined(PCIE_OOB) || defined(PCIE_INB_DW)
518 bool ds_enabled;
519 #endif
520 #ifdef DHD_PCIE_RUNTIMEPM
521 bool chk_pm; /* To avoid counting of wake up from Runtime PM */
522 #endif /* DHD_PCIE_RUNTIMEPM */
523 #if defined(PCIE_INB_DW)
524 bool calc_ds_exit_latency;
525 bool deep_sleep; /* Indicates deep_sleep set or unset by the DHD IOVAR deep_sleep */
526 uint64 ds_exit_latency;
527 uint64 ds_exit_ts1;
528 uint64 ds_exit_ts2;
529 #endif /* PCIE_INB_DW */
530 bool _dar_war;
531 #ifdef GDB_PROXY
532 /* True if firmware loaded and backplane accessible */
533 bool gdb_proxy_access_enabled;
534 /* ID set by last "gdb_proxy_probe" iovar */
535 uint32 gdb_proxy_last_id;
536 /* True if firmware was started in bootloader mode */
537 bool gdb_proxy_bootloader_mode;
538 #endif /* GDB_PROXY */
539 uint8 dma_chan;
540
541 bool cto_enable; /* enable PCIE CTO Prevention and recovery */
542 uint32 cto_threshold; /* PCIE CTO timeout threshold */
543 bool cto_triggered; /* CTO is triggered */
544 bool intr_enabled; /* ready to receive interrupts from dongle */
545 int pwr_req_ref;
546 bool flr_force_fail; /* user intends to simulate flr force fail */
547
548 /* Information used to compose the memory map and to write the memory map,
549 * FW, and FW signature to dongle RAM.
550 * This information is used by the bootloader.
551 */
552 uint32 ramtop_addr; /* Dongle address of unused space at top of RAM */
553 uint32 fw_download_addr; /* Dongle address of FW download */
554 uint32 fw_download_len; /* Length in bytes of FW download */
555 uint32 fwsig_download_addr; /* Dongle address of FW signature download */
556 uint32 fwsig_download_len; /* Length in bytes of FW signature download */
557 uint32 fwstat_download_addr; /* Dongle address of FWS status download */
558 uint32 fwstat_download_len; /* Length in bytes of FWS status download */
559 uint32 fw_memmap_download_addr; /* Dongle address of FWS memory-info download */
560 uint32 fw_memmap_download_len; /* Length in bytes of FWS memory-info download */
561
562 char fwsig_filename[DHD_FILENAME_MAX]; /* Name of FW signature file */
563 char bootloader_filename[DHD_FILENAME_MAX]; /* Name of bootloader image file */
564 uint32 bootloader_addr; /* Dongle address of bootloader download */
565 bool force_bt_quiesce; /* send bt_quiesce command to BT driver. */
566 bool rc_ep_aspm_cap; /* RC and EP ASPM capable */
567 bool rc_ep_l1ss_cap; /* EC and EP L1SS capable */
568 #if defined(DHD_H2D_LOG_TIME_SYNC)
569 ulong dhd_rte_time_sync_count; /* OSL_SYSUPTIME_US() */
570 #endif /* DHD_H2D_LOG_TIME_SYNC */
571 #ifdef D2H_MINIDUMP
572 bool d2h_minidump; /* This flag will be set if Host and FW handshake to collect minidump */
573 bool d2h_minidump_override; /* Force disable minidump through dhd IOVAR */
574 #endif /* D2H_MINIDUMP */
575 #ifdef BCMSLTGT
576 int xtalfreq; /* Xtal frequency used for htclkratio calculation */
577 uint32 ilp_tick; /* ILP ticks per second read from pmutimer */
578 uint32 xtal_ratio; /* xtal ticks per 4 ILP ticks read from pmu_xtalfreq */
579 #endif /* BCMSLTGT */
580 #ifdef BT_OVER_PCIE
581 /* whether the chip is in BT over PCIE mode or not */
582 bool btop_mode;
583 #endif /* BT_OVER_PCIE */
584 uint16 hp2p_txcpl_max_items;
585 uint16 hp2p_rxcpl_max_items;
586 /* PCIE coherent status */
587 uint32 coherent_state;
588 uint32 inb_dw_deassert_cnt;
589 uint64 arm_oor_time;
590 uint64 rd_shared_pass_time;
591 uint32 hwa_mem_base;
592 uint32 hwa_mem_size;
593 } dhd_bus_t;
594
595 #ifdef DHD_MSI_SUPPORT
596 extern uint enable_msi;
597 #endif /* DHD_MSI_SUPPORT */
598
599 enum {
600 PCIE_INTX = 0,
601 PCIE_MSI = 1
602 };
603
604 static INLINE bool
__dhd_check_bus_in_lps(dhd_bus_t * bus)605 __dhd_check_bus_in_lps(dhd_bus_t *bus)
606 {
607 bool ret = (bus->bus_low_power_state == DHD_BUS_D3_INFORM_SENT) ||
608 (bus->bus_low_power_state == DHD_BUS_D3_ACK_RECIEVED);
609 return ret;
610 }
611
612 static INLINE bool
dhd_check_bus_in_lps(dhd_bus_t * bus)613 dhd_check_bus_in_lps(dhd_bus_t *bus)
614 {
615 unsigned long flags_bus;
616 bool ret;
617 DHD_BUS_LP_STATE_LOCK(bus->bus_lp_state_lock, flags_bus);
618 ret = __dhd_check_bus_in_lps(bus);
619 DHD_BUS_LP_STATE_UNLOCK(bus->bus_lp_state_lock, flags_bus);
620 return ret;
621 }
622
623 static INLINE bool
__dhd_check_bus_lps_d3_acked(dhd_bus_t * bus)624 __dhd_check_bus_lps_d3_acked(dhd_bus_t *bus)
625 {
626 bool ret = (bus->bus_low_power_state == DHD_BUS_D3_ACK_RECIEVED);
627 return ret;
628 }
629
630 static INLINE bool
dhd_check_bus_lps_d3_acked(dhd_bus_t * bus)631 dhd_check_bus_lps_d3_acked(dhd_bus_t *bus)
632 {
633 unsigned long flags_bus;
634 bool ret;
635 DHD_BUS_LP_STATE_LOCK(bus->bus_lp_state_lock, flags_bus);
636 ret = __dhd_check_bus_lps_d3_acked(bus);
637 DHD_BUS_LP_STATE_UNLOCK(bus->bus_lp_state_lock, flags_bus);
638 return ret;
639 }
640
641 static INLINE void
__dhd_set_bus_not_in_lps(dhd_bus_t * bus)642 __dhd_set_bus_not_in_lps(dhd_bus_t *bus)
643 {
644 bus->bus_low_power_state = DHD_BUS_NO_LOW_POWER_STATE;
645 return;
646 }
647
648 static INLINE void
dhd_set_bus_not_in_lps(dhd_bus_t * bus)649 dhd_set_bus_not_in_lps(dhd_bus_t *bus)
650 {
651 unsigned long flags_bus;
652 DHD_BUS_LP_STATE_LOCK(bus->bus_lp_state_lock, flags_bus);
653 __dhd_set_bus_not_in_lps(bus);
654 DHD_BUS_LP_STATE_UNLOCK(bus->bus_lp_state_lock, flags_bus);
655 return;
656 }
657
658 static INLINE void
__dhd_set_bus_lps_d3_informed(dhd_bus_t * bus)659 __dhd_set_bus_lps_d3_informed(dhd_bus_t *bus)
660 {
661 bus->bus_low_power_state = DHD_BUS_D3_INFORM_SENT;
662 return;
663 }
664
665 static INLINE void
dhd_set_bus_lps_d3_informed(dhd_bus_t * bus)666 dhd_set_bus_lps_d3_informed(dhd_bus_t *bus)
667 {
668 unsigned long flags_bus;
669 DHD_BUS_LP_STATE_LOCK(bus->bus_lp_state_lock, flags_bus);
670 __dhd_set_bus_lps_d3_informed(bus);
671 DHD_BUS_LP_STATE_UNLOCK(bus->bus_lp_state_lock, flags_bus);
672 return;
673 }
674
675 static INLINE void
__dhd_set_bus_lps_d3_acked(dhd_bus_t * bus)676 __dhd_set_bus_lps_d3_acked(dhd_bus_t *bus)
677 {
678 bus->bus_low_power_state = DHD_BUS_D3_ACK_RECIEVED;
679 return;
680 }
681
682 static INLINE void
dhd_set_bus_lps_d3_acked(dhd_bus_t * bus)683 dhd_set_bus_lps_d3_acked(dhd_bus_t *bus)
684 {
685 unsigned long flags_bus;
686 DHD_BUS_LP_STATE_LOCK(bus->bus_lp_state_lock, flags_bus);
687 __dhd_set_bus_lps_d3_acked(bus);
688 DHD_BUS_LP_STATE_UNLOCK(bus->bus_lp_state_lock, flags_bus);
689 return;
690 }
691
692 /* check routines */
693 #define DHD_CHK_BUS_IN_LPS(bus) dhd_check_bus_in_lps(bus)
694 #define __DHD_CHK_BUS_IN_LPS(bus) __dhd_check_bus_in_lps(bus)
695
696 #define DHD_CHK_BUS_NOT_IN_LPS(bus) !(DHD_CHK_BUS_IN_LPS(bus))
697 #define __DHD_CHK_BUS_NOT_IN_LPS(bus) !(__DHD_CHK_BUS_IN_LPS(bus))
698
699 #define DHD_CHK_BUS_LPS_D3_INFORMED(bus) DHD_CHK_BUS_IN_LPS(bus)
700 #define __DHD_CHK_BUS_LPS_D3_INFORMED(bus) __DHD_CHK_BUS_IN_LPS(bus)
701
702 #define DHD_CHK_BUS_LPS_D3_ACKED(bus) dhd_check_bus_lps_d3_acked(bus)
703 #define __DHD_CHK_BUS_LPS_D3_ACKED(bus) __dhd_check_bus_lps_d3_acked(bus)
704
705 /* set routines */
706 #define DHD_SET_BUS_NOT_IN_LPS(bus) dhd_set_bus_not_in_lps(bus)
707 #define __DHD_SET_BUS_NOT_IN_LPS(bus) __dhd_set_bus_not_in_lps(bus)
708
709 #define DHD_SET_BUS_LPS_D3_INFORMED(bus) dhd_set_bus_lps_d3_informed(bus)
710 #define __DHD_SET_BUS_LPS_D3_INFORMED(bus) __dhd_set_bus_lps_d3_informed(bus)
711
712 #define DHD_SET_BUS_LPS_D3_ACKED(bus) dhd_set_bus_lps_d3_acked(bus)
713 #define __DHD_SET_BUS_LPS_D3_ACKED(bus) __dhd_set_bus_lps_d3_acked(bus)
714
715 /* function declarations */
716
717 extern uint32* dhdpcie_bus_reg_map(osl_t *osh, ulong addr, int size);
718 extern int dhdpcie_bus_register(void);
719 extern void dhdpcie_bus_unregister(void);
720 extern bool dhdpcie_chipmatch(uint16 vendor, uint16 device);
721
722 extern int dhdpcie_bus_attach(osl_t *osh, dhd_bus_t **bus_ptr,
723 volatile char *regs, volatile char *tcm, void *pci_dev, wifi_adapter_info_t *adapter);
724 extern uint32 dhdpcie_bus_cfg_read_dword(struct dhd_bus *bus, uint32 addr, uint32 size);
725 extern void dhdpcie_bus_cfg_write_dword(struct dhd_bus *bus, uint32 addr, uint32 size, uint32 data);
726 extern void dhdpcie_bus_intr_enable(struct dhd_bus *bus);
727 extern void dhdpcie_bus_intr_disable(struct dhd_bus *bus);
728 extern int dhpcie_bus_mask_interrupt(dhd_bus_t *bus);
729 extern void dhdpcie_bus_release(struct dhd_bus *bus);
730 extern int32 dhdpcie_bus_isr(struct dhd_bus *bus);
731 extern void dhdpcie_free_irq(dhd_bus_t *bus);
732 extern void dhdpcie_bus_ringbell_fast(struct dhd_bus *bus, uint32 value);
733 extern void dhdpcie_bus_ringbell_2_fast(struct dhd_bus *bus, uint32 value, bool devwake);
734 extern void dhdpcie_dongle_reset(dhd_bus_t *bus);
735 extern int dhd_bus_cfg_sprom_ctrl_bp_reset(struct dhd_bus *bus);
736 extern int dhd_bus_cfg_ss_ctrl_bp_reset(struct dhd_bus *bus);
737 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
738 extern int dhdpcie_bus_suspend(struct dhd_bus *bus, bool state, bool byint);
739 #else
740 extern int dhdpcie_bus_suspend(struct dhd_bus *bus, bool state);
741 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
742 extern int dhdpcie_pci_suspend_resume(struct dhd_bus *bus, bool state);
743 extern uint32 dhdpcie_force_alp(struct dhd_bus *bus, bool enable);
744 extern uint32 dhdpcie_set_l1_entry_time(struct dhd_bus *bus, int force_l1_entry_time);
745 extern bool dhdpcie_tcm_valid(dhd_bus_t *bus);
746 extern void dhdpcie_pme_active(osl_t *osh, bool enable);
747 extern bool dhdpcie_pme_cap(osl_t *osh);
748 extern uint32 dhdpcie_lcreg(osl_t *osh, uint32 mask, uint32 val);
749 extern void dhdpcie_set_pmu_min_res_mask(struct dhd_bus *bus, uint min_res_mask);
750 extern uint8 dhdpcie_clkreq(osl_t *osh, uint32 mask, uint32 val);
751 extern int dhdpcie_disable_irq(dhd_bus_t *bus);
752 extern int dhdpcie_disable_irq_nosync(dhd_bus_t *bus);
753 extern int dhdpcie_enable_irq(dhd_bus_t *bus);
754
755 extern void dhd_bus_dump_dar_registers(struct dhd_bus *bus);
756
757 #if defined(linux) || defined(LINUX)
758 extern uint32 dhdpcie_rc_config_read(dhd_bus_t *bus, uint offset);
759 extern uint32 dhdpcie_rc_access_cap(dhd_bus_t *bus, int cap, uint offset, bool is_ext,
760 bool is_write, uint32 writeval);
761 extern uint32 dhdpcie_ep_access_cap(dhd_bus_t *bus, int cap, uint offset, bool is_ext,
762 bool is_write, uint32 writeval);
763 extern uint32 dhd_debug_get_rc_linkcap(dhd_bus_t *bus);
764 #else
dhdpcie_rc_config_read(dhd_bus_t * bus,uint offset)765 static INLINE uint32 dhdpcie_rc_config_read(dhd_bus_t *bus, uint offset) { return 0;}
dhdpcie_rc_access_cap(dhd_bus_t * bus,int cap,uint offset,bool is_ext,bool is_write,uint32 writeval)766 static INLINE uint32 dhdpcie_rc_access_cap(dhd_bus_t *bus, int cap, uint offset, bool is_ext,
767 bool is_write, uint32 writeval) { return -1;}
dhdpcie_ep_access_cap(dhd_bus_t * bus,int cap,uint offset,bool is_ext,bool is_write,uint32 writeval)768 static INLINE uint32 dhdpcie_ep_access_cap(dhd_bus_t *bus, int cap, uint offset, bool is_ext,
769 bool is_write, uint32 writeval) { return -1;}
dhd_debug_get_rc_linkcap(dhd_bus_t * bus)770 static INLINE uint32 dhd_debug_get_rc_linkcap(dhd_bus_t *bus) { return -1;}
771 #endif
772 #if defined(linux) || defined(LINUX)
773 extern int dhdpcie_start_host_dev(dhd_bus_t *bus);
774 extern int dhdpcie_stop_host_dev(dhd_bus_t *bus);
775 extern int dhdpcie_disable_device(dhd_bus_t *bus);
776 extern int dhdpcie_alloc_resource(dhd_bus_t *bus);
777 extern void dhdpcie_free_resource(dhd_bus_t *bus);
778 extern void dhdpcie_dump_resource(dhd_bus_t *bus);
779 extern int dhdpcie_bus_request_irq(struct dhd_bus *bus);
780 void dhdpcie_os_setbar1win(dhd_bus_t *bus, uint32 addr);
781 void dhdpcie_os_wtcm8(dhd_bus_t *bus, ulong offset, uint8 data);
782 uint8 dhdpcie_os_rtcm8(dhd_bus_t *bus, ulong offset);
783 void dhdpcie_os_wtcm16(dhd_bus_t *bus, ulong offset, uint16 data);
784 uint16 dhdpcie_os_rtcm16(dhd_bus_t *bus, ulong offset);
785 void dhdpcie_os_wtcm32(dhd_bus_t *bus, ulong offset, uint32 data);
786 uint32 dhdpcie_os_rtcm32(dhd_bus_t *bus, ulong offset);
787 #ifdef DHD_SUPPORT_64BIT
788 void dhdpcie_os_wtcm64(dhd_bus_t *bus, ulong offset, uint64 data);
789 uint64 dhdpcie_os_rtcm64(dhd_bus_t *bus, ulong offset);
790 #endif
791 #endif /* LINUX || linux */
792
793 #if defined(linux) || defined(LINUX) || defined(DHD_EFI)
794 extern int dhdpcie_enable_device(dhd_bus_t *bus);
795 #endif
796
797 #ifdef BCMPCIE_OOB_HOST_WAKE
798 extern int dhdpcie_oob_intr_register(dhd_bus_t *bus);
799 extern void dhdpcie_oob_intr_unregister(dhd_bus_t *bus);
800 extern void dhdpcie_oob_intr_set(dhd_bus_t *bus, bool enable);
801 extern int dhdpcie_get_oob_irq_num(struct dhd_bus *bus);
802 extern int dhdpcie_get_oob_irq_status(struct dhd_bus *bus);
803 extern int dhdpcie_get_oob_irq_level(void);
804 #endif /* BCMPCIE_OOB_HOST_WAKE */
805 #ifdef PCIE_OOB
806 extern void dhd_oob_set_bt_reg_on(struct dhd_bus *bus, bool val);
807 extern int dhd_oob_get_bt_reg_on(struct dhd_bus *bus);
808 extern void dhdpcie_oob_init(dhd_bus_t *bus);
809 extern int dhd_os_oob_set_device_wake(struct dhd_bus *bus, bool val);
810 extern void dhd_os_ib_set_device_wake(struct dhd_bus *bus, bool val);
811 #endif /* PCIE_OOB */
812 #if defined(PCIE_OOB) || defined(PCIE_INB_DW)
813 extern void dhd_bus_doorbell_timeout_reset(struct dhd_bus *bus);
814 #endif /* defined(PCIE_OOB) || defined(PCIE_INB_DW) */
815
816 #if defined(linux) || defined(LINUX)
817 /* XXX: SWWLAN-82173 Making PCIe RC D3cold by force during system PM
818 * exynos_pcie_pm_suspend : RC goes to suspend status & assert PERST
819 * exynos_pcie_pm_resume : de-assert PERST & RC goes to resume status
820 */
821 #if defined(CONFIG_ARCH_EXYNOS)
822 #define EXYNOS_PCIE_VENDOR_ID 0x144d
823 #if defined(CONFIG_MACH_UNIVERSAL7420) || defined(CONFIG_SOC_EXYNOS7420)
824 #define EXYNOS_PCIE_DEVICE_ID 0xa575
825 #define EXYNOS_PCIE_CH_NUM 1
826 #elif defined(CONFIG_SOC_EXYNOS8890)
827 #define EXYNOS_PCIE_DEVICE_ID 0xa544
828 #define EXYNOS_PCIE_CH_NUM 0
829 #elif defined(CONFIG_SOC_EXYNOS8895) || defined(CONFIG_SOC_EXYNOS9810) || \
830 defined(CONFIG_SOC_EXYNOS9820) || defined(CONFIG_SOC_EXYNOS9830) || \
831 defined(CONFIG_SOC_EXYNOS2100) || defined(CONFIG_SOC_EXYNOS1000) || \
832 defined(CONFIG_SOC_GS101)
833 #define EXYNOS_PCIE_DEVICE_ID 0xecec
834 #define EXYNOS_PCIE_CH_NUM 0
835 #else
836 #error "Not supported platform"
837 #endif /* CONFIG_SOC_EXYNOSXXXX & CONFIG_MACH_UNIVERSALXXXX */
838 extern void exynos_pcie_pm_suspend(int ch_num);
839 extern void exynos_pcie_pm_resume(int ch_num);
840 #endif /* CONFIG_ARCH_EXYNOS */
841
842 #if defined(CONFIG_ARCH_MSM)
843 #define MSM_PCIE_VENDOR_ID 0x17cb
844 #if defined(CONFIG_ARCH_APQ8084)
845 #define MSM_PCIE_DEVICE_ID 0x0101
846 #elif defined(CONFIG_ARCH_MSM8994)
847 #define MSM_PCIE_DEVICE_ID 0x0300
848 #elif defined(CONFIG_ARCH_MSM8996)
849 #define MSM_PCIE_DEVICE_ID 0x0104
850 #elif defined(CONFIG_ARCH_MSM8998)
851 #define MSM_PCIE_DEVICE_ID 0x0105
852 #elif defined(CONFIG_ARCH_SDM845) || defined(CONFIG_ARCH_SM8150) || \
853 defined(CONFIG_ARCH_KONA) || defined(CONFIG_ARCH_LAHAINA)
854 #define MSM_PCIE_DEVICE_ID 0x0106
855 #else
856 #error "Not supported platform"
857 #endif
858 #endif /* CONFIG_ARCH_MSM */
859
860 #if defined(CONFIG_X86)
861 #define X86_PCIE_VENDOR_ID 0x8086
862 #define X86_PCIE_DEVICE_ID 0x9c1a
863 #endif /* CONFIG_X86 */
864
865 #if defined(CONFIG_ARCH_TEGRA)
866 #define TEGRA_PCIE_VENDOR_ID 0x14e4
867 #define TEGRA_PCIE_DEVICE_ID 0x4347
868 #endif /* CONFIG_ARCH_TEGRA */
869
870 #if defined(BOARD_HIKEY)
871 #define HIKEY_PCIE_VENDOR_ID 0x19e5
872 #define HIKEY_PCIE_DEVICE_ID 0x3660
873 #endif /* BOARD_HIKEY */
874
875 #define DUMMY_PCIE_VENDOR_ID 0xffff
876 #define DUMMY_PCIE_DEVICE_ID 0xffff
877
878 #if defined(CONFIG_ARCH_EXYNOS)
879 #define PCIE_RC_VENDOR_ID EXYNOS_PCIE_VENDOR_ID
880 #define PCIE_RC_DEVICE_ID EXYNOS_PCIE_DEVICE_ID
881 #elif defined(CONFIG_ARCH_MSM)
882 #define PCIE_RC_VENDOR_ID MSM_PCIE_VENDOR_ID
883 #define PCIE_RC_DEVICE_ID MSM_PCIE_DEVICE_ID
884 #elif defined(CONFIG_X86)
885 #define PCIE_RC_VENDOR_ID X86_PCIE_VENDOR_ID
886 #define PCIE_RC_DEVICE_ID X86_PCIE_DEVICE_ID
887 #elif defined(CONFIG_ARCH_TEGRA)
888 #define PCIE_RC_VENDOR_ID TEGRA_PCIE_VENDOR_ID
889 #define PCIE_RC_DEVICE_ID TEGRA_PCIE_DEVICE_ID
890 #elif defined(BOARD_HIKEY)
891 #define PCIE_RC_VENDOR_ID HIKEY_PCIE_VENDOR_ID
892 #define PCIE_RC_DEVICE_ID HIKEY_PCIE_DEVICE_ID
893 #else
894 /* Use dummy vendor and device IDs */
895 #define PCIE_RC_VENDOR_ID DUMMY_PCIE_VENDOR_ID
896 #define PCIE_RC_DEVICE_ID DUMMY_PCIE_DEVICE_ID
897 #endif /* CONFIG_ARCH_EXYNOS */
898 #endif /* linux || LINUX */
899
900 #define DHD_REGULAR_RING 0
901 #define DHD_HP2P_RING 1
902
903 #ifdef CONFIG_ARCH_TEGRA
904 extern int tegra_pcie_pm_suspend(void);
905 extern int tegra_pcie_pm_resume(void);
906 #endif /* CONFIG_ARCH_TEGRA */
907
908 extern int dhd_buzzz_dump_dngl(dhd_bus_t *bus);
909 #ifdef IDLE_TX_FLOW_MGMT
910 extern int dhd_bus_flow_ring_resume_request(struct dhd_bus *bus, void *arg);
911 extern void dhd_bus_flow_ring_resume_response(struct dhd_bus *bus, uint16 flowid, int32 status);
912 extern int dhd_bus_flow_ring_suspend_request(struct dhd_bus *bus, void *arg);
913 extern void dhd_bus_flow_ring_suspend_response(struct dhd_bus *bus, uint16 flowid, uint32 status);
914 extern void dhd_flow_ring_move_to_active_list_head(struct dhd_bus *bus,
915 flow_ring_node_t *flow_ring_node);
916 extern void dhd_flow_ring_add_to_active_list(struct dhd_bus *bus,
917 flow_ring_node_t *flow_ring_node);
918 extern void dhd_flow_ring_delete_from_active_list(struct dhd_bus *bus,
919 flow_ring_node_t *flow_ring_node);
920 extern void __dhd_flow_ring_delete_from_active_list(struct dhd_bus *bus,
921 flow_ring_node_t *flow_ring_node);
922 #endif /* IDLE_TX_FLOW_MGMT */
923
924 extern int dhdpcie_send_mb_data(dhd_bus_t *bus, uint32 h2d_mb_data);
925
926 #ifdef DHD_WAKE_STATUS
927 int bcmpcie_get_total_wake(struct dhd_bus *bus);
928 int bcmpcie_set_get_wake(struct dhd_bus *bus, int flag);
929 #endif /* DHD_WAKE_STATUS */
930 #ifdef DHD_MMIO_TRACE
931 extern void dhd_dump_bus_mmio_trace(dhd_bus_t *bus, struct bcmstrbuf *strbuf);
932 #endif /* defined(DHD_MMIO_TRACE) */
933 extern void dhd_dump_bus_ds_trace(dhd_bus_t *bus, struct bcmstrbuf *strbuf);
934 extern bool dhdpcie_bus_get_pcie_hostready_supported(dhd_bus_t *bus);
935 extern void dhd_bus_hostready(struct dhd_bus *bus);
936 #ifdef PCIE_OOB
937 extern bool dhdpcie_bus_get_pcie_oob_dw_supported(dhd_bus_t *bus);
938 #endif /* PCIE_OOB */
939 #ifdef PCIE_INB_DW
940 extern bool dhdpcie_bus_get_pcie_inband_dw_supported(dhd_bus_t *bus);
941 extern void dhdpcie_bus_set_pcie_inband_dw_state(dhd_bus_t *bus,
942 enum dhd_bus_ds_state state);
943 extern enum dhd_bus_ds_state dhdpcie_bus_get_pcie_inband_dw_state(dhd_bus_t *bus);
944 extern const char * dhd_convert_inb_state_names(enum dhd_bus_ds_state inbstate);
945 extern const char * dhd_convert_dsval(uint32 val, bool d2h);
946 extern int dhd_bus_inb_set_device_wake(struct dhd_bus *bus, bool val);
947 extern void dhd_bus_inb_ack_pending_ds_req(dhd_bus_t *bus);
948 #endif /* PCIE_INB_DW */
949 extern void dhdpcie_bus_enab_pcie_dw(dhd_bus_t *bus, uint8 dw_option);
950 #if defined(LINUX) || defined(linux)
951 extern int dhdpcie_irq_disabled(struct dhd_bus *bus);
952 extern int dhdpcie_set_master_and_d0_pwrstate(struct dhd_bus *bus);
953 #else
dhdpcie_irq_disabled(struct dhd_bus * bus)954 static INLINE bool dhdpcie_irq_disabled(struct dhd_bus *bus) { return BCME_ERROR;}
dhdpcie_set_master_and_d0_pwrstate(struct dhd_bus * bus)955 static INLINE int dhdpcie_set_master_and_d0_pwrstate(struct dhd_bus *bus)
956 { return BCME_ERROR;}
957 #endif /* defined(LINUX) || defined(linux) */
958
959 #ifdef DHD_EFI
960 extern bool dhdpcie_is_arm_halted(struct dhd_bus *bus);
961 extern int dhd_os_wifi_platform_set_power(uint32 value);
962 extern void dhdpcie_dongle_pwr_toggle(dhd_bus_t *bus);
963 void dhdpcie_dongle_flr_or_pwr_toggle(dhd_bus_t *bus);
964 int dhd_control_signal(dhd_bus_t *bus, char *arg, int len, int set);
965 extern int dhd_wifi_properties(struct dhd_bus *bus, char *arg, int len);
966 extern int dhd_otp_dump(dhd_bus_t *bus, char *arg, int len);
967 extern int dhdpcie_deinit_phase1(dhd_bus_t *bus);
968 int dhdpcie_disable_intr_poll(dhd_bus_t *bus);
969 int dhdpcie_enable_intr_poll(dhd_bus_t *bus);
970 #ifdef BT_OVER_PCIE
971 int dhd_btop_test(dhd_bus_t *bus, char *arg, int len);
972 #endif /* BT_OVER_PCIE */
973 #else
dhdpcie_is_arm_halted(struct dhd_bus * bus)974 static INLINE bool dhdpcie_is_arm_halted(struct dhd_bus *bus) {return TRUE;}
dhd_os_wifi_platform_set_power(uint32 value)975 static INLINE int dhd_os_wifi_platform_set_power(uint32 value) {return BCME_OK; }
976 static INLINE void
dhdpcie_dongle_flr_or_pwr_toggle(dhd_bus_t * bus)977 dhdpcie_dongle_flr_or_pwr_toggle(dhd_bus_t *bus)
978 { return; }
979 #endif /* DHD_EFI */
980
981 int dhdpcie_config_check(dhd_bus_t *bus);
982 int dhdpcie_config_restore(dhd_bus_t *bus, bool restore_pmcsr);
983 int dhdpcie_config_save(dhd_bus_t *bus);
984 int dhdpcie_set_pwr_state(dhd_bus_t *bus, uint state);
985
986 extern bool dhdpcie_bus_get_pcie_hwa_supported(dhd_bus_t *bus);
987 extern bool dhdpcie_bus_get_pcie_idma_supported(dhd_bus_t *bus);
988 extern bool dhdpcie_bus_get_pcie_ifrm_supported(dhd_bus_t *bus);
989 extern bool dhdpcie_bus_get_pcie_dar_supported(dhd_bus_t *bus);
990 extern bool dhdpcie_bus_get_hp2p_supported(dhd_bus_t *bus);
991
992 static INLINE uint32
dhd_pcie_config_read(dhd_bus_t * bus,uint offset,uint size)993 dhd_pcie_config_read(dhd_bus_t *bus, uint offset, uint size)
994 {
995 /* For 4375 or prior chips to 4375 */
996 if (bus->sih && bus->sih->buscorerev <= 64) {
997 OSL_DELAY(100);
998 }
999 return OSL_PCI_READ_CONFIG(bus->osh, offset, size);
1000 }
1001
1002 static INLINE uint32
dhd_pcie_corereg_read(si_t * sih,uint val)1003 dhd_pcie_corereg_read(si_t *sih, uint val)
1004 {
1005 /* For 4375 or prior chips to 4375 */
1006 if (sih->buscorerev <= 64) {
1007 OSL_DELAY(100);
1008 }
1009 si_corereg(sih, sih->buscoreidx, OFFSETOF(sbpcieregs_t, configaddr), ~0, val);
1010 return si_corereg(sih, sih->buscoreidx, OFFSETOF(sbpcieregs_t, configdata), 0, 0);
1011 }
1012
1013 extern int dhdpcie_get_fwpath_otp(dhd_bus_t *bus, char *fw_path, char *nv_path,
1014 char *clm_path, char *txcap_path);
1015
1016 extern int dhd_pcie_debug_info_dump(dhd_pub_t *dhd);
1017 extern void dhd_pcie_intr_count_dump(dhd_pub_t *dhd);
1018 extern void dhdpcie_bus_clear_intstatus(dhd_bus_t *bus);
1019 #ifdef DHD_HP2P
1020 extern uint16 dhd_bus_get_hp2p_ring_max_size(dhd_bus_t *bus, bool tx);
1021 #endif
1022
1023 #if defined(DHD_EFI)
1024 extern wifi_properties_t *dhd_get_props(dhd_bus_t *bus);
1025 #endif
1026
1027 #if defined(DHD_EFI) || defined(NDIS)
1028 extern int dhd_get_platform(dhd_pub_t* dhd, char *progname);
1029 extern bool dhdpcie_is_chip_supported(uint32 chipid, int *idx);
1030 extern bool dhdpcie_is_sflash_chip(uint32 chipid);
1031 #endif
1032
1033 extern int dhd_get_pcie_linkspeed(dhd_pub_t *dhd);
1034 extern void dhdpcie_bar1_window_switch_enab(dhd_bus_t *bus);
1035
1036 #ifdef PCIE_INB_DW
1037 extern void dhdpcie_set_dongle_deepsleep(dhd_bus_t *bus, bool val);
1038 extern void dhd_init_dongle_ds_lock(dhd_bus_t *bus);
1039 extern void dhd_deinit_dongle_ds_lock(dhd_bus_t *bus);
1040 #endif /* PCIE_INB_DW */
1041
1042 #endif /* dhd_pcie_h */
1043