1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 #ifndef AUDIO_REG_H 19 #define AUDIO_REG_H 20 #include "../sys.h" 21 22 #define REG_AUDIO_AHB_BASE 0x120000 23 #define REG_CODEC_BASE_ADDR 0x120200 24 #define REG_AUDIO_APB_BASE 0x140500 25 #define reg_fifo_buf_adr(i) REG_AUDIO_AHB_BASE + (i)*0x40 26 #define reg_audio_en REG_ADDR8(REG_AUDIO_APB_BASE + 0x00) 27 enum { 28 FLD_AUDIO_I2S_CLK_EN = BIT(0), 29 FLD_AUDIO_CLK_DIV2 = BIT(1), 30 FLD_AUDIO_MC_CLK_EN = BIT(2), 31 FLD_AUDIO_MC_CLK_INV_O = BIT(3), 32 }; 33 34 #define reg_i2s_cfg REG_ADDR8(REG_AUDIO_APB_BASE + 0x01) 35 enum { 36 FLD_AUDIO_I2S_FORMAT = BIT_RNG(0, 1), 37 FLD_AUDIO_I2S_WL = BIT_RNG(2, 3), 38 FLD_AUDIO_I2S_LRP = BIT(4), 39 FLD_AUDIO_I2S_LRSWAP = BIT(5), 40 FLD_AUDIO_I2S_ADC_DCI_MS = BIT(6), 41 FLD_AUDIO_I2S_DAC_DCI_MS = BIT(7), 42 }; 43 44 #define reg_i2s_cfg2 REG_ADDR8(REG_AUDIO_APB_BASE + 0x02) 45 46 enum { 47 FLD_AUDIO_FIFO1_RST = BIT(3), 48 }; 49 #define reg_audio_ctrl REG_ADDR8(REG_AUDIO_APB_BASE + 0x03) 50 enum { 51 FLD_AUDIO_I2S_CMODE = BIT_RNG(0, 1), 52 FLD_AUDIO_CODEC_I2S_SEL = BIT(2), 53 FLD_AUDIO_I2S_OUT_BIT_SEL = BIT(3), 54 }; 55 56 #define reg_audio_tune REG_ADDR8(REG_AUDIO_APB_BASE + 0x04) 57 enum { 58 FLD_AUDIO_I2S_I2S_AIN0_COME = BIT_RNG(0, 1), 59 FLD_AUDIO_I2S_I2S_AIN1_COME = BIT_RNG(2, 3), 60 FLD_AUDIO_I2S_I2S_AOUT_COME = BIT_RNG(4, 6), 61 }; 62 63 #define reg_audio_sel REG_ADDR8(REG_AUDIO_APB_BASE + 0x05) 64 enum { 65 FLD_AUDIO_AIN0_SEL = BIT_RNG(0, 1), 66 FLD_AUDIO_AOUT0_SEL = BIT_RNG(2, 3), 67 FLD_AUDIO_AIN1_SEL = BIT_RNG(4, 5), 68 FLD_AUDIO_AOUT1_SEL = BIT_RNG(6, 7), 69 }; 70 71 #define reg_audio_i2c_addr REG_ADDR8(REG_AUDIO_APB_BASE + 0x08) 72 #define reg_audio_i2c_mode REG_ADDR8(REG_AUDIO_APB_BASE + 0x09) 73 74 #define reg_fifo_trig0 REG_ADDR8(REG_AUDIO_APB_BASE + 0x0a) 75 76 #define reg_audio_ptr_set REG_ADDR8(REG_AUDIO_APB_BASE + 0x10) 77 enum { 78 FLD_AUDIO_TX_PTR_SEL = BIT(0), 79 FLD_AUDIO_RX_PTR_SEL = BIT(4), 80 }; 81 82 #define reg_audio_ptr_en REG_ADDR8(REG_AUDIO_APB_BASE + 0x11) 83 enum { 84 FLD_AUDIO_TX_WPTR_PTR_EN = BIT(0), 85 FLD_AUDIO_TX_RPTR_PTR_EN = BIT(1), 86 FLD_AUDIO_RX_WPTR_PTR_EN = BIT(2), 87 FLD_AUDIO_RX_RPTR_PTR_EN = BIT(3), 88 }; 89 90 enum { 91 FLD_AUDIO_FIFO_AOUT0_TRIG_NUM = BIT_RNG(0, 3), 92 FLD_AUDIO_FIFO_AIN0_TRIG_NUM = BIT_RNG(4, 7), 93 }; 94 95 #define fifo_trig1 REG_ADDR8(REG_AUDIO_APB_BASE + 0x0b) 96 97 enum { 98 FLD_AUDIO_FIFO_AOUT1_TRIG_NUM = BIT_RNG(0, 3), 99 FLD_AUDIO_FIFO_AIN1_TRIG_NUM = BIT_RNG(4, 7), 100 }; 101 102 #define reg_tx_wptr REG_ADDR16(REG_AUDIO_APB_BASE + 0x20) 103 #define reg_tx_rptr REG_ADDR16(REG_AUDIO_APB_BASE + 0x22) 104 105 #define reg_tx_max REG_ADDR16(REG_AUDIO_APB_BASE + 0x26) 106 107 #define reg_rx_rptr REG_ADDR16(REG_AUDIO_APB_BASE + 0x2a) 108 #define reg_rx_wptr REG_ADDR16(REG_AUDIO_APB_BASE + 0x28) 109 110 #define reg_rx_max REG_ADDR16(REG_AUDIO_APB_BASE + 0x2e) 111 112 #define reg_th0_h1 REG_ADDR16(REG_AUDIO_APB_BASE + 0x30) // tx 113 #define reg_th0_l1 REG_ADDR16(REG_AUDIO_APB_BASE + 0x32) // tx 114 115 #define reg_th0_h2 REG_ADDR16(REG_AUDIO_APB_BASE + 0x38) // tx 116 #define reg_th0_l2 REG_ADDR16(REG_AUDIO_APB_BASE + 0x3a) // tx 117 118 #define reg_th1_h1 REG_ADDR16(REG_AUDIO_APB_BASE + 0x40) // rx 119 #define reg_th1_l1 REG_ADDR16(REG_AUDIO_APB_BASE + 0x42) // rx 120 121 #define reg_th1_h2 REG_ADDR16(REG_AUDIO_APB_BASE + 0x48) // rx 122 #define reg_th1_l2 REG_ADDR16(REG_AUDIO_APB_BASE + 0x4a) // rx 123 124 #define reg_irq_fifo_state REG_ADDR8(REG_AUDIO_APB_BASE + 0x5c) 125 typedef enum { 126 FLD_AUDIO_IRQ_TXFIFO_L_L1 = BIT(0), 127 FLD_AUDIO_IRQ_TXFIFO_H_L1 = BIT(1), 128 FLD_AUDIO_IRQ_TXFIFO_L_L2 = BIT(2), 129 FLD_AUDIO_IRQ_TXFIFO_H_L2 = BIT(3), 130 131 FLD_AUDIO_IRQ_RXFIFO_L_L1 = BIT(4), 132 FLD_AUDIO_IRQ_RXFIFO_H_L1 = BIT(5), 133 FLD_AUDIO_IRQ_RXFIFO_L_L2 = BIT(6), 134 FLD_AUDIO_IRQ_RXFIFO_H_L2 = BIT(7), 135 } audio_fifo_irq_status_type_e; 136 137 #define reg_irq_fifo_mask REG_ADDR8(REG_AUDIO_APB_BASE + 0x5d) 138 139 typedef enum { 140 FLD_AUDIO_IRQ_TXFIFO_L_L1_EN = BIT(0), 141 FLD_AUDIO_IRQ_TXFIFO_H_L1_EN = BIT(1), 142 FLD_AUDIO_IRQ_TXFIFO_L_L2_EN = BIT(2), 143 FLD_AUDIO_IRQ_TXFIFO_H_L2_EN = BIT(3), 144 145 FLD_AUDIO_IRQ_RXFIFO_L_L1_EN = BIT(4), 146 FLD_AUDIO_IRQ_RXFIFO_H_L1_EN = BIT(5), 147 FLD_AUDIO_IRQ_RXFIFO_L_L2_EN = BIT(6), 148 FLD_AUDIO_IRQ_RXFIFO_H_L2_EN = BIT(7), 149 } audio_fifo_irq_mask_type_e; 150 151 #define reg_irq_manual_en REG_ADDR8(REG_AUDIO_APB_BASE + 0x5e) 152 enum { 153 FLD_AUDIO_IRQ_TXFIFO_L_L1_MAN_EN = BIT(0), 154 FLD_AUDIO_IRQ_TXFIFO_H_L1_MAN_EN = BIT(1), 155 FLD_AUDIO_IRQ_TXFIFO_L_L2_MAN_EN = BIT(2), 156 FLD_AUDIO_IRQ_TXFIFO_H_L2_MAN_EN = BIT(3), 157 158 FLD_AUDIO_IRQ_RXFIFO_L_L1_MAN_EN = BIT(4), 159 FLD_AUDIO_IRQ_RXFIFO_H_L1_MAN_EN = BIT(5), 160 FLD_AUDIO_IRQ_RXFIFO_L_L2_MAN_EN = BIT(6), 161 FLD_AUDIO_IRQ_RXFIFO_H_L2_MAN_EN = BIT(7) 162 }; 163 164 #define reg_int_pcm_num REG_ADDR16(REG_AUDIO_APB_BASE + 0x50) 165 #define reg_dec_pcm_num REG_ADDR16(REG_AUDIO_APB_BASE + 0x52) 166 167 #define reg_pcm_clk_num REG_ADDR8(REG_AUDIO_APB_BASE + 0x54) 168 169 #define reg_audio_codec_stat_ctr REG_ADDR8(REG_CODEC_BASE_ADDR + (0x00 << 2)) 170 #define addr_audio_codec_stat_ctr 0x00 171 enum { 172 FLD_AUDIO_CODEC_ADC12_LOCKED = BIT(3), 173 FLD_AUDIO_CODEC_DAC_LOCKED = BIT(4), 174 FLD_AUDIO_CODEC_PON_ACK = BIT(7), 175 }; 176 177 #define reg_audio_codec_vic_ctr REG_ADDR8(REG_CODEC_BASE_ADDR + (0x06 << 2)) 178 #define addr_audio_codec_vic_ctr 0x06 179 enum { 180 FLD_AUDIO_CODEC_SB = BIT(0), 181 FLD_AUDIO_CODEC_SB_ANALOG = BIT(1), 182 FLD_AUDIO_CODEC_SLEEP_ANALOG = BIT(2), 183 }; 184 185 #define reg_audio_codec_dac_itf_ctr REG_ADDR8(REG_CODEC_BASE_ADDR + (0x08 << 2)) 186 #define addr_audio_codec_dac_itf_ctr 0x08 187 188 #define reg_audio_codec_adc_itf_ctr REG_ADDR8(REG_CODEC_BASE_ADDR + (0x09 << 2)) 189 #define addr_audio_codec_adc_itf_ctr 0x09 190 enum { 191 FLD_AUDIO_CODEC_FORMAT = BIT_RNG(0, 1), 192 FLD_AUDIO_CODEC_DAC_ITF_SB = BIT(4), 193 FLD_AUDIO_CODEC_SLAVE = BIT(5), 194 FLD_AUDIO_CODEC_WL = BIT_RNG(6, 7), 195 }; 196 197 #define reg_audio_codec_adc2_ctr REG_ADDR8(REG_CODEC_BASE_ADDR + (0x0a << 2)) 198 #define addr_audio_codec_adc2_ctr 0x0a 199 enum { 200 FLD_AUDIO_CODEC_ADC12_SB = BIT(0), 201 }; 202 203 #define reg_audio_codec_dac_freq_ctr REG_ADDR8(REG_CODEC_BASE_ADDR + (0x0b << 2)) 204 #define addr_audio_codec_dac_freq_ctr 0x0b 205 enum { 206 FLD_AUDIO_CODEC_DAC_FREQ = BIT_RNG(0, 3), 207 }; 208 209 #define reg_audio_codec_adc_wnf_ctr REG_ADDR8(REG_CODEC_BASE_ADDR + (0x0e << 2)) 210 #define addr_audio_codec_adc_wnf_ctr 0x0e 211 enum { 212 FLD_AUDIO_CODEC_ADC12_WNF = BIT_RNG(0, 1), 213 }; 214 215 #define reg_audio_codec_adc_freq_ctr REG_ADDR8(REG_CODEC_BASE_ADDR + (0x0f << 2)) 216 #define addr_audio_codec_adc_freq_ctr 0x0f 217 enum { 218 FLD_AUDIO_CODEC_ADC_FREQ = BIT_RNG(0, 3), 219 FLD_AUDIO_CODEC_ADC12_HPF_EN = BIT(4), 220 }; 221 222 #define reg_audio_dmic_12 REG_ADDR8(REG_CODEC_BASE_ADDR + (0x10 << 2)) 223 #define addr_audio_dmic_12 0x10 224 enum { 225 FLD_AUDIO_CODEC_ADC_DMIC_SEL2 = BIT_RNG(0, 1), 226 FLD_AUDIO_CODEC_ADC_DMIC_SEL1 = BIT_RNG(2, 3), 227 FLD_AUDIO_CODEC_DMIC2_SB = BIT(6), 228 FLD_AUDIO_CODEC_DMIC1_SB = BIT(7), 229 }; 230 231 #define reg_audio_codec_hpl_gain REG_ADDR8(REG_CODEC_BASE_ADDR + (0x15 << 2)) 232 #define addr_audio_codec_hpl_gain 0x15 233 234 enum { 235 FLD_AUDIO_CODEC_HPL_GOL = BIT_RNG(0, 4), 236 FLD_AUDIO_CODEC_HPL_LRGO = BIT(7), 237 }; 238 239 #define reg_audio_codec_hpr_gain REG_ADDR8(REG_CODEC_BASE_ADDR + (0x16 << 2)) 240 #define addr_audio_codec_hpr_gain 0x16 241 enum { 242 FLD_AUDIO_CODEC_HPR_GOR = BIT_RNG(0, 4), 243 }; 244 245 #define reg_audio_codec_mic1_ctr REG_ADDR8(REG_CODEC_BASE_ADDR + (0x17 << 2)) 246 #define addr_audio_codec_mic1_ctr 0x17 247 248 enum { 249 FLD_AUDIO_CODEC_MIC1_SEL = BIT(0), 250 FLD_AUDIO_CODEC_MICBIAS1_SB = BIT(5), 251 FLD_AUDIO_CODEC_MIC_DIFF1 = BIT(6), 252 FLD_AUDIO_CODEC_MICBIAS1_V = BIT(7), 253 }; 254 255 #define reg_audio_codec_mic2_ctr REG_ADDR8(REG_CODEC_BASE_ADDR + (0x18 << 2)) 256 #define addr_audio_codec_mic2_ctr 0x18 257 enum { 258 FLD_AUDIO_CODEC_MIC2_SEL = BIT(0), 259 FLD_AUDIO_CODEC_MIC_DIFF2 = BIT(6), 260 }; 261 262 #define reg_audio_codec_dacl_gain REG_ADDR8(REG_CODEC_BASE_ADDR + (0x2a << 2)) 263 #define addr_audio_codec_dacl_gain 0x2a 264 enum { 265 FLD_AUDIO_CODEC_DAC_GODL = BIT_RNG(0, 5), 266 FLD_AUDIO_CODEC_DAC_LRGOD = BIT(7), 267 }; 268 269 #define reg_audio_codec_dacr_gain REG_ADDR8(REG_CODEC_BASE_ADDR + (0x2b << 2)) 270 #define addr_audio_codec_dacr_gain 0x2b 271 enum { 272 FLD_AUDIO_CODEC_DAC_GODR = BIT_RNG(0, 5), 273 }; 274 275 #define reg_audio_codec_mic_l_R_gain REG_ADDR8(REG_CODEC_BASE_ADDR + (0x1f << 2)) 276 #define addr_audio_codec_mic_l_R_gain 0x1f 277 enum { 278 FLD_AUDIO_CODEC_AMIC_L_GAIN = BIT_RNG(0, 2), 279 FLD_AUDIO_CODEC_AMIC_R_GAIN = BIT_RNG(3, 5), 280 }; 281 282 #define reg_audio_codec_dac_ctr REG_ADDR8(REG_CODEC_BASE_ADDR + (0x23 << 2)) 283 #define addr_audio_codec_dac_ctr 0x23 284 enum { 285 FLD_AUDIO_CODEC_DAC_SB = BIT(4), 286 FLD_AUDIO_CODEC_DAC_LEFT_ONLY = BIT(5), 287 FLD_AUDIO_CODEC_DAC_SOFT_MUTE = BIT(7), 288 }; 289 290 #define reg_audio_codec_adc12_ctr REG_ADDR8(REG_CODEC_BASE_ADDR + (0x24 << 2)) 291 #define addr_audio_codec_adc12_ctr 0x24 292 enum { 293 FLD_AUDIO_CODEC_ADC1_SB = BIT(4), 294 FLD_AUDIO_CODEC_ADC2_SB = BIT(5), 295 FLD_AUDIO_CODEC_ADC12_SOFT_MUTE = BIT(7), 296 }; 297 298 #define reg_audio_adc1_gain REG_ADDR8(REG_CODEC_BASE_ADDR + (0x2c << 2)) 299 #define addr_audio_adc1_gain 0x2c 300 enum { 301 FLD_AUDIO_CODEC_ADC_GID1 = BIT_RNG(0, 5), 302 FLD_AUDIO_CODEC_ADC_LRGID = BIT(7), 303 }; 304 305 #define reg_audio_adc2_gain REG_ADDR8(REG_CODEC_BASE_ADDR + (0x2d << 2)) 306 enum { 307 FLD_AUDIO_CODEC_ADC_GID2 = BIT_RNG(0, 5), 308 }; 309 310 #endif 311