1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 #ifndef USB_REG_H 19 #define USB_REG_H 20 #include "../sys.h" 21 22 /******************************* usb registers: 0x100800 ******************************/ 23 #define reg_ctrl_ep_ptr REG_ADDR8(0x100800) 24 #define reg_ctrl_ep_dat REG_ADDR8(0x100801) 25 #define reg_ctrl_ep_ctrl REG_ADDR8(0x100802) 26 enum { 27 FLD_EP_DAT_ACK = BIT(0), 28 FLD_EP_DAT_STALL = BIT(1), 29 FLD_EP_STA_ACK = BIT(2), 30 FLD_EP_STA_STALL = BIT(3), 31 }; 32 33 #define reg_ctrl_ep_irq_sta REG_ADDR8(0x100803) 34 enum { 35 FLD_CTRL_EP_IRQ_TRANS = BIT_RNG(0, 3), 36 FLD_CTRL_EP_IRQ_SETUP = BIT(4), 37 FLD_CTRL_EP_IRQ_DATA = BIT(5), 38 FLD_CTRL_EP_IRQ_STA = BIT(6), 39 FLD_CTRL_EP_IRQ_INTF = BIT(7), 40 }; 41 42 #define reg_ctrl_ep_irq_mode REG_ADDR8(0x100804) 43 enum { 44 FLD_CTRL_EP_AUTO_ADDR = BIT(0), 45 FLD_CTRL_EP_AUTO_CFG = BIT(1), 46 FLD_CTRL_EP_AUTO_INTF = BIT(2), 47 FLD_CTRL_EP_AUTO_STA = BIT(3), 48 FLD_CTRL_EP_AUTO_SYN = BIT(4), 49 FLD_CTRL_EP_AUTO_DESC = BIT(5), 50 FLD_CTRL_EP_AUTO_FEAT = BIT(6), 51 FLD_CTRL_EP_AUTO_STD = BIT(7), 52 }; 53 54 #define reg_usb_ctrl REG_ADDR8(0x100805) 55 enum { 56 FLD_USB_CTRL_AUTO_CLK = BIT(0), 57 FLD_USB_CTRL_LOW_SPD = BIT(1), 58 FLD_USB_CTRL_LOW_JITT = BIT(2), 59 FLD_USB_CTRL_TST_MODE = BIT(3), 60 }; 61 62 #define reg_usb_cycl_cali REG_ADDR16(0x100806) 63 #define reg_usb_cych_cali REG_ADDR16(0x100807) 64 #define reg_usb_mdev REG_ADDR8(0x10080a) 65 enum { 66 FLD_USB_MDEV_SELF_PWR = BIT(0), 67 FLD_USB_MDEV_SUSP_STA = BIT(1), 68 FLD_USB_MDEV_WAKE_FEA = BIT(2), 69 FLD_USB_MDEV_VEND_CMD = BIT(3), 70 FLD_USB_MDEV_VEND_DIS = BIT(4), 71 }; 72 73 #define reg_usb_host_conn REG_ADDR8(0x10080b) 74 #define reg_usb_sups_cyc_cali REG_ADDR8(0x10080c) 75 #define reg_usb_intf_alt REG_ADDR8(0x10080d) 76 #define reg_usb_edp_en REG_ADDR8(0x10080e) 77 typedef enum { 78 FLD_USB_EDP8_EN = BIT(0), // printer 79 FLD_USB_EDP1_EN = BIT(1), // keyboard 80 FLD_USB_EDP2_EN = BIT(2), // mouse 81 FLD_USB_EDP3_EN = BIT(3), 82 FLD_USB_EDP4_EN = BIT(4), 83 FLD_USB_EDP5_EN = BIT(5), // printer 84 FLD_USB_EDP6_EN = BIT(6), // audio 85 FLD_USB_EDP7_EN = BIT(7), // audio 86 } usb_ep_en_e; 87 88 #define reg_usb_irq_mask REG_ADDR8(0x10080f) 89 enum { 90 FLD_USB_IRQ_RESET_MASK = BIT(0), 91 FLD_USB_IRQ_250US_MASK = BIT(1), 92 FLD_USB_IRQ_SUSPEND_MASK = BIT(2), 93 FLD_USB_IRQ_RESET_LVL = BIT(3), 94 FLD_USB_IRQ_250US_LVL = BIT(4), 95 FLD_USB_IRQ_RESET_O = BIT(5), 96 FLD_USB_IRQ_250US_O = BIT(6), 97 FLD_USB_IRQ_SUSPEND_O = BIT(7), 98 }; 99 100 #define reg_usb_ep8123_ptr REG_ADDR32(0x100810) 101 #define reg_usb_ep8_ptr REG_ADDR8(0x100810) 102 #define reg_usb_ep1_ptr REG_ADDR8(0x100811) 103 #define reg_usb_ep2_ptr REG_ADDR8(0x100812) 104 #define reg_usb_ep3_ptr REG_ADDR8(0x100813) 105 #define reg_usb_ep4567_ptr REG_ADDR32(0x100814) 106 #define reg_usb_ep4_ptr REG_ADDR8(0x100814) 107 #define reg_usb_ep5_ptr REG_ADDR8(0x100815) 108 #define reg_usb_ep6_ptr REG_ADDR8(0x100816) 109 #define reg_usb_ep7_ptr REG_ADDR8(0x100817) 110 #define reg_usb_ep_ptr(i) REG_ADDR8(0x100810 + ((i)&0x07)) 111 112 #define reg_usb_ep8123_dat REG_ADDR32(0x100818) 113 #define reg_usb_ep8_dat REG_ADDR8(0x100818) 114 #define reg_usb_ep1_dat REG_ADDR8(0x100819) 115 #define reg_usb_ep2_dat REG_ADDR8(0x10081a) 116 #define reg_usb_ep3_dat REG_ADDR8(0x10081b) 117 #define reg_usb_ep4567_dat REG_ADDR32(0x10081c) 118 #define reg_usb_ep4_dat REG_ADDR8(0x10081c) 119 #define reg_usb_ep5_dat REG_ADDR8(0x10081d) 120 #define reg_usb_ep6_dat REG_ADDR8(0x10081e) 121 #define reg_usb_ep7_dat REG_ADDR8(0x10081f) 122 #define reg_usb_ep_dat(i) REG_ADDR8(0x100818 + ((i)&0x07)) 123 124 #define reg_usb_ep8_ctrl REG_ADDR8(0x100820) 125 #define reg_usb_ep1_ctrl REG_ADDR8(0x100821) 126 #define reg_usb_ep2_ctrl REG_ADDR8(0x100822) 127 #define reg_usb_ep3_ctrl REG_ADDR8(0x100823) 128 #define reg_usb_ep4_ctrl REG_ADDR8(0x100824) 129 #define reg_usb_ep5_ctrl REG_ADDR8(0x100825) 130 #define reg_usb_ep6_ctrl REG_ADDR8(0x100826) 131 #define reg_usb_ep7_ctrl REG_ADDR8(0x100827) 132 #define reg_usb_ep_ctrl(i) REG_ADDR8(0x100820 + ((i)&0x07)) 133 134 enum { 135 FLD_USB_EP_BUSY = BIT(0), 136 FLD_USB_EP_STALL = BIT(1), 137 FLD_USB_EP_DAT0 = BIT(2), 138 FLD_USB_EP_DAT1 = BIT(3), 139 FLD_USB_EP_MONO = BIT(6), 140 FLD_USB_EP_EOF_ISO = BIT(7), 141 }; 142 143 #define reg_usb_ep8123_buf_addr REG_ADDR32(0x100828) 144 #define reg_usb_ep8_buf_addr REG_ADDR8(0x100828) 145 #define reg_usb_ep1_buf_addr REG_ADDR8(0x100829) 146 #define reg_usb_ep2_buf_addr REG_ADDR8(0x10082a) 147 #define reg_usb_ep3_buf_addr REG_ADDR8(0x10082b) 148 #define reg_usb_ep4567_buf_addr REG_ADDR32(0x10082c) 149 #define reg_usb_ep4_buf_addr REG_ADDR8(0x10082c) 150 #define reg_usb_ep5_buf_addr REG_ADDR8(0x10082d) 151 #define reg_usb_ep6_buf_addr REG_ADDR8(0x10082e) 152 #define reg_usb_ep7_buf_addr REG_ADDR8(0x10082f) 153 #define reg_usb_ep_buf_addr(i) REG_ADDR8(0x100828 + ((i)&0x07)) 154 155 #define reg_usb_ram_ctrl REG_ADDR8(0x100830) 156 157 enum { 158 FLD_USB_CEN_PWR_DN = BIT(0), 159 FLD_USB_CLK_PWR_DN = BIT(1), 160 FLD_USB_WEN_PWR_DN = BIT(3), 161 FLD_USB_CEN_FUNC = BIT(4), 162 }; 163 164 #define reg_usb_iso_mode REG_ADDR8(0x100838) 165 166 #define reg_usb_ep_irq_status REG_ADDR8(0x100839) 167 #define reg_usb_ep_irq_mask REG_ADDR8(0x10083a) 168 typedef enum { 169 FLD_USB_EDP8_IRQ = BIT(0), 170 FLD_USB_EDP1_IRQ = BIT(1), 171 FLD_USB_EDP2_IRQ = BIT(2), 172 FLD_USB_EDP3_IRQ = BIT(3), 173 FLD_USB_EDP4_IRQ = BIT(4), 174 FLD_USB_EDP5_IRQ = BIT(5), 175 FLD_USB_EDP6_IRQ = BIT(6), 176 FLD_USB_EDP7_IRQ = BIT(7), 177 } usb_ep_irq_e; 178 179 #define reg_usb_ep8_send_max REG_ADDR8(0x10083b) 180 #define reg_usb_ep8_send_thre REG_ADDR8(0x10083c) 181 #define reg_usb_ep8_fifo_mode REG_ADDR8(0x10083d) 182 enum { 183 FLD_USB_ENP8_FIFO_MODE = BIT(0), 184 FLD_USB_ENP8_FULL_FLAG = BIT(1), 185 }; 186 187 #define reg_usb_ep_max_size REG_ADDR8(0x10083e) 188 #define reg_usb_ep_tick REG_ADDR8(0x10083f) 189 190 #define reg_usb_mic_dat0 REG_ADDR16(0x1800) 191 #define reg_usb_mic_dat1 REG_ADDR16(0x1802) 192 193 #endif 194