1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 #ifndef DMA_REG_H 19 #define DMA_REG_H 20 #include "../sys.h" 21 /******************************* dma registers: 0x100400 ******************************/ 22 #define reg_dma_id REG_ADDR32(0x100400) 23 #define reg_dma_cfg REG_ADDR32(0x100410) 24 25 #define FLD_DMA_CHANNEL_NUM = BIT_RNG(0, 3), 26 #define FLD_DMA_FIFO_DEPTH = BIT_RNG(4, 9), 27 #define FLD_DMA_REQ_NUM = BIT_RNG(10, 14), 28 #define FLD_DMA_REQ_SYNC = BIT(30), 29 #define FLD_DMA_CHANINXFR = BIT(31), 30 31 #define reg_dma_ctrl(i) REG_ADDR32((0x00100444 + (i)*0x14)) 32 33 enum { 34 FLD_DMA_CHANNEL_ENABLE = BIT(0), 35 FLD_DMA_CHANNEL_TC_MASK = BIT(1), 36 FLD_DMA_CHANNEL_ERR_MASK = BIT(2), 37 FLD_DMA_CHANNEL_ABT_MASK = BIT(3), 38 FLD_DMA_CHANNEL_DST_REQ_SEL = BIT_RNG(4, 8), 39 FLD_DMA_CHANNEL_SRC_REQ_SEL = BIT_RNG(9, 13), 40 FLD_DMA_CHANNEL_DST_ADDR_CTRL = BIT_RNG(14, 15), 41 FLD_DMA_CHANNEL_SRC_ADDR_CTRL = BIT_RNG(16, 17), 42 FLD_DMA_CHANNEL_DST_MODE = BIT(18), 43 FLD_DMA_CHANNEL_SRC_MODE = BIT(19), 44 FLD_DMA_CHANNEL_DST_WIDTH = BIT_RNG(20, 21), 45 FLD_DMA_CHANNEL_SRC_WIDTH = BIT_RNG(22, 23), 46 }; 47 48 #define reg_dma_ctr0(i) REG_ADDR8((0x00100444 + (i)*0x14)) 49 50 #define reg_dma_err_isr REG_ADDR8(0x100430) 51 #define reg_dma_abt_isr REG_ADDR8(0x100431) 52 #define reg_dma_tc_isr REG_ADDR8(0x100432) 53 54 enum { 55 FLD_DMA_CHANNEL0_IRQ = BIT(0), 56 FLD_DMA_CHANNEL1_IRQ = BIT(1), 57 FLD_DMA_CHANNEL2_IRQ = BIT(2), 58 FLD_DMA_CHANNEL3_IRQ = BIT(3), 59 FLD_DMA_CHANNEL4_IRQ = BIT(4), 60 FLD_DMA_CHANNEL5_IRQ = BIT(5), 61 FLD_DMA_CHANNEL6_IRQ = BIT(6), 62 FLD_DMA_CHANNEL7_IRQ = BIT(7), 63 }; 64 65 #define reg_dma_ctr3(i) REG_ADDR8((0x00100447 + (i)*0x14)) 66 67 enum { 68 FLD_DMA_SRC_BURST_SIZE = BIT_RNG(0, 2), 69 FLD_DMA_R_NUM_EN = BIT(4), 70 FLD_DMA_PRIORITY = BIT(5), 71 FLD_DMA_W_NUM_EN = BIT(6), 72 FLD_DMA_AUTO_ENABLE_EN = BIT(7), 73 }; 74 75 #define reg_dma_src_addr(i) REG_ADDR32((0x00100448 + (i)*0x14)) 76 #define reg_dma_dst_addr(i) REG_ADDR32((0x0010044c + (i)*0x14)) 77 #define reg_dma_size(i) REG_ADDR32((0x00100450 + (i)*0x14)) 78 79 enum { 80 FLD_DMA_TX_SIZE = BIT_RNG(0, 21), 81 FLD_DMA_TX_SIZE_IDX = BIT_RNG(22, 23), 82 }; 83 84 #define reg_dma_cr3_size(i) (*(volatile unsigned long *)(0x00100452 + (i)*0x14)) 85 86 enum { 87 FLD_DMA_TSR2_SIZE_IDX = BIT_RNG(6, 7), 88 }; 89 90 #define reg_dma_llp(i) REG_ADDR32((0x00100454 + (i)*0x14)) 91 92 #define reg_dma_rx_wptr REG_ADDR8(0x801004f4) 93 #define reg_dma_tx_wptr REG_ADDR8(0x80100500) 94 95 enum { 96 FLD_DMA_WPTR_MASK = BIT_RNG(0, 4), 97 }; 98 99 #define reg_dma_rx_rptr REG_ADDR8(0x801004f5) 100 #define reg_dma_tx_rptr REG_ADDR8(0x80100501) 101 enum { 102 FLD_DMA_RPTR_MASK = BIT_RNG(0, 4), 103 FLD_DMA_RPTR_SET = BIT(5), 104 FLD_DMA_RPTR_NEXT = BIT(6), 105 FLD_DMA_RPTR_CLR = BIT(7), 106 }; 107 108 #endif 109