1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 #ifndef I2C_REG_H_ 19 #define I2C_REG_H_ 20 #include "../sys.h" 21 /******************************* i2c registers: 0x140280 ******************************/ 22 23 #define REG_I2C_BASE 0x140280 24 25 #define reg_i2c_data_buf0_addr 0x80140288 26 27 /** 28 * this register to configure I2C master clock speed,eagle i2c has default clock speed. 29 * for eagle i2c,its default clock resource is 24M, its default speed is 200K. 30 * user can configure this register to get other speed: i2c clock = i2c_system_clock/(4*DivClock) 31 * DivClock=0x80140280[7:0].max_value=0xff. 32 */ 33 #define reg_i2c_sp REG_ADDR8(REG_I2C_BASE) 34 35 /** 36 * this register to configure I2C ID. 37 * BIT[0] to set write or read bit:0=0 for write, bit:0=1 for read. 38 * BIT[7:1] for ID. 39 */ 40 #define reg_i2c_id REG_ADDR8(REG_I2C_BASE + 0x01) 41 enum { 42 FLD_I2C_WRITE_READ_BIT = BIT(0), 43 FLD_I2C_ID = BIT_RNG(1, 7), 44 }; 45 46 /** 47 * this register is to configure i2c master 48 * BIT[0] means i2c bus whether busy. 49 * BIT[1] means that a start signal is coming, it is 1, and an end signal is coming it will be 0. 50 * BIT[2] Indicates the status of master send and receive,bit[2]=1, 51 * means have not ability to send or receivebit[2]=0,means have ability to send or receive. 52 * BIT_RNG[3:5] Indicate what state the i2c is in when it acts as master, 53 * BIT_RNG[3:5] defaule value is 0x06 it means master's state is IDLE. 54 * BIT_RNG[6:7] Indicate what state the i2c is in when it acts as slave. 55 */ 56 #define reg_i2c_mst REG_ADDR8(REG_I2C_BASE + 0x02) 57 enum { 58 FLD_I2C_MST_BUSY = BIT(0), 59 FLD_I2C_SCS_N = BIT(1), 60 FLD_I2C_ACK_IN = BIT(2), 61 FLD_I2C_MST_P = BIT_RNG(3, 5), 62 FLD_I2C_SS = BIT_RNG(6, 7), 63 }; 64 65 /** 66 * This shows the status control register of i2c 67 * BIT[0] i2c master enable. 68 * BIT[1] clk stretch enable: suspend transimission by pulling SCL down to low level, 69 * and continue transmission after SCL is pelesed to hign level. 70 * BIT[2] rx interrupt enable.RX is related to rx_irq_trig_lev function 71 * (this function is always present and does not need any setting to enable). 72 * fifo_data_cnt> = rx_irq_trig_lev generates an interrupt. 73 * BIT[3] tx interrupt enable.Related to tx_irq_trig_lev function, 74 * (This function is always present and does not require any setting to enable). 75 * fifo_data_cnt <= tx_irq_trig_lev, generate interrupt. 76 * BIT[4] tx_done.An interrupt is generated when one frame of data is sent. 77 * BIT[5] rx_done.An interrupt is generated when one frame of data is received. 78 * BIT[6] If the bit is set to 1, when the master reads, the hardware will automatically return ack / nak, 79 * no software processing is required. 80 * It is a new feature of eagle.Previously, software processed it through FLD_I2C_LS_ACK. 81 * Setting this bit to 0 will ack, and setting it to 1 will NAK. 82 * BIT[7] means,before master ack, delay sda data bus. 83 */ 84 #define reg_i2c_sct0 REG_ADDR8(REG_I2C_BASE + 0x03) 85 typedef enum { 86 FLD_I2C_MASTER = BIT(0), 87 FLD_I2C_R_CLK_STRETCH_EN = BIT(1), 88 FLD_I2C_RX_BUF_MASK = BIT(2), 89 FLD_I2C_TX_BUF_MASK = BIT(3), 90 FLD_I2C_TX_DONE_MASK = BIT(4), 91 FLD_I2C_RX_DONE_MASK = BIT(5), 92 FLD_I2C_RNCK_EN = BIT(6), 93 FLD_I2C_MANUAL_SDA_DELAY = BIT(7), 94 } i2c_mask_irq_type_e; 95 96 /** 97 * This shows the status control register of i2c 98 * BIT[0] launch i2c ID cycle. 99 * BIT[1] launch i2c address cycle. 100 * BIT[2] launch data write cycle. 101 * BIT[3] launch data read cycle. 102 * BIT[4] launch start cycle. 103 * BIT[5] launch stop cycle. 104 * BIT[6] enable if BIT[6]=1,Its role is to convert the SDA from output to input, 105 * so that the master can accept the data sent by the slave when it reads. 106 * BIT[7] enable ACK in read command.When the master is reading, it needs to return to ack or nak. 107 * If it is in manual mode,when the master is reading, 108 * you need to configure this bit to determine whether it will ack. 109 * BIT[7] = 0,return ack. BIT[7] = 1,return nak. 110 */ 111 #define reg_i2c_sct1 REG_ADDR8(REG_I2C_BASE + 0x04) 112 enum { 113 FLD_I2C_LS_ID = BIT(0), 114 FLD_I2C_LS_ADDR = BIT(1), 115 FLD_I2C_LS_DATAW = BIT(2), 116 FLD_I2C_LS_DATAR = BIT(3), 117 FLD_I2C_LS_START = BIT(4), 118 FLD_I2C_LS_STOP = BIT(5), 119 FLD_I2C_LS_ID_R = BIT(6), 120 FLD_I2C_LS_ACK = BIT(7), 121 }; 122 123 /** 124 * This is the register that configures the i2c trigger interrupt 125 * BIT_RNG[0,3] to configure the interrupt trigger level of rx_status, 126 * for example BIT_RNG[0:3]=0x04,when rx 4bytes,will trigger interrupt. 127 * BIT_RNG[4,7] to configure the interrupt trigger level of tx_status, 128 * for example BIT_RNG[0:3]=0x04,when tx 4bytes,will trigger interrupt. 129 */ 130 #define reg_i2c_trig REG_ADDR8(REG_I2C_BASE + 0x05) 131 enum { 132 FLD_I2C_RX_IRQ_TRIG_LEV = BIT_RNG(0, 3), 133 FLD_I2C_TX_IRQ_TRIG_LEV = BIT_RNG(4, 7), 134 }; 135 136 /** 137 * As a master, you need to configure this length for both sending and receiving, 138 * and the hardware needs to know what the length is. 139 */ 140 #define reg_i2c_len REG_ADDR8(REG_I2C_BASE + 0x06) 141 142 /** 143 * This register is to configure the slave stretch function. 144 * BIT[0] slave auto stretch clk eanble,open this function, use slave to receive data,when data buffer is full, 145 * scl bus will be low to stop receive data. 146 * BIT[1] slave manul stretch clk enable,open this function, use slave to receive data,when data buffer is full, 147 * scl bus will be low to stop receive data. 148 * BIT[2] clear slave stretch. 149 * BIT[6] in high speed mode,when open slave auto stretch clk function,Suddenly data came over, 150 * to meet the requirements of time setting. 151 * BIT[7] in fast speed mode,when open slave auto stretch clk function,Suddenly data came over, 152 * to meet the requirements of time setting. 153 */ 154 #define reg_i2c_slave_strech_en REG_ADDR8(REG_I2C_BASE + 0x07) 155 enum { 156 FLD_I2C_R_CLK_STRETCH_SEN = BIT(0), 157 FLD_I2C_R_MANUAL_STRETCH = BIT(1), 158 FLD_I2C_MANUAL_STRETCH_CLR = BIT(2), 159 FLD_I2C_R_HS_MODE = BIT(6), 160 FLD_I2C_R_FAST_MODE = BIT(7), 161 }; 162 163 #define reg_i2c_data_buf(i) REG_ADDR8((REG_I2C_BASE + 0x08 + (i))) 164 /** 165 * This register represents the data buffer of i2c. 166 * BIT_RNG[0,7] Buffer that stores one byte of data 167 */ 168 #define reg_i2c_data_buf0 REG_ADDR8(REG_I2C_BASE + 0x08) 169 enum { 170 FLD_I2C_BUF0 = BIT_RNG(0, 7), 171 }; 172 173 /** 174 * This register represents the data buffer of i2c. 175 * BIT_RNG[0,7] Buffer that stores one byte of data 176 */ 177 #define reg_i2c_data_buf1 REG_ADDR8(REG_I2C_BASE + 0x09) 178 enum { 179 FLD_I2C_BUF1 = BIT_RNG(0, 7), 180 }; 181 182 /** 183 * This register represents the data buffer of i2c. 184 * BIT_RNG[0,7] Buffer that stores one byte of data 185 */ 186 #define reg_i2c_data_buf2 REG_ADDR8(REG_I2C_BASE + 0x0a) 187 enum { 188 FLD_I2C_BUF2 = BIT_RNG(0, 7), 189 }; 190 191 /** 192 * This register represents the data buffer of i2c. 193 * BIT_RNG[0,7] Buffer that stores one byte of data 194 */ 195 #define reg_i2c_data_buf3 REG_ADDR8(REG_I2C_BASE + 0x0b) 196 enum { 197 FLD_I2C_BUF3 = BIT_RNG(0, 7), 198 }; 199 200 /** 201 * This register is used to configure the number of bytes in the i2c buffer 202 * BIT_RNG[0,3] rx_bufcnt is equivalent to a pointer to fifo, one in data plus one, one out data minus one. 203 * BIT_RNG[4,7] tx_bufcnt is equivalent to a pointer to fifo, one in data plus one, one out data minus one. 204 */ 205 #define reg_i2c_buf_cnt REG_ADDR8(REG_I2C_BASE + 0x0c) 206 enum { 207 FLD_I2C_RX_BUFCNT = BIT_RNG(0, 3), 208 FLD_I2C_TX_BUFCNT = BIT_RNG(4, 7), 209 }; 210 211 /** 212 * This register used to configure the status of i2c. 213 * BIT_RNG[0,2] rbcnt is the accumulation of this action read, fifo clear will clear. 214 * BIT[3] Indicates whether i2c is in an interrupted state. 215 * BIT_RNG[4,6] if configure BIT[6]=1,will manual clean rx_fifo. BIT[5,4] Indicates the number of bytes of tx_buffer. 216 * BIT[7] if configure BIT[7]=1,will manual clean tx_fifo. 217 */ 218 #define reg_i2c_status REG_ADDR8(REG_I2C_BASE + 0x0d) 219 enum { 220 FLD_I2C_RBCNT = BIT_RNG(0, 2), 221 FLD_I2C_IRQ_O = BIT(3), 222 FLD_I2C_WBCNT = BIT_RNG(4, 6), 223 FLD_I2C_RX_CLR = BIT(6), 224 FLD_I2C_TX_CLR = BIT(7), 225 }; 226 227 /** 228 * This register is used to indicate the interrupt status of i2c. 229 * BIT[0] means Generate an interrupt after the transmission is completed. 230 * BIT[1] If there is data in tx_buffer, an interrupt will be generated. 231 * BIT[2] means Generate an interrupt after the receive is completed. 232 * BIT[3] If there is data in rx_buffer, an interrupt will be generated. 233 * BIT[4] Enable transmission function. 234 */ 235 #define reg_i2c_irq_status REG_ADDR8(REG_I2C_BASE + 0x0e) 236 enum { 237 FLD_I2C_TXDONE = BIT(0), 238 FLD_I2C_TX_BUF_IRQ = BIT(1), 239 FLD_I2C_RXDONE = BIT(2), 240 FLD_I2C_RX_BUF_IRQ = BIT(3), 241 FLD_I2C_TX_EN = BIT(4), 242 }; 243 244 /** 245 * reg_i2c_rx_fifo_len is the number actually entered in the hardware fifo, it is an accumulated value, 246 * and fifo clear will clear. 247 */ 248 #define reg_i2c_rx_fifo_len REG_ADDR8(REG_I2C_BASE + 0x0f) 249 enum { 250 FLD_I2C_RX_FIFO_LEN = BIT_RNG(0, 7), 251 }; 252 253 #endif 254