1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 #pragma once 19 20 #include "../sys.h" 21 22 /******************************* MSPI registers: 0x140100 ******************************/ 23 #define reg_mspi_data REG_ADDR8(0x140100) 24 25 #define reg_mspi_fm REG_ADDR8(0x140101) 26 enum { 27 FLD_MSPI_RD_TRIG_EN = BIT(0), 28 FLD_MSPI_RD_MODE = BIT(1), 29 FLD_MSPI_DATA_LINE = BIT_RNG(2, 3), 30 FLD_MSPI_CSN = BIT(4), 31 }; 32 33 #define reg_mspi_status REG_ADDR8(0x140102) 34 enum { 35 FLD_MSPI_BUSY = BIT(0), 36 }; 37 38 #define reg_mspi_fm1 REG_ADDR8(0x140103) 39 enum { 40 FLD_MSPI_TIMEOUT_CNT = BIT_RNG(0, 2), 41 FLD_MSPI_CS2SCL_CNT = BIT_RNG(3, 4), 42 FLD_MSPI_CS2CS_CNT = BIT_RNG(5, 7), 43 }; 44 45 #define reg_mspi_set_l REG_ADDR8(0x140104) 46 enum { 47 FLD_MSPI_MULTIBOOT_ADDR_OFFSET = BIT_RNG(0, 2), 48 }; 49 50 #define reg_mspi_set_h REG_ADDR8(0x140105) 51 enum { 52 FLD_MSPI_PROGRAM_SPACE_SIZE = BIT_RNG(0, 6), 53 }; 54 55 #define reg_mspi_cmd_ahb REG_ADDR8(0x140106) 56 enum { 57 FLD_MSPI_RD_CMD = BIT_RNG(0, 7), 58 }; 59 60 #define reg_mspi_fm_ahb REG_ADDR8(0x140107) 61 enum { 62 FLD_MSPI_DUMMY = BIT_RNG(0, 3), 63 FLD_MSPI_DAT_LINE = BIT_RNG(4, 5), 64 FLD_MSPI_ADDR_LINE = BIT(6), 65 FLD_MSPI_CMD_LINE = BIT(7), 66 }; 67