1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 #ifndef PWM_REG_H 19 #define PWM_REG_H 20 21 #include "../sys.h" 22 23 /******************************* pwm registers: 0x140400 ******************************/ 24 #define reg_pwm_data_buf_adr 0x80140448 25 26 /** 27 * Represents the base address register of the PWM 28 */ 29 #define REG_PWM_BASE 0x140400 30 31 /** 32 * This register is used to enable PWM5 ~ PWM1 33 */ 34 #define reg_pwm_enable REG_ADDR8(REG_PWM_BASE) 35 enum { 36 FLD_PWM1_EN = BIT(1), 37 FLD_PWM2_EN = BIT(2), 38 FLD_PWM3_EN = BIT(3), 39 FLD_PWM4_EN = BIT(4), 40 FLD_PWM5_EN = BIT(5), 41 }; 42 43 /** 44 * This register is used to enable PWM0. 45 */ 46 #define reg_pwm0_enable REG_ADDR8(REG_PWM_BASE + 0x01) 47 enum { 48 FLD_PWM0_EN = BIT(0), 49 }; 50 51 /** 52 * This register is used to set the division factor of the PWM clock. 53 */ 54 #define reg_pwm_clkdiv REG_ADDR8(REG_PWM_BASE + 0x02) 55 56 /** 57 * BIT[3:0] of this register is used to set the working mode of PWM0.Only PWM0 supports 5 modes. 58 */ 59 #define reg_pwm0_mode REG_ADDR8(REG_PWM_BASE + 0x03) 60 61 /** 62 * This register is used to set the inversion of the output state of PWM5 ~ PWM0. 63 * PWM and PWM_N can be inverted independently 64 */ 65 #define reg_pwm_invert REG_ADDR8(REG_PWM_BASE + 0x04) 66 enum { 67 FLD_PWM0_OUT_INVERT = BIT(0), 68 FLD_PWM1_OUT_INVERT = BIT(1), 69 FLD_PWM2_OUT_INVERT = BIT(2), 70 FLD_PWM3_OUT_INVERT = BIT(3), 71 FLD_PWM4_OUT_INVERT = BIT(4), 72 FLD_PWM5_OUT_INVERT = BIT(5), 73 }; 74 75 /** 76 * This register is used to set the inversion of the output state of PWM5_N ~ PWM0_N. 77 * PWM and PWM_N can be inverted independently 78 */ 79 #define reg_pwm_n_invert REG_ADDR8(REG_PWM_BASE + 0x05) 80 enum { 81 FLD_PWM0_INV_OUT_INVERT = BIT(0), 82 FLD_PWM1_INV_OUT_INVERT = BIT(1), 83 FLD_PWM2_INV_OUT_INVERT = BIT(2), 84 FLD_PWM3_INV_OUT_INVERT = BIT(3), 85 FLD_PWM4_INV_OUT_INVERT = BIT(4), 86 FLD_PWM5_INV_OUT_INVERT = BIT(5), 87 }; 88 89 /* 90 * This register represents Signal frame polarity of PWM5~PWM0.By default, 91 * PWM outputs high level under Count status and low level under Remaining status. 92 * If the corresponding bit is set to 1, the high and low levels in different states will be reversed. 93 * BIT(0):pwm0 out low level first. ~BIT(0):pwm0 out high level first. 94 * BIT(1):pwm1 out low level first. ~BIT(1):pwm1 out high level first. 95 * BIT(2):pwm2 out low level first. ~BIT(2):pwm2 out high level first. 96 * BIT(3):pwm3 out low level first. ~BIT(3):pwm3 out high level first. 97 * BIT(4):pwm4 out low level first. ~BIT(4):pwm4 out high level first. 98 * BIT(5):pwm5 out low level first. ~BIT(5):pwm5 out high level first. 99 */ 100 #define reg_pwm_pol REG_ADDR8(REG_PWM_BASE + 0x06) 101 enum { 102 FLD_PWM0_FIRST_OUT_LEVEL = BIT(0), 103 FLD_PWM1_FIRST_OUT_LEVEL = BIT(1), 104 FLD_PWM2_FIRST_OUT_LEVEL = BIT(2), 105 FLD_PWM3_FIRST_OUT_LEVEL = BIT(3), 106 FLD_PWM4_FIRST_OUT_LEVEL = BIT(4), 107 FLD_PWM5_FIRST_OUT_LEVEL = BIT(5), 108 }; 109 110 /* 111 * This register represents 32K clock source with PWM5 ~ PWM0 enabled 112 * If the system has a 32K clock source, whether it is 32K_RC or 32K_Crystal, as long as the corresponding 113 * BIT of 0x140407 is configured, the corresponding PWM Channel can get 32K clock source. 114 */ 115 #define reg_pwm_mode32k REG_ADDR8(REG_PWM_BASE + 0x07) 116 enum { 117 FLD_PWM0_32K_ENABLE = BIT(0), 118 FLD_PWM1_32K_ENABLE = BIT(1), 119 FLD_PWM2_32K_ENABLE = BIT(2), 120 FLD_PWM3_32K_ENABLE = BIT(3), 121 FLD_PWM4_32K_ENABLE = BIT(4), 122 FLD_PWM5_32K_ENABLE = BIT(5), 123 }; 124 125 /** 126 * This register configures the length of the capture segment of PWM5 ~ PWM0. 127 * This value has a total of 16 bits, divided into lower 8 bits and higher 8 bits. 128 */ 129 #define reg_pwm_cmp(i) REG_ADDR16(REG_PWM_BASE + 0x14 + ((i) << 2)) 130 131 /** 132 * This register is used to configure the period of the PWM waveform. There are 32 bits in total. 133 * The lower 16 bits indicate the length of the CMP segment. The higher 16 bits indicate the length of the MAX segment 134 */ 135 #define reg_pwm_cycle(i) REG_ADDR32(REG_PWM_BASE + 0x14 + ((i) << 2)) 136 137 // in C99 FLD_PWM_MAX = BIT_RNG(16,31) is error 138 #define FLD_PWM_CMP = BIT_RNG(0, 15), 139 #define FLD_PWM_MAX = BIT_RNG(16, 31), 140 /** 141 * This register configures the length of the max segment of PWM5 ~ PWM0. 142 * This value has a total of 16 bits, divided into lower 8 bits and higher 8 bits. 143 */ 144 #define reg_pwm_max(i) REG_ADDR16(REG_PWM_BASE + 0x16 + ((i) << 2)) 145 146 /** 147 * When PWM0 is in count mode or ir mode, the total number of pulse_number is set by the following two registers. 148 */ 149 #define reg_pwm0_pulse_num0 REG_ADDR8(REG_PWM_BASE + 0x2c) // 0x2c[7:0] 150 #define reg_pwm0_pulse_num1 REG_ADDR8(REG_PWM_BASE + 0x2d) // 0x2d[5:0] 151 152 /** 153 * PWM interrupt mask or interrupt status 154 */ 155 156 typedef enum { 157 FLD_PWM0_PNUM_IRQ = BIT(0), 158 FLD_PWM0_IR_DMA_FIFO_IRQ = BIT(1), 159 FLD_PWM0_FRAME_DONE_IRQ = BIT(2), 160 FLD_PWM1_FRAME_DONE_IRQ = BIT(3), 161 FLD_PWM2_FRAME_DONE_IRQ = BIT(4), 162 FLD_PWM3_FRAME_DONE_IRQ = BIT(5), 163 FLD_PWM4_FRAME_DONE_IRQ = BIT(6), 164 FLD_PWM5_FRAME_DONE_IRQ = BIT(7), 165 FLD_PWM0_IR_FIFO_IRQ = BIT(16), 166 } pwm_irq_e; 167 168 /** 169 * This register is used to configure the PWM interrupt function. 170 * BIT[0]:If this bit is set, an interrupt will be generated after a set of pulses has been sent. 171 * When this interrupt is enabled, 172 * you can capture an interrupt after a pulse is sent by detecting whether bit[0] of 0x140431 is set. 173 * BIT[1]:Enable ir dma fifo mode interrupt.This bit is usually used with 0x140431BIT[1]. 174 * BIT[2]:Enable pwm0 frame interrupt. 175 * BIT[3]:Enable pwm1 frame interrupt. 176 * BIT[4]:Enable pwm2 frame interrupt. 177 * BIT[5]:Enable pwm3 frame interrupt. 178 * BIT[6]:Enable pwm4 frame interrupt. 179 * BIT[7]:Enable pwm5 frame interrupt. 180 * BIT[16]:The Bit is to enable the mask_lvl 181 * (This level specifically indicates the number of bytes in the FIFO that can trigger an interrupt) interrupt. 182 */ 183 #define reg_pwm_irq_mask(i) REG_ADDR8(REG_PWM_BASE + 0x30 + (i) * 2) 184 185 /** 186 * The bits in this register are used to indicate the various interrupt states of the PWM. 187 * BIT[0]:This bit is usually used with BIT[0] of 0x140430. If this bit is set to 1, 188 * it means that a pulse group of PWM has been sent.An interrupt was also generated. 189 * You can manually write 1 to clear the interrupt flag. 190 * BIT[1]:In ir dma fifo mode. If this is set 1 Indicates that a set of pulse of group has been sent. 191 * You can manually write 1 to clear the interrupt flag. 192 * BIT[2]:If this is set 1 Indicates that a signal frame interrupt has been generated. 193 * You can manually write 1 to clear the interrupt flag. 194 * BIT[3]:If this is set 1 Indicates that a signal frame interrupt has been generated. 195 * You can manually write 1 to clear the interrupt flag. 196 * BIT[4]:If this is set 1 Indicates that a signal frame interrupt has been generated. 197 * You can manually write 1 to clear the interrupt flag. 198 * BIT[5]:If this is set 1 Indicates that a signal frame interrupt has been generated. 199 * You can manually write 1 to clear the interrupt flag. 200 * BIT[6]:If this is set 1 Indicates that a signal frame interrupt has been generated. 201 * You can manually write 1 to clear the interrupt flag. 202 * BIT[7]:If this is set 1 Indicates that a signal frame interrupt has been generated. 203 * You can manually write 1 to clear the interrupt flag. 204 * BIT[16]:When the FIFO value is less than the set value, an interrupt is generated 205 * (The premise is that this interrupt has been enabled by register 0x140432 previous). 206 * The user can know whether this interrupt is generated by reading the status of this register. 207 * If BIT(16):1 Indicates that this interrupt has been generated. 208 */ 209 #define reg_pwm_irq_sta(i) REG_ADDR8(REG_PWM_BASE + 0x31 + (i) * 2) 210 211 /** 212 * This register is used to count the number of PWM5~PWM0 pulses.The number of pulses of each PWM consists of 16 bits 213 */ 214 #define reg_pwm_cnt(i) REG_ADDR16(REG_PWM_BASE + 0x34 + ((i) << 1)) 215 216 /** 217 * PWM0 pulse_cnt value BIT[7:0]. 218 */ 219 #define reg_pwm_ncnt_l REG_ADDR8(REG_PWM_BASE + 0x40) 220 221 /** 222 * PWM0 pulse_cnt value BIT[15:8]. 223 */ 224 #define reg_pwm_ncnt_h REG_ADDR8(REG_PWM_BASE + 0x41) 225 226 /** 227 * [7:0] bits 7-0 of PWM0's high time or low time(if pola[0]=1), 228 * if shadow bit(fifo data[14]) is 1 in ir fifo mode or dma fifo mode. 229 */ 230 #define reg_pwm_tcmp0_shadow REG_ADDR16(REG_PWM_BASE + 0x44) 231 232 /** 233 * [15:8] bits 15-8 of PWM0's high time or low time(if pola[0]=1), 234 * if shadow bit(fifo data[14]) is 1 in ir fifo mode or dma fifo mode. 235 */ 236 #define reg_pwm_tmax0_shadow REG_ADDR16(REG_PWM_BASE + 0x46) 237 238 /** 239 * PWM data fifo.0x140448~0x14044b. 240 */ 241 #define reg_pwm_ir_fifo_dat(i) REG_ADDR16(REG_PWM_BASE + 0x48 + (i) * 2) 242 243 /** 244 * This register BIT[3:0] indicates the interrupt trigger level in ir_fifo mode. 245 * When fifo numbers is less than this value.It's will take effect. 246 */ 247 #define reg_pwm_ir_fifo_irq_trig_level REG_ADDR8(REG_PWM_BASE + 0x4c) 248 enum { 249 FLD_PWM0_FIFO_NUM_OF_TRIGGLE_LEVEL = BIT_RNG(0, 3), 250 }; 251 252 /** 253 * This register indicates the fifo data status in. 254 * BIT[3:0]:Indicates the amount of data in the FIFO. 255 * BIT[4]:if BIT[4]=1,Indicates the data fifo is empty. 256 * BIT[5]:if BIT[5]=1,Indicates the data fifo is full. 257 */ 258 #define reg_pwm_ir_fifo_data_status REG_ADDR8(0x14044d) 259 enum { 260 FLD_PWM0_IR_FIFO_DATA_NUM = BIT_RNG(0, 3), 261 FLD_PWM0_IR_FIFO_EMPTY = BIT(4), 262 FLD_PWM0_IR_FIFO_FULL = BIT(5), 263 }; 264 265 /** 266 * This register can be configured to clear the data FIFO. 267 * BIT[0]:if BIT[0]=1,Indicates the data FIFO is clear. 268 */ 269 #define reg_pwm_ir_clr_fifo_data REG_ADDR8(0x14044e) 270 enum { 271 FLD_PWM0_IR_FIFO_CLR_DATA = BIT(0), 272 }; 273 274 #endif 275