1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 #ifndef STIMER_REG_H_ 19 #define STIMER_REG_H_ 20 21 #include "../sys.h" 22 /******************************* sys clock registers: 0x140200 ******************************/ 23 #define STIMER_BASE_ADDR 0x140200 24 #define reg_system_tick REG_ADDR32(STIMER_BASE_ADDR) 25 26 #define reg_system_irq_level REG_ADDR32(STIMER_BASE_ADDR + 0x4) 27 28 #define reg_system_irq_mask REG_ADDR8(STIMER_BASE_ADDR + 0x8) 29 enum { 30 FLD_SYSTEM_IRQ_MASK = BIT_RNG(0, 2), 31 FLD_SYSTEM_TRIG_PAST_EN = BIT(3), 32 }; 33 34 #define reg_system_cal_irq REG_ADDR8(STIMER_BASE_ADDR + 0x9) 35 36 typedef enum { 37 FLD_SYSTEM_IRQ = BIT(0), 38 FLD_SYSTEM_32K_IRQ = BIT(1), 39 } stimer_irq_e; 40 41 #define reg_system_ctrl REG_ADDR8(STIMER_BASE_ADDR + 0xa) 42 enum { 43 FLD_SYSTEM_32K_WR_EN = BIT(0), 44 FLD_SYSTEM_TIMER_EN = BIT(1), 45 FLD_SYSTEM_TIMER_AUTO = BIT(2), 46 FLD_SYSTEM_32K_TRACK_EN = BIT(3), 47 FLD_SYSTEM_32K_CAL_MODE = BIT_RNG(4, 7), 48 }; 49 50 #define reg_system_st REG_ADDR8(STIMER_BASE_ADDR + 0xb) 51 52 enum { 53 FLD_SYSTEM_CMD_STOP = BIT(1), 54 FLD_SYSTEM_CMD_SYNC = BIT(3), 55 FLD_SYSTEM_CLK_32K = BIT(4), 56 FLD_SYSTEM_CLR_RD_DONE = BIT(5), 57 FLD_SYSTEM_RD_BUSY = BIT(6), 58 FLD_SYSTEM_CMD_SET_DLY_DONE = BIT(7), 59 }; 60 61 #define reg_system_timer_set_32k REG_ADDR32(STIMER_BASE_ADDR + 0xc) 62 63 #define reg_system_timer_read_32k REG_ADDR32(STIMER_BASE_ADDR + 0x10) 64 65 #define reg_system_cal_latch_32k REG_ADDR32(STIMER_BASE_ADDR + 0x14) 66 67 #define reg_system_up_32k REG_ADDR32(STIMER_BASE_ADDR + 0x18) 68 enum { 69 FLD_SYSTEM_UPDATE_UPON_32K = BIT(0), 70 FLD_SYSTEM_RUN_UPON_NXT_32K = BIT(1), 71 }; 72 73 #endif /* STIMER_REG_H_ */ 74