1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 #ifndef TIMER_REG_H 19 #define TIMER_REG_H 20 #include "../sys.h" 21 22 /******************************* timer registers: 0x140140 ******************************/ 23 #define reg_tmr_ctrl0 REG_ADDR8(0x140140) 24 #define reg_tmr_ctrl16 REG_ADDR16(0x140140) 25 #define reg_tmr_ctrl32 REG_ADDR32(0x140140) 26 enum { 27 FLD_TMR0_MODE = BIT_RNG(0, 1), 28 FLD_TMR0_EN = BIT(2), 29 FLD_TMR0_NOWRAP = BIT(3), 30 FLD_TMR1_MODE = BIT_RNG(4, 5), 31 FLD_TMR1_EN = BIT(6), 32 FLD_TMR1_NOWRAP = BIT(7), 33 }; 34 35 #define reg_tmr_ctrl2 REG_ADDR8(0x140142) 36 37 enum { 38 FLD_TMR_WD_EN = BIT(7), 39 }; 40 41 #define reg_tmr_sta REG_ADDR8(0x140143) 42 enum { 43 FLD_TMR_STA_TMR0 = BIT(0), 44 FLD_TMR_STA_TMR1 = BIT(1), 45 FLD_TMR_STA_WD = BIT(2), 46 FLD_TMR_WD_CNT_CLR = BIT(3), 47 FLD_TMR_SW_IRQ = BIT(7), 48 }; 49 50 #define reg_tmr0_capt REG_ADDR32(0x140144) 51 #define reg_tmr1_capt REG_ADDR32(0x140148) 52 #define reg_tmr_capt(i) REG_ADDR32(0x140144 + ((i) << 2)) 53 54 #define reg_wt_target0 REG_ADDR8(0x14014c) // always is 0x00 55 #define reg_wt_target1 REG_ADDR8(0x14014d) 56 #define reg_wt_target2 REG_ADDR8(0x14014e) 57 #define reg_wt_target3 REG_ADDR8(0x14014f) 58 #define reg_wt_target REG_ADDR32(0x14014c) 59 60 #define reg_tmr0_tick REG_ADDR32(0X140150) 61 #define reg_tmr1_tick REG_ADDR32(0X140154) 62 #define reg_tmr_tick(i) REG_ADDR32(0X140150 + ((i) << 2)) 63 64 #endif 65