1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 #ifndef UART_REG_H 19 #define UART_REG_H 20 #include "../sys.h" 21 22 /******************************* uart0 registers: 0x140080 *******************************/ 23 /******************************* uart1 registers: 0x1400c0 ******************************/ 24 #define reg_uart_data_buf_adr(i) (0x140080 + (i)*0x40) // uart(i) 25 26 #define reg_uart_data_buf(i, j) REG_ADDR8(reg_uart_data_buf_adr(i) + (j)) // uart(i)_buf(j) 27 #define reg_uart_data_hword_buf(i, j) REG_ADDR16(reg_uart_data_buf_adr(i) + (j)*2) 28 29 #define reg_uart_data_word_buf(i) REG_ADDR32(reg_uart_data_buf_adr(i)) // uart(i) 30 31 #define reg_uart_clk_div(i) REG_ADDR16(0x140084 + (i)*0x40) 32 33 enum { FLD_UART_CLK_DIV = BIT_RNG(0, 14), FLD_UART_CLK_DIV_EN = BIT(15) }; 34 35 #define reg_uart_ctrl0(i) REG_ADDR8(0x140086 + (i)*0x40) 36 37 enum { FLD_UART_BPWC_O = BIT_RNG(0, 3), FLD_UART_MASK_RX_IRQ = BIT(6), FLD_UART_MASK_TX_IRQ = BIT(7) }; 38 39 #define reg_uart_ctrl1(i) REG_ADDR8(0x140087 + (i)*0x40) 40 41 enum { 42 FLD_UART_TX_CTS_POLARITY = BIT(0), 43 FLD_UART_TX_CTS_ENABLE = BIT(1), 44 FLD_UART_PARITY_ENABLE = BIT(2), 45 FLD_UART_PARITY_POLARITY = BIT(3), // 1:odd parity 0:even parity 46 FLD_UART_STOP_SEL = BIT_RNG(4, 5), 47 FLD_UART_TTL_ENABLE = BIT(6), 48 FLD_UART_LOOPBACK_O = BIT(7), 49 }; 50 51 #define reg_uart_ctrl2(i) REG_ADDR16(0x140088 + (i)*0x40) 52 53 enum { 54 FLD_UART_RTS_TRIQ_LEV = BIT_RNG(0, 3), 55 FLD_UART_RTS_POLARITY = BIT(4), 56 FLD_UART_RTS_MANUAL_V = BIT(5), 57 FLD_UART_RTS_MANUAL_M = BIT(6), 58 FLD_UART_RTS_EN = BIT(7), 59 }; 60 61 #define reg_uart_ctrl3(i) REG_ADDR8(0x140089 + (i)*0x40) 62 63 enum { 64 FLD_UART_RX_IRQ_TRIQ_LEV = BIT_RNG(0, 3), 65 FLD_UART_TX_IRQ_TRIQ_LEV = BIT_RNG(4, 7), 66 }; 67 //////////////////////////////////////////////////// 68 #define reg_uart_rx_timeout0(i) REG_ADDR8(0x14008a + (i)*0x40) 69 70 enum { 71 FLD_UART_TIMEOUT_BW = BIT_RNG(0, 7), 72 }; 73 74 #define reg_uart_rx_timeout1(i) REG_ADDR8(0x14008b + 0x40 * (i)) 75 76 enum { 77 FLD_UART_TIMEOUT_MUL = BIT_RNG(0, 1), 78 FLD_UART_MARK_RXDONE = BIT(2), 79 // rsvd BIT(4) 80 FLD_UART_P7816_EN = BIT(5), 81 FLD_UART_MASK_TXDONE = BIT(6), 82 FLD_UART_MASK_ERR_IRQ = BIT(7), 83 }; 84 85 #define reg_uart_buf_cnt(i) REG_ADDR8(0x14008c + (i)*0x40) 86 enum { 87 FLD_UART_RX_BUF_CNT = BIT_RNG(0, 3), 88 FLD_UART_TX_BUF_CNT = BIT_RNG(4, 7), 89 }; 90 91 #define reg_uart_status1(i) REG_ADDR8(0x14008d + ((i)*0x40)) 92 enum { 93 FLD_UART_RBCNT = BIT_RNG(0, 2), 94 FLD_UART_IRQ_O = BIT(3), 95 FLD_UART_WBCNT = BIT_RNG(4, 6), // R 96 FLD_UART_CLEAR_RX = BIT(6), // Write 1 clear RX 97 FLD_UART_RX_ERR = BIT(7), // R 98 FLD_UART_CLEAR_TX = BIT(7), // Write 1 clear TX 99 }; 100 101 #define reg_uart_status2(i) REG_ADDR8((0x14008e) + (0x40 * (i))) 102 enum { 103 FLD_UART_TX_DONE = BIT(0), // only for dma default 1. 104 FLD_UART_TX_BUF_IRQ = BIT(1), 105 FLD_UART_RX_DONE = BIT(2), 106 FLD_UART_RX_BUF_IRQ = BIT(3), 107 }; 108 109 // state machine use for IC debug 110 #define reg_uart_state(i) REG_ADDR8(0x14008f + 0x40 * (i)) 111 enum { 112 FLD_UART_TSTATE_i = BIT_RNG(0, 2), // only for dma default 1. 113 FLD_UART_RSTATE_i = BIT_RNG(4, 7), 114 }; 115 116 /******************************* 7816 registers: 0x1401f0 ******************************/ 117 #define reg_7816_clk_div REG_ADDR8(0x1401f0) 118 enum { 119 FLD_7816_CLK_DIV = BIT_RNG(4, 7), 120 }; 121 #endif 122