1 /* 2 * drivers/amvdec_ports/decoder/aml_hevc_parser.h 3 * 4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 */ 17 18 19 #ifndef AML_HEVC_PARSER_H 20 #define AML_HEVC_PARSER_H 21 22 #include "../aml_vcodec_drv.h" 23 #include "../utils/common.h" 24 25 #define MAX_DPB_SIZE 16 // A.4.1 26 #define MAX_REFS 16 27 28 #define MAX_NB_THREADS 16 29 #define SHIFT_CTB_WPP 2 30 31 /** 32 * 7.4.2.1 33 */ 34 #define MAX_SUB_LAYERS 7 35 #define MAX_VPS_COUNT 16 36 #define MAX_SPS_COUNT 32 37 #define MAX_PPS_COUNT 256 38 #define MAX_SHORT_TERM_RPS_COUNT 64 39 #define MAX_CU_SIZE 128 40 41 //TODO: check if this is really the maximum 42 #define MAX_TRANSFORM_DEPTH 5 43 44 #define MAX_TB_SIZE 32 45 #define MAX_PB_SIZE 64 46 #define MAX_LOG2_CTB_SIZE 6 47 #define MAX_QP 51 48 #define DEFAULT_INTRA_TC_OFFSET 2 49 50 #define HEVC_CONTEXTS 183 51 52 #define MRG_MAX_NUM_CANDS 5 53 54 #define L0 0 55 #define L1 1 56 57 #define EPEL_EXTRA_BEFORE 1 58 #define EPEL_EXTRA_AFTER 2 59 #define EPEL_EXTRA 3 60 61 #define FF_PROFILE_HEVC_MAIN 1 62 #define FF_PROFILE_HEVC_MAIN_10 2 63 #define FF_PROFILE_HEVC_MAIN_STILL_PICTURE 3 64 #define FF_PROFILE_HEVC_REXT 4 65 66 /** 67 * Value of the luma sample at position (x, y) in the 2D array tab. 68 */ 69 #define SAMPLE(tab, x, y) ((tab)[(y) * s->sps->width + (x)]) 70 #define SAMPLE_CTB(tab, x, y) ((tab)[(y) * min_cb_width + (x)]) 71 #define SAMPLE_CBF(tab, x, y) ((tab)[((y) & ((1<<log2_trafo_size)-1)) * MAX_CU_SIZE + ((x) & ((1<<log2_trafo_size)-1))]) 72 73 #define IS_IDR(s) (s->nal_unit_type == NAL_IDR_W_RADL || s->nal_unit_type == NAL_IDR_N_LP) 74 #define IS_BLA(s) (s->nal_unit_type == NAL_BLA_W_RADL || s->nal_unit_type == NAL_BLA_W_LP || \ 75 s->nal_unit_type == NAL_BLA_N_LP) 76 #define IS_IRAP(s) (s->nal_unit_type >= 16 && s->nal_unit_type <= 23) 77 78 /** 79 * Table 7-3: NAL unit type codes 80 */ 81 enum HEVCNALUnitType { 82 HEVC_NAL_TRAIL_N = 0, 83 HEVC_NAL_TRAIL_R = 1, 84 HEVC_NAL_TSA_N = 2, 85 HEVC_NAL_TSA_R = 3, 86 HEVC_NAL_STSA_N = 4, 87 HEVC_NAL_STSA_R = 5, 88 HEVC_NAL_RADL_N = 6, 89 HEVC_NAL_RADL_R = 7, 90 HEVC_NAL_RASL_N = 8, 91 HEVC_NAL_RASL_R = 9, 92 HEVC_NAL_VCL_N10 = 10, 93 HEVC_NAL_VCL_R11 = 11, 94 HEVC_NAL_VCL_N12 = 12, 95 HEVC_NAL_VCL_R13 = 13, 96 HEVC_NAL_VCL_N14 = 14, 97 HEVC_NAL_VCL_R15 = 15, 98 HEVC_NAL_BLA_W_LP = 16, 99 HEVC_NAL_BLA_W_RADL = 17, 100 HEVC_NAL_BLA_N_LP = 18, 101 HEVC_NAL_IDR_W_RADL = 19, 102 HEVC_NAL_IDR_N_LP = 20, 103 HEVC_NAL_CRA_NUT = 21, 104 HEVC_NAL_IRAP_VCL22 = 22, 105 HEVC_NAL_IRAP_VCL23 = 23, 106 HEVC_NAL_RSV_VCL24 = 24, 107 HEVC_NAL_RSV_VCL25 = 25, 108 HEVC_NAL_RSV_VCL26 = 26, 109 HEVC_NAL_RSV_VCL27 = 27, 110 HEVC_NAL_RSV_VCL28 = 28, 111 HEVC_NAL_RSV_VCL29 = 29, 112 HEVC_NAL_RSV_VCL30 = 30, 113 HEVC_NAL_RSV_VCL31 = 31, 114 HEVC_NAL_VPS = 32, 115 HEVC_NAL_SPS = 33, 116 HEVC_NAL_PPS = 34, 117 HEVC_NAL_AUD = 35, 118 HEVC_NAL_EOS_NUT = 36, 119 HEVC_NAL_EOB_NUT = 37, 120 HEVC_NAL_FD_NUT = 38, 121 HEVC_NAL_SEI_PREFIX = 39, 122 HEVC_NAL_SEI_SUFFIX = 40, 123 }; 124 125 enum HEVCSliceType { 126 HEVC_SLICE_B = 0, 127 HEVC_SLICE_P = 1, 128 HEVC_SLICE_I = 2, 129 }; 130 131 enum { 132 // 7.4.3.1: vps_max_layers_minus1 is in [0, 62]. 133 HEVC_MAX_LAYERS = 63, 134 // 7.4.3.1: vps_max_sub_layers_minus1 is in [0, 6]. 135 HEVC_MAX_SUB_LAYERS = 7, 136 // 7.4.3.1: vps_num_layer_sets_minus1 is in [0, 1023]. 137 HEVC_MAX_LAYER_SETS = 1024, 138 139 // 7.4.2.1: vps_video_parameter_set_id is u(4). 140 HEVC_MAX_VPS_COUNT = 16, 141 // 7.4.3.2.1: sps_seq_parameter_set_id is in [0, 15]. 142 HEVC_MAX_SPS_COUNT = 16, 143 // 7.4.3.3.1: pps_pic_parameter_set_id is in [0, 63]. 144 HEVC_MAX_PPS_COUNT = 64, 145 146 // A.4.2: MaxDpbSize is bounded above by 16. 147 HEVC_MAX_DPB_SIZE = 16, 148 // 7.4.3.1: vps_max_dec_pic_buffering_minus1[i] is in [0, MaxDpbSize - 1]. 149 HEVC_MAX_REFS = HEVC_MAX_DPB_SIZE, 150 151 // 7.4.3.2.1: num_short_term_ref_pic_sets is in [0, 64]. 152 HEVC_MAX_SHORT_TERM_REF_PIC_SETS = 64, 153 // 7.4.3.2.1: num_long_term_ref_pics_sps is in [0, 32]. 154 HEVC_MAX_LONG_TERM_REF_PICS = 32, 155 156 // A.3: all profiles require that CtbLog2SizeY is in [4, 6]. 157 HEVC_MIN_LOG2_CTB_SIZE = 4, 158 HEVC_MAX_LOG2_CTB_SIZE = 6, 159 160 // E.3.2: cpb_cnt_minus1[i] is in [0, 31]. 161 HEVC_MAX_CPB_CNT = 32, 162 163 // A.4.1: in table A.6 the highest level allows a MaxLumaPs of 35 651 584. 164 HEVC_MAX_LUMA_PS = 35651584, 165 // A.4.1: pic_width_in_luma_samples and pic_height_in_luma_samples are 166 // constrained to be not greater than sqrt(MaxLumaPs * 8). Hence height/ 167 // width are bounded above by sqrt(8 * 35651584) = 16888.2 samples. 168 HEVC_MAX_WIDTH = 16888, 169 HEVC_MAX_HEIGHT = 16888, 170 171 // A.4.1: table A.6 allows at most 22 tile rows for any level. 172 HEVC_MAX_TILE_ROWS = 22, 173 // A.4.1: table A.6 allows at most 20 tile columns for any level. 174 HEVC_MAX_TILE_COLUMNS = 20, 175 176 // 7.4.7.1: in the worst case (tiles_enabled_flag and 177 // entropy_coding_sync_enabled_flag are both set), entry points can be 178 // placed at the beginning of every Ctb row in every tile, giving an 179 // upper bound of (num_tile_columns_minus1 + 1) * PicHeightInCtbsY - 1. 180 // Only a stream with very high resolution and perverse parameters could 181 // get near that, though, so set a lower limit here with the maximum 182 // possible value for 4K video (at most 135 16x16 Ctb rows). 183 HEVC_MAX_ENTRY_POINT_OFFSETS = HEVC_MAX_TILE_COLUMNS * 135, 184 }; 185 186 struct ShortTermRPS { 187 u32 num_negative_pics; 188 int num_delta_pocs; 189 int rps_idx_num_delta_pocs; 190 int delta_poc[32]; 191 u8 used[32]; 192 }; 193 194 struct LongTermRPS { 195 int poc[32]; 196 u8 used[32]; 197 u8 nb_refs; 198 }; 199 200 struct SliceHeader { 201 u32 pps_id; 202 203 ///< address (in raster order) of the first block in the current slice segment 204 u32 slice_segment_addr; 205 ///< address (in raster order) of the first block in the current slice 206 u32 slice_addr; 207 208 enum HEVCSliceType slice_type; 209 210 int pic_order_cnt_lsb; 211 212 u8 first_slice_in_pic_flag; 213 u8 dependent_slice_segment_flag; 214 u8 pic_output_flag; 215 u8 colour_plane_id; 216 217 ///< RPS coded in the slice header itself is stored here 218 int short_term_ref_pic_set_sps_flag; 219 int short_term_ref_pic_set_size; 220 struct ShortTermRPS slice_rps; 221 const struct ShortTermRPS *short_term_rps; 222 int long_term_ref_pic_set_size; 223 struct LongTermRPS long_term_rps; 224 u32 list_entry_lx[2][32]; 225 226 u8 rpl_modification_flag[2]; 227 u8 no_output_of_prior_pics_flag; 228 u8 slice_temporal_mvp_enabled_flag; 229 230 u32 nb_refs[2]; 231 232 u8 slice_sample_adaptive_offset_flag[3]; 233 u8 mvd_l1_zero_flag; 234 235 u8 cabac_init_flag; 236 u8 disable_deblocking_filter_flag; ///< slice_header_disable_deblocking_filter_flag 237 u8 slice_loop_filter_across_slices_enabled_flag; 238 u8 collocated_list; 239 240 u32 collocated_ref_idx; 241 242 int slice_qp_delta; 243 int slice_cb_qp_offset; 244 int slice_cr_qp_offset; 245 246 u8 cu_chroma_qp_offset_enabled_flag; 247 248 int beta_offset; ///< beta_offset_div2 * 2 249 int tc_offset; ///< tc_offset_div2 * 2 250 251 u32 max_num_merge_cand; ///< 5 - 5_minus_max_num_merge_cand 252 253 u8 *entry_point_offset; 254 int * offset; 255 int * size; 256 int num_entry_point_offsets; 257 258 char slice_qp; 259 260 u8 luma_log2_weight_denom; 261 s16 chroma_log2_weight_denom; 262 263 s16 luma_weight_l0[16]; 264 s16 chroma_weight_l0[16][2]; 265 s16 chroma_weight_l1[16][2]; 266 s16 luma_weight_l1[16]; 267 268 s16 luma_offset_l0[16]; 269 s16 chroma_offset_l0[16][2]; 270 271 s16 luma_offset_l1[16]; 272 s16 chroma_offset_l1[16][2]; 273 274 int slice_ctb_addr_rs; 275 }; 276 277 struct HEVCWindow { 278 u32 left_offset; 279 u32 right_offset; 280 u32 top_offset; 281 u32 bottom_offset; 282 }; 283 284 struct VUI { 285 struct AVRational sar; 286 287 int overscan_info_present_flag; 288 int overscan_appropriate_flag; 289 290 int video_signal_type_present_flag; 291 int video_format; 292 int video_full_range_flag; 293 int colour_description_present_flag; 294 u8 colour_primaries; 295 u8 transfer_characteristic; 296 u8 matrix_coeffs; 297 298 int chroma_loc_info_present_flag; 299 int chroma_sample_loc_type_top_field; 300 int chroma_sample_loc_type_bottom_field; 301 int neutra_chroma_indication_flag; 302 303 int field_seq_flag; 304 int frame_field_info_present_flag; 305 306 int default_display_window_flag; 307 struct HEVCWindow def_disp_win; 308 309 int vui_timing_info_present_flag; 310 u32 vui_num_units_in_tick; 311 u32 vui_time_scale; 312 int vui_poc_proportional_to_timing_flag; 313 int vui_num_ticks_poc_diff_one_minus1; 314 int vui_hrd_parameters_present_flag; 315 316 int bitstream_restriction_flag; 317 int tiles_fixed_structure_flag; 318 int motion_vectors_over_pic_boundaries_flag; 319 int restricted_ref_pic_lists_flag; 320 int min_spatial_segmentation_idc; 321 int max_bytes_per_pic_denom; 322 int max_bits_per_min_cu_denom; 323 int log2_max_mv_length_horizontal; 324 int log2_max_mv_length_vertical; 325 }; 326 327 struct PTLCommon { 328 u8 profile_space; 329 u8 tier_flag; 330 u8 profile_idc; 331 u8 profile_compatibility_flag[32]; 332 u8 level_idc; 333 u8 progressive_source_flag; 334 u8 interlaced_source_flag; 335 u8 non_packed_constraint_flag; 336 u8 frame_only_constraint_flag; 337 }; 338 339 struct PTL { 340 struct PTLCommon general_ptl; 341 struct PTLCommon sub_layer_ptl[HEVC_MAX_SUB_LAYERS]; 342 343 u8 sub_layer_profile_present_flag[HEVC_MAX_SUB_LAYERS]; 344 u8 sub_layer_level_present_flag[HEVC_MAX_SUB_LAYERS]; 345 }; 346 347 struct h265_VPS_t { 348 u8 vps_temporal_id_nesting_flag; 349 int vps_max_layers; 350 int vps_max_sub_layers; ///< vps_max_temporal_layers_minus1 + 1 351 352 struct PTL ptl; 353 int vps_sub_layer_ordering_info_present_flag; 354 u32 vps_max_dec_pic_buffering[HEVC_MAX_SUB_LAYERS]; 355 u32 vps_num_reorder_pics[HEVC_MAX_SUB_LAYERS]; 356 u32 vps_max_latency_increase[HEVC_MAX_SUB_LAYERS]; 357 int vps_max_layer_id; 358 int vps_num_layer_sets; ///< vps_num_layer_sets_minus1 + 1 359 u8 vps_timing_info_present_flag; 360 u32 vps_num_units_in_tick; 361 u32 vps_time_scale; 362 u8 vps_poc_proportional_to_timing_flag; 363 int vps_num_ticks_poc_diff_one; ///< vps_num_ticks_poc_diff_one_minus1 + 1 364 int vps_num_hrd_parameters; 365 }; 366 367 struct ScalingList { 368 /* This is a little wasteful, since sizeID 0 only needs 8 coeffs, 369 * and size ID 3 only has 2 arrays, not 6. */ 370 u8 sl[4][6][64]; 371 u8 sl_dc[2][6]; 372 }; 373 374 struct h265_SPS_t { 375 u8 vps_id; 376 u8 sps_id; 377 int chroma_format_idc; 378 u8 separate_colour_plane_flag; 379 380 struct HEVCWindow output_window; 381 struct HEVCWindow pic_conf_win; 382 383 int bit_depth; 384 int bit_depth_chroma; 385 int pixel_shift; 386 int pix_fmt; 387 388 u32 log2_max_poc_lsb; 389 int pcm_enabled_flag; 390 391 int max_sub_layers; 392 struct { 393 int max_dec_pic_buffering; 394 int num_reorder_pics; 395 int max_latency_increase; 396 } temporal_layer[HEVC_MAX_SUB_LAYERS]; 397 u8 temporal_id_nesting_flag; 398 399 struct VUI vui; 400 struct PTL ptl; 401 402 u8 scaling_list_enable_flag; 403 struct ScalingList scaling_list; 404 405 u32 nb_st_rps; 406 struct ShortTermRPS st_rps[HEVC_MAX_SHORT_TERM_REF_PIC_SETS]; 407 408 u8 amp_enabled_flag; 409 u8 sao_enabled; 410 411 u8 long_term_ref_pics_present_flag; 412 u16 lt_ref_pic_poc_lsb_sps[HEVC_MAX_LONG_TERM_REF_PICS]; 413 u8 used_by_curr_pic_lt_sps_flag[HEVC_MAX_LONG_TERM_REF_PICS]; 414 u8 num_long_term_ref_pics_sps; 415 416 struct { 417 u8 bit_depth; 418 u8 bit_depth_chroma; 419 u32 log2_min_pcm_cb_size; 420 u32 log2_max_pcm_cb_size; 421 u8 loop_filter_disable_flag; 422 } pcm; 423 u8 sps_temporal_mvp_enabled_flag; 424 u8 sps_strong_intra_smoothing_enable_flag; 425 426 u32 log2_min_cb_size; 427 u32 log2_diff_max_min_coding_block_size; 428 u32 log2_min_tb_size; 429 u32 log2_max_trafo_size; 430 u32 log2_ctb_size; 431 u32 log2_min_pu_size; 432 433 int max_transform_hierarchy_depth_inter; 434 int max_transform_hierarchy_depth_intra; 435 436 int sps_range_extension_flag; 437 int transform_skip_rotation_enabled_flag; 438 int transform_skip_context_enabled_flag; 439 int implicit_rdpcm_enabled_flag; 440 int explicit_rdpcm_enabled_flag; 441 int extended_precision_processing_flag; 442 int intra_smoothing_disabled_flag; 443 int high_precision_offsets_enabled_flag; 444 int persistent_rice_adaptation_enabled_flag; 445 int cabac_bypass_alignment_enabled_flag; 446 447 ///< coded frame dimension in various units 448 int width; 449 int height; 450 int ctb_width; 451 int ctb_height; 452 int ctb_size; 453 int min_cb_width; 454 int min_cb_height; 455 int min_tb_width; 456 int min_tb_height; 457 int min_pu_width; 458 int min_pu_height; 459 int tb_mask; 460 461 int hshift[3]; 462 int vshift[3]; 463 464 int qp_bd_offset; 465 466 u8 data[4096]; 467 int data_size; 468 }; 469 470 struct h265_PPS_t { 471 u32 sps_id; ///< seq_parameter_set_id 472 473 u8 sign_data_hiding_flag; 474 475 u8 cabac_init_present_flag; 476 477 int num_ref_idx_l0_default_active; ///< num_ref_idx_l0_default_active_minus1 + 1 478 int num_ref_idx_l1_default_active; ///< num_ref_idx_l1_default_active_minus1 + 1 479 int pic_init_qp_minus26; 480 481 u8 constrained_intra_pred_flag; 482 u8 transform_skip_enabled_flag; 483 484 u8 cu_qp_delta_enabled_flag; 485 int diff_cu_qp_delta_depth; 486 487 int cb_qp_offset; 488 int cr_qp_offset; 489 u8 pic_slice_level_chroma_qp_offsets_present_flag; 490 u8 weighted_pred_flag; 491 u8 weighted_bipred_flag; 492 u8 output_flag_present_flag; 493 u8 transquant_bypass_enable_flag; 494 495 u8 dependent_slice_segments_enabled_flag; 496 u8 tiles_enabled_flag; 497 u8 entropy_coding_sync_enabled_flag; 498 499 int num_tile_columns; ///< num_tile_columns_minus1 + 1 500 int num_tile_rows; ///< num_tile_rows_minus1 + 1 501 u8 uniform_spacing_flag; 502 u8 loop_filter_across_tiles_enabled_flag; 503 504 u8 seq_loop_filter_across_slices_enabled_flag; 505 506 u8 deblocking_filter_control_present_flag; 507 u8 deblocking_filter_override_enabled_flag; 508 u8 disable_dbf; 509 int beta_offset; ///< beta_offset_div2 * 2 510 int tc_offset; ///< tc_offset_div2 * 2 511 512 u8 scaling_list_data_present_flag; 513 struct ScalingList scaling_list; 514 515 u8 lists_modification_present_flag; 516 int log2_parallel_merge_level; ///< log2_parallel_merge_level_minus2 + 2 517 int num_extra_slice_header_bits; 518 u8 slice_header_extension_present_flag; 519 u8 log2_max_transform_skip_block_size; 520 u8 cross_component_prediction_enabled_flag; 521 u8 chroma_qp_offset_list_enabled_flag; 522 u8 diff_cu_chroma_qp_offset_depth; 523 u8 chroma_qp_offset_list_len_minus1; 524 char cb_qp_offset_list[6]; 525 char cr_qp_offset_list[6]; 526 u8 log2_sao_offset_scale_luma; 527 u8 log2_sao_offset_scale_chroma; 528 529 // Inferred parameters 530 u32 *column_width; ///< ColumnWidth 531 u32 *row_height; ///< RowHeight 532 u32 *col_bd; ///< ColBd 533 u32 *row_bd; ///< RowBd 534 int *col_idxX; 535 536 int *ctb_addr_rs_to_ts; ///< CtbAddrRSToTS 537 int *ctb_addr_ts_to_rs; ///< CtbAddrTSToRS 538 int *tile_id; ///< TileId 539 int *tile_pos_rs; ///< TilePosRS 540 int *min_tb_addr_zs; ///< MinTbAddrZS 541 int *min_tb_addr_zs_tab;///< MinTbAddrZS 542 }; 543 544 struct h265_param_sets { 545 bool vps_parsed; 546 bool sps_parsed; 547 bool pps_parsed; 548 /* currently active parameter sets */ 549 struct h265_VPS_t vps; 550 struct h265_SPS_t sps; 551 struct h265_PPS_t pps; 552 }; 553 554 int h265_decode_extradata_ps(u8 *data, int size, struct h265_param_sets *ps); 555 556 #endif /* AML_HEVC_PARSER_H */ 557 558