1
2 // Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
3 //
4 // Licensed under the Apache License, Version 2.0 (the "License");
5 // you may not use this file except in compliance with the License.
6 // You may obtain a copy of the License at
7 //
8 // http://www.apache.org/licenses/LICENSE-2.0
9 //
10 // Unless required by applicable law or agreed to in writing, software
11 // distributed under the License is distributed on an "AS IS" BASIS,
12 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 // See the License for the specific language governing permissions and
14 // limitations under the License.
15
16 #include "soc/rtc.h"
17 #include "soc/dport_reg.h"
18 #include "soc/dport_access.h"
19 #include "soc/i2s_reg.h"
20 #include "hal/cpu_hal.h"
21 #include "driver/periph_ctrl.h"
22 #include "bootloader_clock.h"
23 #include "hal/wdt_hal.h"
24
25 #include "driver/spi_common_internal.h" // [refactor-todo]: for spicommon_periph_in_use
26
27 #include "esp_log.h"
28
29 #include "esp32/clk.h"
30 #include "esp32/rom/rtc.h"
31 #include "esp_rom_uart.h"
32
33 #include "sdkconfig.h"
34
35 static const char* TAG = "clk";
36
37 /* Number of cycles to wait from the 32k XTAL oscillator to consider it running.
38 * Larger values increase startup delay. Smaller values may cause false positive
39 * detection (i.e. oscillator runs for a few cycles and then stops).
40 */
41 #define SLOW_CLK_CAL_CYCLES CONFIG_ESP32_RTC_CLK_CAL_CYCLES
42
43 #ifdef CONFIG_ESP32_RTC_XTAL_CAL_RETRY
44 #define RTC_XTAL_CAL_RETRY CONFIG_ESP32_RTC_XTAL_CAL_RETRY
45 #else
46 #define RTC_XTAL_CAL_RETRY 1
47 #endif
48
49 /* Lower threshold for a reasonably-looking calibration value for a 32k XTAL.
50 * The ideal value (assuming 32768 Hz frequency) is 1000000/32768*(2**19) = 16*10^6.
51 */
52 #define MIN_32K_XTAL_CAL_VAL 15000000L
53
54 /* Indicates that this 32k oscillator gets input from external oscillator, rather
55 * than a crystal.
56 */
57 #define EXT_OSC_FLAG BIT(3)
58
59 /* This is almost the same as rtc_slow_freq_t, except that we define
60 * an extra enum member for the external 32k oscillator.
61 * For convenience, lower 2 bits should correspond to rtc_slow_freq_t values.
62 */
63 typedef enum {
64 SLOW_CLK_150K = RTC_SLOW_FREQ_RTC, //!< Internal 150 kHz RC oscillator
65 SLOW_CLK_32K_XTAL = RTC_SLOW_FREQ_32K_XTAL, //!< External 32 kHz XTAL
66 SLOW_CLK_8MD256 = RTC_SLOW_FREQ_8MD256, //!< Internal 8 MHz RC oscillator, divided by 256
67 SLOW_CLK_32K_EXT_OSC = RTC_SLOW_FREQ_32K_XTAL | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin
68 } slow_clk_sel_t;
69
select_rtc_slow_clk(slow_clk_sel_t slow_clk)70 static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
71 {
72 rtc_slow_freq_t rtc_slow_freq = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V;
73 uint32_t cal_val = 0;
74 /* number of times to repeat 32k XTAL calibration
75 * before giving up and switching to the internal RC
76 */
77 int retry_32k_xtal = RTC_XTAL_CAL_RETRY;
78
79 do {
80 if (rtc_slow_freq == RTC_SLOW_FREQ_32K_XTAL) {
81 /* 32k XTAL oscillator needs to be enabled and running before it can
82 * be used. Hardware doesn't have a direct way of checking if the
83 * oscillator is running. Here we use rtc_clk_cal function to count
84 * the number of main XTAL cycles in the given number of 32k XTAL
85 * oscillator cycles. If the 32k XTAL has not started up, calibration
86 * will time out, returning 0.
87 */
88 ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
89 if (slow_clk == SLOW_CLK_32K_XTAL) {
90 rtc_clk_32k_enable(true);
91 } else if (slow_clk == SLOW_CLK_32K_EXT_OSC) {
92 rtc_clk_32k_enable_external();
93 }
94 // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
95 if (SLOW_CLK_CAL_CYCLES > 0) {
96 cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES);
97 if (cal_val == 0 || cal_val < MIN_32K_XTAL_CAL_VAL) {
98 if (retry_32k_xtal-- > 0) {
99 continue;
100 }
101 ESP_EARLY_LOGW(TAG, "32 kHz XTAL not found, switching to internal 150 kHz oscillator");
102 rtc_slow_freq = RTC_SLOW_FREQ_RTC;
103 }
104 }
105 } else if (rtc_slow_freq == RTC_SLOW_FREQ_8MD256) {
106 rtc_clk_8m_enable(true, true);
107 }
108 rtc_clk_slow_freq_set(rtc_slow_freq);
109
110 if (SLOW_CLK_CAL_CYCLES > 0) {
111 /* TODO: 32k XTAL oscillator has some frequency drift at startup.
112 * Improve calibration routine to wait until the frequency is stable.
113 */
114 cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
115 } else {
116 const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
117 cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz());
118 }
119 } while (cal_val == 0);
120 ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
121 esp_clk_slowclk_cal_set(cal_val);
122 }
123
esp_clk_init(void)124 __attribute__((weak)) void esp_clk_init(void)
125 {
126 rtc_config_t cfg = RTC_CONFIG_DEFAULT();
127 rtc_init(cfg);
128
129 #if (CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS || CONFIG_ESP32_APP_INIT_CLK)
130 /* Check the bootloader set the XTAL frequency.
131
132 Bootloaders pre-v2.1 don't do this.
133 */
134 rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
135 if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
136 ESP_EARLY_LOGW(TAG, "RTC domain not initialised by bootloader");
137 bootloader_clock_configure();
138 }
139 #else
140 /* If this assertion fails, either upgrade the bootloader or enable CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS */
141 assert(rtc_clk_xtal_freq_get() != RTC_XTAL_FREQ_AUTO);
142 #endif
143
144 rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M);
145
146 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
147 // WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed.
148 // If the frequency changes from 150kHz to 32kHz, then the timeout set for the WDT will increase 4.6 times.
149 // Therefore, for the time of frequency change, set a new lower timeout value (1.6 sec).
150 // This prevents excessive delay before resetting in case the supply voltage is drawdown.
151 // (If frequency is changed from 150kHz to 32kHz then WDT timeout will increased to 1.6sec * 150/32 = 7.5 sec).
152 wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
153 uint32_t stage_timeout_ticks = (uint32_t)(1600ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
154 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
155 wdt_hal_feed(&rtc_wdt_ctx);
156 //Bootloader has enabled RTC WDT until now. We're only modifying timeout, so keep the stage and timeout action the same
157 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
158 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
159 #endif
160
161 #if defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS)
162 select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
163 #elif defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_OSC)
164 select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC);
165 #elif defined(CONFIG_ESP32_RTC_CLK_SRC_INT_8MD256)
166 select_rtc_slow_clk(SLOW_CLK_8MD256);
167 #else
168 select_rtc_slow_clk(RTC_SLOW_FREQ_RTC);
169 #endif
170
171 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
172 // After changing a frequency WDT timeout needs to be set for new frequency.
173 stage_timeout_ticks = (uint32_t)((uint64_t)CONFIG_BOOTLOADER_WDT_TIME_MS * rtc_clk_slow_freq_get_hz() / 1000);
174 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
175 wdt_hal_feed(&rtc_wdt_ctx);
176 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
177 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
178 #endif
179
180 rtc_cpu_freq_config_t old_config;
181 rtc_cpu_freq_config_t new_config;
182 rtc_clk_cpu_freq_get_config(&old_config);
183 const uint32_t old_freq_mhz = old_config.freq_mhz;
184 const uint32_t new_freq_mhz = CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ;
185
186 bool res = rtc_clk_cpu_freq_mhz_to_config(new_freq_mhz, &new_config);
187 assert(res);
188
189 // Wait for UART TX to finish, otherwise some UART output will be lost
190 // when switching APB frequency
191 if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
192 esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
193 }
194
195 rtc_clk_cpu_freq_set_config(&new_config);
196
197 // Re calculate the ccount to make time calculation correct.
198 cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * new_freq_mhz / old_freq_mhz );
199 }
200
201 /* This function is not exposed as an API at this point.
202 * All peripheral clocks are default enabled after chip is powered on.
203 * This function disables some peripheral clocks when cpu starts.
204 * These peripheral clocks are enabled when the peripherals are initialized
205 * and disabled when they are de-initialized.
206 */
esp_perip_clk_init(void)207 __attribute__((weak)) void esp_perip_clk_init(void)
208 {
209 uint32_t common_perip_clk;
210 uint32_t hwcrypto_perip_clk;
211 uint32_t wifi_bt_sdio_clk;
212
213 #if CONFIG_FREERTOS_UNICORE
214 RESET_REASON rst_reas[1];
215 #else
216 RESET_REASON rst_reas[2];
217 #endif
218
219 rst_reas[0] = rtc_get_reset_reason(0);
220
221 #if !CONFIG_FREERTOS_UNICORE
222 rst_reas[1] = rtc_get_reset_reason(1);
223 #endif
224
225 /* For reason that only reset CPU, do not disable the clocks
226 * that have been enabled before reset.
227 */
228 if ((rst_reas[0] >= TGWDT_CPU_RESET && rst_reas[0] <= RTCWDT_CPU_RESET)
229 #if !CONFIG_FREERTOS_UNICORE
230 || (rst_reas[1] >= TGWDT_CPU_RESET && rst_reas[1] <= RTCWDT_CPU_RESET)
231 #endif
232 ) {
233 common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
234 hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERI_CLK_EN_REG);
235 wifi_bt_sdio_clk = ~DPORT_READ_PERI_REG(DPORT_WIFI_CLK_EN_REG);
236 }
237 else {
238 common_perip_clk = DPORT_WDG_CLK_EN |
239 DPORT_PCNT_CLK_EN |
240 DPORT_LEDC_CLK_EN |
241 DPORT_TIMERGROUP1_CLK_EN |
242 DPORT_PWM0_CLK_EN |
243 DPORT_TWAI_CLK_EN |
244 DPORT_PWM1_CLK_EN |
245 DPORT_PWM2_CLK_EN |
246 DPORT_PWM3_CLK_EN;
247 hwcrypto_perip_clk = DPORT_PERI_EN_AES |
248 DPORT_PERI_EN_SHA |
249 DPORT_PERI_EN_RSA |
250 DPORT_PERI_EN_SECUREBOOT;
251 wifi_bt_sdio_clk = DPORT_WIFI_CLK_WIFI_EN |
252 DPORT_WIFI_CLK_BT_EN_M |
253 DPORT_WIFI_CLK_UNUSED_BIT5 |
254 DPORT_WIFI_CLK_UNUSED_BIT12 |
255 DPORT_WIFI_CLK_SDIOSLAVE_EN |
256 DPORT_WIFI_CLK_SDIO_HOST_EN |
257 DPORT_WIFI_CLK_EMAC_EN;
258 }
259
260 //Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state.
261 common_perip_clk |= DPORT_I2S0_CLK_EN |
262 #if CONFIG_ESP_CONSOLE_UART_NUM != 0
263 DPORT_UART_CLK_EN |
264 #endif
265 #if CONFIG_ESP_CONSOLE_UART_NUM != 1
266 DPORT_UART1_CLK_EN |
267 #endif
268 #if CONFIG_ESP_CONSOLE_UART_NUM != 2
269 DPORT_UART2_CLK_EN |
270 #endif
271 DPORT_SPI2_CLK_EN |
272 DPORT_I2C_EXT0_CLK_EN |
273 DPORT_UHCI0_CLK_EN |
274 DPORT_RMT_CLK_EN |
275 DPORT_UHCI1_CLK_EN |
276 DPORT_SPI3_CLK_EN |
277 DPORT_I2C_EXT1_CLK_EN |
278 DPORT_I2S1_CLK_EN |
279 DPORT_SPI_DMA_CLK_EN;
280
281 common_perip_clk &= ~DPORT_SPI01_CLK_EN;
282
283 #if CONFIG_SPIRAM_SPEED_80M
284 //80MHz SPIRAM uses SPI2/SPI3 as well; it's initialized before this is called. Because it is used in
285 //a weird mode where clock to the peripheral is disabled but reset is also disabled, it 'hangs'
286 //in a state where it outputs a continuous 80MHz signal. Mask its bit here because we should
287 //not modify that state, regardless of what we calculated earlier.
288 if (spicommon_periph_in_use(HSPI_HOST)) {
289 common_perip_clk &= ~DPORT_SPI2_CLK_EN;
290 }
291 if (spicommon_periph_in_use(VSPI_HOST)) {
292 common_perip_clk &= ~DPORT_SPI3_CLK_EN;
293 }
294 #endif
295
296 /* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,
297 * the current is not reduced when disable I2S clock.
298 */
299 DPORT_SET_PERI_REG_MASK(I2S_CLKM_CONF_REG(0), I2S_CLKA_ENA);
300 DPORT_SET_PERI_REG_MASK(I2S_CLKM_CONF_REG(1), I2S_CLKA_ENA);
301
302 /* Disable some peripheral clocks. */
303 DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, common_perip_clk);
304 DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, common_perip_clk);
305
306 /* Disable hardware crypto clocks. */
307 DPORT_CLEAR_PERI_REG_MASK(DPORT_PERI_CLK_EN_REG, hwcrypto_perip_clk);
308 DPORT_SET_PERI_REG_MASK(DPORT_PERI_RST_EN_REG, hwcrypto_perip_clk);
309
310 /* Disable WiFi/BT/SDIO clocks. */
311 DPORT_CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
312
313 /* Enable RNG clock. */
314 periph_module_enable(PERIPH_RNG_MODULE);
315 }
316
rtc_clk_select_rtc_slow_clk(void)317 void rtc_clk_select_rtc_slow_clk(void)
318 {
319 select_rtc_slow_clk(RTC_SLOW_FREQ_32K_XTAL);
320 }
321