1 // Copyright (C) 2022 Beken Corporation 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 typedef volatile struct { 22 /* REG_0x0 */ 23 union { 24 struct { 25 uint32_t tx_fifo_int_level: 2; /**< bit[0:1] */ 26 uint32_t rx_fifo_int_level: 2; /**< bit[2:3] */ 27 uint32_t tx_udf_int_en: 1; /**< bit[4] tx fifo underflow int enable */ 28 uint32_t rx_ovf_int_en: 1; /**< bit[5] rx fifo overflow int enable */ 29 uint32_t tx_fifo_int_en: 1; /**< bit[6] */ 30 uint32_t rx_fifo_int_en: 1; /**< bit[7] */ 31 uint32_t clk_rate: 8; /**< bit[8:15] spi clock rate */ 32 uint32_t slave_release_int_en: 1; /**< bit[16] only for 4 wire mode */ 33 uint32_t wire3_en: 1; /**< bit[17] 0: 4 wire, 1: 3 wire */ 34 uint32_t bit_width: 1; /**< bit[18] 0: 8bit, 1: 16bit */ 35 uint32_t lsb_first_en: 1; /**< bit[19] 0: MSB first, 1: LSB first */ 36 uint32_t cpol: 1; /**< bit[20] */ 37 uint32_t cpha: 1; /**< bit[21] */ 38 uint32_t master_en: 1; /**< bit[22] */ 39 uint32_t enable: 1; /**< bit[23] */ 40 uint32_t byte_interval: 6; /**< bit[24:29] */ 41 uint32_t reserved: 2; /**< bit[30:31] */ 42 }; 43 uint32_t v; 44 } ctrl; 45 46 /* REG_0x1 */ 47 union { 48 struct { 49 uint32_t tx_en: 1; /**< bit[0] */ 50 uint32_t rx_en: 1; /**< bit[1] */ 51 uint32_t tx_finish_int_en: 1; /**< bit[2] */ 52 uint32_t rx_finish_int_en: 1; /**< bit[3] */ 53 uint32_t reserved: 4; /**< bit[4:7] */ 54 uint32_t tx_trans_len: 12; /**< bit[8:19] */ 55 uint32_t rx_trans_len: 12; /**< bit[20:31] */ 56 }; 57 uint32_t v; 58 } cfg; 59 60 /* REG_0x2 */ 61 union { 62 struct { 63 uint32_t reserved0: 1; /**< bit[0] */ 64 uint32_t tx_fifo_wr_ready: 1; /**< bit[1] */ 65 uint32_t rx_fifo_rd_ready: 1; /**< bit[2] */ 66 uint32_t reserved1: 1; /**< bit[3] */ 67 uint32_t reserved2: 4; /**< bit[4:7] */ 68 uint32_t tx_fifo_int: 1; /**< bit[8] */ 69 uint32_t rx_fifo_int: 1; /**< bit[9] */ 70 uint32_t slave_release_int: 1; /**< bit[10] */ 71 uint32_t tx_underflow_int: 1; /**< bit[11] */ 72 uint32_t rx_overflow_int: 1; /**< bit[12] */ 73 uint32_t tx_finish_int: 1; /**< bit[13] */ 74 uint32_t rx_finish_int: 1; /**< bit[14] */ 75 uint32_t reserved3: 1; /**< bit[15] */ 76 uint32_t tx_fifo_clr: 1; /**< bit[16] */ 77 uint32_t rx_fifo_clr: 1; /**< bit[17] */ 78 uint32_t reserved4: 14; /**< bit[18:31] */ 79 }; 80 uint32_t v; 81 } int_status; 82 83 /* REG_0x3 */ 84 union { 85 struct { 86 uint32_t fifo_data: 16; /**< bit[0:15] */ 87 uint32_t reserved: 16; /**< bit[16:31] */ 88 }; 89 uint32_t v; 90 } data; 91 } spi_hw_t; 92 93 #ifdef __cplusplus 94 } 95 #endif 96 97