1 // Copyright (C) 2022 Beken Corporation 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 typedef volatile struct { 22 /* REG_0x00 */ 23 union { 24 struct { 25 uint32_t tx_enable: 1; /**< bit[0] uart tx enable */ 26 uint32_t rx_enable: 1; /**< bit[1] uart rx enable */ 27 uint32_t mode: 1; /**< bit[2] 0: uart mode, 1: idra mode */ 28 /* uart length 29 * 0: 5bit 30 * 1: 6bit 31 * 2: 7bit 32 * 3: 8bit 33 */ 34 uint32_t data_bits: 2; /**< bit[3:4] data bits */ 35 uint32_t parity_en: 1; /**< bit[5] 0: disable, 1: enable */ 36 uint32_t parity: 1; /**< bit[6] parity 0: Even, 1: Odd */ 37 uint32_t stop_bits: 1; /**< bit[7] stop bits, 0: 1 bit, 1: 2bit */ 38 uint32_t clk_div: 13; /**< bit[8:20] clk_div = uart_clk/baud_rate */ 39 uint32_t reserved: 11; 40 }; 41 uint32_t v; 42 } config; 43 44 /* REG_0x01 */ 45 union { 46 struct { 47 uint32_t tx_fifo_threshold: 8; /**< bit[0:7] */ 48 uint32_t rx_fifo_threshold: 8; /**< bit[8:15] */ 49 /* rx stop detect time 50 * 0: 32 51 * 1: 64 52 * 2: 128 53 * 3: 256 54 */ 55 uint32_t rx_stop_detect_time: 2; /**< bit[16:17] */ 56 uint32_t reserved: 14; 57 }; 58 uint32_t v; 59 } fifo_config; 60 61 /* REG_0x02 */ 62 union { 63 struct { 64 uint32_t tx_fifo_count: 8; /**< bit[0:7] */ 65 uint32_t rx_fifo_count: 8; /**< bit[8:15] */ 66 uint32_t tx_fifo_full: 1; /**< bit[16] */ 67 uint32_t tx_fifo_empty: 1; /**< bit[17] */ 68 uint32_t rx_fifo_full: 1; /**< bit[18] */ 69 uint32_t rx_fifo_empty: 1; /**< bit[19] */ 70 uint32_t fifo_wr_ready: 1; /**< bit[20] */ 71 uint32_t fifo_rd_ready: 1; /**< bit[21] */ 72 uint32_t reserved: 10; 73 }; 74 uint32_t v; 75 } fifo_status; 76 77 /* REG_0x03 */ 78 union { 79 struct { 80 uint32_t tx_fifo_data_in: 8; /**< bit[0:7] */ 81 uint32_t rx_fifo_data_out: 8; /**< bit[8:15] */ 82 uint32_t reserved: 16; 83 }; 84 uint32_t v; 85 } fifo_port; 86 87 /* REG_0x04 */ 88 union { 89 struct { 90 uint32_t tx_fifo_need_write: 1; /**< bit[0] */ 91 uint32_t rx_fifo_need_read: 1; /**< bit[1] */ 92 uint32_t rx_fifo_overflow: 1; /**< bit[2] */ 93 uint32_t rx_parity_err: 1; /**< bit[3] */ 94 uint32_t rx_stop_bits_err: 1; /**< bit[4] */ 95 uint32_t tx_finish: 1; /**< bit[5] */ 96 uint32_t rx_finish: 1; /**< bit[6] */ 97 uint32_t rxd_wakeup: 1; /**< bit[7] */ 98 uint32_t reserved: 24; 99 }; 100 uint32_t v; 101 } int_enable; 102 103 /* REG_0x05 */ 104 union { 105 struct { 106 uint32_t tx_fifo_need_write: 1; /**< bit[0] */ 107 uint32_t rx_fifo_need_read: 1; /**< bit[1] */ 108 uint32_t rx_fifo_overflow: 1; /**< bit[2] */ 109 uint32_t rx_parity_err: 1; /**< bit[3] */ 110 uint32_t rx_stop_bits_err: 1; /**< bit[4] */ 111 uint32_t tx_finish: 1; /**< bit[5] */ 112 uint32_t rx_finish: 1; /**< bit[6] */ 113 uint32_t rxd_wakeup: 1; /**< bit[7] */ 114 uint32_t reserved: 24; 115 }; 116 uint32_t v; 117 } int_status; 118 119 /* REG_0x06 */ 120 union { 121 struct { 122 uint32_t flow_ctrl_low_cnt: 8; /**< bit[0:7] */ 123 uint32_t flow_ctrl_high_cnt: 8; /**< bit[8:15] */ 124 uint32_t flow_ctrl_en: 1; /**< bit[16] */ 125 uint32_t rts_polarity_sel: 1; /**< bit[17] */ 126 uint32_t cts_polarity_sel: 1; /**< bit[18] */ 127 uint32_t reserved: 13; /**< bit[19:31] */ 128 }; 129 uint32_t v; 130 } flow_ctrl_config; 131 132 /* REG_0x07 */ 133 union { 134 struct { 135 uint32_t wake_cnt: 10; /**< bit[0:9] */ 136 uint32_t txd_wait_cnt: 10; /**< bit[10:19] */ 137 uint32_t rxd_wake_en: 1; /**< bit[20] */ 138 uint32_t txd_wake_en: 1; /**< bit[21] */ 139 uint32_t rxd_neg_edge_wake_en: 1; /**< bit[22] */ 140 uint32_t reserved: 9; 141 }; 142 uint32_t v; 143 } wake_config; 144 145 } uart_hw_t; 146 147 #ifdef __cplusplus 148 } 149 #endif 150 151