1 /*
2 * Copyright (c) 2023 HPMicro
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7 #ifndef HPM_MCAN_DRV_H
8 #define HPM_MCAN_DRV_H
9
10 #include "hpm_common.h"
11 #include "hpm_mcan_regs.h"
12 #include "hpm_mcan_soc.h"
13
14 #ifdef __cplusplus
15 extern "C" {
16 #endif
17
18 /**
19 * @brief MCAN driver APIs
20 * @defgroup mcan_interface MCAN driver APIs
21 * @ingroup mcan_interfaces
22 * @{
23 *
24 */
25
26
27 enum {
28 status_mcan_filter_index_out_of_range = MAKE_STATUS(status_group_mcan, 0),
29 status_mcan_rxfifo_empty,
30 status_mcan_rxfifo_full,
31 status_mcan_txbuf_full,
32 status_mcan_txfifo_full,
33 status_mcan_rxfifo0_busy,
34 status_mcan_rxfifo1_busy,
35 status_mcan_txbuf_index_out_of_range,
36 status_mcan_rxbuf_index_out_of_range,
37 status_mcan_rxbuf_empty,
38 status_mcan_tx_evt_fifo_empty,
39 status_mcan_timestamp_not_exist,
40 status_mcan_ram_out_of_range,
41 };
42
43 /**
44 * @brief CAN Interrupt Mask
45 */
46 #define MCAN_INT_ACCESS_TO_RESERVED_ADDR MCAN_IR_ARA_MASK /*!< Access to Reserved Address */
47 #define MCAN_INT_PROTOCOL_ERR_IN_DATA_PHASE MCAN_IR_PED_MASK /*!< Protocol Error Happened at Data Phase */
48 #define MCAN_INT_PROTOCOL_ERR_IN_ARB_PHASE MCAN_IR_PEA_MASK /*!< Protocol Error Happened at Arbitration Phase */
49 #define MCAN_INT_WATCHDOG_INT MCAN_IR_WDI_MASK /*!< Watchdog interrupt */
50
51 #define MCAN_INT_BUS_OFF_STATUS MCAN_IR_BO_MASK /*!< Bus-off State Change */
52 #define MCAN_INT_WARNING_STATUS MCAN_IR_EW_MASK /*!< Error Warning State Change */
53 #define MCAN_INT_ERROR_PASSIVE MCAN_IR_EP_MASK /*!< Error Passive State Change */
54 #define MCAN_INT_ERROR_LOGGING_OVERFLOW MCAN_IR_ELO_MASK /*!< Error Logging Overflow */
55 #define MCAN_INT_BIT_ERROR_UNCORRECTED MCAN_IR_BEU_MASK /*!< Bit Error was not corrected */
56 #define MCAN_INT_BIT_ERROR_CORRECTED MCAN_IR_BEC_MASK /*!< Bit Error was corrected */
57
58 #define MCAN_INT_MSG_STORE_TO_RXBUF MCAN_IR_DRX_MASK /*!< Message was stored to RX Buffer */
59 #define MCAN_INT_TIMEOUT_OCCURRED MCAN_IR_TOO_MASK /*!< Timeout Interrupt */
60 #define MCAN_INT_MSG_RAM_ACCESS_FAILURE MCAN_IR_MRAF_MASK /*!< Message RAM Access Failure */
61 #define MCAN_INT_TIMESTAMP_WRAPAROUND MCAN_IR_TSW_MASK /*!< Timestamp Counter Wrap Around */
62
63 #define MCAN_INT_TX_EVT_FIFO_EVT_LOST MCAN_IR_TEFL_MASK /*!< TX Event FIFO Element Lost */
64 #define MCAN_INT_TX_EVT_FIFO_FULL MCAN_IR_TEFF_MASK /*!< TX Event FIFO Full */
65 #define MCAN_INT_TX_EVT_FIFO_WMK_REACHED MCAN_IR_TEFW_MASK /*!< TX Event FIFO Watermark Reached */
66 #define MCAN_INT_TX_EVT_FIFO_NEW_ENTRY MCAN_IR_TEFN_MASK /*!< TX Event FIFO New Entry */
67
68 #define MCAN_INT_TXFIFO_EMPTY MCAN_IR_TFE_MASK /*!< TX FIFO Empty */
69 #define MCAN_INT_TX_CANCEL_FINISHED MCAN_IR_TCF_MASK /*!< Transmission Cancellation Finished */
70 #define MCAN_INT_TX_COMPLETED MCAN_IR_TC_MASK /*!< Transmission Completed */
71 #define MCAN_INT_HIGH_PRIORITY_MSG MCAN_IR_HPM_MASK /*!< High Priority Message */
72
73 #define MCAN_INT_RXFIFO1_MSG_LOST MCAN_IR_RF1L_MASK /*!< RX FIFO0 Message Lost */
74 #define MCAN_INT_RXFIFO1_FULL MCAN_IR_RF1F_MASK /*!< RX FIFO1 Full */
75 #define MCAN_INT_RXFIFO1_WMK_REACHED MCAN_IR_RF1W_MASK /*!< RX FIFO1 Watermark Reached */
76 #define MCAN_INT_RXFIFO1_NEW_MSG MCAN_IR_RF1N_MASK /*!< RX FIFO1 New Message */
77
78 #define MCAN_INT_RXFIFO0_MSG_LOST MCAN_IR_RF0L_MASK /*!< RX FIFO0 Message Lost */
79 #define MCAN_INT_RXFIFO0_FULL MCAN_IR_RF0F_MASK /*!< RX FIFO0 Full */
80 #define MCAN_INT_RXFIFO0_WMK_REACHED MCAN_IR_RF0W_MASK /*!< RX FIFO0 Watermark Reached */
81 #define MCAN_INT_RXFIFI0_NEW_MSG MCAN_IR_RF0N_MASK /*!< RX FIFO0 New Message */
82
83 /**
84 * @brief MCAN Receive Event Flags
85 */
86 #define MCAN_EVENT_RECEIVE (MCAN_INT_RXFIFI0_NEW_MSG | MCAN_INT_RXFIFO1_NEW_MSG | MCAN_INT_MSG_STORE_TO_RXBUF)
87
88 /**
89 * @brief MCAN Transmit Event Flags
90 */
91 #define MCAN_EVENT_TRANSMIT (MCAN_INT_TX_COMPLETED)
92 /**
93 * @brief MCAN Error Event Flags
94 */
95 #define MCAN_EVENT_ERROR (MCAN_INT_BUS_OFF_STATUS | MCAN_INT_WARNING_STATUS \
96 | MCAN_INT_ERROR_PASSIVE | MCAN_INT_BIT_ERROR_UNCORRECTED \
97 | MCAN_INT_PROTOCOL_ERR_IN_DATA_PHASE | MCAN_INT_PROTOCOL_ERR_IN_ARB_PHASE)
98
99 /**
100 * @brief Maximum Transmission Retry Count
101 */
102 #define MCAN_TX_RETRY_COUNT_MAX (10000000UL)
103 /**
104 * @brief Maximum Receive Wait Retry Count
105 */
106 #define MCAN_RX_RETRY_COUNT_MAX (80000000UL)
107
108 /**
109 * @brief MCAN Last Error Code
110 */
111 typedef enum mcan_last_error_code {
112 mcan_last_error_code_no_error = 0, /*!< No error happened */
113 mcan_last_error_code_stuff_error, /*!< Stuff Error */
114 mcan_last_error_code_format_error, /*!< Format Error */
115 mcan_last_error_code_ack_error, /*!< Acknowledge Error */
116 mcan_last_error_code_bit1_error, /*!< Sent logic 1 but monitored value is logic 0 */
117 mcan_last_error_code_bit0_error, /*!< Sent logic 0 but monitored value is logic 1 */
118 mcan_last_error_code_crc_error, /*!< CRC checksum for received message is wrong */
119 mcan_last_error_code_no_change, /*!< Error code was not changed */
120 } mcan_last_err_code_t;
121
122 /**
123 * @brief MCAN Communication State
124 */
125 typedef enum mcan_activity_enum {
126 mcan_activity_sync = 0, /*!< Node is synchronizing on CAN communication */
127 mcan_activity_idle, /*!< Node is neither receiver nor transmitter */
128 mcan_activity_receiver, /*!< Node is operating as receiver */
129 mcan_activity_transmitter, /*!< Node is operating as transmitter */
130 } mcan_activity_state_t;
131
132 /***********************************************************************************************************************
133 * @brief Default CAN RAM definitions
134 **********************************************************************************************************************/
135 #define MCAN_RAM_WORD_SIZE (640U) /*!< RAM WORD Size */
136 /* CAN Filter Element Size Definitions */
137 #define MCAN_FILTER_ELEM_STD_ID_SIZE (4U) /*!< Standard Filter Element Size in Bytes */
138 #define MCAN_FILTER_ELEM_EXT_ID_SIZE (8U) /*!< Extended Filter Element SIze in Bytes */
139 #define MCAN_STD_FILTER_ELEM_SIZE_MAX (128U) /*!< Maximum Standard Filter Element Count */
140 #define MCAN_EXT_FILTER_ELEM_SIZE_MAX (64U) /*!< Maximum Extended Filter Element Count */
141 /* MCAN Default Field Size Definitions for CAN2.0 */
142 #define MCAN_TXRX_ELEM_SIZE_CAN_MAX (4U * sizeof(uint32_t))
143 #define MCAN_FILTER_SIZE_CAN_DEFAULT (32U)
144 #define MCAN_TXBUF_SIZE_CAN_DEFAULT (32U)
145 #define MCAN_RXFIFO_SIZE_CAN_DEFAULT (32U)
146 #define MCAN_RXBUF_SIZE_CAN_DEFAULT (16U)
147 /* MCAN Default Field Size Definitions for CANFD */
148 #define MCAN_TXRX_ELEM_SIZE_CANFD_MAX (18U * sizeof(uint32_t))
149 #define MCAN_FILTER_SIZE_CANFD_DEFAULT (16U)
150 #define MCAN_TXBUF_SIZE_CANFD_DEFAULT (8U)
151 #define MCAN_RXFIFO_SIZE_CANFD_DEFAULT (8U)
152 #define MCAN_RXBUF_SIZE_CANFD_DEFAULT (4U)
153
154 #define MCAN_TXEVT_ELEM_SIZE (8U)
155
156 /**
157 * @brief CAN Bit Timing Parameters
158 */
159 typedef struct mcan_bit_timing_param_struct {
160 uint16_t prescaler; /*!< Data Bit Rate Prescaler */
161 uint16_t num_seg1; /*!< Time segment before sample point (including prop_seg and phase_sge1 */
162 uint16_t num_seg2; /*!< Time segment after sample point */
163 uint8_t num_sjw; /*!< Data (Re)Synchronization Jump Width */
164 bool enable_tdc; /*!< Enable TDC flag, for CANFD data bit timing only */
165 } mcan_bit_timing_param_t;
166
167 /**
168 * @brief CAN Bit Timing Options
169 */
170 typedef enum mcan_bit_timing_option {
171 mcan_bit_timing_can2_0, /**< CAN 2.0 bit timing option */
172 mcan_bit_timing_canfd_nominal, /**< CANFD nominal timing option */
173 mcan_bit_timing_canfd_data, /**< CANFD data timing option */
174 } mcan_bit_timing_option_t;
175
176 /**
177 * @brief CAN Message Header Size
178 */
179 #define MCAN_MESSAGE_HEADER_SIZE_IN_BYTES (8U)
180 #define MCAN_MESSAGE_HEADER_SIZE_IN_WORDS (2U)
181
182 /**
183 * @brief CAN Transmit Message Frame
184 *
185 * @note Users need to pay attention to the CAN Identifier settings
186 * For standard identifier, the use_ext_id should be set to 0 and the std_id should be used
187 * For extended identifier, the use_ext_id should be set to 1 and the ext_id should be used
188 */
189 typedef struct mcan_tx_message_struct {
190 union {
191 struct {
192 uint32_t ext_id: 29; /*!< Extended CAN Identifier */
193 uint32_t rtr: 1; /*!< Remote Transmission Request */
194 uint32_t use_ext_id: 1; /*!< Extended Identifier */
195 uint32_t error_state_indicator: 1; /*!< Error State Indicator */
196 };
197 struct {
198 uint32_t : 18;
199 uint32_t std_id: 11; /*!< Standard CAN Identifier */
200 uint32_t : 3;
201 };
202 };
203 struct {
204 uint32_t : 8;
205 uint32_t message_marker_h: 8; /*!< Message Marker[15:8] */
206 uint32_t dlc: 4; /*!< Data Length Code */
207 uint32_t bitrate_switch: 1; /*!< Bit Rate Switch */
208 uint32_t canfd_frame: 1; /*!< CANFD frame */
209 uint32_t timestamp_capture_enable: 1; /*!< Timestamp Capture Enable for TSU */
210 uint32_t event_fifo_control: 1; /*!< Event FIFO control */
211 uint32_t message_marker_l: 8; /*!< Message Marker[7:0] */
212 };
213 union {
214 uint8_t data_8[64]; /*!< Data buffer as byte array */
215 uint32_t data_32[16]; /*!< Data buffer as word array */
216 };
217 } mcan_tx_frame_t;
218
219 /**
220 * @brief CAN Receive Message Frame
221 *
222 * @note Users need to pay attention to the CAN Identifier settings
223 * For standard identifier, the use_ext_id should be set to 0 and the std_id should be used
224 * For extended identifier, the use_ext_id should be set to 1 and the ext_id should be used
225 */
226 typedef struct mcan_rx_message_struct {
227 union {
228 struct {
229 uint32_t ext_id: 29; /*!< Extended CAN Identifier */
230 uint32_t rtr: 1; /*!< Remote Frame Flag */
231 uint32_t use_ext_id: 1; /*!< Extended Identifier */
232 uint32_t error_state_indicator: 1; /*!< Error State Indicator */
233 };
234 struct {
235 uint32_t : 18;
236 uint32_t std_id: 11; /*!< Standard CAN Identifier */
237 uint32_t : 3;
238 };
239 };
240 struct {
241 union {
242 uint16_t rx_timestamp; /*!< Received timestamp */
243 struct {
244 uint16_t rx_timestamp_pointer: 4; /*!< Timestamp Pointer */
245 uint16_t rx_timestamp_captured: 1; /*!< Timestamp Captured flag */
246 uint16_t : 11;
247 };
248 };
249 };
250 struct {
251 uint16_t dlc: 4; /*!< Data Length Code */
252 uint16_t bitrate_switch: 1; /*!< Bit rate switch flag */
253 uint16_t canfd_frame: 1; /*!< CANFD Frame flag */
254 uint16_t : 1;
255 uint16_t filter_index: 7; /*!< CAN filter index */
256 uint16_t accepted_non_matching_frame: 1; /*!< Accept non-matching Frame flag */
257 };
258 union {
259 uint8_t data_8[64]; /*!< Data buffer as byte array */
260 uint32_t data_32[16]; /*!< Data buffer as word array */
261 };
262 } mcan_rx_message_t;
263
264 /**
265 * @brief TX Event Fifo Element Structure
266 */
267 typedef union mcan_tx_event_fifo_elem_struct {
268 struct {
269 /* First word */
270 union {
271 struct {
272 uint32_t ext_id: 29; /*!< CAN Identifier */
273 uint32_t rtr: 1; /*!< Remote Transmission Request */
274 uint32_t extend_id: 1; /*!< Extended Identifier */
275 uint32_t error_state_indicator: 1; /*!< Error State Indicator */
276 };
277 struct {
278 uint32_t : 18;
279 uint32_t std_id: 11;
280 uint32_t : 3;
281 };
282 };
283
284 /* first 16-bit of the 2nd word */
285 union {
286 uint16_t tx_timestamp; /*!< Tx Timestamp */
287 struct {
288 uint16_t tx_timestamp_pointer: 4; /*!< TX timestamp pointer */
289 uint16_t tx_timestamp_captured: 1; /*!< TX timestamp captured flag */
290 uint16_t : 11;
291 };
292 };
293 /* high-half 16-bit of the 2nd word */
294 struct {
295 uint16_t dlc: 4; /*!< Data length code */
296 uint16_t bitrate_switch: 1; /*!< Bitrate Switch flag */
297 uint16_t canfd_frame: 1; /*!< CANFD frame */
298 uint16_t event_type: 2; /*!< Event type */
299 uint16_t message_marker: 8; /*!< Message Marker */
300 };
301 };
302 uint32_t words[2];
303 } mcan_tx_event_fifo_elem_t;
304
305
306
307 /**
308 * @brief CAN Identifier Types
309 */
310 #define MCAN_CAN_ID_TYPE_STANDARD (0U) /*!< Standard Identifier */
311 #define MCAN_CAN_ID_TYPE_EXTENDED (1U) /*!< Extended Identifier */
312
313 /**
314 * @brief MCAN Filter Configuration
315 */
316 typedef union mcan_filter_config_struct {
317 struct {
318 uint16_t list_start_addr; /*!< List Start address (CAN Message Buffer Offset) */
319 uint16_t list_size; /*!< Element Count */
320 };
321 uint32_t reg_val; /*!< Register value */
322 } mcan_filter_config_t;
323
324 /**
325 * @brief MCAN RXFIFO Configuration
326 */
327 typedef union mcan_rxfifo_config_struct {
328 struct {
329 uint32_t start_addr: 16; /*!< Start address (CAN Message Buffer Offset) */
330 uint32_t fifo_size: 8; /*!< FIFO element count */
331 uint32_t watermark: 7; /*!< FIFO watermark */
332 uint32_t operation_mode: 1; /*!< Operation mode */
333 };
334 uint32_t reg_val; /*!< Register value */
335 } mcan_rxfifo_config_t;
336
337 /**
338 * @brief MCAN RXBUF Configuration
339 */
340 typedef struct {
341 uint32_t start_addr; /*!< Start address (CAN Message Buffer Offset) */
342 } mcan_rxbuf_config_t;
343
344 /**
345 * @brief MCAN Data Field Size Definitions
346 */
347 #define MCAN_DATA_FIELD_SIZE_8BYTES (0U)
348 #define MCAN_DATA_FIELD_SIZE_12BYTES (1U)
349 #define MCAN_DATA_FIELD_SIZE_16BYTES (2U)
350 #define MCAN_DATA_FIELD_SIZE_20BYTES (3U)
351 #define MCAN_DATA_FIELD_SIZE_24BYTES (4U)
352 #define MCAN_DATA_FIELD_SIZE_32BYTES (5U)
353 #define MCAN_DATA_FIELD_SIZE_48BYTES (6U)
354 #define MCAN_DATA_FIELD_SIZE_64BYTES (7U)
355
356 /**
357 * @brief MCAN FIFO Operation Mode types
358 */
359 #define MCAN_FIFO_OPERATION_MODE_BLOCKING (0U)
360 #define MCAN_FIFO_OPERATION_MODE_OVERWRITE (1U)
361
362 /**
363 * @brief MCAN RXBUF or RXFIFO Element Configuration
364 */
365 typedef union mcan_rx_fifo_or_buf_elem_config_struct {
366 struct {
367 uint32_t fifo0_data_field_size: 4; /*!< FIFO0 data field size option */
368 uint32_t fifo1_data_field_size: 4; /*!< FIFO1 data field size option */
369 uint32_t buf_data_field_size: 4; /*!< Buffer Data field size option */
370 uint32_t : 20;
371 };
372 uint32_t reg_val; /*!< Register value */
373 } mcan_rx_fifo_or_buf_elem_config_t;
374
375 /**
376 * @brief MCAN TXBUF operation mode types
377 */
378 #define MCAN_TXBUF_OPERATION_MODE_FIFO (0U)
379 #define MCAN_TXBUF_OPERATION_MODE_QUEUE (1U)
380
381
382 typedef union mcan_txbuf_config_struct {
383 struct {
384 uint32_t start_addr: 16; /*!< Start address (CAN Message Buffer Offset) */
385 uint32_t dedicated_tx_buf_size: 6; /*!< Dedicated TX buffer size */
386 uint32_t : 2;
387 uint32_t fifo_queue_size: 6; /*!< FIFO or Queue Size */
388 uint32_t tx_fifo_queue_mode: 1; /*!< FIFO or Queue mode selection */
389 uint32_t : 1;
390 };
391 uint32_t reg_val; /*!< register value */
392 } mcan_txbuf_config_t;
393
394 typedef struct mcan_txbuf_elem_config_struct {
395 uint32_t data_field_size; /*!< Data Field size option */
396 } mcan_txbuf_elem_config_t;
397
398 /**
399 * @brief MCAN TX Event FIFO Structure
400 */
401 typedef union {
402 struct {
403 uint16_t start_addr; /*!< Start Address(CAN Message Buffer Offset */
404 uint8_t fifo_size; /*!< FIFO element count */
405 uint8_t fifo_watermark; /*!< FIFO watermark */
406 };
407 uint32_t reg_val; /*!< register value */
408 } mcan_tx_evt_fifo_config_t;
409
410 /**
411 * @brief MCAN RAM Flexible Configuration
412 *
413 * @Note This Configuration provides the full MCAN RAM configuration, this configuration is recommended only for
414 * experienced developers who is skilled at the MCAN IP
415 */
416 typedef struct mcan_ram_flexible_config_struct {
417 bool enable_std_filter; /*!< Enable Standard Identifier Filter */
418 bool enable_ext_filter; /*!< Enable Extended Identifier Filter */
419 bool enable_rxfifo0; /*!< Enable RXFIFO */
420 bool enable_rxfifo1; /*!< Enable RXFIF1 */
421 bool enable_rxbuf; /*!< Enable RXBUF */
422 bool enable_txbuf; /*!< Enable TXBUF */
423 bool enable_tx_evt_fifo; /*!< Enable TX Event FIFO */
424
425 mcan_filter_config_t std_filter_config; /*!< Standard Identifier Filter Configuration */
426 mcan_filter_config_t ext_filter_config; /*!< Extended Identifier Filter Configuration */
427
428 mcan_txbuf_config_t txbuf_config; /*!< TXBUF Configuration */
429 mcan_txbuf_elem_config_t txbuf_elem_config; /*!< TXBUF Element Configuration */
430 mcan_tx_evt_fifo_config_t tx_evt_fifo_config; /*!< TX Event FIFO Configuration */
431
432 mcan_rxfifo_config_t rxfifo0_config; /*!< RXFIFO0 Configuration */
433 mcan_rxfifo_config_t rxfifo1_config; /*!< RXFIFO1 Configuration */
434 mcan_rxbuf_config_t rxbuf_config; /*!< RXBUF Configuration */
435 mcan_rx_fifo_or_buf_elem_config_t rx_elem_config; /*!< RX Element Configuration */
436 } mcan_ram_flexible_config_t;
437
438 /**
439 * @brief MCAN RAM configuration
440 *
441 * @Note: This Configuration focuses on the minimum required information for MCAN RAM configuration
442 * The Start address of each BUF/FIFO will be automatically calculated by the MCAN Driver API
443 * This RAM configuration is recommended for the most developers
444 */
445 typedef struct mcan_ram_config_struct {
446 bool enable_std_filter; /*!< Enable Standard Identifier Filter */
447 uint8_t std_filter_elem_count; /*!< Standard Identifier Filter Element Count */
448
449 bool enable_ext_filter; /*!< Enable Extended Identifier Filter */
450 uint8_t ext_filter_elem_count; /*!< Extended Identifier Filter Element Count */
451
452 struct {
453 uint32_t enable: 4; /*!< Enable Flag for RXFIFO */
454 uint32_t elem_count: 8; /*!< Element Count for RXFIFO */
455 uint32_t watermark: 8; /*!< Watermark for RXFIFO */
456 uint32_t operation_mode: 4; /*!< Operation Mode for RXFIFO */
457 uint32_t data_field_size: 8; /*!< Data field size option for RXFIFO */
458 } rxfifos[2];
459
460 bool enable_rxbuf; /*!< Enable RXBUF */
461 uint8_t rxbuf_elem_count; /*!< RXBUF Element count */
462 uint16_t rxbuf_data_field_size; /*!< RXBUF Data Field Size option */
463
464 bool enable_txbuf; /*!< Enable TXBUF */
465 uint8_t txbuf_data_field_size; /*!< TXBUF Data Field Size option */
466 uint8_t txbuf_dedicated_txbuf_elem_count; /*!< Dedicated TXBUF element count */
467 uint8_t txbuf_fifo_or_queue_elem_count; /*!< FIFO/Queue element count */
468 uint8_t txfifo_or_txqueue_mode; /*!< TXFIFO/QUEUE mode */
469
470 bool enable_tx_evt_fifo; /*!< Enable TX Event FIFO */
471 uint8_t tx_evt_fifo_elem_count; /*!< TX Event FIFO Element count */
472 uint8_t tx_evt_fifo_watermark; /*!< TX Event FIFO Watermark */
473 } mcan_ram_config_t;
474
475 /**
476 * @brief MCAN Accept Non-Matching Frame options
477 */
478 #define MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0 (0U) /*!< Save non-matching frame to RXFIFO0 */
479 #define MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO1 (1U) /*!< Save non-matching frame to RXFIFO1 */
480 #define MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_REJECT (2U) /*!< Reject non-matching frame */
481
482 /**
483 * @brief MCAN Global CAN configuration
484 */
485 typedef struct mcan_global_filter_config_struct {
486 uint8_t accept_non_matching_std_frame_option; /*!< Accept non-matching standard frame option */
487 uint8_t accept_non_matching_ext_frame_option; /*!< Accept non-matching extended frame option */
488 bool reject_remote_std_frame; /*!< Reject Remote Standard Frame */
489 bool reject_remote_ext_frame; /*!< Reject Remote Extended Frame */
490 } mcan_global_filter_config_t;
491
492 /**
493 * @brief MCAN Filter type definitions
494 */
495 #define MCAN_FILTER_TYPE_RANGE_FILTER (0U) /*!< CAN Identifier Range filter */
496 #define MCAN_FILTER_TYPE_SPECIFIED_ID_FILTER (1U) /*!< CAN Identifier ID filter */
497 #define MCAN_FILTER_TYPE_CLASSIC_FILTER (2U) /*!< CAN classic filter */
498 #define MCAN_FILTER_TYPE_FILTER_DISABLED (3U) /*!< CAN filter disabled */
499 #define MCAN_FILTER_TYPE_DUAL_ID_EXT_FILTER_IGNORE_MASK /*!< CAN Identifier Range filter, ignoring extended ID mask */
500
501 /**
502 * @brief MCAN Filter Configuration Options
503 */
504 #define MCAN_FILTER_ELEM_CFG_DISABLED (0) /*!< Disable Filter Element */
505 #define MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH (1U) /*!< Store data into RXFIFO0 if matching */
506 #define MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO1_IF_MATCH (2U) /*!< Store data into RXFIFO1 if matching */
507 #define MCAN_FILTER_ELEM_CFG_REJECT_ID_IF_MATCH (3U) /*!< Reject ID if matching */
508 #define MCAN_FILTER_ELEM_CFG_SET_PRIORITY_IF_MATCH (4U) /*!< Set Priority if matching */
509 /*!< Set Priority and store into RXFIFO0 if matching */
510 #define MCAN_FILTER_ELEM_CFG_SET_PRIORITY_AND_STORE_IN_FIFO0_IF_MATCH (5U)
511 /*!< Set Priority and store into RXFIFO1 if matching */
512 #define MCAN_FILTER_ELEM_CFG_SET_PRIORITY_AND_STORE_IN_FIFO1_IF_MATCH (6U)
513 #define MCAN_FILTER_ELEM_CFG_STORE_INTO_RX_BUFFER_OR_AS_DBG_MSG (7U) /*!< Store into RXBUF if matching */
514
515 /**
516 * @brief MCAN Filter Element definitions
517 */
518 typedef struct mcan_std_id_filter_elem_struct {
519 uint8_t filter_type; /*!< Filter type */
520 uint8_t filter_config; /*!< Filter configuration */
521 uint8_t can_id_type; /*!< CAN ID type */
522 uint8_t sync_message; /*!< Sync Message */
523 union {
524 /* This definition takes effect if the filter type is range filter */
525 struct {
526 uint32_t start_id; /*!< Start of ID range */
527 uint32_t end_id; /*!< End of ID range */
528 };
529 /* This definition takes effect if the filter type is dual id filter */
530 struct {
531 uint32_t id1; /*!< ID1 */
532 uint32_t id2; /*!< ID2 */
533 };
534 /* This definition takes effect if the filter type is classic filter */
535 struct {
536 uint32_t filter_id; /*!< Filter ID */
537 uint32_t filter_mask; /*!< Filter Mask */
538 };
539 /* This definition takes effect if the filter configuration is "store into RX Buffer or as debug message"
540 *
541 * In this definition, only the exact ID matching mode is activated
542 */
543 struct {
544 uint32_t match_id; /*!< Matching ID */
545 uint32_t offset: 6; /*!< RX Buffer Index */
546 uint32_t filter_event: 3; /*!< Filter event, set to 0 */
547 uint32_t store_location: 2; /*!< Store location, 0 - RX buffer */
548 uint32_t : 21;
549 };
550 };
551 } mcan_filter_elem_t;
552
553 /**
554 * @brief MCAN Filter Element List structure
555 */
556 typedef struct mcan_filter_elem_list_struct {
557 uint32_t mcan_filter_elem_count; /*!< Number of Filter element */
558 const mcan_filter_elem_t *filter_elem_list; /*!< Filter element list */
559 } mcan_filter_elem_list_t;
560
561 /**
562 * @brief MCAN Configuration for all filters
563 *
564 * @Note The MCAN RAM related settings are excluded
565 */
566 typedef struct mcan_all_filters_config_struct {
567 mcan_global_filter_config_t global_filter_config; /*!< Global Filter configuration */
568 uint32_t ext_id_mask; /*!< Extended ID mask */
569 mcan_filter_elem_list_t std_id_filter_list; /*!< Standard Identifier Configuration List */
570 mcan_filter_elem_list_t ext_id_filter_list; /*!< Extended Identifier Configuration List */
571 } mcan_all_filters_config_t;
572
573 /**
574 * @brief CAN Node Mode types
575 */
576 typedef enum mcan_node_mode_enum {
577 mcan_mode_normal = 0, /*!< CAN works in normal mode */
578 mcan_mode_loopback_internal = 1, /*!< CAN works in internal loopback mode */
579 mcan_mode_loopback_external = 2, /*!< CAN works in external loopback mode */
580 mcan_mode_listen_only = 3, /*!< CAN works in listen-only mode */
581 } mcan_node_mode_t;
582
583 /**
584 * @brief MCAN Timestamp Value
585 */
586 typedef struct mcan_timestamp_value_struct {
587 bool is_16bit; /*!< Timestamp is 16-bit */
588 bool is_32bit; /*!< Timestamp is 32-bit */
589 bool is_64bit; /*!< Timestamp is 64-bit */
590 bool is_empty; /*!< Timestamp is empty */
591 union {
592 uint16_t ts_16bit; /*!< 16-bit timestamp value */
593 uint32_t ts_32bit; /*!< 32-bit timestamp value */
594 uint64_t ts_64bit; /*!< 64-bit timestamp value */
595 uint32_t words[2]; /*!< timestamp words */
596 };
597 } mcan_timestamp_value_t;
598
599 /**
600 * @brief MCAN TSU Configuration
601 */
602 typedef struct mcan_tsu_config_struct {
603 uint16_t prescaler; /*!< Prescaler for MCAN clock, Clock source: AHB clock */
604 bool capture_on_sof; /*!< Capture On SOF, true - Capture on SOF, false - Capture on EOF */
605 bool use_ext_timebase; /*!< Use External Timebase */
606 uint8_t ext_timebase_src; /*!< External Timebase source, see the hpm_mcan_soc.h for more details */
607 uint8_t tbsel_option; /*!< Timebase selection option, see the hpm_mcan_soc.h for more details */
608 bool enable_tsu; /*!< Enable Timestamp Unit */
609 bool enable_64bit_timestamp; /*!< Enable 64bit Timestamp */
610 } mcan_tsu_config_t;
611
612 /**
613 * @brief MCAN Timestamp Select
614 */
615 #define MCAN_TIMESTAMP_SEL_MIN (0U)
616 #define MCAN_TIMESTAMP_SEL_VALUE_ALWAYS_ZERO (0U) /*!< Timestamp value always equal to 0 */
617 #define MCAN_TIMESTAMP_SEL_VALUE_INCREMENT (1U) /*!< Timestamp value increments according to prescaler */
618 #define MCAN_TIMESTAMP_SEL_EXT_TS_VAL_USED (2U) /*!< External Timestamp value used */
619 #define MCAN_TIMESTAMP_SEL_MAX (MCAN_TIMESTAMP_SEL_EXT_TS_VAL_USED)
620
621 /**
622 * @brief MCAN Internal timestamp configuration
623 */
624 typedef struct mcan_internal_timestamp_config_struct {
625 uint8_t counter_prescaler; /*!< Timestamp Counter Prescaler, clock source: AHB clock */
626 uint8_t timestamp_selection; /*!< Timestamp Select */
627 } mcan_internal_timestamp_config_t;
628
629 /**
630 * @brief MCAN Configuration Structure
631 */
632 typedef struct mcan_config_struct {
633 union {
634 /* This struct takes effect if use_lowlevl_timing_setting = false */
635 struct {
636 uint32_t baudrate; /*!< CAN 2.0 baudrate/CAN-FD Nominal Baudrate, in terms of bps */
637 uint32_t baudrate_fd; /*!< CANFD data baudrate, in terms of bps */
638 uint16_t can20_samplepoint_min; /*!< Value = Minimum CAN2.0 sample point * 10 */
639 uint16_t can20_samplepoint_max; /*!< Value = Maximum CAN2.0 sample point * 10 */
640 uint16_t canfd_samplepoint_min; /*!< Value = Minimum CANFD sample point * 10 */
641 uint16_t canfd_samplepoint_max; /*!< Value = Maximum CANFD sample point * 10 */
642 };
643 /* This struct takes effect if use_lowlevl_timing_setting = true */
644 struct {
645 mcan_bit_timing_param_t can_timing; /*!< CAN2.0/CANFD nominal timing setting */
646 mcan_bit_timing_param_t canfd_timing; /*!< CANFD data timing setting */
647 };
648 };
649 bool use_lowlevel_timing_setting; /*!< Use Low-level timing setting */
650 mcan_node_mode_t mode; /*!< CAN node mode */
651 bool enable_non_iso_mode; /*!< Enable Non-ISO FD mode */
652 bool enable_transmit_pause; /*!< Enable Transmit Pause */
653 bool enable_edge_filtering; /*!< Enable Edge Filtering */
654 bool disable_protocol_exception_handling; /*!< Disable Protocol Exception Handling */
655 bool enable_wide_message_marker; /*!< Enable Wide Message Marker */
656 bool use_timestamping_unit; /*!< Use external Timestamp Unit */
657 bool enable_canfd; /*!< Enable CANFD mode */
658 bool enable_tdc; /*!< Enable transmitter delay compensation */
659 bool enable_restricted_operation_mode; /*!< Enable Resricted Operation Mode: Receive only */
660 bool disable_auto_retransmission; /*!< Disable auto retransmission */
661 uint8_t padding[2];
662 mcan_internal_timestamp_config_t timestamp_cfg; /*!< Internal Timestamp Configuration */
663 mcan_tsu_config_t tsu_config; /*!< TSU configuration */
664 mcan_ram_config_t ram_config; /*!< MCAN RAM configuration */
665 mcan_all_filters_config_t all_filters_config; /*!< All Filter configuration */
666
667 uint32_t interrupt_mask; /*!< Interrupt Enable mask */
668 uint32_t txbuf_trans_interrupt_mask; /*!< Tx Buffer Transmission Interrupt Enable mask */
669 uint32_t txbuf_cancel_finish_interrupt_mask; /*!< TX Buffer Cancellation Finished Interrupt Enable Mask */
670 } mcan_config_t;
671
672 /**
673 * @brief MCAN Timeout Selection Options
674 */
675 #define MCAN_TIMEOUT_SEL_TYPE_CONTINUOUS_OPERATION (0U)
676 #define MCAN_TIMEOUT_SEL_TYPE_TIMEOUT_CTRL_BY_TX_EVT_FIFO (1U)
677 #define MCAN_TIMEOUT_SEL_TYPE_TIMEOUT_CTRL_BY_RX_FIFO0 (2U)
678 #define MCAN_TIMEOUT_SEL_TYPE_TIMEOUT_CTRL_BY_RX_FIFO1 (3U)
679
680 /**
681 * @brief MCAN Timeout Counter Configuration
682 */
683 typedef struct mcan_timeout_counter_config_struct {
684 bool enable_timeout_counter; /*!< Enable Timeout counter */
685 uint8_t timeout_selection; /*!< Timeout source selection */
686 uint16_t timeout_period; /*!< Timeout period */
687 } mcan_timeout_counter_config_t;
688
689 /**
690 * @brief MCAN Error Count Information
691 */
692 typedef struct mcan_error_count_struct {
693 uint8_t transmit_error_count; /*!< Transmit Error Count */
694 uint8_t receive_error_count; /*!< Receive Error Count */
695 bool receive_error_passive; /*!< The Receive Error Counter has reached the error passive level */
696 uint8_t can_error_logging_count; /*!< CAN Error Logging count */
697 } mcan_error_count_t;
698
699 /**
700 * @brief MCAN Protocol Status
701 */
702 typedef struct mcan_protocol_status {
703 uint8_t tdc_val; /*!< Transmitter Delay Compensation Value */
704 mcan_activity_state_t activity; /*!< Current communication state */
705 mcan_last_err_code_t last_error_code; /*!< Last Error code */
706 bool protocol_exception_evt_occurred; /*!< Protocol Exception Event occurred */
707 bool canfd_msg_received; /*!< CANFD message was received */
708 bool brs_flag_set_in_last_rcv_canfd_msg; /*!< Bitrate Switch bit is set in last received CANFD message */
709 bool esi_flag_set_in_last_rcv_canfd_msg; /*!< Error State Indicator bit is set in last received CANFD message */
710 bool in_bus_off_state; /*!< Node is in bus-off state */
711 bool in_warning_state; /*!< Node is in warning state */
712 bool in_error_passive_state; /*!< Node is in error passive state */
713 } mcan_protocol_status_t;
714
715 /**
716 * @brief MCAN Transmitter Delay Compensation Configuration
717 */
718 typedef struct mcan_tdc_config_t {
719 uint8_t ssp_offset; /*!< SSP offset */
720 uint8_t filter_window_length; /*!< Filter Window Length */
721 } mcan_tdc_config_t;
722
723
724 /**
725 * @brief MCAN Message Storage Indicator Types
726 */
727 #define MCAN_MESSAGE_STORAGE_INDICATOR_NO_FIFO_SELECTED (0U)
728 #define MCAN_MESSAGE_STORAGE_INDICATOR_FIFO_MESSAGE_LOST (1U)
729 #define MCAN_MESSAGE_STORAGE_INDICATOR_RXFIFO0 (2U)
730 #define MCAN_MESSAGE_STORAGE_INDICATOR_RXFIFO1 (3U)
731
732 /**
733 * @brief MCAN High Priority Message Status Information
734 */
735 typedef struct mcan_high_priority_message_status_struct {
736 uint8_t filter_list_type; /*!< Filter List Type, 0 - STD filter, 1 - EXT filter */
737 uint8_t filter_index; /*!< Filter Elem List */
738 uint8_t message_storage_indicator; /*!< Message Storage Indicator */
739 uint8_t buffer_index;
740 } mcan_high_priority_message_status_t;
741
742 /**
743 * @brief Enable Transmit Pause
744 * @param [in] ptr MCAN base
745 */
mcan_enable_transmit_pause(MCAN_Type * ptr)746 static inline void mcan_enable_transmit_pause(MCAN_Type *ptr)
747 {
748 ptr->CCCR |= MCAN_CCCR_TXP_MASK;
749 }
750
751 /**
752 * @brief Disable Transmit Pause
753 * @param [in] ptr MCAN base
754 */
mcan_disable_transmit_pause(MCAN_Type * ptr)755 static inline void mcan_disable_transmit_pause(MCAN_Type *ptr)
756 {
757 ptr->CCCR &= ~MCAN_CCCR_TXP_MASK;
758 }
759
760 /**
761 * @brief Enable Edge Filtering
762 * @param [in] ptr MCAN base
763 */
mcan_enable_edge_filtering(MCAN_Type * ptr)764 static inline void mcan_enable_edge_filtering(MCAN_Type *ptr)
765 {
766 ptr->CCCR |= MCAN_CCCR_EFBI_MASK;
767 }
768
769 /**
770 * @brief Disable Edge Filtering
771 * @param [in] ptr MCAN base
772 */
mcan_disable_edge_filtering(MCAN_Type * ptr)773 static inline void mcan_disable_edge_filtering(MCAN_Type *ptr)
774 {
775 ptr->CCCR &= ~MCAN_CCCR_EFBI_MASK;
776 }
777
778 /**
779 * @brief Enable Protocol Exception Handling
780 * @param [in] ptr MCAN base
781 */
mcan_enable_protocol_exception_handling(MCAN_Type * ptr)782 static inline void mcan_enable_protocol_exception_handling(MCAN_Type *ptr)
783 {
784 ptr->CCCR &= ~MCAN_CCCR_PXHD_MASK;
785 }
786
787 /**
788 * @brief Disable Protocol Exception Handling
789 * @param [in] ptr MCAN base
790 */
mcan_disable_protocol_exception_handling(MCAN_Type * ptr)791 static inline void mcan_disable_protocol_exception_handling(MCAN_Type *ptr)
792 {
793 ptr->CCCR |= MCAN_CCCR_PXHD_MASK;
794 }
795
796 /**
797 * @brief Enable Wide Message Marker
798 * @param [in] ptr MCAN base
799 */
mcan_enable_wide_message_marker(MCAN_Type * ptr)800 static inline void mcan_enable_wide_message_marker(MCAN_Type *ptr)
801 {
802 ptr->CCCR |= MCAN_CCCR_WMM_MASK;
803 }
804
805 /**
806 * @brief Disable Wide Message Marker
807 * @param [in] ptr MCAN base
808 */
mcan_disable_wide_message_marker(MCAN_Type * ptr)809 static inline void mcan_disable_wide_message_marker(MCAN_Type *ptr)
810 {
811 ptr->CCCR &= ~MCAN_CCCR_WMM_MASK;
812 }
813
814 /**
815 * @brief Enable External Timestamp Unit
816 * @param [in] ptr MCAN base
817 */
mcan_enable_tsu(MCAN_Type * ptr)818 static inline void mcan_enable_tsu(MCAN_Type *ptr)
819 {
820 ptr->CCCR |= MCAN_CCCR_UTSU_MASK;
821 }
822
823 /**
824 * @brief Disable External Timestamp Unit
825 * @param [in] ptr MCAN base
826 */
mcan_disable_tsu(MCAN_Type * ptr)827 static inline void mcan_disable_tsu(MCAN_Type *ptr)
828 {
829 ptr->CCCR &= ~MCAN_CCCR_UTSU_MASK;
830 }
831
832 /**
833 * @brief Check whether TSU is used
834 * @param [in] ptr MCAN base
835 * @retval true if TSU is used
836 * @retval false if TSU is not used
837 */
mcan_is_tsu_used(MCAN_Type * ptr)838 static inline bool mcan_is_tsu_used(MCAN_Type *ptr)
839 {
840 return ((ptr->CCCR & MCAN_CCCR_UTSU_MASK) != 0U);
841 }
842
843 /**
844 * @brief Check whether 64-bit TSU timestamp is used
845 * @param [in] ptr MCAN base
846 * @retval true if 64-bit timestamp is used
847 * @retval false if 32-bit timestamp is used
848 */
mcan_is_64bit_tsu_timestamp_used(MCAN_Type * ptr)849 static inline bool mcan_is_64bit_tsu_timestamp_used(MCAN_Type *ptr)
850 {
851 return ((ptr->TSCFG & MCAN_TSCFG_EN64_MASK) != 0U);
852 }
853
854 /**
855 * @brief Enable Bit Rate Switch
856 * @param [in] ptr MCAN base
857 */
mcan_enable_bitrate_switch(MCAN_Type * ptr)858 static inline void mcan_enable_bitrate_switch(MCAN_Type *ptr)
859 {
860 ptr->CCCR |= MCAN_CCCR_BRSE_MASK;
861 }
862
863 /**
864 * @brief Disable Bit Rate Switch
865 * @param [in] ptr MCAN base
866 */
mcan_disable_bitrate_switch(MCAN_Type * ptr)867 static inline void mcan_disable_bitrate_switch(MCAN_Type *ptr)
868 {
869 ptr->CCCR &= ~MCAN_CCCR_BRSE_MASK;
870 }
871
872 /**
873 * @brief Enable Auto Retransmission
874 * @param [in] ptr MCAN base
875 */
mcan_enable_auto_retransmission(MCAN_Type * ptr)876 static inline void mcan_enable_auto_retransmission(MCAN_Type *ptr)
877 {
878 ptr->CCCR &= ~MCAN_CCCR_DAR_MASK;
879 }
880
881 /**
882 * @brief Disable Auto Transmission
883 * @param [in] ptr MCAN base
884 */
mcan_disable_auto_retransmission(MCAN_Type * ptr)885 static inline void mcan_disable_auto_retransmission(MCAN_Type *ptr)
886 {
887 ptr->CCCR |= MCAN_CCCR_DAR_MASK;
888 }
889
890 /**
891 * @brief Enable Bus monitoring Mode
892 * @param [in] ptr MCAN base
893 */
mcan_enable_bus_monitoring_mode(MCAN_Type * ptr)894 static inline void mcan_enable_bus_monitoring_mode(MCAN_Type *ptr)
895 {
896 ptr->CCCR |= MCAN_CCCR_MON_MASK;
897 }
898
899 /**
900 * @brief Stop MCAN clock
901 * @param [in] ptr MCAN base
902 */
mcan_stop_clock(MCAN_Type * ptr)903 static inline void mcan_stop_clock(MCAN_Type *ptr)
904 {
905 ptr->CCCR |= MCAN_CCCR_CSR_MASK;
906 }
907
908 /**
909 * @brief Enable MCAN clock
910 * @param [in] ptr MCAN base
911 */
mcan_enable_clock(MCAN_Type * ptr)912 static inline void mcan_enable_clock(MCAN_Type *ptr)
913 {
914 ptr->CCCR &= ~MCAN_CCCR_CSR_MASK;
915 }
916
mcan_is_clock_enabled(MCAN_Type * ptr)917 static inline bool mcan_is_clock_enabled(MCAN_Type *ptr)
918 {
919 return ((ptr->CCCR & MCAN_CCCR_CSR_MASK) == 0UL);
920 }
921
922 /**
923 * @brief Disable Bus monitoring Mode
924 * @param [in] ptr MCAN base
925 */
mcan_disable_bus_monitoring_mode(MCAN_Type * ptr)926 static inline void mcan_disable_bus_monitoring_mode(MCAN_Type *ptr)
927 {
928 ptr->CCCR &= ~MCAN_CCCR_MON_MASK;
929 }
930
931 /**
932 * @brief Check whether CAN clock is stopped or not
933 * @param [in] ptr MCAN base
934 */
mcan_is_clock_stopped(MCAN_Type * ptr)935 static inline bool mcan_is_clock_stopped(MCAN_Type *ptr)
936 {
937 return ((ptr->CCCR & MCAN_CCCR_CSA_MASK) != 0U);
938 }
939
940 /**
941 * @brief Enable Restricted Operation Mode
942 * @param [in] ptr MCAN base
943 */
mcan_enable_restricted_operation_mode(MCAN_Type * ptr)944 static inline void mcan_enable_restricted_operation_mode(MCAN_Type *ptr)
945 {
946 ptr->CCCR |= MCAN_CCCR_ASM_MASK;
947 }
948
949 /**
950 * @brief Disable Restricted Operation Mode
951 * @param [in] ptr MCAN base
952 */
mcan_disable_restricted_operation_mode(MCAN_Type * ptr)953 static inline void mcan_disable_restricted_operation_mode(MCAN_Type *ptr)
954 {
955 ptr->CCCR &= ~MCAN_CCCR_ASM_MASK;
956 }
957
958 /**
959 * @brief Enable Write Access to Protected Configuration Registers
960 * @param [in] ptr MCAN base
961 */
mcan_enable_write_to_prot_config_registers(MCAN_Type * ptr)962 static inline void mcan_enable_write_to_prot_config_registers(MCAN_Type *ptr)
963 {
964 ptr->CCCR |= MCAN_CCCR_CCE_MASK;
965 }
966
967 /**
968 * @brief Disalbe Write Access to Protected Configuration Registers
969 * @param [in] ptr MCAN base
970 */
mcan_disable_write_to_prot_config_registers(MCAN_Type * ptr)971 static inline void mcan_disable_write_to_prot_config_registers(MCAN_Type *ptr)
972 {
973 ptr->CCCR &= ~MCAN_CCCR_CCE_MASK;
974 }
975
976 /**
977 * @brief Get Timestamp Counter Value
978 * @param [in] ptr MCAN base
979 * @return timestamp value
980 */
mcan_get_timestamp_counter_value(MCAN_Type * ptr)981 static inline uint16_t mcan_get_timestamp_counter_value(MCAN_Type *ptr)
982 {
983 return ptr->TSCV;
984 }
985
986 /**
987 * @brief Switch MCAN to Initialization mode
988 * @param [in] ptr MCAN base
989 */
mcan_enter_init_mode(MCAN_Type * ptr)990 static inline void mcan_enter_init_mode(MCAN_Type *ptr)
991 {
992 ptr->CCCR |= MCAN_CCCR_INIT_MASK;
993 }
994
995 /**
996 * @brief Switch MCAN to Normal mode
997 * @param [in] ptr MCAN base
998 */
mcan_enter_normal_mode(MCAN_Type * ptr)999 static inline void mcan_enter_normal_mode(MCAN_Type *ptr)
1000 {
1001 ptr->CCCR &= ~MCAN_CCCR_INIT_MASK;
1002 }
1003
1004 /**
1005 * @brief Get Timeout value
1006 * @param [in] ptr MCAN base
1007 * @return timeout value
1008 */
mcan_get_timeout_counter_value(MCAN_Type * ptr)1009 static inline uint16_t mcan_get_timeout_counter_value(MCAN_Type *ptr)
1010 {
1011 return ptr->TOCV;
1012 }
1013
1014 /**
1015 * @brief Get Error Counter Information
1016 * @param [in] ptr MCAN base
1017 * @param [out] err_cnt Error Count buffer
1018 */
mcan_get_error_counter(MCAN_Type * ptr,mcan_error_count_t * err_cnt)1019 static inline void mcan_get_error_counter(MCAN_Type *ptr, mcan_error_count_t *err_cnt)
1020 {
1021 uint32_t ecr = ptr->ECR;
1022 err_cnt->transmit_error_count = MCAN_ECR_TEC_GET(ecr);
1023 err_cnt->receive_error_count = MCAN_ECR_REC_GET(ecr);
1024 err_cnt->receive_error_passive = (MCAN_ECR_RP_GET(ecr) == 1U);
1025 err_cnt->can_error_logging_count = MCAN_ECR_CEL_GET(ecr);
1026 }
1027
1028 /**
1029 * @brief Get Last Error Code
1030 * @param [in] ptr MCAN base
1031 * @return Last Error code
1032 */
mcan_get_last_error_code(MCAN_Type * ptr)1033 static inline uint8_t mcan_get_last_error_code(MCAN_Type *ptr)
1034 {
1035 return MCAN_PSR_LEC_GET(ptr->PSR);
1036 }
1037
1038 /**
1039 * @brief Get Last Data Phase Error Code
1040 * @param [in] ptr MCAN base
1041 * @return Last Error Code in Data phase
1042 */
mcan_get_last_data_error_code(MCAN_Type * ptr)1043 static inline uint8_t mcan_get_last_data_error_code(MCAN_Type *ptr)
1044 {
1045 return MCAN_PSR_DLEC_GET(ptr->PSR);
1046 }
1047
1048 /**
1049 * @brief Get CAN Activity
1050 * @param [in] ptr MCAN base
1051 * @return CAN IP activity
1052 */
mcan_get_activity(MCAN_Type * ptr)1053 static inline uint8_t mcan_get_activity(MCAN_Type *ptr)
1054 {
1055 return MCAN_PSR_ACT_GET(ptr->PSR);
1056 }
1057
1058 /**
1059 * @brief Check whether the CAN node is under error passive state
1060 * @param [in] ptr MCAN base
1061 * @return true is CAN is under error passive state
1062 */
mcan_is_in_err_passive_state(MCAN_Type * ptr)1063 static inline bool mcan_is_in_err_passive_state(MCAN_Type *ptr)
1064 {
1065 return (MCAN_PSR_EP_GET(ptr->PSR) == 1U);
1066 }
1067
1068 /**
1069 * @brief Check whether the CAN mode is under Warning State
1070 * @param [in] ptr MCAN base
1071 * @return true if the CAN node is under Error Warning State
1072 */
mcan_is_in_error_warning_state(MCAN_Type * ptr)1073 static inline bool mcan_is_in_error_warning_state(MCAN_Type *ptr)
1074 {
1075 return (MCAN_PSR_EW_GET(ptr->PSR) == 1U);
1076 }
1077
1078 /**
1079 * @brief Check whether the CAN node is under Bus-off state
1080 * @param [in] ptr MCAN base
1081 * @return true if the CAN node is under Bus-off state
1082 */
mcan_is_in_busoff_state(MCAN_Type * ptr)1083 static inline bool mcan_is_in_busoff_state(MCAN_Type *ptr)
1084 {
1085 return (MCAN_PSR_BO_GET(ptr->PSR) == 1U);
1086 }
1087
1088 /**
1089 * @brief Get the Last Data Phase Error
1090 * @param [in] ptr MCAN base
1091 * @deprecated This API will be removed in later SDK release
1092 * @return The last Data Phase Error
1093 */
mcan_get_data_phase_last_error_code(MCAN_Type * ptr)1094 static inline uint8_t mcan_get_data_phase_last_error_code(MCAN_Type *ptr)
1095 {
1096 return MCAN_PSR_DLEC_GET(ptr->PSR);
1097 }
1098
1099 /**
1100 * @brief Check Whether the Error Status Indicator Flag is set in the last received CANFD message
1101 * @param [in] ptr MCAN base
1102 * @return true if the Error Status Indicator Flag is set in the last received CANFD Message
1103 */
mcan_is_error_state_indicator_flag_set_in_last_received_canfd_msg(MCAN_Type * ptr)1104 static inline bool mcan_is_error_state_indicator_flag_set_in_last_received_canfd_msg(MCAN_Type *ptr)
1105 {
1106 return (MCAN_PSR_RESI_GET(ptr->PSR) == 1U);
1107 }
1108
1109 /**
1110 * @brief Check whether the Bitrate Switch Flag is set in the last received CANFD message
1111 * @param [in] ptr MCAN base
1112 * @return true if Bit rate switch flag is set in the last received CANFD message
1113 */
mcan_is_bitrate_switch_flag_set_in_last_received_canfd_msg(MCAN_Type * ptr)1114 static inline bool mcan_is_bitrate_switch_flag_set_in_last_received_canfd_msg(MCAN_Type *ptr)
1115 {
1116 return (MCAN_PSR_RBRS_GET(ptr->PSR) == 1U);
1117 }
1118
1119 /**
1120 * @brief Check whether CANFD messages were received
1121 * @param [in] ptr MCAN base
1122 * @return true if a CANFD message was received
1123 */
mcan_is_canfd_message_received(MCAN_Type * ptr)1124 static inline bool mcan_is_canfd_message_received(MCAN_Type *ptr)
1125 {
1126 return (MCAN_PSR_RFDF_GET(ptr->PSR) == 1U);
1127 }
1128
1129 /**
1130 * @brief Check whether Protocol Exception Events were occurred
1131 * @param [in] ptr MCAN base
1132 * @return true if Protocol Exception Events were occurred
1133 */
mcan_is_protocol_exception_event_occurred(MCAN_Type * ptr)1134 static inline bool mcan_is_protocol_exception_event_occurred(MCAN_Type *ptr)
1135 {
1136 return (MCAN_PSR_PXE_GET(ptr->PSR) == 1U);
1137 }
1138
1139 /**
1140 * @brief Get the Transmitter Delay Compensation Value
1141 * @param [in] ptr MCAN base
1142 * @return Transmitter Delay Compensation value
1143 */
mcan_get_transmitter_delay_compensation_value(MCAN_Type * ptr)1144 static inline uint8_t mcan_get_transmitter_delay_compensation_value(MCAN_Type *ptr)
1145 {
1146 return MCAN_PSR_TDCV_GET(ptr->PSR);
1147 }
1148
1149 /**
1150 * @brief Get Interrupt Flags
1151 * @param [in] ptr MCAN base
1152 * @return Interrupt Flags
1153 */
mcan_get_interrupt_flags(MCAN_Type * ptr)1154 static inline uint32_t mcan_get_interrupt_flags(MCAN_Type *ptr)
1155 {
1156 return ptr->IR;
1157 }
1158
1159 /**
1160 * @brief Clear Interrupt Flags
1161 * @param [in] ptr MCAN base
1162 * @param [in] mask Interrupt Mask
1163 */
mcan_clear_interrupt_flags(MCAN_Type * ptr,uint32_t mask)1164 static inline void mcan_clear_interrupt_flags(MCAN_Type *ptr, uint32_t mask)
1165 {
1166 ptr->IR = mask;
1167 }
1168
1169 /**
1170 * @brief Enable Interrupts
1171 * @param [in] ptr MCAN base
1172 * @param [in] mask Interrupt mask
1173 */
mcan_enable_interrupts(MCAN_Type * ptr,uint32_t mask)1174 static inline void mcan_enable_interrupts(MCAN_Type *ptr, uint32_t mask)
1175 {
1176 ptr->ILS &= ~mask;
1177 ptr->IE |= mask;
1178 ptr->ILE = 1U;
1179 }
1180
1181 /**
1182 * @brief Enable TXBUF Interrupt
1183 * @deprecated This API is deprecated, will be removed in later SDK release
1184 * @param [in] ptr MCAN base
1185 * @param [in] mask Interrupt mask
1186 */
mcan_enable_txbuf_interrupt(MCAN_Type * ptr,uint32_t mask)1187 static inline void mcan_enable_txbuf_interrupt(MCAN_Type *ptr, uint32_t mask)
1188 {
1189 ptr->TXBTIE |= mask;
1190 }
1191
1192 /**
1193 * @brief Disable TXBUF Interrupt
1194 * @deprecated This API is deprecated, will be removed in later SDK release
1195 * @param [in] ptr MCAN base
1196 * @param [in] mask Interrupt mask
1197 */
mcan_disable_txbuf_interrupt(MCAN_Type * ptr,uint32_t mask)1198 static inline void mcan_disable_txbuf_interrupt(MCAN_Type *ptr, uint32_t mask)
1199 {
1200 ptr->TXBTIE &= ~mask;
1201 }
1202
1203 /**
1204 * @brief Disable Interrupts
1205 * @param [in] ptr MCAN base
1206 * @param [in] mask Interrupt mask
1207 */
mcan_disable_interrupts(MCAN_Type * ptr,uint32_t mask)1208 static inline void mcan_disable_interrupts(MCAN_Type *ptr, uint32_t mask)
1209 {
1210 ptr->IE &= ~mask;
1211 }
1212
1213 /**
1214 * @brief Enable TXBUF Transmission interrupt
1215 * @param [in] ptr MCAN base
1216 * @param [in] mask Interrupt mask
1217 */
mcan_enable_txbuf_transmission_interrupt(MCAN_Type * ptr,uint32_t mask)1218 static inline void mcan_enable_txbuf_transmission_interrupt(MCAN_Type *ptr, uint32_t mask)
1219 {
1220 ptr->TXBTIE |= mask;
1221 }
1222
1223 /**
1224 * @brief Disable TXBUF Transmission interrupt
1225 * @param [in] ptr MCAN base
1226 * @param [in] mask Interrupt mask
1227 */
mcan_disable_txbuf_transmission_interrupt(MCAN_Type * ptr,uint32_t mask)1228 static inline void mcan_disable_txbuf_transmission_interrupt(MCAN_Type *ptr, uint32_t mask)
1229 {
1230 ptr->TXBTIE &= ~mask;
1231 }
1232
1233 /**
1234 * @brief Enable TXBUF Cancellation Finish interrupt
1235 * @param [in] ptr MCAN base
1236 * @param [in] mask Interrupt mask
1237 */
mcan_enable_txbuf_cancel_finish_interrupt(MCAN_Type * ptr,uint32_t mask)1238 static inline void mcan_enable_txbuf_cancel_finish_interrupt(MCAN_Type *ptr, uint32_t mask)
1239 {
1240 ptr->TXBCIE |= mask;
1241 }
1242
1243 /**
1244 * @brief Disable TXBUF Cancellation Finish interrupt
1245 * @param [in] ptr MCAN base
1246 * @param [in] mask Interrupt mask
1247 */
mcan_disable_txbuf_cancel_finish_interrupt(MCAN_Type * ptr,uint32_t mask)1248 static inline void mcan_disable_txbuf_cancel_finish_interrupt(MCAN_Type *ptr, uint32_t mask)
1249 {
1250 ptr->TXBCIE &= ~mask;
1251 }
1252
1253 /**
1254 * @brief Select Interrupt Line
1255 * @param [in] ptr MCAN base
1256 * @param [in] mask Interrupt mask
1257 * @param [in] line_index Interrupt Line Index
1258 */
mcan_interrupt_line_select(MCAN_Type * ptr,uint32_t mask,uint8_t line_index)1259 static inline void mcan_interrupt_line_select(MCAN_Type *ptr, uint32_t mask, uint8_t line_index)
1260 {
1261 if (line_index == 0) {
1262 ptr->ILS &= ~mask;
1263 } else {
1264 ptr->ILS |= mask;
1265 }
1266 ptr->ILE = (1UL << line_index);
1267 }
1268
1269 /**
1270 * @brief Check whether a TXFIFO/TXBUF transmission request is pending
1271 * @param [in] ptr CAN Base
1272 * @param [in] index TXBUF/TXFIFO Index
1273 * @return True is the specified TXFIFO/TXBUF Transmission request is pending
1274 */
mcan_is_transmit_request_pending(MCAN_Type * ptr,uint32_t index)1275 static inline bool mcan_is_transmit_request_pending(MCAN_Type *ptr, uint32_t index)
1276 {
1277 return ((ptr->TXBRP & ((1UL << index))) != 0U);
1278 }
1279
1280 /**
1281 * @brief Check whether TXFIFO is full
1282 * @param [in] ptr MCAN base
1283 * @return true if TXFIFO is full
1284 */
mcan_is_txfifo_full(MCAN_Type * ptr)1285 static inline bool mcan_is_txfifo_full(MCAN_Type *ptr)
1286 {
1287 return ((ptr->TXFQS & MCAN_TXFQS_TFQF_MASK) != 0U);
1288 }
1289
1290 /**
1291 * @brief Get the TXFIFO Put Index
1292 * @param [in] ptr MCAN base
1293 * @return The TX FIFO Put Index
1294 */
mcan_get_txfifo_put_index(MCAN_Type * ptr)1295 static inline uint32_t mcan_get_txfifo_put_index(MCAN_Type *ptr)
1296 {
1297 return MCAN_TXFQS_TFQPI_GET(ptr->TXFQS);
1298 }
1299
1300 /**
1301 * @brief Request A Transmission via specified TXBUF Index
1302 * @param [in] ptr MCAN Base
1303 * @param [in] index TXBUF index
1304 */
mcan_send_add_request(MCAN_Type * ptr,uint32_t index)1305 static inline void mcan_send_add_request(MCAN_Type *ptr, uint32_t index)
1306 {
1307 ptr->TXBAR = (1UL << index);
1308 }
1309
1310 /**
1311 * @brief Check whether the Transmission completed via specified TXBUF/TXFIFO
1312 * @param [in] ptr MCAN base
1313 * @param [in] index TXBUF Index
1314 * @return True is the Transmission completed via specified TXBUF
1315 */
mcan_is_transmit_occurred(MCAN_Type * ptr,uint32_t index)1316 static inline bool mcan_is_transmit_occurred(MCAN_Type *ptr, uint32_t index)
1317 {
1318 return ((ptr->TXBTO & (1UL << index)) != 0U);
1319 }
1320
1321 /**
1322 * @brief Check Whether there are data available in specified RXBUF
1323 * @param [in] ptr MCAN Base
1324 * @param [in] index RXBUF index
1325 * @return True if there are data available
1326 */
mcan_is_rxbuf_data_available(MCAN_Type * ptr,uint32_t index)1327 static inline bool mcan_is_rxbuf_data_available(MCAN_Type *ptr, uint32_t index)
1328 {
1329 bool result;
1330 if (index < 32U) {
1331 result = (ptr->NDAT1 & (1UL << index)) != 0U;
1332 } else if (index < 64U) {
1333 result = (ptr->NDAT2 & (1UL << (index - 32U))) != 0U;
1334 } else {
1335 result = false;
1336 }
1337 return result;
1338 }
1339
1340 /**
1341 * @brief Clear RXBUF Data available Flag for specified RXBUF
1342 * @param [in] ptr MCAN base
1343 * @param [in] index RXBUF index
1344 */
mcan_clear_rxbuf_data_available_flag(MCAN_Type * ptr,uint32_t index)1345 static inline void mcan_clear_rxbuf_data_available_flag(MCAN_Type *ptr, uint32_t index)
1346 {
1347 if (index < 32U) {
1348 ptr->NDAT1 = (1UL << index);
1349 } else if (index < 64U) {
1350 ptr->NDAT2 = (1UL << (index - 32U));
1351 } else {
1352 /* Do nothing */
1353 }
1354 }
1355
1356 /**
1357 * @brief Check whether specified Interrupt is set
1358 * @param [in] ptr MCAN Base
1359 * @param [in] mask Interrupt Flags
1360 * @retval true if corresponding bits are set
1361 */
mcan_is_interrupt_flag_set(MCAN_Type * ptr,uint32_t mask)1362 static inline bool mcan_is_interrupt_flag_set(MCAN_Type *ptr, uint32_t mask)
1363 {
1364 return ((ptr->IR & mask) != 0U);
1365 }
1366
1367 /**
1368 * @brief Check whether the TSU timestamp is available
1369 *
1370 * @param [in] ptr MCAN base
1371 * @param [in] index Timestamp pointer
1372 * @retval true TSU Timestamp is available
1373 * @retval false TSU timestamp is unavailable
1374 */
mcan_is_tsu_timestamp_available(MCAN_Type * ptr,uint32_t index)1375 static inline bool mcan_is_tsu_timestamp_available(MCAN_Type *ptr, uint32_t index)
1376 {
1377 bool is_available = false;
1378 if (index < ARRAY_SIZE(ptr->TS_SEL)) {
1379 is_available = ((ptr->TSS1 & (1UL << index)) != 0U);
1380 }
1381 return is_available;
1382 }
1383
1384 /**
1385 * @brief Read 32bit Timestamp value from TSU
1386 * @param [in] ptr MCAN Base
1387 * @param [in] index Timestamp pointer
1388 * @return Timestamp value
1389 */
1390 uint32_t mcan_read_32bit_tsu_timestamp(MCAN_Type *ptr, uint32_t index);
1391
1392 /**
1393 * @brief Read 64bit Timestamp value from TSU
1394 * @param [in] ptr MCAN Base
1395 * @param [in] index Timestamp pointer
1396 * @return Timestamp value
1397 */
1398 uint64_t mcan_read_64bit_tsu_timestamp(MCAN_Type *ptr, uint32_t index);
1399
1400 /**
1401 * @brief Get High Priority Message Status
1402 * @param [in] ptr MCAN base
1403 * @param [out] status Pointer to High Priority Message Status Buffer
1404 */
1405 void mcan_get_high_priority_message_status(MCAN_Type *ptr, mcan_high_priority_message_status_t *status);
1406
1407 /**
1408 * @brief Get Default CAN configuration
1409 * @param [in] ptr MCAN base
1410 * @param [out] config CAN configuration
1411 */
1412 void mcan_get_default_config(MCAN_Type *ptr, mcan_config_t *config);
1413
1414 /**
1415 * @brief Get message Size from Data Length Code
1416 * @param [in] dlc Data Length Code
1417 * @return Message Size in Bytes
1418 */
1419 uint8_t mcan_get_message_size_from_dlc(uint8_t dlc);
1420
1421 /**
1422 * @brief Get the Data field size from data field size option
1423 *
1424 * @param [in] data_field_size_option Data size option
1425 * @return data field size in bytes
1426 */
1427 uint8_t mcan_get_data_field_size(uint8_t data_field_size_option);
1428
1429 /**
1430 * @brief Get Default Full MCAN RAM configuration
1431 * If the device is configured as classic CAN node, the default CAN RAM settings are as below:
1432 * - Standard Identifier Filter Elements: 32
1433 * - Extended Identifier Filter Elements: 32
1434 * - TXBUF Elements Info:
1435 * - Element Count:32
1436 * - Dedicated TXBUF element count: 16
1437 * - TXFIFO/QQueue element count: 16
1438 * - Data Field Size: 8
1439 * - RXFIFO0 Elements Info:
1440 * - Element Count :32
1441 * - Data Field Size: 8
1442 * - RXFIFO1 Elements Info:
1443 * - Element Count : 32
1444 * - Data Field Size: 8
1445 * - RXBUF Element Info:
1446 * - Element Count: 16
1447 * - Data Field Size : 8
1448 * - TX Event FIFO Element Count: 32
1449 * If the device is configured as CANFD node, the default CAN RAM settings are as below:
1450 * - Standard Identifier Filter Elements: 16
1451 * - Extended Identifier Filter Elements: 16
1452 * - TXBUF Elements Info:
1453 * - Element Count:8
1454 * - Dedicated TXBUF element count: 4
1455 * - TXFIFO/QQueue element count: 4
1456 * - Data Field Size: 64
1457 * - RXFIFO0 Elements Info:
1458 * - Element Count : 8
1459 * - Data Field Size: 64
1460 * - RXFIFO1 Elements Info:
1461 * - Element Count : 8
1462 * - Data Field Size: 64
1463 * - RXBUF Element Info:
1464 * - Element Count: 4
1465 * - Data Field Size : 64
1466 * - TX Event FIFO Element Count: 8
1467 *
1468 * @param [in] ptr MCAN base
1469 * @param [out] ram_config CAN RAM Configuration
1470 * @param [in] enable_canfd CANFD enable flag
1471 */
1472 void mcan_get_default_ram_flexible_config(MCAN_Type *ptr, mcan_ram_flexible_config_t *ram_config, bool enable_canfd);
1473
1474 /**
1475 * @brief Get Default MCAN RAM configuration
1476 * If the device is configured as classic CAN node, the default CAN RAM settings are as below:
1477 * - Standard Identifier Filter Elements: 32
1478 * - Extended Identifier Filter Elements: 32
1479 * - TXBUF Elements Info:
1480 * - Element Count:32
1481 * - Dedicated TXBUF element count: 16
1482 * - TXFIFO/QQueue element count: 16
1483 * - Data Field Size: 8
1484 * - RXFIFO0 Elements Info:
1485 * - Element Count :32
1486 * - Data Field Size: 8
1487 * - RXFIFO1 Elements Info:
1488 * - Element Count : 32
1489 * - Data Field Size: 8
1490 * - RXBUF Element Info:
1491 * - Element Count: 16
1492 * - Data Field Size : 8
1493 * - TX Event FIFO Element Count: 32
1494 * If the device is configured as CANFD node, the default CAN RAM settings are as below:
1495 * - Standard Identifier Filter Elements: 16
1496 * - Extended Identifier Filter Elements: 16
1497 * - TXBUF Elements Info:
1498 * - Element Count:8
1499 * - Dedicated TXBUF element count: 4
1500 * - TXFIFO/QQueue element count: 4
1501 * - Data Field Size: 64
1502 * - RXFIFO0 Elements Info:
1503 * - Element Count : 8
1504 * - Data Field Size: 64
1505 * - RXFIFO1 Elements Info:
1506 * - Element Count : 8
1507 * - Data Field Size: 64
1508 * - RXBUF Element Info:
1509 * - Element Count: 4
1510 * - Data Field Size : 64
1511 * - TX Event FIFO Element Count: 8
1512 *
1513 * @param [in] ptr MCAN base
1514 * @param [out] ram_config CAN RAM Configuration
1515 * @param [in] enable_canfd CANFD enable flag
1516 */
1517 void mcan_get_default_ram_config(MCAN_Type *ptr, mcan_ram_config_t *simple_config, bool enable_canfd);
1518
1519 /**
1520 * @brief Initialize CAN controller
1521 * @param [in] ptr MCAN base
1522 * @param [in] config CAN configuration
1523 * @param [in] src_clk_freq CAN clock frequency
1524 * @retval status_success if operation is successful
1525 * @retval status_invalid_argument if any parameters are invalid
1526 */
1527 hpm_stat_t mcan_init(MCAN_Type *ptr, mcan_config_t *config, uint32_t src_clk_freq);
1528
1529 /**
1530 * @brief De-Initialize CAN controller
1531 *
1532 * @param [in] ptr MCAN base
1533 */
1534 void mcan_deinit(MCAN_Type *ptr);
1535
1536 /**
1537 * @brief Configure MCAN RAM will Full RAM configuration
1538 * @param [in] ptr MCAN base
1539 * @param [in] config MCAN RAM Full Configuration
1540 * @return status_success if no errors reported
1541 */
1542 hpm_stat_t mcan_config_ram_with_flexible_config(MCAN_Type *ptr, mcan_ram_flexible_config_t *config);
1543
1544 /**
1545 * @brief Configure MCAN RAM will Simplified RAM configuration
1546 * @param [in] ptr MCAN base
1547 * @param [in] config MCAN RAM configuration
1548 * @return status_success if no errors reported
1549 */
1550 hpm_stat_t mcan_config_ram(MCAN_Type *ptr, mcan_ram_config_t *config);
1551
1552 /**
1553 * @brief Configure All CAN filters
1554 * @param [in] ptr MCAN base
1555 * @param [in] config All CAN Filter configuration
1556 * @return status_success if no errors reported
1557 */
1558 hpm_stat_t mcan_config_all_filters(MCAN_Type *ptr, mcan_all_filters_config_t *config);
1559
1560 /**
1561 * @brief Configure Transmitter Delay Compensation
1562 * @param [in] ptr MCAN base
1563 * @param [in] config Transmitter Delay compensation configure
1564 * @return status_success if no errors reported
1565 */
1566 hpm_stat_t mcan_config_transmitter_delay_compensation(MCAN_Type *ptr, mcan_tdc_config_t *config);
1567
1568 /**
1569 * @brief Configure Global Filter
1570 * @param [in] ptr MCAN base
1571 * @param [in] filter_config Global Filter Configuration
1572 * @return status_success if no errors reported
1573 */
1574 hpm_stat_t mcan_set_global_filter_config(MCAN_Type *ptr, mcan_global_filter_config_t *filter_config);
1575
1576 /**
1577 * @brief Set CAN filter element
1578 * @param [in] ptr MCAN base
1579 * @param [in] filter_elem CAN filter element
1580 * @param [in] index CAN Filter element index
1581 * @return status_success if no errors reported
1582 */
1583 hpm_stat_t mcan_set_filter_element(MCAN_Type *ptr, const mcan_filter_elem_t *filter_elem, uint32_t index);
1584
1585 /**
1586 * @brief Write Frame to CAN TX Buffer
1587 * @param [in] ptr MCAN base
1588 * @param [in] index TX Buffer Index
1589 * @param [in] tx_frame TX frame
1590 * @return status_success if no errors reported
1591 */
1592 hpm_stat_t mcan_write_txbuf(MCAN_Type *ptr, uint32_t index, mcan_tx_frame_t *tx_frame);
1593
1594 /**
1595 * @brief Write Frame CAN to TXFIFO
1596 * @param [in] ptr MCAN base
1597 * @param [in] tx_frame TX frame
1598 * @return status_success if no errors reported
1599 */
1600 hpm_stat_t mcan_write_txfifo(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame);
1601
1602 /**
1603 * @brief Read message from CAN RXBUF
1604 * @param [in] ptr MCAN base
1605 * @param [in] index Index of RXBUF
1606 * @param [out] rx_frame Buffer to hold RX frame
1607 * @return status_success if no errors reported
1608 */
1609 hpm_stat_t mcan_read_rxbuf(MCAN_Type *ptr, uint32_t index, mcan_rx_message_t *rx_frame);
1610
1611 /**
1612 * @brief Read message from CAN RXBUF
1613 * @param [in] ptr MCAN base
1614 * @param [in] fifo_index RXFIFO index, 0 - RXFO0, 1 - RXFIFO1
1615 * @param [out] rx_frame Buffer to hold RX frame
1616 * @return status_success if no errors reported
1617 */
1618 hpm_stat_t mcan_read_rxfifo(MCAN_Type *ptr, uint32_t fifo_index, mcan_rx_message_t *rx_frame);
1619
1620 /**
1621 * @brief Read TX Event from CAN TX EVENT FIFO
1622 * @param [in] ptr MCAN base
1623 * @param [out] tx_evt TX Event Buffer
1624 * @retval status_success if no errors happened
1625 * @retval status_mcan_tx_evt_fifo_empty if there are no TX events available
1626 * @retval status_invalid_argument if any parameters are invalid
1627 */
1628 hpm_stat_t mcan_read_tx_evt_fifo(MCAN_Type *ptr, mcan_tx_event_fifo_elem_t *tx_evt);
1629
1630 /**
1631 * @brief Transmit CAN message in blocking way
1632 * @param [in] ptr MCAN base
1633 * @param [in] tx_frame CAN Transmit Message buffer
1634 * @return status_success if no errors reported
1635 */
1636 hpm_stat_t mcan_transmit_blocking(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame);
1637
1638 /**
1639 * @brief Transmit CAN message via TX FIFO in non-blocking way
1640 * @param [in] ptr MCAN base
1641 * @param [in] tx_frame CAN Transmit Message buffer
1642 * @param [out] fifo_index The index of the element in FIFO assigned to the tx_frame
1643 *
1644 * @return status_success if no errors reported
1645 */
1646 hpm_stat_t mcan_transmit_via_txfifo_nonblocking(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame, uint32_t *fifo_index);
1647
1648 /**
1649 * @brief Transmit CAN message via TX in non-blocking way
1650 * @param [in] ptr MCAN base
1651 * @param [in] index Index of TX Buffer
1652 * @param [in] tx_frame CAN Transmit Message buffer
1653 * @return status_success if no errors reported
1654 */
1655 hpm_stat_t mcan_transmit_via_txbuf_nonblocking(MCAN_Type *ptr, uint32_t index, mcan_tx_frame_t *tx_frame);
1656
1657 /**
1658 * @brief Receive CAN Frame from RXBUF in blocking way
1659 * @param [in] ptr MCAN base
1660 * @param [in] index RXBUF index
1661 * @param [out] rx_frame Buffer to hold Received Frame
1662 * @return status_success if no errors reported
1663 */
1664 hpm_stat_t mcan_receive_from_buf_blocking(MCAN_Type *ptr, uint32_t index, mcan_rx_message_t *rx_frame);
1665
1666 /**
1667 * @brief Receive CAN Frame from RXFIFO in blocking way
1668 * @param [in] ptr MCAN base
1669 * @param [in] fifo_index RXFIFO index, 0 - RXFIFO0, 1 - RXFIFO1
1670 * @param [out] rx_frame Buffer to hold Received Frame
1671 * @return status_success if no errors reported
1672 */
1673 hpm_stat_t mcan_receive_from_fifo_blocking(MCAN_Type *ptr, uint32_t fifo_index, mcan_rx_message_t *rx_frame);
1674
1675 /**
1676 * @brief Get Timstamp from MCAN TX Event
1677 * @param [in] ptr MCAN base
1678 * @param [in] tx_evt TX Event Element
1679 * @param [out] timestamp Timestamp value
1680 * @retval status_success if no errors happened
1681 * @retval status_invalid_argument if any parameters are invalid
1682 * @retval status_mcan_timestamp_not_exist if no timestamp information is available
1683 */
1684 hpm_stat_t mcan_get_timestamp_from_tx_event(MCAN_Type *ptr,
1685 const mcan_tx_event_fifo_elem_t *tx_evt,
1686 mcan_timestamp_value_t *timestamp);
1687
1688 /**
1689 * @brief Get Timstamp from MCAN RX frame
1690 * @param [in] ptr MCAN base
1691 * @param [in] rx_msg Received message
1692 * @param [out] timestamp Timestamp value
1693 * @retval status_success if no errors happened
1694 * @retval status_invalid_argument if any parameters are invalid
1695 * @retval status_mcan_timestamp_not_exist if no timestamp information is available
1696 */
1697 hpm_stat_t mcan_get_timestamp_from_received_message(MCAN_Type *ptr,
1698 const mcan_rx_message_t *rx_msg,
1699 mcan_timestamp_value_t *timestamp);
1700
1701 /**
1702 * @brief Parse the Protocol Status register value
1703 * @param [in] psr Protocol Status Register Value
1704 * @param [out] protocol_status Translated Protocol Status
1705 *
1706 * @retval status_invalid_argument if any parameters are invalid
1707 * @retval status_success if no errors happened
1708 */
1709 hpm_stat_t mcan_parse_protocol_status(uint32_t psr, mcan_protocol_status_t *protocol_status);
1710
1711 /**
1712 * @brief Get MCAN Protocol Status
1713 * @param [in] ptr MCAN base
1714 * @param [out] protocol_status Translated Protocol status
1715 *
1716 * @retval status_invalid_argument if any parameters are invalid
1717 * @retval status_success if no errors happened
1718 */
1719 hpm_stat_t mcan_get_protocol_status(MCAN_Type *ptr, mcan_protocol_status_t *protocol_status);
1720
1721 /**
1722 * @}
1723 *
1724 */
1725
1726 #ifdef __cplusplus
1727 }
1728 #endif
1729
1730
1731 #endif /* HPM_MCAN_DRV_H */
1732