1 /*
2 // Copyright (C) 2022 Beken Corporation
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15 #ifndef _SCTRL_H_
16 #define _SCTRL_H_
17
18 #include <common/sys_config.h>
19 #include <common/bk_include.h>
20
21 #if (CONFIG_SOC_BK7271)
22 #include "bk_lbus.h"
23 #endif
24
25 #define SCTRL_DEBUG 0
26
27 #if SCTRL_DEBUG
28 #define SCTRL_PRT os_printf
29 #else
30 #define SCTRL_PRT os_null_printf
31 #endif
32
33 #define DPLL_DELAY_EN 1
34 #define DPLL_DELAY_TIME_10US 120
35 #define DPLL_DELAY_TIME_200US 3400
36
37 #define SCTRL_BASE (0x00800000)
38
39 #define SCTRL_CHIP_ID (SCTRL_BASE + 00 * 4)
40 #define CHIP_ID_DEFAULT (0x7111)
41 #define CHIP_ID_BK7231N (0x7231C)
42
43 #define SCTRL_DEVICE_ID (SCTRL_BASE + 01 * 4)
44 #define DEVICE_ID_MASK (0xFFFF0000) //as wangjian advised, only check high 16 bits
45 #define DEVICE_ID_DEFAULT (0x20150414)
46 #define DEVICE_ID_BK7231N_B (0x20521024)
47 #define DEVICE_ID_BK7231N_C (0x20521025)
48 #define DEVICE_ID_BK7231N_D (0x20521026)
49 #define DEVICE_ID_BK7231N_E (0x20521027)
50 #define DEVICE_ID_BK7231N_F (0x20521028)
51 #define DEVICE_ID_BK7231N_N (0x20521010)
52 #define DEVICE_ID_BK7231N_P (0x20A21020)
53
54 #define SCTRL_CONTROL (SCTRL_BASE + 02 * 4)
55
56 #if (CONFIG_SOC_BK7271)
57 #define BT_IMEM_BASE_ADDR (0x10000000)
58
59 #define MAC_HCLK_EN_BIT (1 << 27)
60 #define PHY_HCLK_EN_BIT (1 << 26)
61 #define MTB_PRIVILEGE_POSI (24)
62 #define MTB_PRIVILEGE_MASK (0x3)
63 #define MTB_PRIVILEGE_ACCESS_NONE (0x0)
64 #define MTB_PRIVILEGE_ACCESS_AHB_PART (0x1)
65 #define MTB_PRIVILEGE_ACCESS_AHB (0x2)
66 #define MTB_PRIVILEGE_ACCESS_AHB_DTCM (0x3)
67
68 #define addPMU_Reg0xd *((volatile unsigned long *) (0x00800200+0xd*4))
69 #define addPMU_Reg0xf *((volatile unsigned long *) (0x00800200+0xf*4))
70 #define addGPIO_Reg0xf *((volatile unsigned long *) (0x00800300+0xf*4))
71 #endif
72
73 #if (CONFIG_SOC_BK7251)
74 #define EFUSE_VDD25_EN (1 << 23)
75
76 #if (CONFIG_SOC_BK7251) || (CONFIG_SOC_BK7271)
77 #define FLASH_SPI_MUX_BIT (1 << 22)
78 #endif // (CONFIG_SOC_BK7251)
79
80 #define PSRAM_VDDPAD_VOLT_POSI (20)
81 #define PSRAM_VDDPAD_VOLT_MASK (0x3)
82 #define FLASH_SCK_IOCAP_POSI (18)
83 #define FLASH_SCK_IOCAP_MASK (0x3)
84 #define QSPI_IO_VOLT_POSI (16)
85 #define QSPI_IO_VOLT_MASK (0x3)
86 #define BLE_RF_EN_BIT (1 << 15)
87 #elif (CONFIG_SOC_BK7231U)
88 #define EFUSE_VDD25_EN (1 << 23)
89 #define PSRAM_VDDPAD_VOLT_POSI (20)
90 #define PSRAM_VDDPAD_VOLT_MASK (0x3)
91 #define FLASH_SCK_IOCAP_POSI (18)
92 #define FLASH_SCK_IOCAP_MASK (0x3)
93 #define QSPI_IO_VOLT_POSI (16)
94 #define QSPI_IO_VOLT_MASK (0x3)
95 #define BLE_RF_EN_BIT (1 << 15)
96 #elif (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX) || (CONFIG_SOC_BK7236)
97 #define BLE_RF_PTA_EN_BIT (1 << 24)
98 #define EFUSE_VDD25_EN (1 << 23)
99 #define FLASH_SPI_MUX_BIT (1 << 22)
100 #define FLASH_SCK_IOCAP_POSI (18)
101 #define FLASH_SCK_IOCAP_MASK (0x3)
102 #define BLE_RF_EN_BIT (1 << 15)
103 #elif (!CONFIG_SOC_BK7231)
104 #define EFUSE_VDD25_EN (1 << 23)
105 #define PSRAM_VDDPAD_VOLT_POSI (20)
106 #define PSRAM_VDDPAD_VOLT_MASK (0x3)
107 #define FLASH_SCK_IOCAP_POSI (18)
108 #define FLASH_SCK_IOCAP_MASK (0x3)
109 #define QSPI_IO_VOLT_POSI (16)
110 #define QSPI_IO_VOLT_MASK (0x3)
111 #define BLE_RF_EN_BIT (1 << 15)
112 #endif // (CONFIG_SOC_BK7251)
113
114 #define DPLL_CLKDIV_RESET_BIT (1 << 14)
115 #define SDIO_CLK_INVERT_BIT (1 << 13)
116 #define MPIF_CLK_INVERT_BIT (1 << 12)
117 #define MAC_CLK480M_PWD_BIT (1 << 11)
118 #define MODEM_CLK480M_PWD_BIT (1 << 10)
119
120 #if (CONFIG_SOC_BK7271)
121 #define HCLK_DIV2_POSI (2)
122 #define HCLK_DIV2_MASK (0x3)
123 #define HCLK_DIV2_EN_BIT (1 << 2)
124 #else
125 #define HCLK_DIV2_EN_BIT (1 << 9)
126 #endif
127
128 #define FLASH_26M_MUX_BIT (1 << 8)
129
130 #define MCLK_DIV_MASK (0x0F)
131 #define MCLK_DIV_POSI (4)
132
133 #define MCLK_MUX_MASK (0x03)
134 #define MCLK_MUX_POSI (0)
135 #define MCLK_FIELD_DCO (0x0)
136 #define MCLK_FIELD_26M_XTAL (0x1)
137 #define MCLK_FIELD_DPLL (0x2)
138 #define MCLK_FIELD_LPO (0x3)
139
140 #define SCTRL_CLK_GATING (SCTRL_BASE + 3 * 4)
141 #define MAC_PI_CLKGATING_BIT (1 << 8)
142 #define MAC_PI_RX_CLKGATING_BIT (1 << 7)
143 #define MAC_PI_TX_CLKGATING_BIT (1 << 6)
144 #define MAC_PRI_CLKGATING_BIT (1 << 5)
145 #define MAC_CRYPT_CLKGATING_BIT (1 << 4)
146 #define MAC_CORE_TX_CLKGATING_BIT (1 << 3)
147 #define MAC_CORE_RX_CLKGATING_BIT (1 << 2)
148 #define MAC_WT_CLKGATING_BIT (1 << 1)
149 #define MAC_MPIF_CLKGATING_BIT (1 << 0)
150
151 #define SCTRL_RESET (SCTRL_BASE + 4 * 4)
152 #if (CONFIG_SOC_BK7271)
153 #define SCTRL_RESET_MASK (0x1FFFFF)
154 #define MAC_SUBSYS_RESET_BIT (1 << 20)
155 #define MODEM_CORE_RESET_BIT (1 << 19)
156 #define MODEM_SUBCHIP_RESET_BIT (1 << 16)
157 #else
158 #define SCTRL_RESET_MASK (0x7F)
159
160 #if (!CONFIG_SOC_BK7231)
161 #define BLE_SUBSYS_RESET (1 << 8)
162 #endif // (!CONFIG_SOC_BK7231)
163
164 #define MAC_WAKEUP_ARM (1 << 7)
165 #define MODEM_CORE_RESET_BIT (1 << 6)
166
167 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX) || (CONFIG_SOC_BK7236)
168 #define BOOT_MODE_BIT (1 << 9)
169 #define MAC_SUBSYS_RESET_BIT (1 << 2)
170 #else
171 #define TL410_EXT_WAIT_BIT (1 << 5)
172 #define USB_SUBSYS_RESET_BIT (1 << 4)
173 #define TL410_BOOT_BIT (1 << 3)
174 #define MAC_SUBSYS_RESET_BIT (1 << 2)
175 #define DSP_SUBSYS_RESET_BIT (1 << 1)
176 #endif
177
178 #define MODEM_SUBCHIP_RESET_BIT (1 << 0)
179 #endif
180
181 #define SCTRL_REG_RESV5 (SCTRL_BASE + 5 * 4)
182 #define SCTRL_REG_RESV6 (SCTRL_BASE + 6 * 4)
183
184 #define SCTRL_FLASH_DELAY (SCTRL_BASE + 7 * 4)
185 #define FLASH_DELAY_CYCLE_POSI (0)
186 #define FLASH_DELAY_CYCLE_MASK (0xFFF)
187
188 #define SCTRL_MODEM_SUBCHIP_RESET_REQ (SCTRL_BASE + 8 * 4)
189
190 #if (CONFIG_SOC_BK7271)
191 #define MODEM_SUBCHIP_RESET_WORD (0x7171e802)
192 #else
193 #define MODEM_SUBCHIP_RESET_WORD (0x7111e802)
194 #endif
195
196 #if (CONFIG_SOC_BK7271)
197 #define SCTRL_MAC_SUBSYS_RESET_REQ (SCTRL_BASE + 12 * 4)
198 #define MAC_SUBSYS_RESET_POSI (0)
199 #define MAC_SUBSYS_RESET_MASK (0xFFFF)
200 #define MAC_SUBSYS_RESET_WORD (0xE802U)
201 #else
202 #define SCTRL_MAC_SUBSYS_RESET_REQ (SCTRL_BASE + 9 * 4)
203 #define MAC_SUBSYS_RESET_WORD (0x7111C802)
204 #endif
205
206 #define SCTRL_USB_SUBSYS_RESET_REQ (SCTRL_BASE + 10 * 4)
207 #define USB_SUBSYS_RESET_WORD (0x7111C12B)
208
209 #define SCTRL_DSP_SUBSYS_RESET_REQ (SCTRL_BASE + 11 * 4)
210 #define DSP_SUBSYS_RESET_WORD (0x7111C410)
211
212 #define SCTRL_MODEM_CORE_RESET_PHY_HCLK (SCTRL_BASE + 12 * 4)
213 #define MODEM_CORE_RESET_POSI (16)
214 #define MODEM_CORE_RESET_MASK (0xFFFF)
215 #define MODEM_CORE_RESET_WORD (0xE802U)
216 #if (!CONFIG_SOC_BK7271)
217 #define MAC_HCLK_EN_BIT (1 << 1)
218 #define PHY_HCLK_EN_BIT (1 << 0)
219 #endif
220
221 #define SCTRL_DEBUG13 (SCTRL_BASE + 13 * 4)
222 #define DBGMACCLKSEL_POSI (20)
223 #define DBGMACCLKSEL_MASK (0x1)
224 #define SMPSOURCE_POSI (16)
225 #define SMPSOURCE_MASK (0xF)
226 #define DBGMDMBANK1MUX_POSI (8)
227 #define DBGMDMBANK1MUX_MASK (0x1F)
228 #define DBGMDMBANK0MUX_POSI (02)
229 #define DBGMDMBANK0MUX_MASK (0x1F)
230
231 #define SCTRL_DEBUG14_MODEM_BANK (SCTRL_BASE + 14 * 4)
232 #define SCTRL_DEBUG15_MAC_BANK (SCTRL_BASE + 15 * 4)
233
234
235 #define SCTRL_ANALOG_SPI (SCTRL_BASE + 16 * 4)
236 #define ANA_SPI_FREQ_DIV_POSI (26)
237 #define ANA_SPI_FREQ_DIV_MASK (0x3F)
238 #if (CONFIG_SOC_BK7231)
239 #define ANA_SPI_STATE_POSI (0)
240 #define ANA_SPI_STAET_MASK (0x1F)
241 #elif (CONFIG_SOC_BK7231U) || (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX) || (CONFIG_SOC_BK7236)
242 #define ANA_SPI_STATE_POSI (0)
243 #define ANA_SPI_STAET_MASK (0x7F)
244 #elif (CONFIG_SOC_BK7251)
245 #define ANA_SPI_STATE_POSI (0)
246 #define ANA_SPI_STAET_MASK (0x7FF)
247 #elif (CONFIG_SOC_BK7271)
248 #define ANA_SPI_STATE_POSI (0)
249 #define ANA_SPI_STAET_MASK (0xFFFF)
250 #endif
251
252 #if (!CONFIG_SOC_BK7231N) && (!CONFIG_SOC_BK7236A) && (!CONFIG_SOC_BK7256XX) && (!CONFIG_SOC_BK7236)
253 #define SCTRL_LA_SAMPLE (SCTRL_BASE + 18 * 4)
254 #define LA_SMP_LEN_POSI (16)
255 #define LA_SMP_LEN_MASK (0xFFFF)
256 #define LA_SMP_FINISH_BIT (1 << 3)
257 #define LA_SMP_CLK_INVERT (1 << 2)
258 #define LA_SMP_MODE_POSI (0)
259 #define LA_SMP_MODE_MASK (0x3)
260
261 #define SCTRL_LA_SAMPLE_VALUE (SCTRL_BASE + 19 * 4)
262 #define SCTRL_LA_SAMPLE_MASK (SCTRL_BASE + 20 * 4)
263 #define SCTRL_LA_SAMPLE_DMA_START_ADDR (SCTRL_BASE + 21 * 4)
264 #endif
265
266 #define SCTRL_ANALOG_CTRL0 (SCTRL_BASE + 22 * 4)
267 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX) || (CONFIG_SOC_BK7236)
268 #define LPEN_DPLL (1 << 27)
269 #endif
270 #define SPI_TRIG_BIT (1 << 19)
271 #define SPI_DET_EN (1 << 4)
272
273 #define SCTRL_ANALOG_CTRL1 (SCTRL_BASE + 23 * 4)
274 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX) || (CONFIG_SOC_BK7236)
275 #define ROSC_TSTEN_BIT (1 << 31)
276 #define DCO_TSTEN_BIT (1 << 30)
277 #define DCO_DIV_POSI (27)
278 #define DCO_DIV_MASK (0x7U)
279 #define DCO_AMSEL_BIT (1 << 26)
280 #define SPI_RST_BIT (1 << 25)
281 #define DCO_CNTI_POSI (16)
282 #define DCO_CNTI_MASK (0x1FFU)
283 #define DCO_TRIG_BIT (1 << 15)
284 #define DCO_ICTRL_POSI (11)
285 #define DCO_ICTRL_MASK (0x7U)
286 #define DCO_MSW_POSI (2)
287 #define DCO_MSW_MASK (0x1FFU)
288 #define DPLL_VREFSEL_BIT (1 << 1)
289 #else
290 #define DIV_BYPASS_BIT (1 << 31)
291 #define SPI_RST_BIT (1 << 25)
292 #define DCO_CNTI_POSI (16)
293 #define DCO_CNTI_MASK (0x1FFU)
294 #define DCO_TRIG_BIT (1 << 15)
295 #define DCO_DIV_POSI (12)
296 #define DCO_DIV_MASK (0x3U)
297 #endif
298
299 #define SCTRL_ANALOG_CTRL2 (SCTRL_BASE + 24 * 4)
300 #define CENTRAL_BAIS_ENABLE_BIT (1 << 13)
301 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX) || (CONFIG_SOC_BK7236)
302 #define XTALH_CTUNE_POSI (2)
303 #define XTALH_CTUNE_MASK (0x7FU)
304 #define BANDGAP_CAL_MANUAL_POSI (23)
305 #define BANDGAP_CAL_MANUAL_MASK (0x3FU)
306 #elif (!CONFIG_SOC_BK7231) && (!CONFIG_SOC_BK7271)
307 #define XTALH_CTUNE_POSI (2)
308 #define XTALH_CTUNE_MASK (0x3FU)
309 #endif // (CONFIG_SOC_BK7231)
310 #define TRXT_TST_ENABLE_BIT (1 << 12)
311
312 #define SCTRL_ANALOG_CTRL3 (SCTRL_BASE + 25 * 4)
313 #if (!CONFIG_SOC_BK7231N) && (!CONFIG_SOC_BK7236A) && (!CONFIG_SOC_BK7256XX) || (CONFIG_SOC_BK7236)
314 #define CHARGE_LC2CVDLYLV_MASK (0x7)
315 #define CHARGE_LC2CVDLYLV_POS (29)
316 #define CHARGE_VLCSWLV_MASK (0xF)
317 #define CHARGE_VLCSWLV_POS (23)
318 #define CHARGE_LCP_MASK (0x1F)
319 #define CHARGE_LCP_POS (8)
320 #endif
321
322 #define SCTRL_ANALOG_CTRL4 (SCTRL_BASE + 26 * 4)
323 #if (CONFIG_SOC_BK7251)
324 #define VSEL_SYS_LDO_POSI (27)
325 #define VSEL_SYS_LDO_MASK (0x3)
326 #define CHARGE_MANMODE_MASK (0x7)
327 #define CHARGE_MANMODE_POS (16)
328 #elif (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX) || (CONFIG_SOC_BK7236)
329 #define VREF_SEL_BIT (1 << 30)
330 #define GADC_CAL_SEL_POSI (19)
331 #define GADC_CAL_SEL_MASK (0x3)
332 #elif (CONFIG_SOC_BK7271)
333 #define BT_ENABLE_1V (1 << 23)
334 #define BT_ENaBLE_LDO_1V (1 << 22)
335 #define XTALH_CTUNE_POSI (7)
336 #define XTALH_CTUNE_MASK (0x3FU)
337 #else
338 #endif
339
340 #define SCTRL_ANALOG_CTRL5 (SCTRL_BASE + 0x1B*4)
341
342 #if (CONFIG_SOC_BK7271)
343 #define SCTRL_ANALOG_CTRL6 (SCTRL_BASE + 0x1C*4)
344 #define SCTRL_ANALOG_CTRL7 (SCTRL_BASE + 0x1D*4)
345 #define SCTRL_ANALOG_CTRL8_REAL (SCTRL_BASE + 0x1E*4)
346 #define SCTRL_ANALOG_CTRL9_REAL (SCTRL_BASE + 0x1F*4)
347 #define ANALOG_LDO_ENABLE (1 << 13)
348 #define VBG_SEL_HIGH_POSI (10)
349 #define VBG_SEL_HIGH_MASK (0x3)
350 #define VBG_SEL_LOW_POSI (8)
351 #define VBG_SEL_LOW_MASK (0x3)
352
353 #define SCTRL_ANALOG_CTRL8 (SCTRL_BASE + 0x20*4) //ana_regA actually
354 #define LINE_IN_EN (1 << 21)
355 #define LINE2_IN_EN (1 << 20)
356 #define LINE_IN_GAIN_MASK (0x3)
357 #define LINE_IN_GAIN_POSI (22)
358 #define AUD_DAC_GAIN_MASK (0x3F)
359 #define AUD_DAC_GAIN_POSI (1)
360 #define AUD_DAC_MUTE_EN (1 << 0)
361
362 #define SCTRL_ANALOG_CTRL9 (SCTRL_BASE + 0x21*4) //ana_regB actually
363 #define DAC_DIFF_EN (1 << 31)
364 #define EN_AUD_DAC_L (1 << 30)
365 #define EN_AUD_DAC_R (1 << 29)
366 #define DAC_PA_OUTPUT_EN (1 << 24)
367 #define DAC_DRIVER_OUTPUT_EN (1 << 23)
368 #define AUD_DAC_DGA_EN (1 << 6)
369
370 #define SCTRL_ANALOG_CTRL10 (SCTRL_BASE + 0x22*4) //ana_regC actually
371 #define DAC_N_END_OUPT_L (1 << 8)
372 #define DAC_N_END_OUPT_R (1 << 7)
373 #define DAC_VSEL_MASK (0x3)
374 #define DAC_VSEL_POSI (1)
375
376 #define SCTRL_ANALOG_CTRL13 (SCTRL_BASE + 0x23*4) //ana_regD for audio
377 #define AUDIO_DCO_EN (1 << 10)
378 #define MIC1_PWR_DOWN (1 << 29)
379 #define MIC2_PWR_DOWN (1 << 24)
380 #define MIC3_PWR_DOWN (1 << 19)
381 #define MIC5_PWR_DOWN (1 << 15)
382 #define MIC4_PWR_DOWN (1 << 14)
383 #define MIC6_PWR_DOWN (1 << 12)
384
385 #define SCTRL_ANALOG_AUDIO_PLL_SDM (SCTRL_BASE + 0x24*4) //ana_regE for audio
386
387 #define SCTRL_ANALOG_AUDIO_PLL_CTRL (SCTRL_BASE + 0x25*4) //ana_regF for audio
388 #define AUDIO_PLL_AUDIO_EN (1 << 31)
389 #define AUDIO_PLL_CKSEL (1 << 29)
390 #define AUDIO_PLL_SPI_TRIGGER (1 << 18)
391 #define AUDIO_PLL_RESET (1 << 3)
392
393 #elif (!CONFIG_SOC_BK7231)
394 #define SCTRL_ANALOG_CTRL6 (SCTRL_BASE + 0x1C*4)
395 #define DPLL_CLK_FOR_AUDIO_EN (1 << 31)
396 #define DPLL_CLK_FOR_USB_EN (1 << 30)
397 #define DPLL_DIVIDER_CLK_SEL (1 << 29)
398 #define DPLL_DIVIDER_CTRL_MASK (0x7)
399 #define DPLL_DIVIDER_CTRL_POSI (26)
400 #define DPLL_CLKOUT_PAD_EN (1 << 25)
401 #define DPLL_XTAL26M_CLK_AUDIO_EN (1 << 24)
402 #define DPLL_REF_CLK_SELECT (1 << 23)
403 #define DPLL_CHARGE_PUMP_CUR_CTRL_MASK (0x7)
404 #define DPLL_CHARGE_PUMP_CUR_CTRL_POSI (20)
405 #define DPLL_DPLL_VCO_BAND_MANUAL_EN (1 << 19)
406 #define DPLL_SPI_TRIGGER (1 << 18)
407 #define DPLL_CLK_REF_LOOP_SEL (1 << 17)
408 #define DPLL_KVCO_CTRL_MASK (0x3)
409 #define DPLL_KVCO_CTRL_POSI (15)
410 #define DPLL_VSEL_CAL (1 << 14)
411 #define DPLL_RP_CTRL_LPF_MASK (0x7)
412 #define DPLL_RP_CTRL_LPF_POSI (11)
413 #define DPLL_RESET (1 << 3)
414
415 #define SCTRL_EFUSE_CTRL (SCTRL_BASE + 0x1D*4)
416 #define EFUSE_OPER_EN (1 << 0)
417 #define EFUSE_OPER_DIR (1 << 1)
418 #define EFUSE_OPER_ADDR_POSI (8)
419 #define EFUSE_OPER_ADDR_MASK (0x1F)
420 #define EFUSE_OPER_WR_DATA_POSI (16)
421 #define EFUSE_OPER_WR_DATA_MASK (0xFF)
422
423 #define SCTRL_EFUSE_OPTR (SCTRL_BASE + 0x1E*4)
424 #define EFUSE_OPER_RD_DATA_POSI (0)
425 #define EFUSE_OPER_RD_DATA_MASK (0xFF)
426 #define EFUSE_OPER_RD_DATA_VALID (1 << 8)
427
428
429 #define SCTRL_DMA_PRIO_VAL (SCTRL_BASE + 0x1F*4)
430
431 #define SCTRL_BLE_SUBSYS_RESET_REQ (SCTRL_BASE + 0x20*4)
432 #if (CONFIG_SOC_BK7251)
433 #define SCTRL_CHARGE_STATUS (SCTRL_BASE + 0x21*4)
434 #define CHARGE_VCAL_MASK (0x3F)
435 #define CHARGE_VCAL_POS (5)
436 #define CHARGE_LCAL_MASK (0x1F)
437 #define CHARGE_LCAL_POS (11)
438 #define CHARGE_VCVCAL_MASK (0x1F)
439 #define CHARGE_VCVCAL_POS (0)
440
441 #define SCTRL_ANALOG_CTRL7 (SCTRL_BASE + 0x22*4)
442
443 #define SCTRL_ANALOG_CTRL8 (SCTRL_BASE + 0x23*4)
444 #define LINE_IN_EN (1 << 24)
445 #define LINE_IN_GAIN_MASK (0x3)
446 #define LINE_IN_GAIN_POSI (22)
447 #define SPI_PWD_AUD_ADC_L (1 << 21)
448 #define SPI_PWD_AUD_ADC_R (1 << 20)
449 #define AUD_DAC_GAIN_MASK (0x1F)
450 #define AUD_DAC_GAIN_POSI (2)
451 #define AUD_DAC_MUTE_EN (1 << 0)
452
453 #define SCTRL_ANALOG_CTRL9 (SCTRL_BASE + 0x24*4)
454 #define DAC_DIFF_EN (1 << 31)
455 #define EN_AUD_DAC_L (1 << 30)
456 #define EN_AUD_DAC_R (1 << 29)
457 #define DAC_PA_OUTPUT_EN (1 << 24)
458 #define DAC_DRIVER_OUTPUT_EN (1 << 23)
459 #define AUD_DAC_DGA_EN (1 << 6)
460
461 #define SCTRL_ANALOG_CTRL10 (SCTRL_BASE + 0x25*4)
462 #define DAC_N_END_OUPT_L (1 << 8)
463 #define DAC_N_END_OUPT_R (1 << 7)
464 #define DAC_VSEL_MASK (0x3)
465 #define DAC_VSEL_POSI (1)
466 #elif (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX) || (CONFIG_SOC_BK7236)
467 #define SCTRL_ANALOG_STATE (SCTRL_BASE + 0x21*4)
468 #define ANALOG_STATE_DPLL_UNLOCK (1 << 15)
469 #define ANALOG_STATE_BGCAL_MASK (0x3FU)
470 #define ANALOG_STATE_BGCAL_POSI (2)
471 #define ANALOG_STATE_MASK (0xFF)
472 #define ANALOG_STATE_POS (0)
473 #endif // (CONFIG_SOC_BK7251)
474 #endif // (!CONFIG_SOC_BK7251)
475
476 #if (CONFIG_SOC_BK7271)
477 #define SCTRL_ROSC_CAL SCTRL_ANALOG_CTRL2
478 #define ROSC_CAL_MANU_CIN_POSI (1)
479 #define ROSC_CAL_MANU_CIN_MASK (0x3F)
480 #define ROSC_CAL_MANU_EN_BIT (1 << 0)
481 #define ROSC_CAL_INTVAL_POSI (22)
482 #define ROSC_CAL_INTVAL_MASK (0x3FF)
483 #define ROSC_CAL_MODE_BIT (1 << 10)
484 #define ROSC_CAL_TRIG_BIT (1 << 11)
485 #define ROSC_CAL_EN_BIT (1 << 9) //confirmed by huaming
486
487 #define SCTRL_BIAS SCTRL_ANALOG_CTRL3
488 #define ROSC_CAL_MANU_FIN_POSI (23)
489 #define ROSC_CAL_MANU_FIN_MASK (0x1FF)
490 #define LDO_VAL_MANUAL_POSI (16)
491 #define LDO_VAL_MANUAL_MASK (0x1F)
492 #define BIAS_CAL_MANUAL_BIT (1 << 22)
493 #define BIAS_CAL_TRIGGER_BIT (1 << 21)
494
495 #define REG_GPIO_EXTRAL_INT_CFG (SCTRL_BASE + 42*4)
496 #define DPLL_UNLOCK_INT_EN (1 << 0)
497 #define AUDIO_DPLL_UNLOCK_INT_EN (1 << 1)
498
499 #define REG_GPIO_EXTRAL_INT_CFG1 (SCTRL_BASE + 43*4)
500 #define DPLL_UNLOCK_INT (1 << 0)
501 #define AUDIO_DPLL_UNLOCK_INT (1 << 1)
502 #define USB_PLUG_IN_INT_EN (1 << 4)
503 #define USB_PLUG_OUT_INT_EN (1 << 5)
504 #define USB_PLUG_IN_INT (1 << 6)
505 #define USB_PLUG_OUT_INT (1 << 7)
506 #define GPIO_EXTRAL_INT_MASK (DPLL_UNLOCK_INT | AUDIO_DPLL_UNLOCK_INT | USB_PLUG_IN_INT | USB_PLUG_OUT_INT)
507
508 #else
509 #define SCTRL_LOW_PWR_CLK (SCTRL_BASE + 64 * 4)
510 #define LPO_CLK_MUX_POSI (0)
511 #define LPO_CLK_MUX_MASK (0x3)
512 #define LPO_SRC_ROSC (0x0)
513 #define LPO_SRC_32K_XTAL (0x1)
514 #define LPO_SRC_32K_DIV (0x2)
515
516 #define DEEP_SLEEP_LPO_SRC LPO_SRC_32K_XTAL
517
518 #define SCTRL_SLEEP (SCTRL_BASE + 65 * 4)
519 #define PROCORE_DLY_POSI (20)
520 #define PROCORE_DLY_MASK (0xF)
521
522 #define GPIO_SLEEP_SWITCH_BIT (1 << 19)
523 #define DCO_PWD_SLEEP_BIT (1 << 17)
524 #define FLASH_PWD_SLEEP_BIT (1 << 18)
525
526 #define ROSC_PWD_DEEPSLEEP_BIT (1 << 16)
527 #define SLEEP_MODE_POSI (0)
528 #define SLEEP_MODE_MASK (0xFFFF)
529 #define SLEEP_MODE_CFG_NORMAL_VOL_WORD (0x4F89)
530 #define SLEEP_MODE_CFG_LOW_VOL_WORD (0xB706)
531 #define SLEEP_MODE_CFG_DEEP_WORD (0xADC1)
532
533 #define SCTRL_DIGTAL_VDD (SCTRL_BASE + 66 * 4)
534 #define DIG_VDD_ACTIVE_POSI (4)
535 #define DIG_VDD_ACTIVE_MASK (0x7)
536 #define DIG_VDD_SLEEP_POSI (0)
537 #define DIG_VDD_SLEEP_MASK (0x7)
538 #define VDD_1_DOT_51 (0x7)
539 #define VDD_1_DOT_38 (0x6)
540 #define VDD_1_DOT_25 (0x5)
541 #define VDD_1_DOT_12 (0x4)
542 #define VDD_0_DOT_99 (0x3)
543 #define VDD_0_DOT_86 (0x2)
544 #define VDD_0_DOT_73 (0x1)
545 #define VDD_0_DOT_60 (0x0)
546
547 #define SCTRL_PWR_MAC_MODEM (SCTRL_BASE + 67 * 4)
548 #define MAC_PWD_POSI (16)
549 #define MAC_PWD_MASK (0xFFFFU)
550 #define MODEM_PWD_POSI (0)
551 #define MODEM_PWD_MASK (0xFFFFU)
552 #define MAC_PWD (0xD802U)
553 #define MODEM_PWD (0xD802U)
554 #define MAC_PWU (0x0001U)
555 #define MODEM_PWU (0x0001U)
556
557 #define SCTRL_DSP_PWR (SCTRL_BASE + 68 * 4)
558 #define DSP_PWD_POSI (0)
559 #define DSP_PWD_MASK (0xFFFF)
560 #define DSP_PWD (0xD410)
561 #define DSP_PWU (0x0001)
562
563 #define SCTRL_USB_PWR (SCTRL_BASE + 69 * 4)
564 #define BLE_PWD_POSI (16)
565 #define BLE_PWD_MASK (0xFFFF)
566 #define BLE_PWD (0xDB1E)
567 #define BLE_PWU (0x0001)
568 #if (!CONFIG_SOC_BK7231N) && (!CONFIG_SOC_BK7236A) && (!CONFIG_SOC_BK7256XX) && (!CONFIG_SOC_BK7236)
569 #define USB_PWD_POSI (0)
570 #define USB_PWD_MASK (0xFFFF)
571 #define USB_PWD (0xD12B)
572 #define USB_PWU (0x0001)
573 #endif
574
575 #define SCTRL_PMU_STATUS (SCTRL_BASE + 70 * 4)
576 #define PMU_MAC_POWER_DOWN_BIT (1 << 3)
577 #define PMU_MODEM_POWER_DOWN_BIT (1 << 2)
578 #if (!CONFIG_SOC_BK7231N) && (!CONFIG_SOC_BK7236A) && (!CONFIG_SOC_BK7256XX) && (!CONFIG_SOC_BK7236)
579 #define PMU_DSP_POWER_DOWN_BIT (1 << 1)
580 #define PMU_USB_POWER_DOWN_BIT (1 << 0)
581 #endif
582
583 #define SCTRL_ROSC_TIMER (SCTRL_BASE + 71 * 4)
584 #define ROSC_TIMER_PERIOD_POSI (16)
585 #define ROSC_TIMER_PERIOD_MASK (0xFFFF)
586 #define ROSC_TIMER_INT_STATUS_BIT (1 << 8)
587 #define ROSC_TIMER_ENABLE_BIT (1 << 0)
588
589 #define SCTRL_GPIO_WAKEUP_EN (SCTRL_BASE + 72 * 4)
590 #define SCTRL_GPIO_WAKEUP_TYPE (SCTRL_BASE + 73 * 4)
591 #define SCTRL_GPIO_WAKEUP_INT_STATUS (SCTRL_BASE + 74 * 4)
592 #define GPIO_WAKEUP_ENABLE_FLAG (1)
593 #define GPIO_WAKEUP_TYPE_POSITIVE_EDGE (0)
594 #define GPIO_WAKEUP_TYPE_NEGATIVE_EDGE (1)
595
596 #if (!CONFIG_SOC_BK7231N) && (!CONFIG_SOC_BK7236A) && (!CONFIG_SOC_BK7256XX)
597 #define SCTRL_USB_PLUG_WAKEUP (SCTRL_BASE + 78 * 4)
598 #define USB_PLUG_IN_EN_BIT (1 << 0)
599 #define USB_PLUG_OUT_EN_BIT (1 << 1)
600 #define USB_PLUG_IN_INT_BIT (1 << 2)
601 #define USB_PLUG_OUT_INT_BIT (1 << 3)
602 #endif
603
604 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX)
605 #define SCTRL_GPIO_WAKEUP_TYPE_SELECT (SCTRL_BASE + 78 * 4)
606 #else
607 #define SCTRL_GPIO_WAKEUP_EN1 (SCTRL_BASE + 81 * 4)
608 #define SCTRL_GPIO_WAKEUP_TYPE1 (SCTRL_BASE + 82 * 4)
609 #define SCTRL_GPIO_WAKEUP_INT_STATUS1 (SCTRL_BASE + 83 * 4)
610 #endif
611
612 enum {
613 SYSCTRL_GPIO00_ID = 0,
614 SYSCTRL_GPIO01_ID,
615 SYSCTRL_GPIO02_ID,
616 SYSCTRL_GPIO03_ID,
617 SYSCTRL_GPIO04_ID,
618 SYSCTRL_GPIO05_ID,
619 SYSCTRL_GPIO06_ID,
620 SYSCTRL_GPIO07_ID,
621 SYSCTRL_GPIO08_ID,
622 SYSCTRL_GPIO09_ID,
623 SYSCTRL_GPIO10_ID,
624 SYSCTRL_GPIO11_ID,
625 SYSCTRL_GPIO12_ID,
626 SYSCTRL_GPIO13_ID,
627 SYSCTRL_GPIO14_ID,
628 SYSCTRL_GPIO15_ID,
629 SYSCTRL_GPIO16_ID,
630 SYSCTRL_GPIO17_ID,
631 SYSCTRL_GPIO18_ID,
632 SYSCTRL_GPIO19_ID,
633 SYSCTRL_GPIO20_ID,
634 SYSCTRL_GPIO21_ID,
635 SYSCTRL_GPIO22_ID,
636 SYSCTRL_GPIO23_ID,
637 SYSCTRL_GPIO24_ID,
638 SYSCTRL_GPIO25_ID,
639 SYSCTRL_GPIO26_ID,
640 SYSCTRL_GPIO27_ID,
641 SYSCTRL_GPIO28_ID,
642 SYSCTRL_GPIO29_ID,
643 SYSCTRL_GPIO30_ID,
644 SYSCTRL_GPIO31_ID
645 };
646
647
648 #define SCTRL_BLOCK_EN_CFG (SCTRL_BASE + 75 * 4)
649 #define BLOCK_EN_WORD_POSI (20)
650 #define BLOCK_EN_WORD_MASK (0xFFFUL)
651 #define BLOCK_EN_WORD_PWD (0xA5CUL)
652
653 #define BLOCK_EN_VALID_MASK (0xFFFFF)
654
655 #if (CONFIG_SOC_BK7231)
656 #define BLK_EN_BIT_LINEIN (1 << 19)
657 #define BLK_EN_MIC_R_CHANNEL (1 << 18)
658 #define BLK_EN_MIC_L_CHANNEL (1 << 17)
659 #define BLK_EN_AUDIO_R_CHANNEL (1 << 16)
660 #define BLK_EN_AUDIO_L_CHANNEL (1 << 15)
661 #elif (CONFIG_SOC_BK7231U) || (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX) || (CONFIG_SOC_BK7236)
662 #define BLK_EN_NC (1 << 19)
663 #define BLK_EN_MIC_QSPI_RAM_OR_FLASH (1 << 18)
664 #define BLK_EN_MIC_PGA (1 << 17)
665 #define BLK_EN_AUDIO_PLL (1 << 16)
666 #define BLK_EN_AUDIO_RANDOM_GENERATOR (1 << 15)
667 #elif (CONFIG_SOC_BK7251)
668 #define BLK_EN_NC (1 << 19)
669 #define BLK_EN_MIC_QSPI_RAM_OR_FLASH (1 << 18)
670 #define BLK_EN_AUDIO (1 << 17)
671 #define BLK_EN_AUDIO_PLL (1 << 16)
672 #define BLK_EN_AUDIO_RANDOM_GENERATOR (1 << 15)
673 #endif // (CONFIG_SOC_BK7231)
674
675 #define BLK_EN_SARADC (1 << 13)
676 #define BLK_EN_TEMPRATURE_SENSOR (1 << 12)
677 #define BLK_EN_26M_XTAL_LOW_POWER (1 << 11)
678 #define BLK_EN_XTAL2RF (1 << 10)
679 #define BLK_EN_IO_LDO_LOW_POWER (1 << 09)
680 #define BLK_EN_ANALOG_SYS_LDO (1 << 8)
681 #define BLK_EN_DIGITAL_CORE_LDO_LOW_POWER (1 << 07)
682 #define BLK_EN_DIGITAL_CORE (1 << 06)
683 #define BLK_EN_DPLL_480M (1 << 05)
684 #define BLK_EN_32K_XTAL (1 << 04)
685 #define BLK_EN_26M_XTAL (1 << 03)
686 #define BLK_EN_ROSC32K (1 << 02)
687 #define BLK_EN_DCO (1 << 01)
688 #define BLK_EN_FLASH (1 << 00)
689
690 #define SCTRL_BIAS (SCTRL_BASE + 76 * 4)
691 #define BIAS_CAL_OUT_POSI (16)
692 #define BIAS_CAL_OUT_MASK (0x1F)
693 #define LDO_VAL_MANUAL_POSI (8)
694 #define LDO_VAL_MANUAL_MASK (0x1F)
695 #define BIAS_CAL_MANUAL_BIT (1 << 4)
696 #define BIAS_CAL_TRIGGER_BIT (1 << 0)
697
698 #define SCTRL_ROSC_CAL (SCTRL_BASE + 77 * 4)
699 #define ROSC_CAL_MANU_FIN_POSI (22)
700 #define ROSC_CAL_MANU_FIN_MASK (0x1FF)
701 #define ROSC_CAL_MANU_CIN_POSI (17)
702 #define ROSC_CAL_MANU_CIN_MASK (0x1F)
703 #define ROSC_CAL_MANU_EN_BIT (1 << 16)
704 #define ROSC_CAL_INTVAL_POSI (4)
705 #define ROSC_CAL_INTVAL_MASK (0x7)
706 #define ROSC_CAL_MODE_BIT (1 << 2)
707 #define ROSC_CAL_TRIG_BIT (1 << 1)
708 #define ROSC_CAL_EN_BIT (1 << 0)
709
710 #define SCTRL_BLOCK_EN_MUX (SCTRL_BASE + 79 * 4)
711 #endif
712 #define SCTRL_ROSC_TIMER_H (SCTRL_BASE + 80 * 4)
713 #define ROSC_TIMER_H_PERIOD_POSI (0)
714 #define ROSC_TIMER_H_PERIOD_MASK (0xFFFF)
715
716 #define SCTRL_SW_RETENTION (SCTRL_BASE + 84 * 4)
717 #define DCO_CNTI_120M (0x127U) // set DCO out clk with 120M
718
719 #include "bk_arm_arch.h"
720
sctrl_analog_get(UINT32 address)721 __inline static UINT32 sctrl_analog_get(UINT32 address)
722 {
723 while (REG_READ(SCTRL_ANALOG_SPI) & (ANA_SPI_STAET_MASK << ANA_SPI_STATE_POSI));
724 return REG_READ(address);
725 }
726
sctrl_analog_set(UINT32 address,UINT32 value)727 __inline static void sctrl_analog_set(UINT32 address, UINT32 value)
728 {
729 REG_WRITE(address, value);
730 while (REG_READ(SCTRL_ANALOG_SPI) & (ANA_SPI_STAET_MASK << ANA_SPI_STATE_POSI));
731 }
732
733 typedef struct sctrl_ps_save_values {
734 UINT32 peri_clk_cfg;
735 UINT32 int_enable_cfg;
736 } SCTRL_PS_SAVE_VALUES;
737
738 #define PS_CLOSE_PERI_CLK 0
739
740 /*******************************************************************************
741 * Function Declarations
742 *******************************************************************************/
743 extern UINT32 sctrl_ctrl(UINT32 cmd, void *parm);
744 extern void sctrl_sub_reset(void);
745
746 #if CONFIG_BLE_PS
747 void sctrl_ble_ps_init(void);
748 #endif
749 #endif // _SCTRL_H_
750 // eof
751
752