1 /*
2 // Copyright (C) 2022 Beken Corporation
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15 #include <common/bk_include.h>
16 #include "bk_arm_arch.h"
17 #include "bk_sys_ctrl.h"
18 #include "sys_ctrl.h"
19 #include "sys_driver.h"
20 #include "bk_misc.h"
21 #include "bk_drv_model.h"
22 #include "bk_uart.h"
23 #if CONFIG_FLASH_ORIGIN_API
24 #include "bk_flash.h"
25 #endif
26 #include <driver/int.h>
27 #include "bk_icu.h"
28 #include "bk_gpio.h"
29 #include "reset_reason.h"
30 #include <os/os.h>
31
32 #if (!CONFIG_SOC_BK7256XX)
33
34 #if CONFIG_BLE
35 #include <modules/ble.h>
36 #endif
37 #if ((CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7256XX))
38 #define GPIO_WAKEUP_INT_BAK_ADDR (0x00808000)
39 #elif ((CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7236))
40 #define GPIO_WAKEUP_INT_BAK_ADDR (0x10E00000)
41 #elif (CONFIG_SOC_BK7256XX && CONFIG_SLAVE_CORE)
42 #define GPIO_WAKEUP_INT_BAK_ADDR (0x00808000)
43 #else
44 #define GPIO_WAKEUP_INT_BAK_ADDR (0x0080a084)
45 #endif
46 #define GPIO_WAKEUP_INT_STATUS_BAK (GPIO_WAKEUP_INT_BAK_ADDR + 0x1 * 4)
47 #define GPIO_WAKEUP_INT_STATUS1_BAK (GPIO_WAKEUP_INT_BAK_ADDR + 0x2 * 4)
48 #if CONFIG_SOC_BK7271
49 #include "pmu.h"
50 #endif
51
52 #include "bk_normal_sleep.h"
53 #include "bk_pm_control.h"
54
55 #define DPLL_DIV 0x0
56 #define DCO_CALIB_26M 0x1
57 #define DCO_CALIB_60M 0x2
58 #define DCO_CALIB_80M 0x3
59 #define DCO_CALIB_120M 0x4
60 #define DCO_CALIB_180M 0x5
61
62 #if (CONFIG_SOC_BK7271)
63 #define DCO_CALIB_240M 0x6
64 #define DCO_CLK_SELECT DCO_CALIB_240M
65 #define USE_DCO_CLK_POWON 0
66 #define SCTRL_AUDIO_PLL_SDM SCTRL_ANALOG_AUDIO_PLL_SDM
67 #define SCTRL_AUDIO_PLL_CTRL SCTRL_ANALOG_AUDIO_PLL_CTRL
68 #elif (CONFIG_SOC_BK7251)
69 #define DCO_CLK_SELECT DCO_CALIB_180M
70 #define USE_DCO_CLK_POWON 1
71
72 UINT8 calib_charger[3] = {
73 0x23, //vlcf
74 0x15, //icp
75 0x1b //vcv
76 };
77 #else
78 #define DCO_CLK_SELECT DCO_CALIB_120M
79 /* BK7231N could not using DCO as main clock when boot since DCO_AMSEL_BIT should be disable during calibration*/
80 #define USE_DCO_CLK_POWON 0
81 #endif
82
83 static SCTRL_PS_SAVE_VALUES ps_saves[2];
84
85 #if (CONFIG_DEEP_PS && PS_SUPPORT_MANUAL_SLEEP)
86 static UINT32 ps_block_value = 0;
87 #endif
88 #if CONFIG_DEEP_PS
89 static UINT32 deep_sleep_gpio_floating_map = 0;
90 static uint32_t gpio_0_31_status = 0;
91 #if (!CONFIG_SOC_BK7231N) && (!CONFIG_SOC_BK7236A) && (!CONFIG_SOC_BK7256XX)
92 static uint32_t gpio_32_39_status = 0;
93 static UINT32 deep_sleep_gpio_last_floating_map = 0;
94 #endif
95 #endif
96 #ifndef CONFIG_SOC_BK7256XX
97 static const DD_OPERATIONS sctrl_op = {
98 NULL,
99 NULL,
100 NULL,
101 NULL,
102 sctrl_ctrl
103 };
104 #endif
105 static sctrl_cal_bias_cb_t s_cal_bias_callback = NULL;
106 static sctrl_wifi_phy_wakeup_rf_reinit_cb_t s_wifi_phy_wakeup_rf_reinit_cb = NULL;
107 static sctrl_wifi_phy_wakeup_wifi_reinit_cb_t s_wifi_phy_wakeup_wifi_reinit_cb = NULL;
108
109 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7256XX)
110 void sctrl_fix_dpll_div(void);
111 #endif
112
113 /**********************************************************************/
114
sctrl_register_cal_bias_callback(sctrl_cal_bias_cb_t cb)115 void sctrl_register_cal_bias_callback(sctrl_cal_bias_cb_t cb)
116 {
117 s_cal_bias_callback = cb;
118 }
119
sctrl_register_wifi_phy_wakeup_rf_reinit_callback(sctrl_wifi_phy_wakeup_rf_reinit_cb_t cb)120 void sctrl_register_wifi_phy_wakeup_rf_reinit_callback(sctrl_wifi_phy_wakeup_rf_reinit_cb_t cb)
121 {
122 s_wifi_phy_wakeup_rf_reinit_cb = cb;
123 }
124
sctrl_register_wifi_phy_wakeup_wifi_reinit_callback(sctrl_wifi_phy_wakeup_wifi_reinit_cb_t cb)125 void sctrl_register_wifi_phy_wakeup_wifi_reinit_callback(sctrl_wifi_phy_wakeup_wifi_reinit_cb_t cb)
126 {
127 s_wifi_phy_wakeup_wifi_reinit_cb = cb;
128 }
129
sctrl_dpll_delay10us(void)130 void sctrl_dpll_delay10us(void)
131 {
132 volatile UINT32 i = 0;
133
134 for (i = 0; i < DPLL_DELAY_TIME_10US; i ++)
135 ;
136 }
137
sctrl_dpll_delay200us(void)138 void sctrl_dpll_delay200us(void)
139 {
140 volatile UINT32 i = 0;
141
142 for (i = 0; i < DPLL_DELAY_TIME_200US; i ++)
143 ;
144 }
145
sctrl_ps_dpll_delay(UINT32 time)146 void sctrl_ps_dpll_delay(UINT32 time)
147 {
148 volatile UINT32 i = 0;
149
150 for (i = 0; i < time; i ++)
151 ;
152 }
153
sctrl_cali_dpll(UINT8 flag)154 void sctrl_cali_dpll(UINT8 flag)
155 {
156 UINT32 param;
157
158 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX)
159 extern void bk7011_update_tx_power_when_cal_dpll(int start_or_stop);
160
161 bk7011_update_tx_power_when_cal_dpll(1);
162 #endif
163 param = sctrl_analog_get(SCTRL_ANALOG_CTRL0);
164 param &= ~(SPI_TRIG_BIT);
165 sctrl_analog_set(SCTRL_ANALOG_CTRL0, param);
166
167 if (!flag)
168 sctrl_dpll_delay10us();
169 else
170 sctrl_ps_dpll_delay(60);
171
172 param |= (SPI_TRIG_BIT);
173 sctrl_analog_set(SCTRL_ANALOG_CTRL0, param);
174
175 param = sctrl_analog_get(SCTRL_ANALOG_CTRL0);
176 param &= ~(SPI_DET_EN);
177 sctrl_analog_set(SCTRL_ANALOG_CTRL0, param);
178
179 if (!flag)
180 sctrl_dpll_delay200us();
181 else
182 sctrl_ps_dpll_delay(340);
183
184 param = sctrl_analog_get(SCTRL_ANALOG_CTRL0);
185 param |= (SPI_DET_EN);
186 sctrl_analog_set(SCTRL_ANALOG_CTRL0, param);
187
188 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX)
189 bk7011_update_tx_power_when_cal_dpll(0);
190 #endif
191 }
192
sctrl_dpll_isr(void)193 void sctrl_dpll_isr(void)
194 {
195 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7256XX)
196 if ((DEVICE_ID_BK7231N_P & DEVICE_ID_MASK) != (sctrl_ctrl(CMD_GET_DEVICE_ID, NULL) & DEVICE_ID_MASK))
197 {
198 os_printf("BIAS Cali\r\n");
199 if (s_cal_bias_callback) {
200 s_cal_bias_callback();
201 }
202 }
203 #elif (CONFIG_SOC_BK7236A)
204 os_printf("BIAS Cali\r\n");
205 if (s_cal_bias_callback) {
206 s_cal_bias_callback();
207 }
208 #endif
209 sddev_control(DD_DEV_TYPE_GPIO, CMD_GPIO_CLR_DPLL_UNLOOK_INT_BIT, NULL);
210 sctrl_cali_dpll(0);
211
212 os_printf("DPLL Unlock\r\n");
213 }
214
sctrl_dpll_int_open(void)215 void sctrl_dpll_int_open(void)
216 {
217 UINT32 param;
218
219 param = (FIQ_DPLL_UNLOCK_BIT);
220 #if (CONFIG_SOC_BK7271)
221 // sddev_control(DD_DEV_TYPE_ICU, CMD_ICU_FIQ_ENABLE, ¶m);
222 (void)sys_drv_fiq_enable(param);
223 #else
224 // sddev_control(DD_DEV_TYPE_ICU, CMD_ICU_INT_ENABLE, ¶m);
225 (void)sys_drv_int_enable(param);
226 #endif
227
228 #if (!CONFIG_SOC_BK7231)
229 param = 1;
230 sddev_control(DD_DEV_TYPE_GPIO, CMD_GPIO_EN_DPLL_UNLOOK_INT, ¶m);
231 #endif
232 }
233
sctrl_dpll_int_close(void)234 void sctrl_dpll_int_close(void)
235 {
236 UINT32 param;
237
238 #if (!CONFIG_SOC_BK7231)
239 param = 0;
240 sddev_control(DD_DEV_TYPE_GPIO, CMD_GPIO_EN_DPLL_UNLOOK_INT, ¶m);
241 #endif
242
243 param = (FIQ_DPLL_UNLOCK_BIT);
244 #if (CONFIG_SOC_BK7271)
245 // sddev_control(DD_DEV_TYPE_ICU, CMD_ICU_FIQ_DISABLE, ¶m);
246 (void)sys_drv_fiq_disable(param);
247 #else
248 // sddev_control(DD_DEV_TYPE_ICU, CMD_ICU_INT_DISABLE, ¶m);
249 (void)sys_drv_int_disable(param);
250 #endif
251 }
clock_dco_cali(UINT32 speed)252 void clock_dco_cali(UINT32 speed)
253 {
254 UINT32 reg_val;
255
256 switch (speed) {
257 #if (CONFIG_SOC_BK7271)
258 case DCO_CALIB_240M:
259 reg_val = sys_drv_analog_get(ANALOG_REG1);
260 reg_val &= ~((DCO_CNTI_MASK << DCO_CNTI_POSI) | (DCO_DIV_MASK << DCO_DIV_POSI));
261 reg_val |= ((0x127 & DCO_CNTI_MASK) << DCO_CNTI_POSI);
262 reg_val |= DIV_BYPASS_BIT;
263 sys_drv_analog_set(ANALOG_REG1, reg_val);
264 break;
265 #endif
266
267 case DCO_CALIB_180M:
268 reg_val = sys_drv_analog_get(ANALOG_REG1);
269 reg_val &= ~((DCO_CNTI_MASK << DCO_CNTI_POSI) | (DCO_DIV_MASK << DCO_DIV_POSI));
270 reg_val |= ((0xDD & DCO_CNTI_MASK) << DCO_CNTI_POSI);
271 #if (!CONFIG_SOC_BK7231N) && (!CONFIG_SOC_BK7236A) && (!CONFIG_SOC_BK7256XX) && (!CONFIG_SOC_BK7236)
272 reg_val |= DIV_BYPASS_BIT;
273 #endif
274 sys_drv_analog_set(ANALOG_REG1, reg_val);
275 break;
276
277 case DCO_CALIB_120M:
278 reg_val = sys_drv_analog_get(ANALOG_REG1);
279 reg_val &= ~((DCO_CNTI_MASK << DCO_CNTI_POSI) | (DCO_DIV_MASK << DCO_DIV_POSI));
280 reg_val |= ((0x127 & DCO_CNTI_MASK) << DCO_CNTI_POSI);
281 sys_drv_analog_set(ANALOG_REG1, reg_val);
282 break;
283
284 case DCO_CALIB_80M:
285 reg_val = sctrl_analog_get(ANALOG_REG1);
286 reg_val &= ~((DCO_CNTI_MASK << DCO_CNTI_POSI) | (DCO_DIV_MASK << DCO_DIV_POSI));
287 reg_val |= ((0x0C5 & DCO_CNTI_MASK) << DCO_CNTI_POSI);
288 sys_drv_analog_set(ANALOG_REG1, reg_val);
289 break;
290
291 case DCO_CALIB_60M:
292 reg_val = sys_drv_analog_get(ANALOG_REG1);
293 reg_val &= ~((DCO_CNTI_MASK << DCO_CNTI_POSI) | (DCO_DIV_MASK << DCO_DIV_POSI));
294 reg_val |= ((0x127 & DCO_CNTI_MASK) << DCO_CNTI_POSI);
295 reg_val |= ((0x02 & DCO_DIV_MASK) << DCO_DIV_POSI);
296 sys_drv_analog_set(ANALOG_REG1, reg_val);
297 break;
298
299 default:
300 reg_val = sys_drv_analog_get(ANALOG_REG1);
301 reg_val &= ~((DCO_CNTI_MASK << DCO_CNTI_POSI) | (DCO_DIV_MASK << DCO_DIV_POSI));
302 reg_val |= ((0xC0 & DCO_CNTI_MASK) << DCO_CNTI_POSI);
303 reg_val |= ((0x03 & DCO_DIV_MASK) << DCO_DIV_POSI);
304 sys_drv_analog_set(ANALOG_REG1, reg_val);
305 break;
306 }
307
308 reg_val = sys_drv_analog_get(ANALOG_REG1);
309 reg_val &= ~(SPI_RST_BIT);
310 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX)
311 reg_val &= ~(DCO_AMSEL_BIT);
312 #endif
313 sys_drv_analog_set(ANALOG_REG1, reg_val);
314
315 reg_val = sys_drv_analog_get(ANALOG_REG1);
316 reg_val |= SPI_RST_BIT;
317 sys_drv_analog_set(ANALOG_REG1, reg_val);
318
319 reg_val = sys_drv_analog_get(ANALOG_REG1);
320 reg_val |= DCO_TRIG_BIT;
321 sys_drv_analog_set(ANALOG_REG1, reg_val);
322
323 reg_val = sys_drv_analog_get(ANALOG_REG1);
324 reg_val &= ~(DCO_TRIG_BIT);
325 sys_drv_analog_set(ANALOG_REG1, reg_val);
326 }
sctrl_dco_cali(UINT32 speed)327 void sctrl_dco_cali(UINT32 speed)
328 {
329 UINT32 reg_val;
330
331 switch (speed) {
332 #if (CONFIG_SOC_BK7271)
333 case DCO_CALIB_240M:
334 reg_val = sctrl_analog_get(SCTRL_ANALOG_CTRL1);
335 reg_val &= ~((DCO_CNTI_MASK << DCO_CNTI_POSI) | (DCO_DIV_MASK << DCO_DIV_POSI));
336 reg_val |= ((0x127 & DCO_CNTI_MASK) << DCO_CNTI_POSI);
337 reg_val |= DIV_BYPASS_BIT;
338 sctrl_analog_set(SCTRL_ANALOG_CTRL1, reg_val);
339 break;
340 #endif
341
342 case DCO_CALIB_180M:
343 reg_val = sctrl_analog_get(SCTRL_ANALOG_CTRL1);
344 reg_val &= ~((DCO_CNTI_MASK << DCO_CNTI_POSI) | (DCO_DIV_MASK << DCO_DIV_POSI));
345 reg_val |= ((0xDD & DCO_CNTI_MASK) << DCO_CNTI_POSI);
346 #if (!CONFIG_SOC_BK7231N) && (!CONFIG_SOC_BK7236A) && (!CONFIG_SOC_BK7256XX) && (!CONFIG_SOC_BK7236)
347 reg_val |= DIV_BYPASS_BIT;
348 #endif
349 sctrl_analog_set(SCTRL_ANALOG_CTRL1, reg_val);
350 break;
351
352 case DCO_CALIB_120M:
353 reg_val = sctrl_analog_get(SCTRL_ANALOG_CTRL1);
354 reg_val &= ~((DCO_CNTI_MASK << DCO_CNTI_POSI) | (DCO_DIV_MASK << DCO_DIV_POSI));
355 reg_val |= ((0x127 & DCO_CNTI_MASK) << DCO_CNTI_POSI);
356 sctrl_analog_set(SCTRL_ANALOG_CTRL1, reg_val);
357 break;
358
359 case DCO_CALIB_80M:
360 reg_val = sctrl_analog_get(SCTRL_ANALOG_CTRL1);
361 reg_val &= ~((DCO_CNTI_MASK << DCO_CNTI_POSI) | (DCO_DIV_MASK << DCO_DIV_POSI));
362 reg_val |= ((0x0C5 & DCO_CNTI_MASK) << DCO_CNTI_POSI);
363 sctrl_analog_set(SCTRL_ANALOG_CTRL1, reg_val);
364 break;
365
366 case DCO_CALIB_60M:
367 reg_val = sctrl_analog_get(SCTRL_ANALOG_CTRL1);
368 reg_val &= ~((DCO_CNTI_MASK << DCO_CNTI_POSI) | (DCO_DIV_MASK << DCO_DIV_POSI));
369 reg_val |= ((0x127 & DCO_CNTI_MASK) << DCO_CNTI_POSI);
370 reg_val |= ((0x02 & DCO_DIV_MASK) << DCO_DIV_POSI);
371 sctrl_analog_set(SCTRL_ANALOG_CTRL1, reg_val);
372 break;
373
374 default:
375 reg_val = sctrl_analog_get(SCTRL_ANALOG_CTRL1);
376 reg_val &= ~((DCO_CNTI_MASK << DCO_CNTI_POSI) | (DCO_DIV_MASK << DCO_DIV_POSI));
377 reg_val |= ((0xC0 & DCO_CNTI_MASK) << DCO_CNTI_POSI);
378 reg_val |= ((0x03 & DCO_DIV_MASK) << DCO_DIV_POSI);
379 sctrl_analog_set(SCTRL_ANALOG_CTRL1, reg_val);
380 break;
381 }
382
383 reg_val = sctrl_analog_get(SCTRL_ANALOG_CTRL1);
384 reg_val &= ~(SPI_RST_BIT);
385 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX)
386 reg_val &= ~(DCO_AMSEL_BIT);
387 #endif
388 sctrl_analog_set(SCTRL_ANALOG_CTRL1, reg_val);
389
390 reg_val = sctrl_analog_get(SCTRL_ANALOG_CTRL1);
391 reg_val |= SPI_RST_BIT;
392 sctrl_analog_set(SCTRL_ANALOG_CTRL1, reg_val);
393
394 reg_val = sctrl_analog_get(SCTRL_ANALOG_CTRL1);
395 reg_val |= DCO_TRIG_BIT;
396 sctrl_analog_set(SCTRL_ANALOG_CTRL1, reg_val);
397
398 reg_val = sctrl_analog_get(SCTRL_ANALOG_CTRL1);
399 reg_val &= ~(DCO_TRIG_BIT);
400 sctrl_analog_set(SCTRL_ANALOG_CTRL1, reg_val);
401 }
402
sctrl_set_cpu_clk_dco(void)403 void sctrl_set_cpu_clk_dco(void)
404 {
405 UINT32 reg_val;
406
407 reg_val = REG_READ(SCTRL_CONTROL);
408 reg_val &= ~(MCLK_DIV_MASK << MCLK_DIV_POSI);
409 reg_val &= ~(MCLK_MUX_MASK << MCLK_MUX_POSI);
410
411 reg_val |= ((MCLK_FIELD_DCO & MCLK_MUX_MASK) << MCLK_MUX_POSI);
412 reg_val |= HCLK_DIV2_EN_BIT;
413
414 REG_WRITE(SCTRL_CONTROL, reg_val);
415 delay(10);
416
417 }
418
419
sctrl_ble_ps_init(void)420 void sctrl_ble_ps_init(void)
421 {
422 }
423
sctrl_mac_ahb_slave_clock_enable(void)424 static void sctrl_mac_ahb_slave_clock_enable(void)
425 {
426 UINT32 reg;
427 #if (CONFIG_SOC_BK7271)
428 reg = REG_READ(SCTRL_CONTROL);
429 REG_WRITE(SCTRL_CONTROL, reg | MAC_HCLK_EN_BIT);
430 #else
431 reg = REG_READ(SCTRL_MODEM_CORE_RESET_PHY_HCLK);
432 REG_WRITE(SCTRL_MODEM_CORE_RESET_PHY_HCLK, reg | MAC_HCLK_EN_BIT);
433 #endif
434 }
435
sctrl_mac_ahb_slave_clock_disable(void)436 void sctrl_mac_ahb_slave_clock_disable(void)
437 {
438 UINT32 reg;
439 #if (CONFIG_SOC_BK7271)
440 reg = REG_READ(SCTRL_CONTROL);
441 reg &= ~MAC_HCLK_EN_BIT;
442 REG_WRITE(SCTRL_CONTROL, reg);
443 #else
444 reg = REG_READ(SCTRL_MODEM_CORE_RESET_PHY_HCLK);
445 reg &= ~MAC_HCLK_EN_BIT;
446 REG_WRITE(SCTRL_MODEM_CORE_RESET_PHY_HCLK, reg);
447 #endif
448 }
449 #ifndef CONFIG_SOC_BK7256XX
sctrl_init(void)450 void sctrl_init(void)
451 {
452 UINT32 param;
453
454 #if (CONFIG_SOC_BK7271)
455 /* told by huaming to avoid reset */
456 addGPIO_Reg0xf = 0x38;
457 //set link bus clock, DPLL div 4
458 param = REG_READ(LBUS_CONF1_REG);
459 param &= ~0x7;
460 param |= 0x7;
461 REG_WRITE(LBUS_CONF1_REG, param);
462 #endif
463
464 sddev_register_dev(DD_DEV_TYPE_SCTRL, (DD_OPERATIONS *)&sctrl_op);
465
466 /*enable blk clk
467 Attention: ENABLE 26m xtal block(BLK_BIT_26M_XTAL), for protect 32k circuit
468 */
469 param = BLK_BIT_26M_XTAL | BLK_BIT_DPLL_480M | BLK_BIT_XTAL2RF | BLK_BIT_DCO;
470 #if (CONFIG_SOC_BK7271)
471 param |= BLK_BIT_AUDIO_PLL;
472 #endif
473 sctrl_ctrl(CMD_SCTRL_BLK_ENABLE, ¶m);
474
475 /*config main clk*/
476 #if !USE_DCO_CLK_POWON
477 param = REG_READ(SCTRL_CONTROL);
478 param &= ~(MCLK_DIV_MASK << MCLK_DIV_POSI);
479 param &= ~(MCLK_MUX_MASK << MCLK_MUX_POSI);
480
481 #if (CONFIG_SOC_BK7271)
482 param &= ~(HCLK_DIV2_MASK << HCLK_DIV2_POSI);
483 param |= HCLK_DIV2_EN_BIT;
484 param &= ~(MTB_PRIVILEGE_MASK << MTB_PRIVILEGE_POSI);
485 param |= (MTB_PRIVILEGE_ACCESS_AHB << MTB_PRIVILEGE_POSI);
486 #elif (CONFIG_SOC_BK7251)
487 /* BK7221U ahb bus max rate is 90MHZ, so ahb bus need div 2 from MCU clock */
488 /* AHB bus is very import to AUDIO and DMA */
489 param |= HCLK_DIV2_EN_BIT;
490 #endif // (CONFIG_SOC_BK7251)
491
492 #if CONFIG_SYS_REDUCE_NORMAL_POWER
493 param |= ((MCLK_DIV_7 & MCLK_DIV_MASK) << MCLK_DIV_POSI);
494 #elif (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7256XX)
495 param |= ((MCLK_DIV_5 & MCLK_DIV_MASK) << MCLK_DIV_POSI);
496 #elif (CONFIG_SOC_BK7271)
497 param |= ((MCLK_DIV_3 & MCLK_DIV_MASK) << MCLK_DIV_POSI);
498 #elif (CONFIG_SOC_BK7236A)
499 // for bk7236, no less than 60MHZ, it better 80M above, here set 120M for debug
500 param |= ((MCLK_DIV_3 & MCLK_DIV_MASK) << MCLK_DIV_POSI);
501 #else // CONFIG_SYS_REDUCE_NORMAL_POWER
502 param |= ((MCLK_DIV_3 & MCLK_DIV_MASK) << MCLK_DIV_POSI);
503 #endif // CONFIG_SYS_REDUCE_NORMAL_POWER
504
505 param |= ((MCLK_FIELD_DPLL & MCLK_MUX_MASK) << MCLK_MUX_POSI);
506
507 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX)
508 param |= (BLE_RF_PTA_EN_BIT);
509 #endif
510 REG_WRITE(SCTRL_CONTROL, param);
511 #endif // (!USE_DCO_CLK_POWON)
512
513 /*sys_ctrl <0x4c> */
514 #if (CONFIG_SOC_BK7271)
515 param = (0x17 << LDO_VAL_MANUAL_POSI) | (BIAS_CAL_MANUAL_BIT);//0x00151510; LDO BIAS CALIBRATION
516 #else
517 param = 0x00171710;//0x00151510; LDO BIAS CALIBRATION
518 #endif
519 REG_WRITE(SCTRL_BIAS, param);
520
521 /*mac & modem power up */
522 #if (CONFIG_SOC_BK7271)
523 sctrl_ctrl(CMD_SCTRL_DSP_POWERUP, NULL);
524 sctrl_ctrl(CMD_SCTRL_BT_POWERUP, NULL);
525 sctrl_ctrl(CMD_SCTRL_LBUS_POWERUP, NULL);
526 #else
527 sctrl_ctrl(CMD_SCTRL_MAC_POWERUP, NULL);
528 #endif
529 sctrl_ctrl(CMD_SCTRL_MODEM_POWERUP, NULL);
530
531 /*sys_ctrl <0x16>, trig spi */
532 //170209,from 0x819A54B to 0x819A55B for auto detect dpll unlock
533 //170614 from 0x819A55B to 0x819A59B for more easy to trigger
534 //181101 xamp:0xf-0 for xtal may dead
535 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX)
536 #if (CONFIG_XTAL_FREQ_40M)
537 param = 0x71125B57;
538 #else
539 param = 0x71104953;//wangjian20200918 Reg0x16<3:1>=1 Reg0x16<9>=0 Reg0x16<13:10>=2
540 #endif
541 #elif (CONFIG_SOC_BK7271)
542 param = 0x61105B57;
543 #else
544 param = 0x819A59B;
545 #endif
546 sctrl_analog_set(SCTRL_ANALOG_CTRL0, param);
547
548 sctrl_cali_dpll(0);
549
550 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX)
551 param = 0x3CC019C2;//wangjian20200918 Reg0x17<1>=1
552 /* BK7271: 0x17[28:26] sw_c<2:0> 0 R/W DCO Frequency Triming; 000=freq max; 111=freq min; */
553 #elif (CONFIG_SOC_BK7271)
554 param = 0x70C03902;
555 #else
556 param = 0x6AC03102;
557 #endif
558
559 sctrl_analog_set(SCTRL_ANALOG_CTRL1, param);
560 /*do dco Calibration*/
561 sctrl_dco_cali(DCO_CLK_SELECT);
562 #if USE_DCO_CLK_POWON
563 sctrl_set_cpu_clk_dco();
564 #endif
565
566 #if (CONFIG_SOC_BK7231)
567 param = 0x24006000;
568 #elif (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7256XX)
569 if ((DEVICE_ID_BK7231N_P & DEVICE_ID_MASK) == (sctrl_ctrl(CMD_GET_DEVICE_ID, NULL) & DEVICE_ID_MASK))
570 {
571 param = 0x580020E2;//wangjian20210422<28:23>=30 as default for BK7231P
572 }
573 else
574 {
575 param = 0x500020E2;//0x400020E0; //wangjian20200822 0x40032030->0x48032030->0x48022032//wangjian20200903<17:16>=0//qunshan20201127<28:23>=20
576 }
577 #elif (CONFIG_SOC_BK7236A)
578 param = 0x500020E2;//0x400020E0; //wangjian20200822 0x40032030->0x48032030->0x48022032//wangjian20200903<17:16>=0//qunshan20201127<28:23>=20
579 #elif (CONFIG_SOC_BK7271)
580 param = 0x80208B00; //for 32k if enable BLK_BIT_ROSC32K
581 #else
582 param = 0x24006080; // xtalh_ctune // 24006080
583 param &= ~(XTALH_CTUNE_MASK << XTALH_CTUNE_POSI);
584 param |= ((0x10 & XTALH_CTUNE_MASK) << XTALH_CTUNE_POSI);
585 #endif // (CONFIG_SOC_BK7231)
586
587 sctrl_analog_set(SCTRL_ANALOG_CTRL2, param);
588
589 #if (CONFIG_SOC_BK7251)
590 param = CHARGE_ANALOG_CTRL3_CHARGE_DEFAULT_VALUE;
591 #elif (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX)
592 param = 0x70000000; //wangjiang20200822 0x00000000->0x70000000
593 #elif (CONFIG_SOC_BK7271)
594 param = 0x004CA800;
595 #else
596 param = 0x4FE06C50;
597 #endif
598 sctrl_analog_set(SCTRL_ANALOG_CTRL3, param);
599
600 /*sys_ctrl <0x1a> */
601 #if (CONFIG_SOC_BK7231)
602 param = 0x59E04520;
603 #elif (CONFIG_SOC_BK7251)
604 param = CHARGE_ANALOG_CTRL4_CAL_DEFAULT_VALUE;
605 #elif (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX)
606 param = 0x19C04520;
607 #elif (CONFIG_SOC_BK7271)
608 param = 0x800C1000;
609 #else
610 param = 0x59C04520; // 0x59E04520
611 #endif // (CONFIG_SOC_BK7231)
612 sctrl_analog_set(SCTRL_ANALOG_CTRL4, param);
613
614 /*regist intteruppt handler for Dpll unlock*/
615 bk_int_isr_register(INT_SRC_PLL_UNLOCK, sctrl_dpll_isr, NULL);
616
617 sctrl_sub_reset();
618
619 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7256XX)
620 if ((DEVICE_ID_BK7231N_P & DEVICE_ID_MASK) != (sctrl_ctrl(CMD_GET_DEVICE_ID, NULL) & DEVICE_ID_MASK)) {
621 sctrl_fix_dpll_div();
622 }
623 #endif
624
625 /*sys ctrl clk gating, for rx dma dead*/
626 REG_WRITE(SCTRL_CLK_GATING, 0x3f);
627
628 /* increase VDD voltage*/
629 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX)
630 param = 4;//wyg// original=3
631 #elif CONFIG_SYS_REDUCE_NORMAL_POWER
632 param = 4;
633 #else
634 param = 5;
635 #endif
636 sctrl_ctrl(CMD_SCTRL_SET_VDD_VALUE, ¶m);
637
638 /*32K Rosc calib*/
639 #if (CONFIG_SOC_BK7271)
640 REG_WRITE(SCTRL_ROSC_CAL, 0x80208B00);
641 #else
642 REG_WRITE(SCTRL_ROSC_CAL, 0x7);
643 #endif
644
645 #if (CONFIG_AUDIO)
646 #if (CONFIG_SOC_BK7251)
647 sctrl_analog_set(SCTRL_ANALOG_CTRL8, 0x0033587C);
648 sctrl_analog_set(SCTRL_ANALOG_CTRL9, 0x82204607);
649 sctrl_analog_set(SCTRL_ANALOG_CTRL10, 0x80801027);
650 #elif (CONFIG_SOC_BK7271)
651 sctrl_analog_set(SCTRL_ANALOG_CTRL5, 0x12A00000);
652 sctrl_analog_set(SCTRL_ANALOG_CTRL6, 0x0009A7F0);
653 sctrl_analog_set(SCTRL_ANALOG_CTRL8_REAL, 0x84200461);
654 sctrl_analog_set(SCTRL_ANALOG_CTRL9_REAL, 0x3CEF9A5F);
655 sctrl_analog_set(SCTRL_ANALOG_CTRL8, 0x000A0877);
656 sctrl_analog_set(SCTRL_ANALOG_CTRL9, 0x84400000);
657 sctrl_analog_set(SCTRL_ANALOG_CTRL10, 0x80800200);
658 sctrl_analog_set(SCTRL_ANALOG_CTRL13, 0x21084000);
659 sctrl_analog_set(SCTRL_ANALOG_AUDIO_PLL_CTRL, 0x00B09350);
660
661 //rtc init
662 addPMU_Reg0xd = 681800000; //from 2000-01-01. date(2000-01-01)=730486
663 addPMU_Reg0xf = 0x1;
664 #endif // (CONFIG_SOC_BK7251)
665 #endif // CONFIG_AUDIO
666
667 sctrl_mac_ahb_slave_clock_enable();
668 //rf_ps_init();
669 }
670
671 #endif
sctrl_exit(void)672 void sctrl_exit(void)
673 {
674 sddev_unregister_dev(DD_DEV_TYPE_SCTRL);
675 }
676
sctrl_modem_core_reset(void)677 void sctrl_modem_core_reset(void)
678 {
679 sctrl_ctrl(CMD_SCTRL_MODEM_CORE_RESET, 0);
680 }
681
sctrl_sub_reset(void)682 void sctrl_sub_reset(void)
683 {
684 sctrl_ctrl(CMD_SCTRL_MPIF_CLK_INVERT, 0);
685 sctrl_ctrl(CMD_SCTRL_MODEM_CORE_RESET, 0);
686 sctrl_ctrl(CMD_SCTRL_MODEM_SUBCHIP_RESET, 0);
687 sctrl_ctrl(CMD_SCTRL_MAC_SUBSYS_RESET, 0);
688 sctrl_ctrl(CMD_SCTRL_USB_SUBSYS_RESET, 0);
689 }
690
691
ps_delay(volatile UINT16 times)692 void ps_delay(volatile UINT16 times)
693 {
694 UINT32 delay = times;
695 while (delay--) ;
696 }
697
698 //////////////////////////////////////////////////////////////////////////
699
sctrl_ps_dump()700 void sctrl_ps_dump()
701 {
702 UINT32 i;
703
704 os_printf("reg dump\r\n");
705 os_printf("sys\r\n0x%8x:0x%8x\r\n", SCTRL_CONTROL, REG_READ(SCTRL_CONTROL));
706 os_printf("0x%8x:0x%8x\r\n", SCTRL_MODEM_CORE_RESET_PHY_HCLK, REG_READ(SCTRL_MODEM_CORE_RESET_PHY_HCLK));
707 os_printf("0x%8x:0x%8x\r\n", SCTRL_BLOCK_EN_CFG, REG_READ(SCTRL_BLOCK_EN_CFG));
708 os_printf("0x%8x:0x%8x\r\n", SCTRL_ROSC_CAL, REG_READ(SCTRL_ROSC_CAL));
709 os_printf("0x%8x:0x%8x\r\n", SCTRL_ANALOG_CTRL2, sctrl_analog_get(SCTRL_ANALOG_CTRL2));
710 //os_printf("0x%8x:0x%8x\r\n", ICU_R_INT_EN, REG_READ(ICU_R_INT_EN));
711 //os_printf("0x%8x:0x%8x\r\n", ICU_PERI_CLK_PWD, REG_READ(ICU_PERI_CLK_PWD));
712 os_printf("0x%8x:0x%8x\r\n", SCTRL_SLEEP, REG_READ(SCTRL_SLEEP));
713 //os_printf("0x%8x:0x%8x\r\n", ICU_R_ARM_WAKEUP_EN, REG_READ(ICU_R_ARM_WAKEUP_EN));
714 // bk_wifi_dump_ps_regs();
715 os_printf("saves dump\r\n");
716
717 for (i = 0; i < (3 * (sizeof(SCTRL_PS_SAVE_VALUES) / 4)); i++)
718 os_printf(" %d 0x%x\r\n", i, *((UINT32 *)(&ps_saves) + i));
719 }
720 #if 0
721 void sctrl_hw_sleep(UINT32 peri_clk)
722 {
723 #if (!CONFIG_SOC_BK7271)
724 uint32_t param, c_mclk_mux;
725
726 //os_printf("h s\r\n");
727 PS_DEBUG_HWDOWN_TRIGER;
728
729 UINT32 reg;
730 sctrl_ctrl(CMD_SCTRL_MCLK_MUX_GET, &c_mclk_mux);
731
732 param = (FIQ_DPLL_UNLOCK_BIT);
733 sddev_control(DD_DEV_TYPE_ICU, CMD_ICU_INT_DISABLE, ¶m);
734
735 PS_DEBUG_HWDOWN_TRIGER;
736
737 #if ((CONFIG_SOC_BK7231) || (CONFIG_SOC_BK7231U) || (CONFIG_SOC_BK7251))
738 REG_WRITE(SCTRL_ROSC_CAL, 0x35);
739 REG_WRITE(SCTRL_ROSC_CAL, 0x37);
740 #endif
741
742 if (c_mclk_mux != MCLK_SELECT_DCO) {
743 /* MCLK(main clock) select:dco*/
744 reg = REG_READ(SCTRL_CONTROL);
745 reg &= ~(MCLK_DIV_MASK << MCLK_DIV_POSI);
746 reg |= ((MCLK_DIV_1 & MCLK_DIV_MASK) << MCLK_DIV_POSI);
747 reg &= ~(MCLK_MUX_MASK << MCLK_MUX_POSI);
748 REG_WRITE(SCTRL_CONTROL, reg);
749 PS_DEBUG_HWDOWN_TRIGER;
750 }
751
752 /*close 32K Rosc calib*/
753 #if (CONFIG_SOC_BK7231)
754 REG_WRITE(SCTRL_ROSC_CAL, 0x36);
755 #endif
756 PS_DEBUG_HWDOWN_TRIGER;
757 /* dpll division reset*/
758 reg = REG_READ(SCTRL_CONTROL);
759 reg |= DPLL_CLKDIV_RESET_BIT;
760 REG_WRITE(SCTRL_CONTROL, reg);
761 PS_DEBUG_HWDOWN_TRIGER;
762 /* dpll (480m) & xtal2rf disable*/
763 reg = REG_READ(SCTRL_BLOCK_EN_CFG);
764 reg &= ~(BLOCK_EN_WORD_MASK << BLOCK_EN_WORD_POSI);
765 reg = reg | (BLOCK_EN_WORD_PWD << BLOCK_EN_WORD_POSI);
766 reg &= ~(BLK_EN_DPLL_480M | BLK_EN_XTAL2RF);
767 REG_WRITE(SCTRL_BLOCK_EN_CFG, reg);
768 PS_DEBUG_HWDOWN_TRIGER;
769 #if (!CONFIG_SOC_BK7251)
770 /* center bias power down*/
771 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL2);
772 reg &= (~(CENTRAL_BAIS_ENABLE_BIT));
773 sctrl_analog_set(SCTRL_ANALOG_CTRL2, reg);
774 #endif
775
776 #if (!CONFIG_SOC_BK7251)
777 while (sctrl_analog_get(SCTRL_ANALOG_CTRL2) & (CENTRAL_BAIS_ENABLE_BIT));
778 #endif
779
780 #if PS_CLOSE_PERI_CLK
781 /* close all peri clock*/
782 ps_saves[0].peri_clk_cfg = REG_READ(ICU_PERI_CLK_PWD);
783 REG_WRITE(ICU_PERI_CLK_PWD, peri_clk);
784 #endif
785
786 ps_delay(1);
787 PS_DEBUG_HWDOWN_TRIGER;
788
789 /* arm clock disable */
790 reg = REG_READ(SCTRL_SLEEP);
791 reg &= ~(SLEEP_MODE_MASK << SLEEP_MODE_POSI);
792 reg = reg | SLEEP_MODE_CFG_NORMAL_VOL_WORD;
793 REG_WRITE(SCTRL_SLEEP, reg);
794 ps_delay(1);//5
795
796 #endif
797 }
798
799 void sctrl_hw_wakeup(void)
800 {
801 #if (!CONFIG_SOC_BK7271)
802 uint32_t c_mclk_mux;
803 UINT32 reg;
804
805 PS_DEBUG_HWUP_TRIGER;
806 #if (!CONFIG_SOC_BK7251)
807 /* center bias power on*/
808 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL2);
809 reg |= CENTRAL_BAIS_ENABLE_BIT;
810 sctrl_analog_set(SCTRL_ANALOG_CTRL2, reg);
811
812 while ((sctrl_analog_get(SCTRL_ANALOG_CTRL2) & CENTRAL_BAIS_ENABLE_BIT) == 0);
813 #endif
814
815 /*dpll(480m) & xtal2rf enable*/
816 reg = REG_READ(SCTRL_BLOCK_EN_CFG);
817 reg &= ~(BLOCK_EN_WORD_MASK << BLOCK_EN_WORD_POSI);
818 reg |= (BLOCK_EN_WORD_PWD << BLOCK_EN_WORD_POSI);
819 reg |= (BLK_EN_DPLL_480M | BLK_EN_XTAL2RF);
820 REG_WRITE(SCTRL_BLOCK_EN_CFG, reg);
821 ps_delay(10);
822 PS_DEBUG_HWUP_TRIGER;
823
824 sctrl_ctrl(CMD_SCTRL_MCLK_MUX_GET, &c_mclk_mux);
825
826 if (c_mclk_mux == MCLK_SELECT_DCO) {
827 /* MCLK(main clock) select:26M*/
828 reg = REG_READ(SCTRL_CONTROL);
829 reg &= ~(MCLK_MUX_MASK << MCLK_MUX_POSI);
830 reg |= ((MCLK_FIELD_26M_XTAL & MCLK_MUX_MASK) << MCLK_MUX_POSI);
831 REG_WRITE(SCTRL_CONTROL, reg);
832
833 ps_delay(500);
834 PS_DEBUG_HWUP_TRIGER;
835 /* dpll division reset release*/
836 reg = REG_READ(SCTRL_CONTROL);
837 reg &= ~(DPLL_CLKDIV_RESET_BIT);
838 REG_WRITE(SCTRL_CONTROL, reg);
839
840 /* MCLK(main clock) select:dpll*//* MCLK division*/
841 reg = REG_READ(SCTRL_CONTROL);
842 reg &= ~(MCLK_DIV_MASK << MCLK_DIV_POSI);
843 reg |= ((MCLK_DIV_7 & MCLK_DIV_MASK) << MCLK_DIV_POSI);
844 reg &= ~(MCLK_MUX_MASK << MCLK_MUX_POSI);
845 reg |= ((MCLK_FIELD_DPLL & MCLK_MUX_MASK) << MCLK_MUX_POSI);
846 REG_WRITE(SCTRL_CONTROL, reg);
847 PS_DEBUG_HWUP_TRIGER;
848
849 } else {
850 ps_delay(500);
851
852 /* dpll division reset release*/
853 reg = REG_READ(SCTRL_CONTROL);
854 reg &= ~(DPLL_CLKDIV_RESET_BIT);
855 REG_WRITE(SCTRL_CONTROL, reg);
856 PS_DEBUG_HWUP_TRIGER;
857
858 }
859
860 sctrl_cali_dpll(1);
861 PS_DEBUG_HWUP_TRIGER;
862 sddev_control(DD_DEV_TYPE_GPIO, CMD_GPIO_CLR_DPLL_UNLOOK_INT_BIT, NULL);
863
864 #if ((CONFIG_SOC_BK7231) || (CONFIG_SOC_BK7231U) || (CONFIG_SOC_BK7251))
865 /*open 32K Rosc calib*/
866 REG_WRITE(SCTRL_ROSC_CAL, 0x35);
867 REG_WRITE(SCTRL_ROSC_CAL, 0x37);
868 #endif
869
870 reg = (FIQ_DPLL_UNLOCK_BIT);
871 // sddev_control(DD_DEV_TYPE_ICU, CMD_ICU_INT_ENABLE, ®);
872 (void)sys_drv_int_enable(reg);
873
874 //os_printf("h w\r\n");
875 PS_DEBUG_HWUP_TRIGER;
876 #endif
877 }
878
879 #endif
sctrl_subsys_power(UINT32 cmd)880 void sctrl_subsys_power(UINT32 cmd)
881 {
882 UINT32 reg = 0;
883 UINT32 reg_val;
884 UINT32 reg_word = 0;
885
886 switch (cmd) {
887 case CMD_SCTRL_DSP_POWERDOWN:
888 reg = SCTRL_DSP_PWR;
889 reg_word = DSP_PWD;
890 break;
891
892 case CMD_SCTRL_DSP_POWERUP:
893 reg = SCTRL_DSP_PWR;
894 reg_word = DSP_PWU;
895 break;
896
897 #if (CONFIG_SOC_BK7271)
898 case CMD_SCTRL_LBUS_POWERDOWN:
899 reg = SCTRL_PMU_STATUS;
900 reg_word = SYNC_BUS_PWD;
901 break;
902
903 case CMD_SCTRL_LBUS_POWERUP:
904 reg = SCTRL_PMU_STATUS;
905 reg_word = SYNC_BUS_PWU;
906 break;
907
908 case CMD_SCTRL_BT_POWERDOWN:
909 reg = SCTRL_BT_PWR;
910 reg_word = BT_PWD;
911 break;
912
913 case CMD_SCTRL_BT_POWERUP:
914 reg = SCTRL_BT_PWR;
915 reg_word = BT_PWU;
916 break;
917 #else
918
919 #if (!CONFIG_SOC_BK7231N) && (!CONFIG_SOC_BK7236A) && (!CONFIG_SOC_BK7256XX) && (!CONFIG_SOC_BK7236)
920 case CMD_SCTRL_USB_POWERDOWN:
921 reg = SCTRL_USB_PWR;
922 reg_val = REG_READ(SCTRL_USB_PWR);
923 reg_val &= ~(USB_PWD_MASK << USB_PWD_POSI);
924 reg_val |= USB_PWD << USB_PWD_POSI;
925 reg_word = reg_val;
926 break;
927
928 case CMD_SCTRL_USB_POWERUP:
929 reg = SCTRL_USB_PWR;
930 reg_val = REG_READ(SCTRL_USB_PWR);
931 reg_val &= ~(USB_PWD_MASK << USB_PWD_POSI);
932 reg_val |= USB_PWU << USB_PWD_POSI;
933 reg_word = reg_val;
934 break;
935 #endif
936
937 case CMD_SCTRL_MAC_POWERDOWN:
938 reg = SCTRL_PWR_MAC_MODEM;
939 reg_val = REG_READ(SCTRL_PWR_MAC_MODEM);
940 reg_val &= ~(MAC_PWD_MASK << MAC_PWD_POSI);
941 reg_val |= MAC_PWD << MAC_PWD_POSI;
942 reg_word = reg_val;
943 break;
944
945 case CMD_SCTRL_MAC_POWERUP:
946 reg = SCTRL_PWR_MAC_MODEM;
947 reg_val = REG_READ(SCTRL_PWR_MAC_MODEM);
948 reg_val &= ~(MAC_PWD_MASK << MAC_PWD_POSI);
949 reg_val |= MAC_PWU << MAC_PWD_POSI;
950 reg_word = reg_val;
951 break;
952 #endif
953 case CMD_SCTRL_MODEM_POWERDOWN:
954 reg = SCTRL_PWR_MAC_MODEM;
955 reg_val = REG_READ(SCTRL_PWR_MAC_MODEM);
956 reg_val &= ~(MODEM_PWD_MASK << MODEM_PWD_POSI);
957 reg_val |= MODEM_PWD << MODEM_PWD_POSI;
958 reg_word = reg_val;
959 break;
960
961 #if (!CONFIG_SOC_BK7271)
962 case CMD_SCTRL_BLE_POWERDOWN:
963 reg = SCTRL_USB_PWR;
964 reg_val = REG_READ(SCTRL_USB_PWR);
965 reg_val &= ~(BLE_PWD_MASK << BLE_PWD_POSI);
966 reg_val |= BLE_PWD << BLE_PWD_POSI;
967 reg_word = reg_val;
968 break;
969 #endif
970
971 case CMD_SCTRL_MODEM_POWERUP:
972 reg = SCTRL_PWR_MAC_MODEM;
973 reg_val = REG_READ(SCTRL_PWR_MAC_MODEM);
974 reg_val &= ~(MODEM_PWD_MASK << MODEM_PWD_POSI);
975 reg_val |= MODEM_PWU << MODEM_PWD_POSI;
976 reg_word = reg_val;
977 break;
978
979 #if (!CONFIG_SOC_BK7271)
980 case CMD_SCTRL_BLE_POWERUP:
981 reg = SCTRL_USB_PWR;
982 reg_val = REG_READ(SCTRL_USB_PWR);
983 reg_val &= ~(BLE_PWD_MASK << BLE_PWD_POSI);
984 reg_val |= BLE_PWU << BLE_PWD_POSI;
985 reg_word = reg_val;
986 break;
987 #endif
988
989 default:
990 break;
991 }
992
993 if (reg)
994 REG_WRITE(reg, reg_word);
995 }
996
sctrl_subsys_reset(UINT32 cmd)997 void sctrl_subsys_reset(UINT32 cmd)
998 {
999 UINT32 reg = 0;
1000 UINT32 reset_word = 0;
1001
1002 switch (cmd) {
1003 case CMD_SCTRL_MODEM_SUBCHIP_RESET:
1004 reg = SCTRL_MODEM_SUBCHIP_RESET_REQ;
1005 reset_word = MODEM_SUBCHIP_RESET_WORD;
1006 break;
1007
1008 case CMD_SCTRL_MAC_SUBSYS_RESET:
1009 reg = SCTRL_MAC_SUBSYS_RESET_REQ;
1010 reset_word = MAC_SUBSYS_RESET_WORD;
1011 break;
1012
1013 #if (CONFIG_SOC_BK7271)
1014 case CMD_SCTRL_USB_SUBSYS_RESET:
1015 reg = SCTRL_USB_SUBSYS_RESET_REQ;
1016 reset_word = USB_SUBSYS_RESET_WORD;
1017 break;
1018
1019 case CMD_SCTRL_DSP_SUBSYS_RESET:
1020 reg = SCTRL_DSP_SUBSYS_RESET_REQ;
1021 reset_word = DSP_SUBSYS_RESET_WORD;
1022 break;
1023 #endif
1024
1025 default:
1026 break;
1027 }
1028
1029 if (reg) {
1030 REG_WRITE(reg, reset_word);
1031 delay(10);
1032 REG_WRITE(reg, 0);
1033 }
1034
1035 return;
1036 }
1037
1038 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7256XX)
sctrl_fix_dpll_div(void)1039 void sctrl_fix_dpll_div(void)
1040 {
1041 volatile INT32 i;
1042 uint32 reg;
1043 uint32 cpu_clock;
1044
1045 GLOBAL_INT_DECLARATION();
1046 GLOBAL_INT_DISABLE();
1047
1048 reg = REG_READ(SCTRL_CONTROL);
1049 cpu_clock = reg & 0xFF;
1050 reg = (reg & 0xFFFFFF00) | 0x52;
1051 REG_WRITE(SCTRL_CONTROL, reg);
1052
1053 for (i = 0; i < 100; i ++);
1054
1055 REG_WRITE(SCTRL_MODEM_SUBCHIP_RESET_REQ, MODEM_SUBCHIP_RESET_WORD);
1056 REG_WRITE(SCTRL_CONTROL, REG_READ(SCTRL_CONTROL) | (1 << 14));
1057
1058 for (i = 0; i < 100; i ++);
1059
1060 REG_WRITE(SCTRL_MODEM_SUBCHIP_RESET_REQ, 0);
1061 REG_WRITE(SCTRL_CONTROL, REG_READ(SCTRL_CONTROL) & ~(1 << 14));
1062
1063 for (i = 0; i < 100; i ++);
1064
1065 reg = REG_READ(SCTRL_CONTROL);
1066 reg = (reg & 0xFFFFFF00) | cpu_clock;
1067 REG_WRITE(SCTRL_CONTROL, reg);
1068
1069 for (i = 0; i < 100; i ++);
1070
1071 GLOBAL_INT_RESTORE();
1072 }
1073 #endif
1074
1075 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7256XX)
sctrl_mdm_reset(void)1076 void sctrl_mdm_reset(void)
1077 {
1078 volatile INT32 i;
1079 GLOBAL_INT_DECLARATION();
1080
1081 os_printf("sctrl_mdm_reset\r\n");
1082
1083 // Disable the interrupts
1084 GLOBAL_INT_DISABLE();
1085
1086 if (1) {
1087 /* MAC reset */
1088 REG_WRITE(SCTRL_MODEM_SUBCHIP_RESET_REQ, MODEM_SUBCHIP_RESET_WORD);
1089 REG_WRITE(SCTRL_CONTROL, REG_READ(SCTRL_CONTROL) | DPLL_CLKDIV_RESET_BIT);
1090
1091 for (i = 0; i < 100; i++);
1092
1093 REG_WRITE(SCTRL_MODEM_SUBCHIP_RESET_REQ, 0);
1094 REG_WRITE(SCTRL_CONTROL, REG_READ(SCTRL_CONTROL) & ~DPLL_CLKDIV_RESET_BIT);
1095
1096 for (i = 0; i < 100; i++);
1097 } else {
1098 /* Modem pwd */
1099 sctrl_ctrl(CMD_SCTRL_MODEM_POWERDOWN, NULL);
1100 REG_WRITE(SCTRL_CONTROL, REG_READ(SCTRL_CONTROL) | DPLL_CLKDIV_RESET_BIT);
1101
1102 for (i = 0; i < 100; i++);
1103
1104 /* Modem pwu */
1105 sctrl_ctrl(CMD_SCTRL_MODEM_POWERUP, NULL);
1106 REG_WRITE(SCTRL_CONTROL, REG_READ(SCTRL_CONTROL) & ~DPLL_CLKDIV_RESET_BIT);
1107
1108 for (i = 0; i < 100; i++);
1109 }
1110
1111 if (s_wifi_phy_wakeup_rf_reinit_cb) {
1112 s_wifi_phy_wakeup_rf_reinit_cb();
1113 }
1114 if (s_wifi_phy_wakeup_wifi_reinit_cb) {
1115 s_wifi_phy_wakeup_wifi_reinit_cb();
1116 }
1117
1118 // Restore the interrupts
1119 GLOBAL_INT_RESTORE();
1120 }
1121 #endif
1122
1123
1124 #if CONFIG_DEEP_PS
1125 #if PS_SUPPORT_MANUAL_SLEEP
sctrl_enter_rtos_idle_sleep(PS_DEEP_CTRL_PARAM deep_param)1126 void sctrl_enter_rtos_idle_sleep(PS_DEEP_CTRL_PARAM deep_param)
1127 {
1128 DD_HANDLE flash_hdl;
1129 UINT32 status;
1130 UINT32 param;
1131 UINT32 reg;
1132
1133 if (4 == flash_get_line_mode())
1134 flash_set_line_mode(2);
1135
1136 #if (!(CONFIG_SOC_BK7256XX && CONFIG_SLAVE_CORE))
1137 uart_wait_tx_over();
1138 #endif
1139
1140 /* close all peri clock*/
1141 ps_saves[1].peri_clk_cfg = REG_READ(ICU_PERI_CLK_PWD);
1142 REG_WRITE(ICU_PERI_CLK_PWD, 0xfffff);
1143
1144 uart2_exit();
1145 #if CONFIG_UART1
1146 uart1_exit();
1147 #endif
1148
1149 reg = REG_READ(SCTRL_ROSC_TIMER);
1150 reg &= ~(ROSC_TIMER_ENABLE_BIT);
1151 REG_WRITE(SCTRL_ROSC_TIMER, reg);
1152
1153 REG_WRITE(SCTRL_GPIO_WAKEUP_EN, 0x0);
1154
1155 REG_WRITE(SCTRL_BLOCK_EN_MUX, 0x0);
1156
1157 param = LPO_SELECT_ROSC;
1158 sddev_control(DD_DEV_TYPE_SCTRL, CMD_SCTRL_SET_LOW_PWR_CLK, ¶m);
1159
1160 /* close all peri int*/
1161 ps_saves[1].int_enable_cfg = REG_READ(ICU_R_INT_EN);
1162 REG_WRITE(ICU_R_INT_EN, 0);
1163
1164 /*Enable BK7011:rc_en,ch0_en*/
1165 rc_cntl_stat_set(0x0);
1166
1167 /* MAC pwd*/
1168 REG_WRITE(SCTRL_PWR_MAC_MODEM, MAC_PWD << MAC_PWD_POSI);
1169
1170 sctrl_mac_ahb_slave_clock_disable();
1171
1172 /* Mac Subsystem clock 480m disable*/
1173 reg = REG_READ(SCTRL_CONTROL);
1174 REG_WRITE(SCTRL_CONTROL, reg | MAC_CLK480M_PWD_BIT);
1175
1176 /* Modem pwd*/
1177 REG_WRITE(SCTRL_PWR_MAC_MODEM, MODEM_PWD << MODEM_PWD_POSI);
1178
1179 /* Modem AHB clock disable*/
1180 #if (CONFIG_SOC_BK7271)
1181 reg = REG_READ(SCTRL_CONTROL);
1182 reg &= ~PHY_HCLK_EN_BIT;
1183 REG_WRITE(SCTRL_CONTROL, reg);
1184 #else
1185 reg = REG_READ(SCTRL_MODEM_CORE_RESET_PHY_HCLK);
1186 reg &= ~PHY_HCLK_EN_BIT;
1187 REG_WRITE(SCTRL_MODEM_CORE_RESET_PHY_HCLK, reg);
1188 #endif
1189
1190 /* Modem Subsystem clock 480m disable*/
1191 reg = REG_READ(SCTRL_CONTROL);
1192 REG_WRITE(SCTRL_CONTROL, reg | MODEM_CLK480M_PWD_BIT);
1193
1194 /* Flash 26MHz clock select dco clock*/
1195 flash_hdl = ddev_open(DD_DEV_TYPE_FLASH, &status, 0);
1196 BK_ASSERT(DD_HANDLE_UNVALID != flash_hdl);
1197 ddev_control(flash_hdl, CMD_FLASH_SET_DCO, 0);
1198
1199 /* MCLK(main clock) select:dco*/ /* MCLK division*/
1200 reg = REG_READ(SCTRL_CONTROL);
1201 reg &= ~(MCLK_MUX_MASK << MCLK_MUX_POSI);
1202 reg &= ~(MCLK_DIV_MASK << MCLK_DIV_POSI);
1203 REG_WRITE(SCTRL_CONTROL, reg);
1204
1205 REG_WRITE(SCTRL_ROSC_CAL, 0x35);
1206 REG_WRITE(SCTRL_ROSC_CAL, 0x37);
1207
1208 ps_delay(10);
1209
1210 /*close 32K Rosc calib*/
1211 REG_WRITE(SCTRL_ROSC_CAL, 0x36);
1212
1213 ps_block_value = REG_READ(SCTRL_BLOCK_EN_CFG) & BLOCK_EN_VALID_MASK;
1214 /* ALL disable*/
1215 reg = 0x0;
1216 reg &= ~(BLOCK_EN_WORD_MASK << BLOCK_EN_WORD_POSI);
1217 reg = reg | (BLOCK_EN_WORD_PWD << BLOCK_EN_WORD_POSI);
1218 reg &= ~(BLOCK_EN_VALID_MASK);
1219 REG_WRITE(SCTRL_BLOCK_EN_CFG, reg);
1220
1221 /* center bias power down*/
1222 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL2);
1223 reg &= (~CENTRAL_BAIS_ENABLE_BIT);
1224 sctrl_analog_set(SCTRL_ANALOG_CTRL2, reg);
1225
1226 reg = 0xFFFFFFFF;
1227 REG_WRITE(SCTRL_GPIO_WAKEUP_INT_STATUS, reg);
1228
1229 if (deep_param.deep_wkway == PS_DEEP_WAKEUP_RTC
1230 && deep_param.param != 0xffffffff) {
1231 reg = REG_READ(SCTRL_ROSC_TIMER);
1232 reg |= ROSC_TIMER_INT_STATUS_BIT;
1233 REG_WRITE(SCTRL_ROSC_TIMER, reg);
1234 reg = REG_READ(SCTRL_ROSC_TIMER);
1235 reg &= ~(ROSC_TIMER_PERIOD_MASK << ROSC_TIMER_PERIOD_POSI);
1236 reg |= (deep_param.param << ROSC_TIMER_PERIOD_POSI);
1237 REG_WRITE(SCTRL_ROSC_TIMER, reg);
1238 reg = REG_READ(SCTRL_ROSC_TIMER);
1239 reg |= ROSC_TIMER_ENABLE_BIT;
1240 REG_WRITE(SCTRL_ROSC_TIMER, reg);
1241
1242 reg = 0x0;
1243 reg &= ~(BLOCK_EN_WORD_MASK << BLOCK_EN_WORD_POSI);
1244 reg = reg | (BLOCK_EN_WORD_PWD << BLOCK_EN_WORD_POSI);
1245 reg |= (BLK_EN_ANALOG_SYS_LDO | BLK_EN_DIGITAL_CORE);
1246 REG_WRITE(SCTRL_BLOCK_EN_CFG, reg);
1247 reg = REG_READ(SCTRL_BLOCK_EN_MUX);
1248 reg &= (~0x1FF);
1249 reg |= (0x1 << 8);
1250 REG_WRITE(SCTRL_BLOCK_EN_MUX, reg);
1251 } else if (deep_param.deep_wkway == PS_DEEP_WAKEUP_GPIO) {
1252 reg = 0xFFFFFFFF;
1253 REG_WRITE(SCTRL_GPIO_WAKEUP_INT_STATUS, reg);
1254 reg = deep_param.gpio_lv;
1255 REG_WRITE(SCTRL_GPIO_WAKEUP_TYPE, reg);
1256 reg = deep_param.param;
1257 REG_WRITE(SCTRL_GPIO_WAKEUP_EN, reg);
1258
1259 }
1260
1261 ps_delay(10);
1262 /* arm clock disable */
1263 reg = REG_READ(SCTRL_SLEEP);
1264 reg &= ~(SLEEP_MODE_MASK << SLEEP_MODE_POSI);
1265 reg = reg | SLEEP_MODE_CFG_LOW_VOL_WORD;
1266 REG_WRITE(SCTRL_SLEEP, reg);
1267 delay(5);
1268 }
1269
sctrl_exit_rtos_idle_sleep(void)1270 void sctrl_exit_rtos_idle_sleep(void)
1271 {
1272 UINT32 reg;
1273
1274 /* center bias power on*/
1275 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL2);
1276 reg |= CENTRAL_BAIS_ENABLE_BIT;
1277 sctrl_analog_set(SCTRL_ANALOG_CTRL2, reg);
1278
1279 /*dpll(480m) & 26m xtal & xtal2rf enable*/
1280 reg = REG_READ(SCTRL_BLOCK_EN_MUX);
1281 reg &= ~(0x1 << 4);
1282 REG_WRITE(SCTRL_BLOCK_EN_MUX, reg);
1283 reg = REG_READ(SCTRL_BLOCK_EN_CFG);
1284 reg &= ~(BLOCK_EN_WORD_MASK << BLOCK_EN_WORD_POSI);
1285 reg |= (BLOCK_EN_WORD_PWD << BLOCK_EN_WORD_POSI);
1286 reg |= ps_block_value;
1287 REG_WRITE(SCTRL_BLOCK_EN_CFG, reg);
1288
1289 delay(20); //delay 1.1ms for 26MHz DCO clock. need change for other dco clock frequency
1290 sctrl_cali_dpll(1);
1291 /* dpll division reset release*/
1292 reg = REG_READ(SCTRL_CONTROL);
1293 reg &= ~(0x1 << 14);
1294 REG_WRITE(SCTRL_CONTROL, reg);
1295
1296 /* MCLK(main clock) select:dpll*//* MCLK division*/
1297 reg = REG_READ(SCTRL_CONTROL);
1298 reg &= ~(MCLK_DIV_MASK << MCLK_DIV_POSI);
1299 reg &= ~(MCLK_MUX_MASK << MCLK_MUX_POSI);
1300 reg |= ((MCLK_DIV_7 & MCLK_DIV_MASK) << MCLK_DIV_POSI);
1301 reg |= ((MCLK_FIELD_DPLL & MCLK_MUX_MASK) << MCLK_MUX_POSI);
1302 REG_WRITE(SCTRL_CONTROL, reg);
1303
1304 /*open 32K Rosc calib*/
1305 REG_WRITE(SCTRL_ROSC_CAL, 0x35);
1306 REG_WRITE(SCTRL_ROSC_CAL, 0x37);
1307
1308 sctrl_mac_ahb_slave_clock_enable();
1309
1310 /* Mac Subsystem clock 480m enable*/
1311 reg = REG_READ(SCTRL_CONTROL);
1312 reg &= ~MAC_CLK480M_PWD_BIT;
1313 REG_WRITE(SCTRL_CONTROL, reg);
1314
1315 /* Modem AHB clock enable*/
1316 #if (CONFIG_SOC_BK7271)
1317 reg = REG_READ(SCTRL_CONTROL);
1318 REG_WRITE(SCTRL_CONTROL, reg | PHY_HCLK_EN_BIT);
1319 #else
1320 reg = REG_READ(SCTRL_MODEM_CORE_RESET_PHY_HCLK);
1321 REG_WRITE(SCTRL_MODEM_CORE_RESET_PHY_HCLK, reg | PHY_HCLK_EN_BIT);
1322 #endif
1323
1324 /* Modem Subsystem clock 480m enable*/
1325 reg = REG_READ(SCTRL_CONTROL);
1326 reg &= ~MODEM_CLK480M_PWD_BIT;
1327 REG_WRITE(SCTRL_CONTROL, reg);
1328
1329 /* Modem pwd*/
1330 reg = REG_READ(SCTRL_PWR_MAC_MODEM);
1331 reg &= ~(MODEM_PWD_MASK << MODEM_PWD_POSI);
1332 reg = reg | (0 << MODEM_PWD_POSI);
1333 REG_WRITE(SCTRL_PWR_MAC_MODEM, reg);
1334
1335 /*Enable BK7011:rc_en,ch0_en*/
1336 rc_cntl_stat_set(0x09);
1337
1338 /* recovery periphral unit clock config*/
1339 REG_WRITE(ICU_PERI_CLK_PWD, ps_saves[1].peri_clk_cfg);
1340
1341 /* recovery periphral unit int config*/
1342 REG_WRITE(ICU_R_INT_EN, ps_saves[1].int_enable_cfg);
1343
1344 /*open 32K Rosc calib*/
1345 REG_WRITE(SCTRL_ROSC_CAL, 0x35);
1346 REG_WRITE(SCTRL_ROSC_CAL, 0x37);
1347
1348 uart2_init();
1349 #if CONFIG_UART1
1350 uart1_init();
1351 #endif
1352
1353 if (4 == flash_get_line_mode())
1354 flash_set_line_mode(4);
1355
1356 os_printf("idle wake up!\r\n");
1357 }
1358 #endif
1359
1360
1361
bk_init_deep_wakeup_gpio_status(void)1362 int bk_init_deep_wakeup_gpio_status(void)
1363 {
1364 gpio_0_31_status = REG_READ(GPIO_WAKEUP_INT_STATUS_BAK);
1365 #if(!CONFIG_SOC_BK7231N) && (!CONFIG_SOC_BK7236A) && (!CONFIG_SOC_BK7256XX)
1366 gpio_32_39_status = REG_READ(GPIO_WAKEUP_INT_STATUS1_BAK);
1367 #endif
1368 REG_WRITE(SCTRL_GPIO_WAKEUP_INT_STATUS, 0xFFFFFFFF);
1369 #if (!CONFIG_SOC_BK7231N) && (!CONFIG_SOC_BK7236A) && (!CONFIG_SOC_BK7256XX) && (!CONFIG_SOC_BK7236)
1370 REG_WRITE(SCTRL_GPIO_WAKEUP_INT_STATUS1, 0xFFFFFFFF);
1371 #endif
1372 return 0;
1373 }
bk_misc_wakeup_get_gpio_num(void)1374 int bk_misc_wakeup_get_gpio_num(void)
1375 {
1376 int wakeup_gpio_num = -1;
1377
1378 REG_WRITE(SCTRL_GPIO_WAKEUP_INT_STATUS, 0xFFFFFFFF);
1379 #if (!CONFIG_SOC_BK7231N) && (!CONFIG_SOC_BK7236A) && (!CONFIG_SOC_BK7256XX) && (!CONFIG_SOC_BK7236)
1380 REG_WRITE(SCTRL_GPIO_WAKEUP_INT_STATUS1, 0xFFFFFFFF);
1381 #endif
1382
1383 if((0 == gpio_0_31_status)
1384 #if (!CONFIG_SOC_BK7231N) && (!CONFIG_SOC_BK7236A) && (!CONFIG_SOC_BK7256XX) && (!CONFIG_SOC_BK7236)
1385 && (0 == gpio_32_39_status)
1386 #endif
1387 )
1388 {
1389 wakeup_gpio_num = -1;
1390 return wakeup_gpio_num;
1391 }
1392
1393 if(gpio_0_31_status)
1394 {
1395 for(int i=0;i<32;i++)
1396 {
1397 if(gpio_0_31_status&0x01)
1398 {
1399 wakeup_gpio_num = i;
1400 break;
1401 }
1402
1403 gpio_0_31_status = gpio_0_31_status >> 1;
1404 }
1405 }
1406 #if (!CONFIG_SOC_BK7231N) && (!CONFIG_SOC_BK7236A) && (!CONFIG_SOC_BK7256XX) && (!CONFIG_SOC_BK7236)
1407 else if(gpio_32_39_status)
1408 {
1409 for(int i=32;i<40;i++)
1410 {
1411 if(gpio_32_39_status&0x01)
1412 {
1413 wakeup_gpio_num = i;
1414 break;
1415 }
1416
1417 gpio_32_39_status = gpio_32_39_status >> 1;
1418 }
1419 }
1420 #endif
1421
1422 return wakeup_gpio_num;
1423 }
1424
sctrl_get_deep_sleep_wake_soure(void)1425 RESET_SOURCE_STATUS sctrl_get_deep_sleep_wake_soure(void)
1426 {
1427 RESET_SOURCE_STATUS waked_source = 0;
1428
1429 #if (!CONFIG_SOC_BK7271)
1430 if (REG_READ(SCTRL_ROSC_TIMER) & ROSC_TIMER_INT_STATUS_BIT)
1431 {
1432 waked_source = RESET_SOURCE_DEEPPS_RTC;
1433 }
1434 else if(gpio_0_31_status
1435 #if (!CONFIG_SOC_BK7231N) && (!CONFIG_SOC_BK7236A) && (!CONFIG_SOC_BK7256XX) && (!CONFIG_SOC_BK7236)
1436 || gpio_32_39_status
1437 #endif
1438 )
1439 waked_source = RESET_SOURCE_DEEPPS_GPIO;
1440 #if (!CONFIG_SOC_BK7231N) && (!CONFIG_SOC_BK7236A) && (!CONFIG_SOC_BK7256XX) && (!CONFIG_SOC_BK7236)
1441 else if (REG_READ(SCTRL_USB_PLUG_WAKEUP) & (USB_PLUG_IN_INT_BIT | USB_PLUG_OUT_INT_BIT))
1442 waked_source = RESET_SOURCE_DEEPPS_USB;
1443 #endif
1444 #endif
1445
1446 return waked_source;
1447 }
1448
sctrl_set_deep_sleep_gpio_floating_map(UINT32 gpio_floating_map)1449 void sctrl_set_deep_sleep_gpio_floating_map(UINT32 gpio_floating_map)
1450 {
1451 deep_sleep_gpio_floating_map = gpio_floating_map;
1452 }
1453
sctrl_get_deep_sleep_gpio_floating_map(void)1454 UINT32 sctrl_get_deep_sleep_gpio_floating_map(void)
1455 {
1456 return deep_sleep_gpio_floating_map;
1457 }
1458
1459 #if (!CONFIG_SOC_BK7231N) && (!CONFIG_SOC_BK7236A) && (!CONFIG_SOC_BK7256XX)
sctrl_set_deep_sleep_gpio_last_floating_map(UINT32 gpio_last_floating_map)1460 void sctrl_set_deep_sleep_gpio_last_floating_map(UINT32 gpio_last_floating_map)
1461 {
1462 deep_sleep_gpio_last_floating_map = gpio_last_floating_map;
1463 }
1464
sctrl_get_deep_sleep_gpio_last_floating_map(void)1465 UINT32 sctrl_get_deep_sleep_gpio_last_floating_map(void)
1466 {
1467 return deep_sleep_gpio_last_floating_map;
1468 }
1469 #endif
1470
1471 #endif
1472
1473 #if (!CONFIG_SOC_BK7231) && (!CONFIG_SOC_BK7271)
sctrl_read_efuse(void * param)1474 static int sctrl_read_efuse(void *param)
1475 {
1476 UINT32 reg, ret = -1;
1477 EFUSE_OPER_PTR efuse;
1478 efuse = (EFUSE_OPER_PTR)param;
1479
1480 if (efuse) {
1481 reg = REG_READ(SCTRL_EFUSE_CTRL);
1482 reg &= ~(EFUSE_OPER_ADDR_MASK << EFUSE_OPER_ADDR_POSI);
1483 reg &= ~(EFUSE_OPER_DIR);
1484
1485 reg |= ((efuse->addr & EFUSE_OPER_ADDR_MASK) << EFUSE_OPER_ADDR_POSI);
1486 reg |= (EFUSE_OPER_EN);
1487 REG_WRITE(SCTRL_EFUSE_CTRL, reg);
1488
1489 do {
1490 reg = REG_READ(SCTRL_EFUSE_CTRL);
1491 } while (reg & EFUSE_OPER_EN);
1492
1493 reg = REG_READ(SCTRL_EFUSE_OPTR);
1494 if (reg & EFUSE_OPER_RD_DATA_VALID) {
1495 efuse->data = ((reg >> EFUSE_OPER_RD_DATA_POSI) & EFUSE_OPER_RD_DATA_MASK);
1496 ret = 0;
1497 } else
1498 efuse->data = 0xFF;
1499 }
1500 return ret;
1501 }
1502
check_efuse_can_write(UINT8 new_byte,UINT8 old_byte)1503 static int check_efuse_can_write(UINT8 new_byte, UINT8 old_byte)
1504 {
1505 if (new_byte == old_byte) {
1506 // no need to read
1507 return 1;
1508 }
1509
1510 for (int i = 0; i < 8; i++) {
1511 UINT8 old_bit = ((old_byte >> i) & 0x01);
1512 UINT8 new_bit = ((new_byte >> i) & 0x01);
1513
1514 if ((old_bit) && (!new_bit)) {
1515 // can not change old from 1 to 0
1516 return 0;
1517 }
1518 }
1519
1520 return 2;
1521 }
1522
sctrl_write_efuse(void * param)1523 static int sctrl_write_efuse(void *param)
1524 {
1525 UINT32 reg, ret = -1;
1526 EFUSE_OPER_ST *efuse, efuse_bak;
1527
1528 #if (CONFIG_SOC_BK7251)
1529 os_printf("BK7251 cannot write efuse via register\r\n");
1530 goto wr_exit;
1531 #endif
1532
1533 efuse = (EFUSE_OPER_PTR)param;
1534 if (efuse) {
1535 efuse_bak.addr = efuse->addr;
1536 efuse_bak.data = efuse->data;
1537 if (sctrl_read_efuse(&efuse_bak) == 0) {
1538 //read before write, ensure this byte and this bit no wrote
1539 ret = check_efuse_can_write(efuse->data, efuse_bak.data);
1540 if (ret == 0) {
1541 ret = -1;
1542 goto wr_exit;
1543 } else if (ret == 1) {
1544 ret = 0;
1545 goto wr_exit;
1546 }
1547 }
1548
1549 // enable vdd2.5v first
1550 reg = REG_READ(SCTRL_CONTROL);
1551 reg |= EFUSE_VDD25_EN;
1552 REG_WRITE(SCTRL_CONTROL, reg);
1553
1554 reg = REG_READ(SCTRL_EFUSE_CTRL);
1555 reg &= ~(EFUSE_OPER_ADDR_MASK << EFUSE_OPER_ADDR_POSI);
1556 reg &= ~(EFUSE_OPER_WR_DATA_MASK << EFUSE_OPER_WR_DATA_POSI);
1557
1558 reg |= EFUSE_OPER_DIR;
1559 reg |= ((efuse->addr & EFUSE_OPER_ADDR_MASK) << EFUSE_OPER_ADDR_POSI);
1560 reg |= ((efuse->data & EFUSE_OPER_WR_DATA_MASK) << EFUSE_OPER_WR_DATA_POSI);
1561 reg |= EFUSE_OPER_EN;
1562 REG_WRITE(SCTRL_EFUSE_CTRL, reg);
1563
1564 do {
1565 reg = REG_READ(SCTRL_EFUSE_CTRL);
1566 } while (reg & EFUSE_OPER_EN);
1567
1568 // disable vdd2.5v at last
1569 reg = REG_READ(SCTRL_CONTROL);
1570 reg &= ~EFUSE_VDD25_EN;
1571 REG_WRITE(SCTRL_CONTROL, reg);
1572
1573 // check, so read
1574 reg = efuse->data;
1575 efuse->data = 0;
1576 if (sctrl_read_efuse(param) == 0) {
1577 if (((UINT8)reg) == efuse->data)
1578 ret = 0;
1579 }
1580 }
1581
1582 wr_exit:
1583 return ret;
1584 }
1585
1586
1587 #endif // (!CONFIG_SOC_BK7231)
1588
1589 #if CONFIG_USB_CHARGE
1590 #if (CONFIG_SOC_BK7271)
1591 #define CHARGER_CTRL_0 SCTRL_ANALOG_CTRL7
1592 #define CHARGER_CTRL_1 SCTRL_ANALOG_CTRL8_REAL
1593 #else
1594 #define CHARGER_CTRL_0 SCTRL_ANALOG_CTRL3
1595 #define CHARGER_CTRL_1 SCTRL_ANALOG_CTRL4
1596 #endif
1597
1598 #if (CONFIG_SOC_BK7251)
usb_charge_oper_val(UINT32 elect)1599 UINT32 usb_charge_oper_val(UINT32 elect)
1600 {
1601 if (elect >= 450) {
1602 /*EXTERNAL CC elect*/
1603 if (elect > 750)
1604 elect = 750;
1605 return (elect - 450) / 20;
1606 } else {
1607 /*INTERNAL CC elect*/
1608 if (elect > 250)
1609 elect = 250;
1610 else if (elect < 20)
1611 elect = 20;
1612
1613 if (elect >= 100 && elect <= 250)
1614 return (elect - 100) / 10 + 16;
1615 else
1616 return (elect - 20) / 10;
1617 }
1618 }
1619
usb_power_is_pluged(void)1620 UINT32 usb_power_is_pluged(void)
1621 {
1622 UINT32 reg;
1623 reg = sctrl_analog_get(SCTRL_CHARGE_STATUS);
1624 return (reg & (1 << 21));
1625 }
1626
charger_module_enable(UINT32 enable)1627 void charger_module_enable(UINT32 enable)
1628 {
1629 sctrl_analog_set(SCTRL_ANALOG_CTRL4, (sctrl_analog_get(SCTRL_ANALOG_CTRL4) & ~(1 << 12)) | (!!enable << 12));
1630 }
1631
charger_vlcf_calibration(UINT32 type)1632 void charger_vlcf_calibration(UINT32 type)
1633 {
1634
1635 if (type == 0) {
1636 /*Internal hardware calibration*/
1637 /*vlcf calibration*/
1638 /*>>> Added 5V voltage on Vusb*/
1639 /*>>> Added 4.2V voltage on vbattery*/
1640 /*>>> Set pwd=0*/
1641 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) | (1 << 12));
1642 /*charge mode select*/
1643 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) | (1 << 19));
1644 /*calEn*/
1645 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) | (1 << 21));
1646 /*softCalen*/
1647 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) & ~(1 << 20));
1648 /*vlcfSel*/
1649 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) & ~(1 << 18));
1650 /*IcalSel*/
1651 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) & ~(1 << 17));
1652 /*vcvSel*/
1653 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) & ~(1 << 16));
1654 /*vlcf_caltrig*/
1655 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) & ~(1 << 21));
1656 /*vlcf_caltrig*/
1657 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) | (1 << 21));
1658 /*Wait for at least 4 clock cycles*/
1659 delay_ms(1);
1660 /*vlcf_caltrig*/
1661 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) & ~(1 << 21));
1662 /*Waiting for 1ms, calibration finished*/
1663 delay_ms(1);
1664 /*Read the value vcal<5:0>, Recorded*/
1665 calib_charger[0] = (sctrl_analog_get(SCTRL_CHARGE_STATUS) >> CHARGE_VCAL_POS) & CHARGE_VCAL_MASK ;
1666 }
1667 }
1668
charger_icp_calibration(UINT32 type)1669 void charger_icp_calibration(UINT32 type)
1670 {
1671
1672 if (type == 0) {
1673 /*Internal hardware calibration*/
1674 /*Icp calibration*/
1675 /*>>> Added parallel 60ohm resistor and 100nF capacitor from vbattery to ground.(Removed the external 4.2V)*/
1676 /*>>> Set pwd=0*/
1677 /*>>> Porb=0*/
1678 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) | (1 << 12));
1679 /*Icp=60mA*/
1680 sctrl_analog_set(SCTRL_ANALOG_CTRL3, (sctrl_analog_get(SCTRL_ANALOG_CTRL3)\
1681 & ~(CHARGE_LCP_MASK << CHARGE_LCP_POS)) | (0x4 << CHARGE_LCP_POS));
1682 /*calEn*/
1683 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) | (1 << 21));
1684 /*softCalen*/
1685 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) & ~(1 << 20));
1686 /*vlcfSel*/
1687 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) | (1 << 18));
1688 /*vcal<5:0>=previous vlcf calibration value*/
1689 sctrl_analog_set(SCTRL_ANALOG_CTRL3, (sctrl_analog_get(SCTRL_ANALOG_CTRL3)\
1690 & ~(CHARGE_VCAL_MASK << 0)) | (calib_charger[0] << 0));
1691 /*IcalSel*/
1692 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) & ~(1 << 17));
1693 /*vcvSel*/
1694 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) & ~(1 << 16));
1695 /*Ical_trig*/
1696 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) & ~(1 << 20));
1697 /*Ical_trig*/
1698 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) | (1 << 20));
1699 /*Wait for at least 4 clock cycles*/
1700 delay_ms(1);
1701 /*Ical_trig*/
1702 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) & ~(1 << 20));
1703 /*Waiting for 1ms, calibration finished*/
1704 delay_ms(1);
1705 /*Read the value Ical<4:0>, Recorded*/
1706 calib_charger[1] = (sctrl_analog_get(SCTRL_CHARGE_STATUS) >> CHARGE_LCAL_POS) & CHARGE_LCAL_MASK ;
1707 }
1708 }
1709
charger_vcv_calibration(UINT32 type)1710 void charger_vcv_calibration(UINT32 type)
1711 {
1712
1713 if (type == 0) {
1714 /*Internal hardware calibration*/
1715 /*vcv calibration*/
1716 /*>>> Added 5V voltage on Vusb*/
1717 /*>>> Added 4.2V voltage on vbattery*/
1718 /*>>> Set pwd=0*/
1719 /*>>> Porb=0*/
1720 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) | (1 << 12));
1721 /*charge mode select*/
1722 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) | (1 << 19));
1723 /*Icp=60mA*/
1724 /*sctrl_analog_set(SCTRL_ANALOG_CTRL3, (sctrl_analog_get(SCTRL_ANALOG_CTRL3)\
1725 * & ~(CHARGE_LCP_MASK << CHARGE_LCP_POS)) | (0x4 << CHARGE_LCP_POS));
1726 **/
1727 /*calEn*/
1728 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) | (1 << 21));
1729 /*softCalen*/
1730 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) & ~(1 << 20));
1731 /*vlcfSel*/
1732 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) | (1 << 18));
1733 /*vcal<5:0>=previous vlcf calibration value*/
1734 sctrl_analog_set(SCTRL_ANALOG_CTRL3, (sctrl_analog_get(SCTRL_ANALOG_CTRL3)\
1735 & ~(CHARGE_VCAL_MASK << 0)) | (calib_charger[0] << 0));
1736 /*IcalSel*/
1737 //sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) | (1 << 17));
1738 /*Ical<4:0>=previous Ical calibration value*/
1739 /*sctrl_analog_set(SCTRL_ANALOG_CTRL4, (sctrl_analog_get(SCTRL_ANALOG_CTRL4)\
1740 * & ~(CHARGE_LCAL_MASK << 27)) | (calib_charger[1] << 27));
1741 */
1742 /*vcvSel*/
1743 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) & ~(1 << 16));
1744 /*vcv_caltrig*/
1745 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) & ~(1 << 19));
1746 /*vcv_caltrig*/
1747 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) | (1 << 19));
1748 /*Wait for at least 4 clock cycles*/
1749 delay_ms(1);
1750 /*vcv_caltrig*/
1751 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) & ~(1 << 19));
1752 /*Waiting for 1ms, calibration finished*/
1753 delay_ms(1);
1754 /*Read the value vcvcal<4:0>, Recorded*/
1755 calib_charger[2] = (sctrl_analog_get(SCTRL_CHARGE_STATUS) >> CHARGE_VCVCAL_POS) & CHARGE_VCVCAL_MASK ;
1756 }
1757 }
1758
charger_calib_get(UINT8 value[])1759 void charger_calib_get(UINT8 value[])
1760 {
1761 value[0] = calib_charger[0];
1762 value[1] = calib_charger[1];
1763 value[2] = calib_charger[2];
1764 return;
1765 }
1766
charger_calib_set(UINT8 value[])1767 void charger_calib_set(UINT8 value[])
1768 {
1769 if (!value[0] || !value[1] || !value[2])
1770 return;
1771
1772 calib_charger[0] = value[0];
1773 calib_charger[1] = value[1];
1774 calib_charger[2] = value[2];
1775 return;
1776 }
1777
charger_is_full(void)1778 UINT32 charger_is_full(void)
1779 {
1780 UINT32 reg;
1781 reg = sctrl_analog_get(SCTRL_CHARGE_STATUS);
1782 return (reg & (1 << 20));
1783 }
1784
charger_start(void * param)1785 void charger_start(void *param)
1786 {
1787 UINT32 charge_cal_type ;
1788 CHARGE_OPER_ST *chrg;
1789
1790 chrg = (CHARGE_OPER_ST *)param;
1791
1792 if (! usb_power_is_pluged()) {
1793 os_printf("%s: not pluged\r\n", __FUNCTION__);
1794 return;
1795 }
1796
1797 charger_calib_set(chrg->cal);
1798 os_printf("%s: %d %d %d %x %x %x\r\n", __FUNCTION__, chrg->type, chrg->step, chrg->elect,
1799 calib_charger[0], calib_charger[1], calib_charger[2]);
1800 if (chrg->step == STEP_START) {
1801 if (chrg->type == INTERNAL_HW_MODE || chrg->type == INTERNAL_SW_MODE) {
1802 /*Internal*/
1803 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) & ~(1 << 21));
1804
1805 if (chrg->type == INTERNAL_HW_MODE) {
1806 /*Internal ,hw control*/
1807 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) & ~(1 << 19));
1808 } else if (chrg->type == INTERNAL_SW_MODE) {
1809 /*Internal ,sw control*/
1810 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) | (1 << 19));
1811 }
1812
1813 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) | (1 << 28));
1814 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) | (1 << 27));
1815 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) | (1 << 12));
1816 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) | (1 << 13)); //vcvcalEn_spilv
1817 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) & ~(1 << 11));
1818 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) | (1 << 18));
1819 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) | (1 << 17));
1820 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) | (1 << 16));
1821 sctrl_analog_set(SCTRL_ANALOG_CTRL3, (sctrl_analog_get(SCTRL_ANALOG_CTRL3)\
1822 & ~(CHARGE_LCP_MASK << CHARGE_LCP_POS)) | (0x1f << CHARGE_LCP_POS));
1823 sctrl_analog_set(SCTRL_ANALOG_CTRL3, (sctrl_analog_get(SCTRL_ANALOG_CTRL3)\
1824 & ~(CHARGE_VCAL_MASK << 0)) | (calib_charger[0] << 0));
1825 sctrl_analog_set(SCTRL_ANALOG_CTRL4, (sctrl_analog_get(SCTRL_ANALOG_CTRL4)\
1826 & ~(CHARGE_LCAL_MASK << 27)) | (calib_charger[1] << 27));
1827 sctrl_analog_set(SCTRL_ANALOG_CTRL4, (sctrl_analog_get(SCTRL_ANALOG_CTRL4)\
1828 & ~(CHARGE_LCAL_MASK << 22)) | (calib_charger[2] << 22));
1829
1830 if (chrg->type == INTERNAL_HW_MODE) {
1831 sctrl_analog_set(SCTRL_ANALOG_CTRL3, (sctrl_analog_get(SCTRL_ANALOG_CTRL3) \
1832 & ~(CHARGE_LC2CVDLYLV_MASK << CHARGE_LC2CVDLYLV_POS)) | (4 << CHARGE_LC2CVDLYLV_POS));
1833 } else if (chrg->type == INTERNAL_SW_MODE) {
1834 sctrl_analog_set(SCTRL_ANALOG_CTRL3, (sctrl_analog_get(SCTRL_ANALOG_CTRL3) \
1835 & ~(CHARGE_LC2CVDLYLV_MASK << CHARGE_LC2CVDLYLV_POS)));
1836 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) | (1 << 22));
1837 sctrl_analog_set(SCTRL_ANALOG_CTRL3, (sctrl_analog_get(SCTRL_ANALOG_CTRL3) \
1838 & ~(CHARGE_VLCSWLV_MASK << CHARGE_VLCSWLV_POS)) | (8 << CHARGE_VLCSWLV_POS));
1839 }
1840
1841 } else if (chrg->type == EXTERNAL_HW_MODE || chrg->type == EXTERNAL_SW_MODE) {
1842 /*External*/
1843 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) & ~(1 << 21));
1844
1845 if (chrg->type == EXTERNAL_HW_MODE) {
1846 /*External ,hw control*/
1847 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) & ~(1 << 19));
1848 } else if (chrg->type == EXTERNAL_SW_MODE) {
1849 /*External ,sw control*/
1850 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) | (1 << 19));
1851 }
1852
1853 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) | (1 << 28));
1854 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) | (1 << 27));
1855 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) | (1 << 12));
1856 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) | (1 << 13)); //vcvcalEn_spilv
1857
1858 if (chrg->type == EXTERNAL_HW_MODE)
1859 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) | (1 << 11));
1860 else if (chrg->type == EXTERNAL_SW_MODE) {
1861 //sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4)& ~(1 << 11));
1862 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) | (1 << 11));
1863 }
1864
1865 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) | (1 << 18));
1866 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) | (1 << 17));
1867 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) | (1 << 16));
1868 sctrl_analog_set(SCTRL_ANALOG_CTRL3, (sctrl_analog_get(SCTRL_ANALOG_CTRL3)\
1869 & ~(CHARGE_LCP_MASK << CHARGE_LCP_POS)) | (0x1f << CHARGE_LCP_POS));
1870 sctrl_analog_set(SCTRL_ANALOG_CTRL3, (sctrl_analog_get(SCTRL_ANALOG_CTRL3)\
1871 & ~(CHARGE_VCAL_MASK << 0)) | (calib_charger[0] << 0));
1872 sctrl_analog_set(SCTRL_ANALOG_CTRL4, (sctrl_analog_get(SCTRL_ANALOG_CTRL4)\
1873 & ~(CHARGE_LCAL_MASK << 27)) | (calib_charger[1] << 27));
1874 sctrl_analog_set(SCTRL_ANALOG_CTRL4, (sctrl_analog_get(SCTRL_ANALOG_CTRL4)\
1875 & ~(CHARGE_LCAL_MASK << 22)) | (calib_charger[2] << 22));
1876 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) | (1 << 28));
1877 sctrl_analog_set(SCTRL_ANALOG_CTRL3, (sctrl_analog_get(SCTRL_ANALOG_CTRL3) \
1878 & ~(CHARGE_LC2CVDLYLV_MASK << CHARGE_LC2CVDLYLV_POS)));
1879 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) & ~(1 << 15));
1880
1881 if (chrg->type == EXTERNAL_HW_MODE) {
1882 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) | (1 << 22));
1883 sctrl_analog_set(SCTRL_ANALOG_CTRL3, (sctrl_analog_get(SCTRL_ANALOG_CTRL3) \
1884 & ~(CHARGE_VLCSWLV_MASK << CHARGE_VLCSWLV_POS)) | (0xf << CHARGE_VLCSWLV_POS));
1885 }
1886 }
1887 } else if (chrg->step == STEP_TRICKLE) {
1888 /*trickle charge*/
1889 if (chrg->type == INTERNAL_SW_MODE || chrg->type == EXTERNAL_SW_MODE) {
1890 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) | (1 << 19));
1891 sctrl_analog_set(SCTRL_ANALOG_CTRL4, (sctrl_analog_get(SCTRL_ANALOG_CTRL4) \
1892 & ~(CHARGE_MANMODE_MASK << CHARGE_MANMODE_POS)) | (4 << CHARGE_MANMODE_POS));
1893 }
1894 } else if (chrg->step == STEP_EXTER_CC) {
1895 /*External CC charge*/
1896 if (chrg->type == EXTERNAL_SW_MODE) {
1897 sctrl_analog_set(SCTRL_ANALOG_CTRL3, (sctrl_analog_get(SCTRL_ANALOG_CTRL3)\
1898 & ~(CHARGE_LCP_MASK << CHARGE_LCP_POS)) | (usb_charge_oper_val(chrg->elect) << CHARGE_LCP_POS));
1899 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) | (1 << 19));
1900 sctrl_analog_set(SCTRL_ANALOG_CTRL4, (sctrl_analog_get(SCTRL_ANALOG_CTRL4) \
1901 & ~(CHARGE_MANMODE_MASK << CHARGE_MANMODE_POS)) | (2 << CHARGE_MANMODE_POS));
1902 }
1903 } else if (chrg->step == STEP_INTER_CC) {
1904 /*Internal CC charge*/
1905 sctrl_analog_set(SCTRL_ANALOG_CTRL3, (sctrl_analog_get(SCTRL_ANALOG_CTRL3)\
1906 & ~(CHARGE_LCP_MASK << CHARGE_LCP_POS)) | (usb_charge_oper_val(chrg->elect) << CHARGE_LCP_POS));
1907
1908 if (chrg->type == INTERNAL_SW_MODE) {
1909 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) | (1 << 19));
1910 sctrl_analog_set(SCTRL_ANALOG_CTRL4, (sctrl_analog_get(SCTRL_ANALOG_CTRL4) \
1911 & ~(CHARGE_MANMODE_MASK << CHARGE_MANMODE_POS)) | (2 << CHARGE_MANMODE_POS));
1912 }
1913
1914 if (chrg->type == EXTERNAL_SW_MODE) {
1915 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) | (1 << 19));
1916 sctrl_analog_set(SCTRL_ANALOG_CTRL4, (sctrl_analog_get(SCTRL_ANALOG_CTRL4) \
1917 & ~(CHARGE_MANMODE_MASK << CHARGE_MANMODE_POS)) | (2 << CHARGE_MANMODE_POS));
1918 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) & ~(1 << 15));
1919 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) & ~(1 << 11));
1920 }
1921 } else if (chrg->step == STEP_INTER_CV) {
1922 /*Internal CV charge*/
1923 if (chrg->type == INTERNAL_SW_MODE || chrg->type == EXTERNAL_SW_MODE) {
1924 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) | (1 << 19));
1925 sctrl_analog_set(SCTRL_ANALOG_CTRL4, (sctrl_analog_get(SCTRL_ANALOG_CTRL4) \
1926 & ~(CHARGE_MANMODE_MASK << CHARGE_MANMODE_POS)) | (1 << CHARGE_MANMODE_POS));
1927 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) & ~(1 << 15));
1928 }
1929
1930 if (chrg->type == EXTERNAL_SW_MODE)
1931 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) & ~(1 << 11));
1932
1933 if (chrg->type == EXTERNAL_HW_MODE) {
1934 sctrl_analog_set(SCTRL_ANALOG_CTRL4, sctrl_analog_get(SCTRL_ANALOG_CTRL4) & ~(1 << 11));
1935 sctrl_analog_set(SCTRL_ANALOG_CTRL3, sctrl_analog_get(SCTRL_ANALOG_CTRL3) & ~(1 << 22));
1936 sctrl_analog_set(SCTRL_ANALOG_CTRL3, (sctrl_analog_get(SCTRL_ANALOG_CTRL3) \
1937 & ~(CHARGE_VLCSWLV_MASK << CHARGE_VLCSWLV_POS)));
1938 }
1939 }
1940
1941 }
1942
charger_stop(UINT32 type)1943 void charger_stop(UINT32 type)
1944 {
1945 os_printf("%s\r\n", __FUNCTION__);
1946 charger_module_enable(0);
1947 }
1948 #endif
1949 #endif
1950
sctrl_ctrl(UINT32 cmd,void * param)1951 UINT32 sctrl_ctrl(UINT32 cmd, void *param)
1952 {
1953 UINT32 ret;
1954 UINT32 reg;
1955 GLOBAL_INT_DECLARATION();
1956
1957 ret = SCTRL_SUCCESS;
1958 GLOBAL_INT_DISABLE();
1959 switch (cmd) {
1960 case CMD_SCTRL_NORMAL_SLEEP:
1961 //sctrl_hw_sleep(*(UINT32 *)param);
1962 break;
1963
1964 case CMD_SCTRL_NORMAL_WAKEUP:
1965 //sctrl_hw_wakeup();
1966 break;
1967
1968 #if CONFIG_DEEP_PS
1969 #if PS_SUPPORT_MANUAL_SLEEP
1970 case CMD_SCTRL_RTOS_IDLE_SLEEP:
1971 sctrl_enter_rtos_idle_sleep(*(PS_DEEP_CTRL_PARAM *)param);
1972 break;
1973
1974 case CMD_SCTRL_RTOS_IDLE_WAKEUP:
1975 sctrl_exit_rtos_idle_sleep();
1976 break;
1977 #endif
1978
1979 case CMD_SCTRL_RTOS_DEEP_SLEEP:
1980 //sctrl_enter_rtos_deep_sleep((PS_DEEP_CTRL_PARAM *)param);
1981 break;
1982 #endif
1983
1984 case CMD_GET_CHIP_ID:
1985 ret = REG_READ(SCTRL_CHIP_ID);
1986 break;
1987
1988 case CMD_SCTRL_SET_FLASH_DPLL:
1989 reg = REG_READ(SCTRL_CONTROL);
1990 reg |= FLASH_26M_MUX_BIT;
1991 REG_WRITE(SCTRL_CONTROL, reg);
1992 break;
1993
1994 case CMD_SCTRL_SET_FLASH_DCO:
1995 reg = REG_READ(SCTRL_CONTROL);
1996 reg &= ~FLASH_26M_MUX_BIT;
1997 REG_WRITE(SCTRL_CONTROL, reg);
1998 break;
1999
2000 case CMD_SCTRL_DSP_POWERDOWN:
2001 case CMD_SCTRL_USB_POWERDOWN:
2002 case CMD_SCTRL_MODEM_POWERDOWN:
2003 case CMD_SCTRL_MAC_POWERDOWN:
2004 case CMD_SCTRL_DSP_POWERUP:
2005 case CMD_SCTRL_USB_POWERUP:
2006 case CMD_SCTRL_MAC_POWERUP:
2007 case CMD_SCTRL_MODEM_POWERUP:
2008 case CMD_SCTRL_BLE_POWERDOWN:
2009 case CMD_SCTRL_BLE_POWERUP:
2010
2011 #if (CONFIG_SOC_BK7271)
2012 case CMD_SCTRL_LBUS_POWERDOWN:
2013 case CMD_SCTRL_LBUS_POWERUP:
2014 case CMD_SCTRL_BT_POWERDOWN:
2015 case CMD_SCTRL_BT_POWERUP:
2016 #endif
2017 sctrl_subsys_power(cmd);
2018 break;
2019
2020 case CMD_GET_DEVICE_ID:
2021 ret = REG_READ(SCTRL_DEVICE_ID);
2022 break;
2023
2024 case CMD_GET_SCTRL_CONTROL:
2025 *((UINT32 *)param) = REG_READ(SCTRL_CONTROL);
2026 break;
2027
2028 case CMD_SET_SCTRL_CONTROL:
2029 REG_WRITE(SCTRL_CONTROL, *((UINT32 *)param));
2030 break;
2031
2032 case CMD_SCTRL_MCLK_SELECT:
2033 reg = REG_READ(SCTRL_CONTROL);
2034 reg &= ~(MCLK_MUX_MASK << MCLK_MUX_POSI);
2035 reg |= ((*(UINT32 *)param) & MCLK_MUX_MASK) << MCLK_MUX_POSI;
2036
2037 #if (CONFIG_SOC_BK7251)
2038 if (((reg >> MCLK_MUX_POSI) & MCLK_MUX_MASK) == MCLK_SELECT_DPLL) {
2039 if ((((reg >> MCLK_DIV_POSI) & MCLK_DIV_MASK) <= MCLK_DIV_7))
2040 reg &= ~HCLK_DIV2_EN_BIT;
2041 else
2042 reg |= HCLK_DIV2_EN_BIT;
2043 }
2044 #endif
2045
2046 REG_WRITE(SCTRL_CONTROL, reg);
2047 break;
2048
2049 case CMD_SCTRL_MCLK_DIVISION:
2050 reg = REG_READ(SCTRL_CONTROL);
2051 reg &= ~(MCLK_DIV_MASK << MCLK_DIV_POSI);
2052 reg |= ((*(UINT32 *)param) & MCLK_DIV_MASK) << MCLK_DIV_POSI;
2053
2054 #if (CONFIG_SOC_BK7251)
2055 if (((reg >> MCLK_MUX_POSI) & MCLK_MUX_MASK) == MCLK_SELECT_DPLL) {
2056 if ((((reg >> MCLK_DIV_POSI) & MCLK_DIV_MASK) <= MCLK_DIV_7))
2057 reg &= ~HCLK_DIV2_EN_BIT;
2058 else
2059 reg |= HCLK_DIV2_EN_BIT;
2060 }
2061 #endif
2062
2063 REG_WRITE(SCTRL_CONTROL, reg);
2064 break;
2065
2066 case CMD_SCTRL_MCLK_MUX_GET:
2067 reg = ((REG_READ(SCTRL_CONTROL) >> MCLK_MUX_POSI) & MCLK_MUX_MASK);
2068 *(UINT32 *)param = reg;
2069 break;
2070
2071 case CMD_SCTRL_MCLK_DIV_GET:
2072 reg = ((REG_READ(SCTRL_CONTROL) >> MCLK_DIV_POSI) & MCLK_DIV_MASK);
2073 *(UINT32 *)param = reg;
2074 break;
2075
2076 case CMD_SCTRL_RESET_SET:
2077 reg = REG_READ(SCTRL_RESET);
2078 reg |= ((*(UINT32 *)param) & SCTRL_RESET_MASK);
2079 REG_WRITE(SCTRL_RESET, reg);
2080 break;
2081
2082 case CMD_SCTRL_RESET_CLR:
2083 reg = REG_READ(SCTRL_RESET);
2084 reg &= ~((*(UINT32 *)param) & SCTRL_RESET_MASK);
2085 REG_WRITE(SCTRL_RESET, reg);
2086 break;
2087
2088 case CMD_SCTRL_MODEM_SUBCHIP_RESET:
2089 case CMD_SCTRL_USB_SUBSYS_RESET:
2090 case CMD_SCTRL_DSP_SUBSYS_RESET:
2091 sctrl_subsys_reset(cmd);
2092 break;
2093
2094 case CMD_SCTRL_MAC_SUBSYS_RESET:
2095 #if (!CONFIG_SOC_BK7271)
2096 sctrl_subsys_reset(cmd);
2097 #else
2098 ret = REG_READ(SCTRL_MODEM_CORE_RESET_PHY_HCLK);
2099 ret = ret & (~((MAC_SUBSYS_RESET_MASK) << MAC_SUBSYS_RESET_POSI));
2100 reg = ret | ((MAC_SUBSYS_RESET_WORD & MAC_SUBSYS_RESET_MASK)
2101 << MAC_SUBSYS_RESET_POSI);
2102 REG_WRITE(SCTRL_MODEM_CORE_RESET_PHY_HCLK, reg);
2103
2104 delay(1);
2105 reg = ret;
2106 REG_WRITE(SCTRL_MODEM_CORE_RESET_PHY_HCLK, reg);
2107
2108 /*resetting, and waiting for done*/
2109 reg = REG_READ(SCTRL_RESET);
2110 while (reg & MODEM_CORE_RESET_BIT) {
2111 delay(10);
2112 reg = REG_READ(SCTRL_RESET);
2113 }
2114 ret = SCTRL_SUCCESS;
2115 #endif
2116 break;
2117
2118 case CMD_SCTRL_MODEM_CORE_RESET:
2119 ret = REG_READ(SCTRL_MODEM_CORE_RESET_PHY_HCLK);
2120 ret = ret & (~((MODEM_CORE_RESET_MASK) << MODEM_CORE_RESET_POSI));
2121 reg = ret | ((MODEM_CORE_RESET_WORD & MODEM_CORE_RESET_MASK)
2122 << MODEM_CORE_RESET_POSI);
2123 REG_WRITE(SCTRL_MODEM_CORE_RESET_PHY_HCLK, reg);
2124
2125 delay(1);
2126 reg = ret;
2127 REG_WRITE(SCTRL_MODEM_CORE_RESET_PHY_HCLK, reg);
2128
2129 /*resetting, and waiting for done*/
2130 reg = REG_READ(SCTRL_RESET);
2131 while (reg & MODEM_CORE_RESET_BIT) {
2132 delay(10);
2133 reg = REG_READ(SCTRL_RESET);
2134 }
2135 ret = SCTRL_SUCCESS;
2136 break;
2137
2138 case CMD_SCTRL_MPIF_CLK_INVERT:
2139 reg = REG_READ(SCTRL_CONTROL);
2140 reg |= MPIF_CLK_INVERT_BIT;
2141 REG_WRITE(SCTRL_CONTROL, reg);
2142 break;
2143
2144 case CMD_SCTRL_BLK_ENABLE:
2145 reg = REG_READ(SCTRL_BLOCK_EN_CFG);
2146 reg &= (~(BLOCK_EN_WORD_MASK << BLOCK_EN_WORD_POSI));
2147 reg |= (BLOCK_EN_WORD_PWD & BLOCK_EN_WORD_MASK) << BLOCK_EN_WORD_POSI;
2148 reg |= ((*(UINT32 *)param) & BLOCK_EN_VALID_MASK);
2149 REG_WRITE(SCTRL_BLOCK_EN_CFG, reg);
2150 break;
2151
2152 case CMD_SCTRL_BLK_DISABLE:
2153 reg = REG_READ(SCTRL_BLOCK_EN_CFG);
2154 reg &= (~(BLOCK_EN_WORD_MASK << BLOCK_EN_WORD_POSI));
2155 reg |= (BLOCK_EN_WORD_PWD & BLOCK_EN_WORD_MASK) << BLOCK_EN_WORD_POSI;
2156 reg &= ~((*(UINT32 *)param) & BLOCK_EN_VALID_MASK);
2157 REG_WRITE(SCTRL_BLOCK_EN_CFG, reg);
2158 break;
2159
2160 case CMD_SCTRL_BIAS_REG_SET:
2161 reg = REG_READ(SCTRL_BIAS);
2162 reg |= (*(UINT32 *)param);
2163 #if (CONFIG_SOC_BK7271)
2164 sctrl_analog_set(SCTRL_BIAS, reg);
2165 #else
2166 REG_WRITE(SCTRL_BIAS, reg);
2167 #endif
2168 break;
2169
2170 case CMD_SCTRL_BIAS_REG_CLEAN:
2171 reg = REG_READ(SCTRL_BIAS);
2172 reg &= ~(*(UINT32 *)param);
2173 #if (CONFIG_SOC_BK7271)
2174 sctrl_analog_set(SCTRL_BIAS, reg);
2175 #else
2176 REG_WRITE(SCTRL_BIAS, reg);
2177 #endif
2178 break;
2179
2180 case CMD_SCTRL_BIAS_REG_READ:
2181 ret = REG_READ(SCTRL_BIAS);
2182 break;
2183
2184 case CMD_SCTRL_BIAS_GET_CALI_OUT:
2185 #if (CONFIG_SOC_BK7271)
2186 reg = REG_READ(PMU_STATUS);
2187 ret = ((reg >> PMU_BAIS_CAL_OUT_POSI) & PMU_BAIS_CAL_OUT_MASK);
2188 #endif
2189 break;
2190
2191 case CMD_SCTRL_BIAS_REG_WRITE:
2192 #if (CONFIG_SOC_BK7271)
2193 sctrl_analog_set(SCTRL_BIAS, *(UINT32 *)param);
2194 #else
2195 REG_WRITE(SCTRL_BIAS, *(UINT32 *)param);
2196 #endif
2197 break;
2198
2199 case CMD_SCTRL_ANALOG_CTRL4_SET:
2200 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL4);
2201 reg |= (*(UINT32 *)param);
2202 sctrl_analog_set(SCTRL_ANALOG_CTRL4, reg);
2203 break;
2204
2205 case CMD_SCTRL_ANALOG_CTRL4_CLEAN:
2206 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL4);
2207 reg &= ~(*(UINT32 *)param);
2208 sctrl_analog_set(SCTRL_ANALOG_CTRL4, reg);
2209 break;
2210
2211 #if (CONFIG_SOC_BK7271)
2212 case CMD_SCTRL_ANALOG_CTRL9_REAL_SET:
2213 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL9_REAL);
2214 reg |= (*(UINT32 *)param);
2215 sctrl_analog_set(SCTRL_ANALOG_CTRL9_REAL, reg);
2216 break;
2217
2218 case CMD_SCTRL_ANALOG_CTRL9_REAL_CLEAN:
2219 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL9_REAL);
2220 reg &= ~(*(UINT32 *)param);
2221 sctrl_analog_set(SCTRL_ANALOG_CTRL9_REAL, reg);
2222 break;
2223 #endif
2224
2225 case CMD_SCTRL_CALI_DPLL:
2226 sctrl_cali_dpll(0);
2227 break;
2228
2229 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX)
2230 case CMD_BLE_RF_PTA_EN:
2231 reg = REG_READ(SCTRL_CONTROL);
2232 reg |= (BLE_RF_PTA_EN_BIT);
2233 REG_WRITE(SCTRL_CONTROL, reg);
2234 break;
2235 case CMD_BLE_RF_PTA_DIS:
2236 reg = REG_READ(SCTRL_CONTROL);
2237 reg &= ~(BLE_RF_PTA_EN_BIT);
2238 REG_WRITE(SCTRL_CONTROL, reg);
2239 break;
2240 #endif
2241
2242
2243 #if (!CONFIG_SOC_BK7231)
2244 #if (CONFIG_SOC_BK7271)
2245 case CMD_SCTRL_SET_XTALH_CTUNE:
2246 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL4);
2247 reg &= ~(XTALH_CTUNE_MASK << XTALH_CTUNE_POSI);
2248 reg |= (((*(UINT32 *)param) &XTALH_CTUNE_MASK) << XTALH_CTUNE_POSI);
2249 sctrl_analog_set(SCTRL_ANALOG_CTRL4, reg);
2250 break;
2251
2252 case CMD_SCTRL_GET_XTALH_CTUNE:
2253 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL4);
2254 ret = ((reg >> XTALH_CTUNE_POSI) & XTALH_CTUNE_MASK);
2255 break;
2256 #else
2257 case CMD_SCTRL_SET_XTALH_CTUNE:
2258 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL2);
2259 reg &= ~(XTALH_CTUNE_MASK << XTALH_CTUNE_POSI);
2260 reg |= (((*(UINT32 *)param) &XTALH_CTUNE_MASK) << XTALH_CTUNE_POSI);
2261 sctrl_analog_set(SCTRL_ANALOG_CTRL2, reg);
2262 break;
2263
2264 case CMD_SCTRL_GET_XTALH_CTUNE:
2265 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL2);
2266 ret = ((reg >> XTALH_CTUNE_POSI) & XTALH_CTUNE_MASK);
2267 break;
2268
2269 case CMD_BLE_RF_BIT_SET:
2270 reg = REG_READ(SCTRL_CONTROL);
2271 reg |= BLE_RF_EN_BIT;
2272 REG_WRITE(SCTRL_CONTROL, reg);
2273 break;
2274
2275 case CMD_BLE_RF_BIT_CLR:
2276 reg = REG_READ(SCTRL_CONTROL);
2277 reg &= ~(BLE_RF_EN_BIT);
2278 REG_WRITE(SCTRL_CONTROL, reg);
2279 break;
2280
2281 case CMD_BLE_RF_BIT_GET:
2282 reg = REG_READ(SCTRL_CONTROL);
2283 *((UINT32 *)param) = reg & (BLE_RF_EN_BIT);
2284 break;
2285
2286 case CMD_EFUSE_WRITE_BYTE:
2287 ret = sctrl_write_efuse(param);
2288 break;
2289
2290 case CMD_EFUSE_READ_BYTE:
2291 ret = sctrl_read_efuse(param);
2292 break;
2293 #endif
2294
2295 #if (!CONFIG_SOC_BK7231N) && (!CONFIG_SOC_BK7236A) && (!CONFIG_SOC_BK7256XX) && (!CONFIG_SOC_BK7236)
2296 case CMD_QSPI_VDDRAM_VOLTAGE:
2297 reg = REG_READ(SCTRL_CONTROL);
2298 reg &= ~(PSRAM_VDDPAD_VOLT_MASK << PSRAM_VDDPAD_VOLT_POSI);
2299 reg |= (((*(UINT32 *)param) & PSRAM_VDDPAD_VOLT_MASK) << PSRAM_VDDPAD_VOLT_POSI);
2300 REG_WRITE(SCTRL_CONTROL, reg);
2301 break;
2302
2303 case CMD_QSPI_IO_VOLTAGE:
2304 reg = REG_READ(SCTRL_CONTROL);
2305 reg &= ~(QSPI_IO_VOLT_MASK << QSPI_IO_VOLT_POSI);
2306 reg |= (((*(UINT32 *)param) & QSPI_IO_VOLT_MASK) << QSPI_IO_VOLT_POSI);
2307 REG_WRITE(SCTRL_CONTROL, reg);
2308 break;
2309 #endif
2310 #endif // (!CONFIG_SOC_BK7231)
2311
2312 #if (CONFIG_SOC_BK7251) || (CONFIG_SOC_BK7271)
2313 case CMD_SCTRL_OPEN_DAC_ANALOG:
2314 #if (CONFIG_SOC_BK7271)
2315 sctrl_analog_set(SCTRL_ANALOG_CTRL8, 0x300B194E);
2316 sctrl_analog_set(SCTRL_ANALOG_CTRL9, 0x82205600);
2317 sctrl_analog_set(SCTRL_ANALOG_CTRL10, 0x80803390);
2318 sctrl_analog_set(SCTRL_ANALOG_CTRL13, 0x2108DB28);
2319
2320 sctrl_analog_set(SCTRL_ANALOG_AUDIO_PLL_CTRL, 0x00B09350 | AUDIO_PLL_AUDIO_EN | AUDIO_PLL_RESET);
2321 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL13);
2322 reg |= AUDIO_DCO_EN;
2323 sctrl_analog_set(SCTRL_ANALOG_CTRL13, reg);
2324 #endif
2325 //cause increase CONFIG_MCU_PS elect
2326 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL9);
2327 reg |= EN_AUD_DAC_L | EN_AUD_DAC_R
2328 | DAC_PA_OUTPUT_EN | DAC_DRIVER_OUTPUT_EN
2329 | AUD_DAC_DGA_EN;
2330 sctrl_analog_set(SCTRL_ANALOG_CTRL9, reg);
2331
2332 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL10);
2333 reg |= DAC_N_END_OUPT_L | DAC_N_END_OUPT_R;
2334 sctrl_analog_set(SCTRL_ANALOG_CTRL10, reg);
2335 break;
2336
2337 case CMD_SCTRL_CLOSE_DAC_ANALOG:
2338 //cause reduce CONFIG_MCU_PS elect
2339 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL9);
2340 reg &= ~(EN_AUD_DAC_L | EN_AUD_DAC_R
2341 | DAC_PA_OUTPUT_EN | DAC_DRIVER_OUTPUT_EN
2342 | AUD_DAC_DGA_EN);
2343 sctrl_analog_set(SCTRL_ANALOG_CTRL9, reg);
2344
2345 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL10);
2346 reg &= ~(DAC_N_END_OUPT_L | DAC_N_END_OUPT_R);
2347 sctrl_analog_set(SCTRL_ANALOG_CTRL10, reg);
2348 break;
2349
2350 #if (!CONFIG_SOC_BK7271)
2351 case CMD_SCTRL_OPEN_ADC_MIC_ANALOG:
2352 //cause increase CONFIG_MCU_PS elect
2353 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL8);
2354 reg &= ~(SPI_PWD_AUD_ADC_L | SPI_PWD_AUD_ADC_R);
2355 sctrl_analog_set(SCTRL_ANALOG_CTRL8, reg);
2356 break;
2357
2358 case CMD_SCTRL_CLOSE_ADC_MIC_ANALOG:
2359 //cause reduce CONFIG_MCU_PS elect
2360 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL8);
2361 reg |= (SPI_PWD_AUD_ADC_L | SPI_PWD_AUD_ADC_R);
2362 sctrl_analog_set(SCTRL_ANALOG_CTRL8, reg);
2363 break;
2364 #else
2365 case CMD_SCTRL_OPEN_ADC_MIC_ANALOG:
2366 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL13);
2367 reg &= ~(MIC1_PWR_DOWN | MIC2_PWR_DOWN | MIC3_PWR_DOWN | MIC4_PWR_DOWN | MIC5_PWR_DOWN | MIC6_PWR_DOWN);
2368 sctrl_analog_set(SCTRL_ANALOG_CTRL13, reg);
2369 break;
2370
2371 case CMD_SCTRL_CLOSE_ADC_MIC_ANALOG:
2372 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL13);
2373 reg |= (MIC1_PWR_DOWN | MIC2_PWR_DOWN | MIC3_PWR_DOWN | MIC4_PWR_DOWN | MIC5_PWR_DOWN | MIC6_PWR_DOWN);
2374 sctrl_analog_set(SCTRL_ANALOG_CTRL13, reg);
2375 break;
2376 #endif
2377
2378 case CMD_SCTRL_ENALBLE_ADC_LINE_IN:
2379 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL8);
2380 reg |= LINE_IN_EN;
2381 #if (CONFIG_SOC_BK7271)
2382 reg |= LINE2_IN_EN;
2383 #endif
2384 sctrl_analog_set(SCTRL_ANALOG_CTRL8, reg);
2385
2386 #if (CONFIG_SOC_BK7271)/*set gpio 2 and 3 to high impendance*/
2387 reg = GPIO_CFG_PARAM(GPIO2, GMODE_SET_HIGH_IMPENDANCE);
2388 sddev_control(DD_DEV_TYPE_GPIO, CMD_GPIO_CFG, ®);
2389 reg = GPIO_CFG_PARAM(GPIO3, GMODE_SET_HIGH_IMPENDANCE);
2390 sddev_control(DD_DEV_TYPE_GPIO, CMD_GPIO_CFG, ®);
2391 #endif
2392 break;
2393
2394 case CMD_SCTRL_DISALBLE_ADC_LINE_IN:
2395 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL8);
2396 reg &= ~LINE_IN_EN;
2397 #if (CONFIG_SOC_BK7271)
2398 reg &= ~LINE2_IN_EN;
2399 #endif
2400 sctrl_analog_set(SCTRL_ANALOG_CTRL8, reg);
2401 break;
2402
2403 case CMD_SCTRL_SET_DAC_VOLUME_ANALOG:
2404 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL8);
2405 reg &= ~(AUD_DAC_GAIN_MASK << AUD_DAC_GAIN_POSI);
2406 reg |= (((*(UINT32 *)param) & AUD_DAC_GAIN_MASK) << AUD_DAC_GAIN_POSI);
2407 sctrl_analog_set(SCTRL_ANALOG_CTRL8, reg);
2408 break;
2409
2410 case CMD_SCTRL_SET_LINEIN_VOLUME_ANALOG:
2411 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL8);
2412 reg &= ~(LINE_IN_GAIN_MASK << LINE_IN_GAIN_POSI);
2413 reg |= (((*(UINT32 *)param) & LINE_IN_GAIN_MASK) << LINE_IN_GAIN_POSI);
2414 sctrl_analog_set(SCTRL_ANALOG_CTRL8, reg);
2415 break;
2416
2417 case CMD_SCTRL_SET_VOLUME_PORT:
2418 if ((*(UINT32 *)param) == AUDIO_DAC_VOL_DIFF_MODE) {
2419 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL9);
2420 reg |= (DAC_DIFF_EN);
2421 sctrl_analog_set(SCTRL_ANALOG_CTRL9, reg);
2422
2423 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL10);
2424 reg |= (DAC_N_END_OUPT_L | DAC_N_END_OUPT_R);
2425 reg &= ~(DAC_VSEL_MASK << DAC_VSEL_POSI);
2426 reg |= ((0x3 & DAC_VSEL_MASK) << DAC_VSEL_POSI);;
2427 sctrl_analog_set(SCTRL_ANALOG_CTRL10, reg);
2428 } else if ((*(UINT32 *)param) == AUDIO_DAC_VOL_SINGLE_MODE) {
2429 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL9);
2430 reg &= ~(DAC_DIFF_EN);
2431 sctrl_analog_set(SCTRL_ANALOG_CTRL9, reg);
2432
2433 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL10);
2434 reg &= ~(DAC_N_END_OUPT_L | DAC_N_END_OUPT_R);
2435 reg &= ~(DAC_VSEL_MASK << DAC_VSEL_POSI);
2436 reg |= ((0 & DAC_VSEL_MASK) << DAC_VSEL_POSI);;
2437 sctrl_analog_set(SCTRL_ANALOG_CTRL10, reg);
2438 }
2439 break;
2440
2441 case CMD_SCTRL_SET_AUD_DAC_MUTE:
2442 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL8);
2443 if ((*(UINT32 *)param) == AUDIO_DAC_ANALOG_MUTE) {
2444 reg |= (AUD_DAC_MUTE_EN);
2445 sctrl_analog_set(SCTRL_ANALOG_CTRL8, reg);
2446 } else if ((*(UINT32 *)param) == AUDIO_DAC_ANALOG_UNMUTE) {
2447 reg &= ~(AUD_DAC_MUTE_EN);
2448 sctrl_analog_set(SCTRL_ANALOG_CTRL8, reg);
2449 }
2450 break;
2451 #endif // (CONFIG_SOC_BK7251) || (CONFIG_SOC_BK7271)
2452
2453 #if (CONFIG_SOC_BK7271)
2454 case CMD_SCTRL_AUDIO_PLL:
2455 if ((*(UINT32 *)param) == 8000) { //8KHz
2456 sctrl_analog_set(SCTRL_ANALOG_AUDIO_PLL_SDM, 0x3C7EA932);
2457 reg = sctrl_analog_get(SCTRL_ANALOG_AUDIO_PLL_CTRL);
2458 reg &= ~(AUDIO_PLL_CKSEL);
2459 sctrl_analog_set(SCTRL_ANALOG_AUDIO_PLL_CTRL, reg);
2460 } else if ((*(UINT32 *)param) == 16000) { //16KHz
2461 sctrl_analog_set(SCTRL_ANALOG_AUDIO_PLL_SDM, 0x3C7EA932);
2462 reg = sctrl_analog_get(SCTRL_ANALOG_AUDIO_PLL_CTRL);
2463 reg &= ~(AUDIO_PLL_CKSEL);
2464 sctrl_analog_set(SCTRL_ANALOG_AUDIO_PLL_CTRL, reg);
2465 } else if ((*(UINT32 *)param) == 44100) { //44.1KHz
2466 sctrl_analog_set(SCTRL_ANALOG_AUDIO_PLL_SDM, 0x37945EA6);
2467 reg = sctrl_analog_get(SCTRL_ANALOG_AUDIO_PLL_CTRL);
2468 reg |= (AUDIO_PLL_CKSEL);
2469 sctrl_analog_set(SCTRL_ANALOG_AUDIO_PLL_CTRL, reg);
2470 } else if ((*(UINT32 *)param) == 48000) { //48KHz
2471 sctrl_analog_set(SCTRL_ANALOG_AUDIO_PLL_SDM, 0x3C7EA932);
2472 reg = sctrl_analog_get(SCTRL_ANALOG_AUDIO_PLL_CTRL);
2473 reg |= (AUDIO_PLL_CKSEL);
2474 sctrl_analog_set(SCTRL_ANALOG_AUDIO_PLL_CTRL, reg);
2475 }
2476 reg = sctrl_analog_get(SCTRL_ANALOG_AUDIO_PLL_CTRL);
2477 reg &= ~(AUDIO_PLL_SPI_TRIGGER);
2478 sctrl_analog_set(SCTRL_ANALOG_AUDIO_PLL_CTRL, reg);
2479 reg |= (AUDIO_PLL_SPI_TRIGGER);
2480 sctrl_analog_set(SCTRL_ANALOG_AUDIO_PLL_CTRL, reg);
2481 break;
2482 #endif
2483
2484 #if ((!CONFIG_SOC_BK7231) && (!CONFIG_SOC_BK7271))
2485 case CMD_SCTRL_SET_ANALOG6:
2486 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL6);
2487 reg |= (DPLL_CLK_FOR_AUDIO_EN | DPLL_DIVIDER_CLK_SEL | DPLL_RESET);
2488 sctrl_analog_set(SCTRL_ANALOG_CTRL6, reg);
2489 break;
2490 #endif
2491 case CMD_SCTRL_SET_ANALOG0:
2492 sctrl_analog_set(SCTRL_ANALOG_CTRL0, (*(UINT32 *)param));
2493 break;
2494 case CMD_SCTRL_SET_ANALOG1:
2495 sctrl_analog_set(SCTRL_ANALOG_CTRL1, (*(UINT32 *)param));
2496 break;
2497 case CMD_SCTRL_SET_ANALOG2:
2498 sctrl_analog_set(SCTRL_ANALOG_CTRL2, (*(UINT32 *)param));
2499 break;
2500 case CMD_SCTRL_SET_ANALOG3:
2501 sctrl_analog_set(SCTRL_ANALOG_CTRL3, (*(UINT32 *)param));
2502 break;
2503 case CMD_SCTRL_SET_ANALOG4:
2504 sctrl_analog_set(SCTRL_ANALOG_CTRL4, (*(UINT32 *)param));
2505 break;
2506 case CMD_SCTRL_SET_ANALOG5:
2507 sctrl_analog_set(SCTRL_ANALOG_CTRL5, (*(UINT32 *)param));
2508 break;
2509 case CMD_SCTRL_GET_ANALOG0:
2510 ret = sctrl_analog_get(SCTRL_ANALOG_CTRL0);
2511 break;
2512 case CMD_SCTRL_GET_ANALOG1:
2513 ret = sctrl_analog_get(SCTRL_ANALOG_CTRL1);
2514 break;
2515 case CMD_SCTRL_GET_ANALOG2:
2516 ret = sctrl_analog_get(SCTRL_ANALOG_CTRL2);
2517 break;
2518 case CMD_SCTRL_GET_ANALOG3:
2519 ret = sctrl_analog_get(SCTRL_ANALOG_CTRL3);
2520 break;
2521 case CMD_SCTRL_GET_ANALOG4:
2522 ret = sctrl_analog_get(SCTRL_ANALOG_CTRL4);
2523 break;
2524 case CMD_SCTRL_GET_ANALOG5:
2525 ret = sctrl_analog_get(SCTRL_ANALOG_CTRL5);
2526 break;
2527 #if (CONFIG_SOC_BK7251)
2528 case CMD_SCTRL_SET_ANALOG7:
2529 sctrl_analog_set(SCTRL_ANALOG_CTRL7, (*(UINT32 *)param));
2530 break;
2531 case CMD_SCTRL_SET_ANALOG8:
2532 sctrl_analog_set(SCTRL_ANALOG_CTRL8, (*(UINT32 *)param));
2533 break;
2534 case CMD_SCTRL_SET_ANALOG9:
2535 sctrl_analog_set(SCTRL_ANALOG_CTRL9, (*(UINT32 *)param));
2536 break;
2537 case CMD_SCTRL_SET_ANALOG10:
2538 sctrl_analog_set(SCTRL_ANALOG_CTRL10, (*(UINT32 *)param));
2539 break;
2540 case CMD_SCTRL_GET_ANALOG7:
2541 ret = sctrl_analog_get(SCTRL_ANALOG_CTRL7);
2542 break;
2543 case CMD_SCTRL_GET_ANALOG8:
2544 ret = sctrl_analog_get(SCTRL_ANALOG_CTRL8);
2545 break;
2546 case CMD_SCTRL_GET_ANALOG9:
2547 ret = sctrl_analog_get(SCTRL_ANALOG_CTRL9);
2548 break;
2549 case CMD_SCTRL_GET_ANALOG10:
2550 ret = sctrl_analog_get(SCTRL_ANALOG_CTRL10);
2551 break;
2552
2553 case CMD_SCTRL_AUDIO_PLL:
2554 if ((*(UINT32 *)param) == 48000000) //48MHz
2555 sctrl_analog_set(SCTRL_ANALOG_CTRL5, 0x3B13B13B);
2556 else if ((*(UINT32 *)param) == 48128000) //48.128MHz
2557 sctrl_analog_set(SCTRL_ANALOG_CTRL5, 0x3B3C05AC);
2558 else if ((*(UINT32 *)param) == 48384000) //48.384MHz
2559 sctrl_analog_set(SCTRL_ANALOG_CTRL5, 0x3B8CAE8E);
2560 else if ((*(UINT32 *)param) == 49152000) //49.152MHz
2561 sctrl_analog_set(SCTRL_ANALOG_CTRL5, 0x3C7EA932);
2562 else if ((*(UINT32 *)param) == 49392000) //49.392MHz
2563 sctrl_analog_set(SCTRL_ANALOG_CTRL5, 0x3CCA4785);
2564 else if ((*(UINT32 *)param) == 50688000) //50.688MHz
2565 sctrl_analog_set(SCTRL_ANALOG_CTRL5, 0x3E629E7C);
2566 else if ((*(UINT32 *)param) == 50803200) //50.8032MHz
2567 sctrl_analog_set(SCTRL_ANALOG_CTRL5, 0x3E86EA7A);
2568 else
2569 sctrl_analog_set(SCTRL_ANALOG_CTRL5, 0x3B13B13B);
2570 break;
2571 #endif
2572
2573 #if CONFIG_USB_CHARGE
2574 case CMD_SCTRL_USB_CHARGE_CAL:
2575 if (1 == ((CHARGE_OPER_PTR)param)->step)
2576 charger_vlcf_calibration(0);
2577 else if (2 == ((CHARGE_OPER_PTR)param)->step)
2578 charger_icp_calibration(0);
2579 else if (3 == ((CHARGE_OPER_PTR)param)->step)
2580 charger_vcv_calibration(0);
2581 else if (4 == ((CHARGE_OPER_PTR)param)->step)
2582 charger_calib_get(((CHARGE_OPER_PTR)param)->cal);
2583 break;
2584 case CMD_SCTRL_USB_CHARGE_START:
2585 charger_start(param);
2586 break;
2587 case CMD_SCTRL_USB_CHARGE_STOP:
2588 charger_stop((*(UINT32 *)param));
2589 break;
2590 #endif
2591
2592 case CMD_SCTRL_SET_LOW_PWR_CLK:
2593 reg = REG_READ(SCTRL_LOW_PWR_CLK);
2594 reg &= ~(LPO_CLK_MUX_MASK);
2595 reg |= ((*(UINT32 *)param) << LPO_CLK_MUX_POSI);
2596 REG_WRITE(SCTRL_LOW_PWR_CLK, reg);
2597 break;
2598
2599 case CMD_SCTRL_SET_GADC_SEL:
2600 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX) || (CONFIG_SOC_BK7236)
2601 reg = sctrl_analog_get(SCTRL_ANALOG_CTRL4);
2602 reg &= ~(GADC_CAL_SEL_MASK << GADC_CAL_SEL_POSI);
2603 reg |= (((*(UINT32 *)param) & GADC_CAL_SEL_MASK) << GADC_CAL_SEL_POSI);
2604 sctrl_analog_set(SCTRL_ANALOG_CTRL4, reg);
2605 #endif
2606 break;
2607
2608 case CMD_SCTRL_SET_VDD_VALUE:
2609 reg = REG_READ(SCTRL_DIGTAL_VDD);
2610 reg &= (~(DIG_VDD_ACTIVE_MASK << DIG_VDD_ACTIVE_POSI));
2611 reg |= ((*(UINT32 *)param) << DIG_VDD_ACTIVE_POSI);
2612 REG_WRITE(SCTRL_DIGTAL_VDD, reg);
2613 break;
2614 case CMD_SCTRL_GET_VDD_VALUE:
2615 reg = REG_READ(SCTRL_DIGTAL_VDD);
2616 ret = (reg >> DIG_VDD_ACTIVE_POSI) & DIG_VDD_ACTIVE_MASK;
2617 break;
2618
2619 case CMD_GET_SCTRL_RETETION:
2620 *((UINT32 *)param) = REG_READ(SCTRL_SW_RETENTION);
2621 break;
2622
2623 case CMD_SET_SCTRL_RETETION:
2624 REG_WRITE(SCTRL_SW_RETENTION, *((UINT32 *)param));
2625 break;
2626
2627 case CMD_SCTRL_MODEM_AHB_CLOCK_DISABLE:
2628 /* Modem AHB clock disable*/
2629 #if (CONFIG_SOC_BK7271)
2630 reg = REG_READ(SCTRL_CONTROL);
2631 reg &= ~PHY_HCLK_EN_BIT;
2632 REG_WRITE(SCTRL_CONTROL, reg);
2633 #else
2634 reg = REG_READ(SCTRL_MODEM_CORE_RESET_PHY_HCLK);
2635 reg &= ~PHY_HCLK_EN_BIT;
2636 REG_WRITE(SCTRL_MODEM_CORE_RESET_PHY_HCLK, reg);
2637 #endif
2638 break;
2639 case CMD_SCTRL_MODEM_CLOCK480M_DISABLE:
2640 /* Modem Subsystem clock 480m disable*/
2641 reg = REG_READ(SCTRL_CONTROL);
2642 REG_WRITE(SCTRL_CONTROL, reg | MODEM_CLK480M_PWD_BIT);
2643 break;
2644
2645 case CMD_SCTRL_MODEM_AHB_CLOCK_ENABLE:
2646 /* Modem AHB clock enable*/
2647 #if (CONFIG_SOC_BK7271)
2648 reg = REG_READ(SCTRL_CONTROL);
2649 REG_WRITE(SCTRL_CONTROL, reg | PHY_HCLK_EN_BIT);
2650 #else
2651 reg = REG_READ(SCTRL_MODEM_CORE_RESET_PHY_HCLK);
2652 REG_WRITE(SCTRL_MODEM_CORE_RESET_PHY_HCLK, reg | PHY_HCLK_EN_BIT);
2653 #endif
2654 break;
2655
2656 case CMD_SCTRL_MODEM_CLOCK480M_ENABLE:
2657 /* Modem Subsystem clock 480m enable*/
2658 reg = REG_READ(SCTRL_CONTROL);
2659 reg &= ~MODEM_CLK480M_PWD_BIT;
2660 REG_WRITE(SCTRL_CONTROL, reg);
2661 break;
2662
2663 case CMD_SCTRL_MAC_AHB_CLOCK_DISABLE:
2664 sctrl_mac_ahb_slave_clock_disable();
2665 break;
2666 case CMD_SCTRL_MAC_CLOCK480M_DISABLE:
2667 /* Mac Subsystem clock 480m disable*/
2668 reg = REG_READ(SCTRL_CONTROL);
2669 REG_WRITE(SCTRL_CONTROL, reg | MAC_CLK480M_PWD_BIT);
2670 break;
2671 case CMD_SCTRL_MAC_AHB_CLOCK_ENABLE:
2672 sctrl_mac_ahb_slave_clock_enable();
2673 break;
2674 case CMD_SCTRL_MAC_CLOCK480M_ENABLE:
2675 /* Mac Subsystem clock 480m enable*/
2676 reg = REG_READ(SCTRL_CONTROL);
2677 reg &= ~MAC_CLK480M_PWD_BIT;
2678 REG_WRITE(SCTRL_CONTROL, reg);
2679 break;
2680
2681 case CMD_SCTRL_BLOCK_EN_MUX_SET:
2682 reg = REG_READ(SCTRL_BLOCK_EN_MUX);
2683 reg &= ~(0x1FF);
2684 reg |= *((UINT32 *)param);
2685 REG_WRITE(SCTRL_BLOCK_EN_MUX, reg);
2686 break;
2687
2688 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7256XX)
2689 case CMD_SCTRL_FIX_DPLL_DIV:
2690 if ((DEVICE_ID_BK7231N_P & DEVICE_ID_MASK) != (sctrl_ctrl(CMD_GET_DEVICE_ID, NULL) & DEVICE_ID_MASK)) {
2691 sctrl_fix_dpll_div();
2692 }
2693 #endif
2694 default:
2695 ret = SCTRL_FAILURE;
2696 break;
2697 }
2698 GLOBAL_INT_RESTORE();
2699
2700 return ret;
2701 }
2702 #endif
2703 // EOF
2704
2705