1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef HPM_SDMMC_CARD_H 9 #define HPM_SDMMC_CARD_H 10 11 #include <stdint.h> 12 13 /** 14 * @brief Common SD/MMC commands 15 */ 16 enum { 17 sdmmc_cmd_go_idle_state = 0, 18 sdmmc_cmd_all_send_cid = 2, 19 sdmmc_cmd_set_dsr = 4, 20 sdmmc_cmd_select_card = 7, 21 sdmmc_cmd_send_csd = 9, 22 sdmmc_cmd_send_cid = 10, 23 sdmmc_cmd_stop_transmission = 12, 24 sdmmc_cmd_send_status = 13, 25 sdmmc_cmd_go_inactive_state = 15, 26 sdmmc_cmd_set_block_length = 16, 27 sdmmc_cmd_read_single_block = 17, 28 sdmmc_cmd_read_multiple_block = 18, 29 sdmmc_cmd_set_block_count = 23, 30 sdmmc_cmd_write_single_block = 24, 31 sdmmc_cmd_write_multiple_block = 25, 32 sdmmc_cmd_program_csd = 27, 33 sdmmc_cmd_set_write_protect = 29, 34 sdmmc_cmd_clear_write_protect = 30, 35 sdmmc_cmd_erase = 38, 36 sdmmc_cmd_lock_unlock = 42, 37 sdmmc_cmd_app_cmd = 55, 38 sdmmc_cmd_general_cmd = 56, 39 sdmmc_cmd_read_ocr = 58, 40 }; 41 42 /** 43 * @brief SD Card specific commands 44 */ 45 enum { 46 sd_acmd_set_bus_width = 6, 47 sd_acmd_sd_status = 13, 48 sd_acmd_set_num_wr_blocks = 22, 49 sd_acmd_set_wr_blk_erase_count = 23, 50 sd_acmd_sd_send_op_cond = 41, 51 sd_acmd_set_clear_card_detect = 42, 52 sd_acmd_send_scr = 51, 53 54 sd_cmd_all_send_cid = 2, 55 sd_cmd_send_relative_addr = 3, 56 sd_cmd_switch = 6, 57 sd_cmd_send_if_cond = 8, 58 sd_cmd_send_csd = 9, 59 sd_voltage_switch = 11, 60 sd_cmd_send_tuning_block = 19, 61 sd_cmd_erase_start = 32, 62 sd_cmd_erase_end = 33, 63 sd_cmd_crc_option = 59, 64 }; 65 66 /** 67 * @brief MMC specific commands 68 */ 69 enum { 70 emmc_cmd_send_op_cond = 1, 71 emmc_cmd_all_send_cid = sdmmc_cmd_all_send_cid, 72 emmc_cmd_set_relative_addr = 3, 73 emmc_cmd_set_dsr = sdmmc_cmd_set_dsr, 74 emmc_cmd_sleep_awake = 5, 75 emmc_cmd_switch = 6, 76 emmc_cmd_select = sdmmc_cmd_select_card, 77 emmc_cmd_send_ext_csd = 8, 78 emmc_cmd_send_csd = sdmmc_cmd_send_csd, 79 emmc_cmd_send_cid = sdmmc_cmd_send_cid, 80 emmc_cmd_stop_transmission = sdmmc_cmd_stop_transmission, 81 emmc_cmd_send_status = sdmmc_cmd_send_status, 82 emmc_cmd_bus_test = 14, 83 emmc_cmd_go_inactive_state = sdmmc_cmd_go_inactive_state, 84 85 emmc_cmd_set_block_length = sdmmc_cmd_set_block_length, 86 emmc_cmd_read_single_block = sdmmc_cmd_read_single_block, 87 emmc_cmd_read_multiple_block = sdmmc_cmd_read_multiple_block, 88 emmc_cmd_send_tuning_block = 21, 89 emmc_cmd_set_block_count = sdmmc_cmd_set_block_count, 90 emmc_cmd_write_single_block = sdmmc_cmd_write_single_block, 91 emmc_cmd_write_multiple_block = sdmmc_cmd_write_multiple_block, 92 emmc_cmd_program_cid = 26, 93 emmc_cmd_program_csd = sdmmc_cmd_program_csd, 94 emmc_cmd_set_time = 49, 95 96 emmc_cmd_erase_group_start = 35, 97 emmc_cmd_erase_group_end = 36, 98 emmc_cmd_erase = sdmmc_cmd_erase, 99 100 emmc_cmd_set_write_prot = 28, 101 emmc_cmd_clear_write_prot = 29, 102 emmc_cmd_send_write_prot = 30, 103 emmc_cmd_send_write_prot_type = 31, 104 105 emmc_cmd_fast_io = 39, 106 emmc_cmd_go_irq_state = 40, 107 emmc_cmd_lock_unlock = sdmmc_cmd_lock_unlock, 108 109 emmc_cmd_app_cmd = sdmmc_cmd_app_cmd, 110 emmc_cmd_gen_cmd = sdmmc_cmd_general_cmd, 111 112 emmc_cmd_protocol_read = 53, 113 emmc_cmd_protocol_write = 54, 114 115 emmc_cmd_queued_task_params = 44, 116 emmc_cmd_queued_task_address = 45, 117 emmc_cmd_execute_read_task = 46, 118 emmc_cmd_execute_write_task = 47, 119 emmc_cmd_cmdq_task_mgmt = 48, 120 }; 121 122 123 /** 124 * @brief SD/MMC R1 register information 125 */ 126 typedef union { 127 uint32_t status; 128 struct { 129 uint32_t : 3; 130 uint32_t ake_seq_error: 1; 131 uint32_t : 1; 132 uint32_t app_cmd: 1; 133 uint32_t fx_event: 1; 134 uint32_t : 1; 135 uint32_t ready_for_data: 1; 136 uint32_t current_state: 4; 137 uint32_t erase_reset: 1; 138 uint32_t card_ecc_disabled: 1; 139 uint32_t wp_erase_skip: 1; 140 uint32_t csd_overwrite: 1; 141 uint32_t : 2; 142 uint32_t error: 1; 143 uint32_t cc_error: 1; 144 uint32_t card_ecc_failed: 1; 145 uint32_t illegal_command: 1; 146 uint32_t com_crc_error: 1; 147 uint32_t lock_unlock_failed: 1; 148 uint32_t card_is_locked: 1; 149 uint32_t wp_violation: 1; 150 uint32_t erase_param: 1; 151 uint32_t erase_seq_error: 1; 152 uint32_t block_len_error: 1; 153 uint32_t address_error: 1; 154 uint32_t out_of_range: 1; 155 }; 156 } sdmmc_r1_status_t; 157 158 /** 159 * @brief SD Card Satus Register Information 160 */ 161 typedef struct { 162 uint8_t bus_width; 163 uint8_t secure_mode; 164 uint16_t card_type; 165 uint32_t protected_size; 166 uint8_t speed_class; 167 uint8_t performance_move; 168 uint8_t uhs_speed_grade; 169 uint8_t erase_offset; 170 uint32_t au_size; 171 uint32_t erase_timeout; 172 uint32_t erase_size; 173 174 uint32_t uhs_au_size; 175 uint8_t reserved[3]; 176 } sd_status_t; 177 178 /** 179 * @brief SD CID Register Information 180 */ 181 typedef union { 182 struct { 183 uint64_t : 1; 184 uint64_t crc7: 7; 185 uint64_t mdt: 12; 186 uint64_t : 4; 187 uint64_t psn: 32; 188 uint64_t prv: 8; 189 uint64_t pnm: 40; 190 uint64_t oid: 16; 191 uint64_t mid: 8; 192 }; 193 uint32_t cid_words[4]; 194 } sd_cid_t; 195 196 /** 197 * @brief SD OCR register information 198 */ 199 typedef union { 200 uint32_t ocr_word; 201 struct { 202 uint32_t : 7; 203 uint32_t low_voltage_range: 1; 204 uint32_t : 7; 205 uint32_t support_2v7_2v8: 1; 206 uint32_t support_2v8_2v9: 1; 207 uint32_t support_2v9_3v0: 1; 208 uint32_t support_3v0_3v1: 1; 209 uint32_t support_3v1_3v2: 1; 210 uint32_t support_3v2_3v3: 1; 211 uint32_t support_3v3_3v4: 1; 212 uint32_t support_3v4_3v5: 1; 213 uint32_t support_3v5_3v6: 1; 214 uint32_t switching_to_1v8_accepted: 1; 215 uint32_t : 2; 216 uint32_t over_2tb_support: 1; 217 uint32_t : 1; 218 uint32_t uhs2_card_status: 1; 219 uint32_t card_capacity_status: 1; 220 uint32_t card_power_up_status: 1; 221 }; 222 } sd_ocr_t; 223 224 225 /** 226 * @brief SD Card CSD register information 227 */ 228 typedef struct _sd_csd { 229 uint8_t csd_structure; 230 uint8_t data_read_access_time1; 231 uint8_t data_read_access_time2; 232 uint8_t transfer_speed; 233 uint16_t card_command_class; 234 bool support_read_block_partial; 235 bool support_write_block_misalignment; 236 bool support_read_block_misalignment; 237 bool is_dsr_implemented; 238 bool support_sdxc; 239 bool is_erase_block_enabled; 240 bool is_write_protection_group_enabled; 241 bool support_write_block_partial; 242 bool support_file_format_group; 243 bool support_copy; 244 bool support_permanent_write_protect; 245 bool support_temporary_write_protect; 246 247 uint8_t read_current_vdd_min; 248 uint8_t read_current_vdd_max; 249 uint8_t write_current_vdd_min; 250 uint8_t write_current_vdd_max; 251 uint8_t device_size_multiplier; 252 uint8_t write_speed_factor; 253 uint8_t file_format; 254 255 uint32_t device_size; 256 uint32_t read_block_len; 257 uint32_t erase_sector_size; 258 uint32_t max_write_block_len; 259 uint32_t write_protect_group_size; 260 } sd_csd_t; 261 262 /** 263 * @brief SD Card SCR register information 264 */ 265 typedef union { 266 struct { 267 uint32_t reserved; 268 uint32_t support_cmd20: 1; 269 uint32_t support_cmd23: 1; 270 uint32_t support_cmd48_or_cmd49: 1; 271 uint32_t support_cmd58_or_cmd59: 1; 272 uint32_t : 2; 273 uint32_t sd_specx: 4; 274 uint32_t sd_spec4: 1; 275 uint32_t ex_security: 4; 276 uint32_t sd_spec3: 1; 277 uint32_t sd_bus_widths: 4; 278 uint32_t sd_security: 3; 279 uint32_t data_stat_after_erase: 1; 280 uint32_t sd_spec: 4; 281 uint32_t scr_structure: 4; 282 }; 283 uint32_t scr_word[2]; 284 } sd_scr_t; 285 286 287 288 typedef enum { 289 card_type_mmc = 0, 290 card_type_sd_v1 = 1, 291 card_type_sd_v2 = 2, 292 card_type_sd_v2_hc = 4, 293 } sdcard_type_t; 294 295 #define SDMMC_BLOCK_SIZE_DEFAULT (512U) 296 297 298 /** 299 * @brief Dummy Byte for SD when Card works in SPI mode 300 */ 301 #define SPISD_DUMMY_BYTE 0xFFU 302 303 /** 304 * @brief sdcard block size in SPI mode 305 */ 306 #define SPI_SD_BLOCK_SIZE (512U) 307 308 /** 309 * @brief R1 register bits when CARD works in SPI mode 310 */ 311 #define SPISD_R1_IDLE_FLAG (0x01) 312 #define SPISD_R1_ERASE_RESET_FLAG (0x02) 313 #define SPISD_R1_ILLEGAL_CMD_FLAG (0x04) 314 #define SPISD_R1_CMD_CRC_FLAG (0x08) 315 #define SPISD_R1_ERASE_SEQ_ERROR_FLAG (0x10) 316 #define SPISD_R1_ADDR_ERROR_FLAG (0x20) 317 #define SPISD_R1_PARAM_ERROR_FLAG (0x40) 318 #define SPISD_R1_ZERO_FLAG (0x80) 319 320 321 #endif /* HPM_SDMMC_CARD_H */