1 // Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_HINF_STRUCT_H_ 15 #define _SOC_HINF_STRUCT_H_ 16 17 #include <stdint.h> 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 typedef volatile struct hinf_dev_s { 24 union { 25 struct { 26 uint32_t user_id_fn1: 16; 27 uint32_t device_id_fn1:16; 28 }; 29 uint32_t val; 30 } cfg_data0; 31 union { 32 struct { 33 uint32_t sdio_enable: 1; 34 uint32_t sdio_ioready1: 1; 35 uint32_t highspeed_enable: 1; 36 uint32_t highspeed_mode: 1; 37 uint32_t sdio_cd_enable: 1; 38 uint32_t sdio_ioready2: 1; 39 uint32_t sdio_int_mask: 1; 40 uint32_t ioenable2: 1; 41 uint32_t cd_disable: 1; 42 uint32_t func1_eps: 1; 43 uint32_t emp: 1; 44 uint32_t ioenable1: 1; 45 uint32_t sdio20_conf0: 4; 46 uint32_t sdio_ver: 12; 47 uint32_t func2_eps: 1; 48 uint32_t sdio20_conf1: 3; 49 }; 50 uint32_t val; 51 } cfg_data1; 52 uint32_t reserved_8; 53 uint32_t reserved_c; 54 uint32_t reserved_10; 55 uint32_t reserved_14; 56 uint32_t reserved_18; 57 union { 58 struct { 59 uint32_t pin_state: 8; 60 uint32_t chip_state: 8; 61 uint32_t sdio_rst: 1; 62 uint32_t sdio_ioready0: 1; 63 uint32_t reserved18: 14; 64 }; 65 uint32_t val; 66 } cfg_data7; 67 uint32_t cis_conf0; /**/ 68 uint32_t cis_conf1; /**/ 69 uint32_t cis_conf2; /**/ 70 uint32_t cis_conf3; /**/ 71 uint32_t cis_conf4; /**/ 72 uint32_t cis_conf5; /**/ 73 uint32_t cis_conf6; /**/ 74 uint32_t cis_conf7; /**/ 75 union { 76 struct { 77 uint32_t user_id_fn2: 16; 78 uint32_t device_id_fn2:16; 79 }; 80 uint32_t val; 81 } cfg_data16; 82 uint32_t reserved_44; 83 uint32_t reserved_48; 84 uint32_t reserved_4c; 85 uint32_t reserved_50; 86 uint32_t reserved_54; 87 uint32_t reserved_58; 88 uint32_t reserved_5c; 89 uint32_t reserved_60; 90 uint32_t reserved_64; 91 uint32_t reserved_68; 92 uint32_t reserved_6c; 93 uint32_t reserved_70; 94 uint32_t reserved_74; 95 uint32_t reserved_78; 96 uint32_t reserved_7c; 97 uint32_t reserved_80; 98 uint32_t reserved_84; 99 uint32_t reserved_88; 100 uint32_t reserved_8c; 101 uint32_t reserved_90; 102 uint32_t reserved_94; 103 uint32_t reserved_98; 104 uint32_t reserved_9c; 105 uint32_t reserved_a0; 106 uint32_t reserved_a4; 107 uint32_t reserved_a8; 108 uint32_t reserved_ac; 109 uint32_t reserved_b0; 110 uint32_t reserved_b4; 111 uint32_t reserved_b8; 112 uint32_t reserved_bc; 113 uint32_t reserved_c0; 114 uint32_t reserved_c4; 115 uint32_t reserved_c8; 116 uint32_t reserved_cc; 117 uint32_t reserved_d0; 118 uint32_t reserved_d4; 119 uint32_t reserved_d8; 120 uint32_t reserved_dc; 121 uint32_t reserved_e0; 122 uint32_t reserved_e4; 123 uint32_t reserved_e8; 124 uint32_t reserved_ec; 125 uint32_t reserved_f0; 126 uint32_t reserved_f4; 127 uint32_t reserved_f8; 128 uint32_t date; /**/ 129 } hinf_dev_t; 130 extern hinf_dev_t HINF; 131 132 #ifdef __cplusplus 133 } 134 #endif 135 136 #endif /* _SOC_HINF_STRUCT_H_ */ 137