1 /*
2 // Copyright (C) 2022 Beken Corporation
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15
16 #include <common/bk_include.h>
17 #include "bk_arm_arch.h"
18
19 #if CONFIG_SDCARD_HOST
20 #include "sdio_driver.h"
21 #include "bk_drv_model.h"
22 #include "bk_sys_ctrl.h"
23 #include <os/mem.h>
24 #include "bk_icu.h"
25 #include "bk_gpio.h"
26 #include <os/os.h>
27
28 #include "gpio_driver.h"
29 #include <driver/hal/hal_gpio_types.h>
30
31 #if CONFIG_SOC_BK7256XX
32 #include "sys_types.h"
33 #include "sys_driver.h"
34 #include <driver/gpio.h>
35 #endif
36
37 /******************************************************************************/
38 /**************************** platform function *******************************/
39 /******************************************************************************/
40
41 /******************************************************************************/
42 /**************************** interface function ******************************/
43 /******************************************************************************/
44 #if (CONFIG_SOC_BK7256XX)
45 /* clk_index: includes clock src and clock divider info */
sdio_set_clock(UINT8 clk_index)46 void sdio_set_clock(UINT8 clk_index)
47 {
48 //temp code, will be switch to sdcard_driver.c
49 *((volatile unsigned long *) (0x44010000+0x9*4)) = (((*((volatile unsigned long *) (0x44010000+0x9*4))) & (~0x3C000)) | ((clk_index) << 14));
50 }
51 #else
beken_sdcard_set_clk_div(UINT8 clkdiv)52 static void beken_sdcard_set_clk_div(UINT8 clkdiv)
53 {
54 UINT32 reg;
55
56 reg = REG_READ(REG_SDCARD_FIFO_THRESHOLD);
57 reg &= ~(SDCARD_FIFO_SD_RATE_SELECT_MASK << SDCARD_FIFO_SD_RATE_SELECT_POSI);
58 reg |= ((clkdiv & SDCARD_FIFO_SD_RATE_SELECT_MASK)
59 << SDCARD_FIFO_SD_RATE_SELECT_POSI);
60 REG_WRITE(REG_SDCARD_FIFO_THRESHOLD, reg);
61 }
62
sdio_set_clock(UINT8 clk_index)63 void sdio_set_clock(UINT8 clk_index)
64 {
65 beken_sdcard_set_clk_div(clk_index);
66 }
67 #endif
68
69 #if (CONFIG_SOC_BK7256XX)
70 #if (CONFIG_PIN_SDIO_GROUP_0)
71 #define PIN_ID_SDIO_CLK (GPIO_14)
72 #define PIN_ID_SDIO_CMD (GPIO_15)
73 #define PIN_ID_SDIO_D0 (GPIO_16)
74 #define PIN_ID_SDIO_D1 (GPIO_17)
75 #define PIN_ID_SDIO_D2 (GPIO_18)
76 #define PIN_ID_SDIO_D3 (GPIO_19)
77 #else
78 #define PIN_ID_SDIO_CLK (GPIO_2)
79 #define PIN_ID_SDIO_CMD (GPIO_3)
80 #define PIN_ID_SDIO_D0 (GPIO_4)
81 #define PIN_ID_SDIO_D1 (GPIO_5)
82 #define PIN_ID_SDIO_D2 (GPIO_10)
83 #define PIN_ID_SDIO_D3 (GPIO_11)
84 #endif
sdio_gpio_config(void)85 void sdio_gpio_config(void)
86 {
87 gpio_dev_unmap(PIN_ID_SDIO_CLK);
88 gpio_dev_unmap(PIN_ID_SDIO_CMD);
89 gpio_dev_unmap(PIN_ID_SDIO_D0);
90
91 #if CONFIG_SDCARD_BUSWIDTH_4LINE
92 gpio_dev_unmap(PIN_ID_SDIO_D1);
93 gpio_dev_unmap(PIN_ID_SDIO_D2);
94 gpio_dev_unmap(PIN_ID_SDIO_D3);
95 #endif
96 gpio_dev_map(PIN_ID_SDIO_CLK, GPIO_DEV_SDIO_HOST_CLK);
97 bk_gpio_pull_up(PIN_ID_SDIO_CLK);
98 bk_gpio_set_capacity(PIN_ID_SDIO_CLK, 3);
99
100 gpio_dev_map(PIN_ID_SDIO_CMD, GPIO_DEV_SDIO_HOST_CMD);
101 bk_gpio_pull_up(PIN_ID_SDIO_CMD);
102 bk_gpio_set_capacity(PIN_ID_SDIO_CMD, 3);
103 gpio_dev_map(PIN_ID_SDIO_D0, GPIO_DEV_SDIO_HOST_DATA0);
104 bk_gpio_pull_up(PIN_ID_SDIO_D0);
105 bk_gpio_set_capacity(PIN_ID_SDIO_D0, 3);
106
107 #if CONFIG_SDCARD_BUSWIDTH_4LINE
108 gpio_dev_map(PIN_ID_SDIO_D1, GPIO_DEV_SDIO_HOST_DATA1);
109 bk_gpio_pull_up(PIN_ID_SDIO_D1);
110 bk_gpio_set_capacity(PIN_ID_SDIO_D1, 3);
111 gpio_dev_map(PIN_ID_SDIO_D2, GPIO_DEV_SDIO_HOST_DATA2);
112 bk_gpio_pull_up(PIN_ID_SDIO_D2);
113 bk_gpio_set_capacity(PIN_ID_SDIO_D2, 3);
114 gpio_dev_map(PIN_ID_SDIO_D3, GPIO_DEV_SDIO_HOST_DATA3);
115 bk_gpio_pull_up(PIN_ID_SDIO_D3);
116 bk_gpio_set_capacity(PIN_ID_SDIO_D3, 3);
117 #endif
118 }
119
120 #if CONFIG_SOC_BK7256XX
121 //1:clock always on, 0:auto gate
sdio_clk_gate_config(uint8_t enable)122 void sdio_clk_gate_config(uint8_t enable)
123 {
124 uint32_t reg = REG_READ(REG_SDCARD_FIFO_THRESHOLD);
125
126 //os_printf("%s:reg=0x%x, en=%d\r\n", __func__, reg, enable);
127 if(enable)
128 reg |= (1<<SDIO_REG0XD_CLK_GATE_ON_POS);
129 else
130 reg &= ~(1<<SDIO_REG0XD_CLK_GATE_ON_POS);
131
132 //reset the fifo realte status
133 if(!enable) //auto gate
134 reg &= ~(SDCARD_FIFO_RX_FIFO_RST | SDCARD_FIFO_TX_FIFO_RST | SDCARD_FIFO_SD_STA_RST);
135
136 REG_WRITE(REG_SDCARD_FIFO_THRESHOLD, reg);
137 }
138 #endif
139
sdio_clk_config(UINT8 enable)140 void sdio_clk_config(UINT8 enable)
141 {
142 sys_drv_dev_clk_pwr_up(CLK_PWR_ID_SDIO, enable);
143 }
144
145 #else
sdio_gpio_config(void)146 void sdio_gpio_config(void)
147 {
148 UINT32 param;
149 #if (CONFIG_SOC_BK7251)
150 #if (CFG_SD_HOST_INTF == CONFIG_SD1_HOST_INTF)
151 param = GFUNC_MODE_SD1_HOST;
152 #else
153 param = GFUNC_MODE_SD_HOST;
154 #endif
155
156 #else
157 #if (CFG_SD_HOST_INTF == CONFIG_SD1_HOST_INTF)
158 param = GFUNC_MODE_SD1_HOST;
159 #else
160 param = GFUNC_MODE_SD_HOST;
161 #endif
162 #endif
163 sddev_control(DD_DEV_TYPE_GPIO, CMD_GPIO_ENABLE_SECOND, ¶m);
164 }
165
sdio_clk_config(UINT8 enable)166 void sdio_clk_config(UINT8 enable)
167 {
168 UINT32 param;
169 UINT32 cmd;
170
171 if (enable)
172 cmd = CMD_CLK_PWR_UP;
173 else
174 cmd = CMD_CLK_PWR_DOWN;
175
176 param = PWD_SDIO_CLK_BIT;
177 sddev_control(DD_DEV_TYPE_ICU, cmd, ¶m);
178 }
179 #endif
180
181
sdio_register_reset(void)182 void sdio_register_reset(void)
183 {
184 UINT32 reg;
185
186 /* Clear cmd rsp int bit */
187 reg = REG_READ(REG_SDCARD_CMD_RSP_INT_SEL);
188 REG_WRITE(REG_SDCARD_CMD_RSP_INT_SEL, reg);
189
190 /* Clear tx/rx fifo */
191 reg = SDCARD_FIFO_RX_FIFO_RST | SDCARD_FIFO_TX_FIFO_RST;
192 REG_WRITE(REG_SDCARD_FIFO_THRESHOLD, reg);
193
194 /* Disabe all sdio interrupt */
195 reg = 0;
196 REG_WRITE(REG_SDCARD_CMD_RSP_INT_MASK, reg);
197
198 /* Config tx/rx fifo threshold */
199 reg = ((SDCARD_RX_FIFO_THRD & SDCARD_FIFO_RX_FIFO_THRESHOLD_MASK)
200 << SDCARD_FIFO_RX_FIFO_THRESHOLD_POSI)
201 | ((SDCARD_TX_FIFO_THRD & SDCARD_FIFO_TX_FIFO_THRESHOLD_MASK)
202 << SDCARD_FIFO_TX_FIFO_THRESHOLD_POSI);
203 REG_WRITE(REG_SDCARD_FIFO_THRESHOLD, reg);
204
205 #if (CONFIG_SOC_BK7256XX)
206 reg = REG_READ(REG_SDCARD_FIFO_THRESHOLD);
207 REG_WRITE(REG_SDCARD_FIFO_THRESHOLD, reg | (1<<SDIO_REG0XD_CLK_REC_SEL_POS));
208 #endif
209 }
210
211 #if 0
212 void sdio_register_reenable(void)
213 {
214 UINT32 reg;
215
216 reg = REG_READ(REG_SDCARD_CMD_RSP_INT_SEL);
217 REG_WRITE(REG_SDCARD_CMD_RSP_INT_SEL, reg);
218
219 reg = REG_READ(REG_SDCARD_FIFO_THRESHOLD);
220 reg |= (SDCARD_FIFO_RX_FIFO_RST | SDCARD_FIFO_TX_FIFO_RST | SDCARD_FIFO_SD_STA_RST);
221 REG_WRITE(REG_SDCARD_FIFO_THRESHOLD, reg);
222
223 rtos_delay_milliseconds(5);
224 /*Config tx/rx fifo threshold*/
225 reg = ((SDCARD_RX_FIFO_THRD & SDCARD_FIFO_RX_FIFO_THRESHOLD_MASK)
226 << SDCARD_FIFO_RX_FIFO_THRESHOLD_POSI)
227 | ((SDCARD_TX_FIFO_THRD & SDCARD_FIFO_TX_FIFO_THRESHOLD_MASK)
228 << SDCARD_FIFO_TX_FIFO_THRESHOLD_POSI);
229 REG_WRITE(REG_SDCARD_FIFO_THRESHOLD, reg);
230 }
231 #endif
232
sdio_sendcmd_function(UINT8 cmd_index,UINT32 flag,UINT32 timeout,VOID * arg)233 void sdio_sendcmd_function(UINT8 cmd_index, UINT32 flag,
234 UINT32 timeout, VOID *arg)
235 {
236 UINT32 reg;
237 flag &= CMD_FLAG_MASK;
238
239 reg = (UINT32)arg;
240 REG_WRITE(REG_SDCARD_CMD_SEND_AGUMENT, reg);
241
242 reg = timeout;
243 REG_WRITE(REG_SDCARD_CMD_RSP_TIMER, reg);
244
245 reg = ((((UINT32)cmd_index)&SDCARD_CMD_SEND_CTRL_CMD_INDEX_MASK)
246 << SDCARD_CMD_SEND_CTRL_CMD_INDEX_POSI)
247 | ((flag & SDCARD_CMD_SEND_CTRL_CMD_FLAGS_MASK)
248 << SDCARD_CMD_SEND_CTRL_CMD_FLAGS_POSI)
249 | SDCARD_CMD_SEND_CTRL_CMD_START;
250 REG_WRITE(REG_SDCARD_CMD_SEND_CTRL, reg);
251 }
252
sdio_wait_cmd_response(UINT32 cmd)253 SDIO_Error sdio_wait_cmd_response(UINT32 cmd)
254 {
255 UINT32 reg;
256 #if (CONFIG_SOC_BK7256XX)
257 uint32_t i_timeout = 0x1000000;
258 #endif
259
260 while (1) {
261 reg = REG_READ(REG_SDCARD_CMD_RSP_INT_SEL);
262 //wait until cmd response
263 if (reg & (SDCARD_CMDRSP_NORSP_END_INT
264 | SDCARD_CMDRSP_RSP_END_INT
265 | SDCARD_CMDRSP_TIMEOUT_INT))
266 break;
267
268 #if (CONFIG_SOC_BK7256XX)
269 i_timeout--;
270 if(i_timeout == 0)
271 {
272 SDCARD_WARN("%s:cmd%d fatal err:no resp/end/timeout int\r\n", __func__, cmd);
273 return SD_CMD_RSP_TIMEOUT;
274 }
275 #endif
276 }
277
278 REG_WRITE(REG_SDCARD_CMD_RSP_INT_SEL, SD_CMD_RSP);//clear the int flag
279 if ((reg & SDCARD_CMDRSP_TIMEOUT_INT) /*||(reg&SDCARD_CMDRSP_NORSP_END_INT)*/) {
280 if ((cmd != 1))
281 SDCARD_WARN("sdcard cmd %d timeout,cmdresp_int_reg:0x%x\r\n", cmd, reg);
282 return SD_CMD_RSP_TIMEOUT;
283 }
284 if (reg & SDCARD_CMDRSP_CMD_CRC_FAIL) {
285
286 if ((cmd != 41) && (cmd != 2) && (cmd != 9) && (cmd != 1)) {
287 SDCARD_WARN("sdcard cmd %d crcfail,cmdresp_int_reg:0x%x\r\n", cmd, reg);
288 return SD_CMD_CRC_FAIL;
289 }
290 }
291
292 //os_printf("%s cmd=%d\r\n", __func__, cmd);
293
294 return SD_OK;
295 }
296
sdio_get_cmdresponse_argument(UINT8 num,UINT32 * resp)297 void sdio_get_cmdresponse_argument(UINT8 num, UINT32 *resp)
298 {
299 switch (num) {
300 case 0:
301 *resp = REG_READ(REG_SDCARD_CMD_RSP_AGUMENT0);
302 break;
303 case 1:
304 *resp = REG_READ(REG_SDCARD_CMD_RSP_AGUMENT1);
305 break;
306 case 2:
307 *resp = REG_READ(REG_SDCARD_CMD_RSP_AGUMENT2);
308 break;
309 case 3:
310 *resp = REG_READ(REG_SDCARD_CMD_RSP_AGUMENT3);
311 break;
312 default:
313 break;
314 }
315 }
316
sdio_setup_data(UINT32 data_dir,UINT32 byte_len)317 void sdio_setup_data(UINT32 data_dir, UINT32 byte_len)
318 {
319 UINT32 reg;
320 if (data_dir == SD_DATA_DIR_RD) {
321 reg = REG_READ(REG_SDCARD_FIFO_THRESHOLD);
322 reg &= (3 << 21);
323 reg |= 0x3ffff; // set fifo
324 REG_WRITE(REG_SDCARD_FIFO_THRESHOLD, reg);
325
326 reg = SDCARD_DATA_REC_CTRL_DATA_EN;
327 } else
328 reg = SDCARD_DATA_REC_CTRL_DATA_WR_DATA_EN;
329
330 reg |= SDCARD_DATA_REC_CTRL_DATA_BYTE_SEL
331 | ((byte_len & SDCARD_DATA_REC_CTRL_BLK_SIZE_MASK)
332 << SDCARD_DATA_REC_CTRL_BLK_SIZE_POSI)
333 #ifdef CONFIG_SDCARD_BUSWIDTH_4LINE
334 | SDCARD_DATA_REC_CTRL_DATA_BUS
335 #endif
336 ;
337
338 REG_WRITE(REG_SDCARD_DATA_REC_CTRL, reg);
339 }
340
sdio_set_data_timeout(UINT32 timeout)341 void sdio_set_data_timeout(UINT32 timeout)
342 {
343 REG_WRITE(REG_SDCARD_DATA_REC_TIMER, timeout);
344 }
345
driver_sdcard_recv_data_start(int timeout)346 void driver_sdcard_recv_data_start(int timeout)
347 {
348 REG_WRITE(REG_SDCARD_DATA_REC_TIMER, timeout);
349 #ifdef CONFIG_SDCARD_BUSWIDTH_4LINE
350 REG_WRITE(REG_SDCARD_DATA_REC_CTRL, (0x1 | (1 << 2) | (512 << 4) | (1 << 17)));
351 #else
352 REG_WRITE(REG_SDCARD_DATA_REC_CTRL, (0x1 | (512 << 4) | (1 << 17)));
353 #endif
354 }
355
sdcard_wait_receive_data(UINT8 * receive_buf)356 SDIO_Error sdcard_wait_receive_data(UINT8 *receive_buf)
357 {
358 #define WAIT_MAX_CNT (0x1000000) //Temp code
359 UINT32 reg, i = 0;
360
361 while (1) {
362 reg = REG_READ(REG_SDCARD_CMD_RSP_INT_SEL);
363 if (reg & (SDCARD_CMDRSP_DATA_REC_END_INT
364 | SDCARD_CMDRSP_DATA_CRC_FAIL
365 | SDCARD_CMDRSP_DATA_TIME_OUT_INT))
366 break;
367
368 //Temp code
369 i++;
370 if((i >= WAIT_MAX_CNT) && (i % 0x100000 == 0))
371 SDCARD_PRT("%s:i=%x,timeout\r\n", __func__, i);
372 }
373
374 REG_WRITE(REG_SDCARD_CMD_RSP_INT_SEL, SD_DATA_RSP);//clear the int flag
375 if (reg & SDCARD_CMDRSP_DATA_TIME_OUT_INT)
376 return SD_DATA_TIMEOUT;
377 if (reg & SDCARD_CMDRSP_DATA_CRC_FAIL) {
378 SDCARD_WARN("sdcard data crcfail,cmdresp_int_reg:0x%x\r\n", reg);
379 return SD_DATA_CRC_FAIL;
380 }
381
382 for (i = 0; i < SD_DEFAULT_BLOCK_SIZE ;) {
383 /* wait fifo data valid */
384 while (1) {
385 //software needn't handle dead-loop,hardware can garantee
386 if (REG_READ(REG_SDCARD_FIFO_THRESHOLD)&SDCARD_FIFO_RXFIFO_RD_READY)
387 break;
388 }
389 reg = REG_READ(REG_SDCARD_RD_DATA_ADDR);
390 *(receive_buf + i++) = reg & 0xff;
391 *(receive_buf + i++) = (reg >> 8) & 0xff;
392 *(receive_buf + i++) = (reg >> 16) & 0xff;
393 *(receive_buf + i++) = (reg >> 24) & 0xff;
394 }
395
396 return SD_OK;
397 }
398
399 #if 0
400 SDIO_Error sdcard_write_data(UINT8 *writebuff, UINT32 block)
401 {
402 UINT32 i, j, reg, tmpval;
403
404 i = 0;
405 // 1. fill the first block to fifo and start write data enable
406 while (REG_READ(REG_SDCARD_FIFO_THRESHOLD) & SDCARD_FIFO_TXFIFO_WR_READY) {
407 tmpval = (writebuff[i] << 24) | (writebuff[i + 1] << 16) | (writebuff[i + 2] << 8) | writebuff[i + 3];
408 REG_WRITE(REG_SDCARD_WR_DATA_ADDR, tmpval);
409 i += 4;
410 if (SD_DEFAULT_BLOCK_SIZE <= i)
411 break;
412 }
413
414 reg = REG_READ(REG_SDCARD_CMD_RSP_INT_MASK);
415 reg |= SDCARD_CMDRSP_TX_FIFO_EMPTY_MASK;
416 REG_WRITE(REG_SDCARD_CMD_RSP_INT_MASK, reg);
417
418 REG_WRITE(REG_SDCARD_DATA_REC_TIMER, DEF_HIGH_SPEED_DATA_TIMEOUT * block);
419 reg = (SD_DEFAULT_BLOCK_SIZE << SDCARD_DATA_REC_CTRL_BLK_SIZE_POSI) |
420 SDCARD_DATA_REC_CTRL_DATA_MUL_BLK | SDCARD_DATA_REC_CTRL_DATA_BYTE_SEL |
421 SDCARD_DATA_REC_CTRL_DATA_WR_DATA_EN
422 #ifdef CONFIG_SDCARD_BUSWIDTH_4LINE
423 | SDCARD_DATA_REC_CTRL_DATA_BUS
424 #endif
425 ;
426 REG_WRITE(REG_SDCARD_DATA_REC_CTRL, reg);
427
428 #if CONFIG_SOC_BK7256XX
429
430 #else
431 do {
432 reg = REG_READ(REG_SDCARD_CMD_RSP_INT_SEL);
433 } while (!(reg & SDCARD_CMDRSP_TX_FIFO_NEED_WRITE));
434 #endif
435
436 // 2. write other blocks
437 while (--block) {
438 j = 0;
439 while (j < SD_DEFAULT_BLOCK_SIZE) {
440 if (REG_READ(REG_SDCARD_FIFO_THRESHOLD) & SDCARD_FIFO_TXFIFO_WR_READY) {
441 tmpval = (writebuff[i] << 24) | (writebuff[i + 1] << 16) | (writebuff[i + 2] << 8) | writebuff[i + 3];
442 REG_WRITE(REG_SDCARD_WR_DATA_ADDR, tmpval);
443 i += 4;
444 j += 4;
445 }
446 }
447
448 do {
449 reg = REG_READ(REG_SDCARD_CMD_RSP_INT_SEL);
450 } while (!(reg & SDCARD_CMDRSP_DATA_WR_END_INT));
451 REG_WRITE(REG_SDCARD_CMD_RSP_INT_SEL, SDCARD_CMDRSP_DATA_WR_END_INT);
452
453 #if CONFIG_SOC_BK7256XX
454
455 #else
456 do {
457 reg = REG_READ(REG_SDCARD_CMD_RSP_INT_SEL);
458 } while (!(reg & SDCARD_CMDRSP_TX_FIFO_NEED_WRITE));
459 #endif
460
461 if (2 != ((reg & SDCARD_CMDRSP_WR_STATU) >> 20))
462 return SD_ERROR;
463 }
464
465 // 3. after the last block,write zero
466 while (1) {
467 reg = REG_READ(REG_SDCARD_FIFO_THRESHOLD);
468 if (reg & SDCARD_FIFO_TXFIFO_WR_READY) {
469 REG_WRITE(REG_SDCARD_WR_DATA_ADDR, 0);
470 break;
471 }
472 }
473
474 // 4.wait and clear flag
475 do {
476 reg = REG_READ(REG_SDCARD_CMD_RSP_INT_SEL);
477 } while (!(reg & SDCARD_CMDRSP_DATA_WR_END_INT));
478 REG_WRITE(REG_SDCARD_CMD_RSP_INT_SEL, SDCARD_CMDRSP_DATA_WR_END_INT);
479
480 if (2 != ((reg & SDCARD_CMDRSP_WR_STATU) >> 20))
481 return SD_ERROR;
482
483 return SD_OK;
484 }
485
486 SDIO_Error sdcard_wait_write_end(void)
487 {
488 UINT32 reg;
489 while (1) {
490 reg = REG_READ(REG_SDCARD_CMD_RSP_INT_SEL);
491 if (reg & (SDCARD_CMDRSP_DATA_WR_END_INT
492 | SDCARD_CMDRSP_DATA_CRC_FAIL
493 | SDCARD_CMDRSP_DATA_TIME_OUT_INT))
494 break;
495 }
496
497 REG_WRITE(REG_SDCARD_CMD_RSP_INT_SEL, SD_DATA_RSP);//clear the int flag
498
499 if (reg & SDCARD_CMDRSP_DATA_TIME_OUT_INT)
500 return SD_DATA_TIMEOUT;
501 if (reg & SDCARD_CMDRSP_DATA_CRC_FAIL) {
502 SDCARD_WARN("sdcard write data crcfail,cmdresp_int_reg:0x%x\r\n", reg);
503 return SD_DATA_CRC_FAIL;
504 }
505
506 return SD_OK;
507 }
508
509 #endif
wait_Receive_Data(void)510 int wait_Receive_Data(void)
511 {
512 uint32 ret = SD_ERR_LONG_TIME_NO_RESPONS, status = 0;
513 uint32 start_tm = rtos_get_time();
514 while (1) {
515 if (rtos_get_time() > start_tm + 4000) { // 4s
516 ret = SD_ERR_LONG_TIME_NO_RESPONS;
517 break;
518 }
519
520 status = REG_READ(REG_SDCARD_CMD_RSP_INT_SEL);
521 if (status & SDCARD_CMDRSP_DATA_REC_END_INT) {
522 if (status & SDCARD_CMDRSP_DATA_CRC_FAIL) {
523 os_printf("aaa\r\n");
524 //ret = SD_DATA_CRC_FAIL;
525 ret = SD_OK;
526 } else
527 ret = SD_OK;
528 break;
529 } else if (status & SDCARD_CMDRSP_DATA_CRC_FAIL) {
530 ret = SD_DATA_CRC_FAIL;
531 break;
532 } else if (status & SDCARD_CMDRSP_DATA_TIME_OUT_INT) {
533 ret = SD_DATA_TIMEOUT;
534 break;
535 }
536 }
537 REG_WRITE(REG_SDCARD_CMD_RSP_INT_SEL, SD_DATA_RSP);/*< clear the int flag */
538 return ret;
539 }
540
541 #endif // CONFIG_SDCARD_HOST
542 // EOF
543
544