1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_SDMMC_STRUCT_H_ 15 #define _SOC_SDMMC_STRUCT_H_ 16 17 #include <stdint.h> 18 19 #include <stdint.h> 20 21 #ifdef __cplusplus 22 extern "C" { 23 #endif 24 25 typedef struct sdmmc_desc_s { 26 uint32_t reserved1: 1; 27 uint32_t disable_int_on_completion: 1; 28 uint32_t last_descriptor: 1; 29 uint32_t first_descriptor: 1; 30 uint32_t second_address_chained: 1; 31 uint32_t end_of_ring: 1; 32 uint32_t reserved2: 24; 33 uint32_t card_error_summary: 1; 34 uint32_t owned_by_idmac: 1; 35 uint32_t buffer1_size: 13; 36 uint32_t buffer2_size: 13; 37 uint32_t reserved3: 6; 38 void* buffer1_ptr; 39 union { 40 void* buffer2_ptr; 41 void* next_desc_ptr; 42 }; 43 } sdmmc_desc_t; 44 45 #define SDMMC_DMA_MAX_BUF_LEN 4096 46 47 _Static_assert(sizeof(sdmmc_desc_t) == 16, "invalid size of sdmmc_desc_t structure"); 48 49 50 typedef struct sdmmc_hw_cmd_s { 51 uint32_t cmd_index: 6; ///< Command index 52 uint32_t response_expect: 1; ///< set if response is expected 53 uint32_t response_long: 1; ///< 0: short response expected, 1: long response expected 54 uint32_t check_response_crc: 1; ///< set if controller should check response CRC 55 uint32_t data_expected: 1; ///< 0: no data expected, 1: data expected 56 uint32_t rw: 1; ///< 0: read from card, 1: write to card (don't care if no data expected) 57 uint32_t stream_mode: 1; ///< 0: block transfer, 1: stream transfer (don't care if no data expected) 58 uint32_t send_auto_stop: 1; ///< set to send stop at the end of the transfer 59 uint32_t wait_complete: 1; ///< 0: send command at once, 1: wait for previous command to complete 60 uint32_t stop_abort_cmd: 1; ///< set if this is a stop or abort command intended to stop current transfer 61 uint32_t send_init: 1; ///< set to send init sequence (80 clocks of 1) 62 uint32_t card_num: 5; ///< card number 63 uint32_t update_clk_reg: 1; ///< 0: normal command, 1: don't send command, just update clock registers 64 uint32_t read_ceata: 1; ///< set if performing read from CE-ATA device 65 uint32_t ccs_expected: 1; ///< set if CCS is expected from CE-ATA device 66 uint32_t enable_boot: 1; ///< set for mandatory boot mode 67 uint32_t expect_boot_ack: 1; ///< when set along with enable_boot, controller expects boot ack pattern 68 uint32_t disable_boot: 1; ///< set to terminate boot operation (don't set along with enable_boot) 69 uint32_t boot_mode: 1; ///< 0: mandatory boot operation, 1: alternate boot operation 70 uint32_t volt_switch: 1; ///< set to enable voltage switching (for CMD11 only) 71 uint32_t use_hold_reg: 1; ///< clear to bypass HOLD register 72 uint32_t reserved: 1; 73 uint32_t start_command: 1; ///< Start command; once command is sent to the card, bit is cleared. 74 } sdmmc_hw_cmd_t; ///< command format used in cmd register; this structure is defined to make it easier to build command values 75 76 _Static_assert(sizeof(sdmmc_hw_cmd_t) == 4, "invalid size of sdmmc_cmd_t structure"); 77 78 79 typedef volatile struct sdmmc_dev_s { 80 union { 81 struct { 82 uint32_t controller_reset: 1; 83 uint32_t fifo_reset: 1; 84 uint32_t dma_reset: 1; 85 uint32_t reserved1: 1; 86 uint32_t int_enable: 1; 87 uint32_t dma_enable: 1; 88 uint32_t read_wait: 1; 89 uint32_t send_irq_response: 1; 90 uint32_t abort_read_data: 1; 91 uint32_t send_ccsd: 1; 92 uint32_t send_auto_stop_ccsd: 1; 93 uint32_t ceata_device_interrupt_status: 1; 94 uint32_t reserved2: 4; 95 uint32_t card_voltage_a: 4; 96 uint32_t card_voltage_b: 4; 97 uint32_t enable_od_pullup: 1; 98 uint32_t use_internal_dma: 1; 99 uint32_t reserved3: 6; 100 }; 101 uint32_t val; 102 } ctrl; 103 104 uint32_t pwren; ///< 1: enable power to card, 0: disable power to card 105 106 union { 107 struct { 108 uint32_t div0: 8; ///< 0: bypass, 1-255: divide clock by (2*div0). 109 uint32_t div1: 8; ///< 0: bypass, 1-255: divide clock by (2*div0). 110 uint32_t div2: 8; ///< 0: bypass, 1-255: divide clock by (2*div0). 111 uint32_t div3: 8; ///< 0: bypass, 1-255: divide clock by (2*div0). 112 }; 113 uint32_t val; 114 } clkdiv; 115 116 union { 117 struct { 118 uint32_t card0: 2; ///< 0-3: select clock divider for card 0 among div0-div3 119 uint32_t card1: 2; ///< 0-3: select clock divider for card 1 among div0-div3 120 uint32_t reserved: 28; 121 }; 122 uint32_t val; 123 } clksrc; 124 125 union { 126 struct { 127 uint32_t cclk_enable: 16; ///< 1: enable clock to card, 0: disable clock 128 uint32_t cclk_low_power: 16; ///< 1: enable clock gating when card is idle, 0: disable clock gating 129 }; 130 uint32_t val; 131 } clkena; 132 133 union { 134 struct { 135 uint32_t response: 8; ///< response timeout, in card output clock cycles 136 uint32_t data: 24; ///< data read timeout, in card output clock cycles 137 }; 138 uint32_t val; 139 } tmout; 140 141 union { 142 struct { 143 uint32_t card_width: 16; ///< one bit for each card: 0: 1-bit mode, 1: 4-bit mode 144 uint32_t card_width_8: 16; ///< one bit for each card: 0: not 8-bit mode (corresponding card_width bit is used), 1: 8-bit mode (card_width bit is ignored) 145 }; 146 uint32_t val; 147 } ctype; 148 149 uint32_t blksiz: 16; ///< block size, default 0x200 150 uint32_t : 16; 151 152 uint32_t bytcnt; ///< number of bytes to be transferred 153 154 union { 155 struct { 156 uint32_t cd: 1; ///< Card detect interrupt enable 157 uint32_t re: 1; ///< Response error interrupt enable 158 uint32_t cmd_done: 1; ///< Command done interrupt enable 159 uint32_t dto: 1; ///< Data transfer over interrupt enable 160 uint32_t txdr: 1; ///< Transmit FIFO data request interrupt enable 161 uint32_t rxdr: 1; ///< Receive FIFO data request interrupt enable 162 uint32_t rcrc: 1; ///< Response CRC error interrupt enable 163 uint32_t dcrc: 1; ///< Data CRC error interrupt enable 164 uint32_t rto: 1; ///< Response timeout interrupt enable 165 uint32_t drto: 1; ///< Data read timeout interrupt enable 166 uint32_t hto: 1; ///< Data starvation-by-host timeout interrupt enable 167 uint32_t frun: 1; ///< FIFO underrun/overrun error interrupt enable 168 uint32_t hle: 1; ///< Hardware locked write error interrupt enable 169 uint32_t sbi_bci: 1; ///< Start bit error / busy clear interrupt enable 170 uint32_t acd: 1; ///< Auto command done interrupt enable 171 uint32_t ebe: 1; ///< End bit error / write no CRC interrupt enable 172 uint32_t sdio: 16; ///< SDIO interrupt enable 173 }; 174 uint32_t val; 175 } intmask; 176 177 uint32_t cmdarg; ///< Command argument to be passed to card 178 179 sdmmc_hw_cmd_t cmd; 180 181 uint32_t resp[4]; ///< Response from card 182 183 union { 184 struct { 185 uint32_t cd: 1; ///< Card detect interrupt masked status 186 uint32_t re: 1; ///< Response error interrupt masked status 187 uint32_t cmd_done: 1; ///< Command done interrupt masked status 188 uint32_t dto: 1; ///< Data transfer over interrupt masked status 189 uint32_t txdr: 1; ///< Transmit FIFO data request interrupt masked status 190 uint32_t rxdr: 1; ///< Receive FIFO data request interrupt masked status 191 uint32_t rcrc: 1; ///< Response CRC error interrupt masked status 192 uint32_t dcrc: 1; ///< Data CRC error interrupt masked status 193 uint32_t rto: 1; ///< Response timeout interrupt masked status 194 uint32_t drto: 1; ///< Data read timeout interrupt masked status 195 uint32_t hto: 1; ///< Data starvation-by-host timeout interrupt masked status 196 uint32_t frun: 1; ///< FIFO underrun/overrun error interrupt masked status 197 uint32_t hle: 1; ///< Hardware locked write error interrupt masked status 198 uint32_t sbi_bci: 1; ///< Start bit error / busy clear interrupt masked status 199 uint32_t acd: 1; ///< Auto command done interrupt masked status 200 uint32_t ebe: 1; ///< End bit error / write no CRC interrupt masked status 201 uint32_t sdio: 16; ///< SDIO interrupt masked status 202 }; 203 uint32_t val; 204 } mintsts; 205 206 union { 207 struct { 208 uint32_t cd: 1; ///< Card detect raw interrupt status 209 uint32_t re: 1; ///< Response error raw interrupt status 210 uint32_t cmd_done: 1; ///< Command done raw interrupt status 211 uint32_t dto: 1; ///< Data transfer over raw interrupt status 212 uint32_t txdr: 1; ///< Transmit FIFO data request raw interrupt status 213 uint32_t rxdr: 1; ///< Receive FIFO data request raw interrupt status 214 uint32_t rcrc: 1; ///< Response CRC error raw interrupt status 215 uint32_t dcrc: 1; ///< Data CRC error raw interrupt status 216 uint32_t rto: 1; ///< Response timeout raw interrupt status 217 uint32_t drto: 1; ///< Data read timeout raw interrupt status 218 uint32_t hto: 1; ///< Data starvation-by-host timeout raw interrupt status 219 uint32_t frun: 1; ///< FIFO underrun/overrun error raw interrupt status 220 uint32_t hle: 1; ///< Hardware locked write error raw interrupt status 221 uint32_t sbi_bci: 1; ///< Start bit error / busy clear raw interrupt status 222 uint32_t acd: 1; ///< Auto command done raw interrupt status 223 uint32_t ebe: 1; ///< End bit error / write no CRC raw interrupt status 224 uint32_t sdio: 16; ///< SDIO raw interrupt status 225 }; 226 uint32_t val; 227 } rintsts; ///< interrupts can be cleared by writing this register 228 229 union { 230 struct { 231 uint32_t fifo_rx_watermark: 1; ///< FIFO reached receive watermark level 232 uint32_t fifo_tx_watermark: 1; ///< FIFO reached transmit watermark level 233 uint32_t fifo_empty: 1; ///< FIFO is empty 234 uint32_t fifo_full: 1; ///< FIFO is full 235 uint32_t cmd_fsm_state: 4; ///< command FSM state 236 uint32_t data3_status: 1; ///< this bit reads 1 if card is present 237 uint32_t data_busy: 1; ///< this bit reads 1 if card is busy 238 uint32_t data_fsm_busy: 1; ///< this bit reads 1 if transmit/receive FSM is busy 239 uint32_t response_index: 6; ///< index of the previous response 240 uint32_t fifo_count: 13; ///< number of filled locations in the FIFO 241 uint32_t dma_ack: 1; ///< DMA acknowledge signal 242 uint32_t dma_req: 1; ///< DMA request signal 243 }; 244 uint32_t val; 245 } status; 246 247 union { 248 struct { 249 uint32_t tx_watermark: 12; ///< FIFO TX watermark level 250 uint32_t reserved1: 4; 251 uint32_t rx_watermark: 12; ///< FIFO RX watermark level 252 uint32_t dw_dma_mts: 3; 253 uint32_t reserved2: 1; 254 }; 255 uint32_t val; 256 } fifoth; 257 258 union { 259 struct { 260 uint32_t cards: 2; ///< bit N reads 0 if card N is present 261 uint32_t reserved: 30; 262 }; 263 uint32_t val; 264 } cdetect; 265 266 union { 267 struct { 268 uint32_t cards: 2; ///< bit N reads 1 if card N is write protected 269 uint32_t reserved: 30; 270 }; 271 uint32_t val; 272 } wrtprt; 273 274 uint32_t gpio; ///< unused 275 uint32_t tcbcnt; ///< transferred (to card) byte count 276 uint32_t tbbcnt; ///< transferred from host to FIFO byte count 277 278 union { 279 struct { 280 uint32_t debounce_count: 24; ///< number of host cycles used by debounce filter, typical time should be 5-25ms 281 uint32_t reserved: 8; 282 }; 283 } debnce; 284 285 uint32_t usrid; ///< user ID 286 uint32_t verid; ///< IP block version 287 uint32_t hcon; ///< compile-time IP configuration 288 union { 289 struct { 290 uint32_t voltage: 16; ///< voltage control for slots; no-op on ESP32. 291 uint32_t ddr: 16; ///< bit N enables DDR mode for card N 292 }; 293 } uhs; ///< UHS related settings 294 295 union { 296 struct { 297 uint32_t cards: 2; ///< bit N resets card N, active low 298 uint32_t reserved: 30; 299 }; 300 } rst_n; 301 302 uint32_t reserved_7c; 303 304 union { 305 struct { 306 uint32_t sw_reset: 1; ///< set to reset DMA controller 307 uint32_t fb: 1; ///< set if AHB master performs fixed burst transfers 308 uint32_t dsl: 5; ///< descriptor skip length: number of words to skip between two unchained descriptors 309 uint32_t enable: 1; ///< set to enable IDMAC 310 uint32_t pbl: 3; ///< programmable burst length 311 uint32_t reserved: 21; 312 }; 313 uint32_t val; 314 } bmod; 315 316 uint32_t pldmnd; ///< set any bit to resume IDMAC FSM from suspended state 317 sdmmc_desc_t* dbaddr; ///< descriptor list base 318 319 union { 320 struct { 321 uint32_t ti: 1; ///< transmit interrupt status 322 uint32_t ri: 1; ///< receive interrupt status 323 uint32_t fbe: 1; ///< fatal bus error 324 uint32_t reserved1: 1; 325 uint32_t du: 1; ///< descriptor unavailable 326 uint32_t ces: 1; ///< card error summary 327 uint32_t reserved2: 2; 328 uint32_t nis: 1; ///< normal interrupt summary 329 uint32_t fbe_code: 3; ///< code of fatal bus error 330 uint32_t fsm: 4; ///< DMAC FSM state 331 uint32_t reserved3: 15; 332 }; 333 uint32_t val; 334 } idsts; 335 336 union { 337 struct { 338 uint32_t ti: 1; ///< transmit interrupt enable 339 uint32_t ri: 1; ///< receive interrupt enable 340 uint32_t fbe: 1; ///< fatal bus error interrupt enable 341 uint32_t reserved1: 1; 342 uint32_t du: 1; ///< descriptor unavailable interrupt enable 343 uint32_t ces: 1; ///< card error interrupt enable 344 uint32_t reserved2: 2; 345 uint32_t ni: 1; ///< normal interrupt interrupt enable 346 uint32_t ai: 1; ///< abnormal interrupt enable 347 uint32_t reserved3: 22; 348 }; 349 uint32_t val; 350 } idinten; 351 352 uint32_t dscaddr; ///< current host descriptor address 353 uint32_t dscaddrl; ///< unused 354 uint32_t dscaddru; ///< unused 355 uint32_t bufaddrl; ///< unused 356 uint32_t bufaddru; ///< unused 357 uint32_t reserved_a8[22]; 358 union { 359 struct { 360 uint32_t read_thr_en : 1; ///< initiate transfer only if FIFO has more space than the read threshold 361 uint32_t busy_clr_int_en : 1; ///< enable generation of busy clear interrupts 362 uint32_t write_thr_en : 1; ///< equivalent of read_thr_en for writes 363 uint32_t reserved1 : 13; 364 uint32_t card_threshold : 12; ///< threshold value for reads/writes, in bytes 365 }; 366 uint32_t val; 367 } cardthrctl; 368 uint32_t back_end_power; 369 uint32_t uhs_reg_ext; 370 uint32_t emmc_ddr_reg; 371 uint32_t enable_shift; 372 uint32_t reserved_114[443]; 373 union { 374 struct { 375 uint32_t phase_dout: 3; ///< phase of data output clock (0x0: 0, 0x1: 90, 0x4: 180, 0x6: 270) 376 uint32_t phase_din: 3; ///< phase of data input clock 377 uint32_t phase_core: 3; ///< phase of the clock to SDMMC peripheral 378 uint32_t div_factor_p: 4; ///< controls clock period; it will be (div_factor_p + 1) / 160MHz 379 uint32_t div_factor_h: 4; ///< controls length of high pulse; it will be (div_factor_h + 1) / 160MHz 380 uint32_t div_factor_m: 4; ///< should be equal to div_factor_p 381 }; 382 uint32_t val; 383 } clock; 384 } sdmmc_dev_t; 385 extern sdmmc_dev_t SDMMC; 386 387 _Static_assert(sizeof(sdmmc_dev_t) == 0x804, "invalid size of sdmmc_dev_t structure"); 388 389 #ifdef __cplusplus 390 } 391 #endif 392 393 #endif //_SOC_SDMMC_STRUCT_H_ 394