1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #include "mp_precomp.h"
27 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
28 #if RT_PLATFORM == PLATFORM_MACOSX
29 #include "phydm_precomp.h"
30 #else
31 #include "../phydm_precomp.h"
32 #endif
33 #else
34 #include "../../phydm_precomp.h"
35 #endif
36
37 #if (RTL8822C_SUPPORT == 1)
38
39 #if 1
40 boolean
_iqk_check_cal_8822c(struct dm_struct * dm,u8 path,u8 cmd)41 _iqk_check_cal_8822c(
42 struct dm_struct *dm,
43 u8 path,
44 u8 cmd)
45 {
46 boolean notready = true, fail = true;
47 u32 delay_count = 0x0;
48
49 while (notready) {
50 if (odm_read_1byte(dm, 0x2d9c) == 0x55) {
51 if (cmd == 0x0) /*LOK*/
52 fail = false;
53 else
54 fail = (boolean)odm_get_bb_reg(dm, R_0x1b08, BIT(26));
55 notready = false;
56 } else {
57 ODM_delay_us(10);
58 delay_count++;
59 }
60
61 if (delay_count >= 30000) {
62 fail = true;
63 RF_DBG(dm, DBG_RF_IQK, "[IQK]IQK timeout!!!\n");
64 break;
65 }
66 }
67 odm_write_1byte(dm, 0x1b10, 0x0);
68 // disable slef-mixer for rx mode
69 //odm_set_rf_reg(dm, (enum rf_path)path, 0x0, 0xf0000, 0x1);
70 if(dm->cut_version == ODM_CUT_E)
71 odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, BIT(14), 0x0);
72 halrf_delay_10us(1);
73 odm_write_4byte(dm, 0x1b00, 0x8 | path << 1);
74 if(!fail)
75 odm_set_bb_reg(dm, R_0x1b20, BIT(26) | BIT(25), 0x2);
76 else
77 odm_set_bb_reg(dm, R_0x1b20, BIT(26) | BIT(25), 0x0);
78 //RF_DBG(dm, DBG_RF_IQK, "[IQK]delay count = 0x%x!!!\n", delay_count);
79 //return fail;
80 return false;
81 }
82
_iqk_idft(struct dm_struct * dm)83 void _iqk_idft(struct dm_struct *dm)
84 {
85
86 odm_write_4byte(dm, 0x1b00, 0x8);
87 odm_write_4byte(dm, 0x1bd8, 0xe0000001);
88 odm_write_4byte(dm, 0x1b00, 0x00000e18);
89 odm_write_4byte(dm, 0x1b00, 0x00000e19);
90 _iqk_check_cal_8822c(dm, RF_PATH_A, 0x0);
91 odm_write_4byte(dm, 0x1b00, 0xa);
92 odm_write_4byte(dm, 0x1bd8, 0xe0000001);
93 odm_write_4byte(dm, 0x1b00, 0x00000e2a);
94 odm_write_4byte(dm, 0x1b00, 0x00000e2b);
95 _iqk_check_cal_8822c(dm, RF_PATH_B, 0x0);
96
97 odm_write_4byte(dm, 0x1b00, 0x8);
98 odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x0);
99 odm_write_4byte(dm, 0x1b00, 0xa);
100 odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x0);
101 }
102
_iqk_rx_cfir_check_8822c(struct dm_struct * dm,u8 t)103 void _iqk_rx_cfir_check_8822c(struct dm_struct *dm, u8 t)
104 {
105 struct dm_iqk_info *iqk_info = &dm->IQK_info;
106 u8 j;
107
108 for (j = 0; j <= 16; j++) {
109 if (iqk_info->rx_cfir_real[0][0][j] != iqk_info->rx_cfir_real[1][0][j] ||
110 iqk_info->rx_cfir_imag[0][0][j] != iqk_info->rx_cfir_imag[1][0][j]) {
111 if (t == 0) {
112 RF_DBG(dm, DBG_RF_IQK, "[ABC]bypass pathA RXCFIR\n");
113 odm_set_bb_reg(dm, 0x180c, BIT(31), 0x0);
114 } else {
115 RF_DBG(dm, DBG_RF_IQK, "[ABC]pathA RX CFIR is changed\n");
116 }
117 break;
118
119 }
120
121 if (iqk_info->rx_cfir_real[0][1][j] != iqk_info->rx_cfir_real[1][1][j] ||
122 iqk_info->rx_cfir_imag[0][1][j] != iqk_info->rx_cfir_imag[1][1][j]) {
123 if (t ==0) {
124 RF_DBG(dm, DBG_RF_IQK, "[ABC]bypass pathB RXCFIR\n");
125 odm_set_bb_reg(dm, 0x410c, BIT(31), 0x0);
126 } else {
127 RF_DBG(dm, DBG_RF_IQK, "[ABC]pathB RX CFIR is changed\n");
128 }
129 break;
130 }
131 }
132 }
133
134
_iqk_get_rxcfir_8822c(void * dm_void,u8 path,u8 t)135 void _iqk_get_rxcfir_8822c(void *dm_void, u8 path, u8 t)
136 {
137 struct dm_struct *dm = (struct dm_struct *)dm_void;
138 struct dm_iqk_info *iqk_info = &dm->IQK_info;
139
140 u8 i;
141 u32 tmp;
142 u32 bit_mask_20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
143
144
145 odm_write_4byte(dm, 0x1b00, 0x8 | path << 1);
146
147 // for (i = 0; i < 0x100/4; i++)
148 // RF_DBG(dm, DBG_RF_DPK, "[CC] (1) 1b%x = 0x%x\n",
149 // i*4, odm_read_4byte(dm, (0x1b00 + i*4)));
150
151 odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x1);
152
153 odm_set_bb_reg(dm, R_0x1bd4, BIT(21), 0x1);
154 odm_set_bb_reg(dm, R_0x1bd4, bit_mask_20_16, 0x10);
155 for (i = 0; i <= 16; i++) {
156 odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0xe0000001 | i << 2);
157 tmp = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
158 iqk_info->rx_cfir_real[t][path][i] = (tmp & 0x0fff0000) >> 16;
159 iqk_info->rx_cfir_imag[t][path][i] = tmp & 0x0fff;
160 }
161 // for (i = 0; i <= 16; i++)
162 // RF_DBG(dm, DBG_RF_IQK, "[CC](7) rx_cfir_real[%d][%d][%x] = %2x\n", t, path, i, iqk_info->rx_cfir_real[t][path][i]);
163 // for (i = 0; i <= 16; i++)
164 // RF_DBG(dm, DBG_RF_IQK, "[CC](7) rx_cfir_imag[%d][%d][%x] = %2x\n", t, path, i, iqk_info->rx_cfir_imag[t][path][i]);
165 odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x0);
166 // odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);
167 }
168
_iqk_reload_rxcfir_8822c(struct dm_struct * dm,u8 path)169 void _iqk_reload_rxcfir_8822c(struct dm_struct *dm, u8 path)
170 {
171 struct dm_iqk_info *iqk_info = &dm->IQK_info;
172 #if 1
173 u8 i;
174 u32 tmp = 0x0, tmp1 = 0x0, tmp2 =0x0;
175
176 odm_set_bb_reg(dm, 0x1b00, MASKDWORD, 0x8 | path << 1);
177 // odm_set_bb_reg(dm, R_0x1b2c, MASKDWORD, 0x7);
178 // odm_set_bb_reg(dm, R_0x1b38, MASKDWORD, 0x40000000);
179 // odm_set_bb_reg(dm, R_0x1b3c, MASKDWORD, 0x40000000);
180 // odm_write_1byte(dm, 0x1bcc, 0x0);
181 odm_set_bb_reg(dm, 0x1b20, BIT(31) | BIT(30), 0x1);
182 tmp1 = 0x60000001;
183 // odm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0x60012303);
184 // odm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0x60045601);
185 halrf_delay_10us(100);
186 #if 1
187 for (i = 0; i <= 16; i++) {
188 tmp2 = tmp1 | iqk_info->rx_cfir_real[0][path][i]<< 8;
189 tmp2 = (tmp2 | i << 2) + 2;
190 odm_set_bb_reg(dm, 0x1bd8, MASKDWORD, tmp2);
191 halrf_delay_10us(100);
192 odm_set_bb_reg(dm, 0x1bd8, BIT(30), 0x0);
193 // odm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0xe0000001);
194 }
195 for (i = 0; i <= 16; i++) {
196 tmp2 = tmp1 | iqk_info->rx_cfir_imag[0][path][i]<< 8;
197 tmp2 = (tmp2 | i << 2);
198 odm_set_bb_reg(dm, 0x1bd8, MASKDWORD, tmp2);
199 halrf_delay_10us(100);
200 odm_set_bb_reg(dm, 0x1bd8, BIT(30), 0x0);
201 // odm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0xe0000001);
202 }
203 #endif
204 // end for write CFIR SRAM
205 odm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0xe0000001);
206 halrf_delay_10us(100);
207 // odm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0xe0000000);
208 // ODM_delay_ms(10);
209 odm_set_bb_reg(dm, 0x1b20, BIT(31) | BIT(30), 0x0);
210 // ODM_delay_ms(10);
211 // odm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0x0);
212 #endif
213 }
214
_iqk_rx_cfir_8822c(struct dm_struct * dm,u8 path)215 void _iqk_rx_cfir_8822c(struct dm_struct *dm, u8 path)
216 {
217
218 u32 xym_tmp[6], cfir_tmp[3];
219 u32 i;
220
221 odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x8 | path << 1);
222 odm_set_bb_reg(dm, 0x1b20, 0xff000000, 0x41);
223 odm_set_bb_reg(dm, 0x1bd8, 0xffffffff, 0xe0000001);
224 odm_set_bb_reg(dm, 0x1bd4, 0xffffffff, 0x00300001);
225
226 odm_set_bb_reg(dm, 0x1bd8, 0xff, 0x01);
227 cfir_tmp[0] = odm_get_bb_reg(dm, 0x1bfc, 0xffffffff);
228 odm_set_bb_reg(dm, 0x1bd8, 0xff, 0x05);
229 cfir_tmp[1] = odm_get_bb_reg(dm, 0x1bfc, 0xffffffff);
230 odm_set_bb_reg(dm, 0x1bd8, 0xff, 0x09);
231 cfir_tmp[2] = odm_get_bb_reg(dm, 0x1bfc, 0xffffffff);
232
233 odm_set_bb_reg(dm, 0x1b20, 0xff000000, 0x05);
234 // odm_set_bb_reg(dm, 0x1bd8, 0xff, 0x00);
235
236 RF_DBG(dm, DBG_RF_IQK, "[CC] S%d RX CFIR = 0x%x, 0x%x, 0x%x\n",
237 path, cfir_tmp[0], cfir_tmp[1], cfir_tmp[2]);
238 }
239
_iqk_tx_cfir_8822c(struct dm_struct * dm,u8 path)240 void _iqk_tx_cfir_8822c(struct dm_struct *dm, u8 path)
241 {
242 u32 xym_tmp[6], cfir_tmp[3];
243 u32 i;
244
245 odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x8 | path << 1);
246 odm_set_bb_reg(dm, 0x1b20, 0xff000000, 0xc1);
247 odm_set_bb_reg(dm, 0x1bd8, 0xffffffff, 0xe0000001);
248 odm_set_bb_reg(dm, 0x1bd4, 0xffffffff, 0x00300001);
249
250 odm_set_bb_reg(dm, 0x1bd8, 0xff, 0x01);
251 cfir_tmp[0] = odm_get_bb_reg(dm, 0x1bfc, 0xffffffff);
252 odm_set_bb_reg(dm, 0x1bd8, 0xff, 0x05);
253 cfir_tmp[1] = odm_get_bb_reg(dm, 0x1bfc, 0xffffffff);
254 odm_set_bb_reg(dm, 0x1bd8, 0xff, 0x09);
255 cfir_tmp[2] = odm_get_bb_reg(dm, 0x1bfc, 0xffffffff);
256
257 odm_set_bb_reg(dm, 0x1b20, 0xff000000, 0x05);
258 // odm_set_bb_reg(dm, 0x1bd8, 0xff, 0x00);
259
260 RF_DBG(dm, DBG_RF_IQK, "[CC] TX CFIR = 0x%x, 0x%x, 0x%x\n",
261 cfir_tmp[0], cfir_tmp[1], cfir_tmp[2]);
262 }
263
264 #endif
265
_iqk_get_efuse_thermal_8822c(struct dm_struct * dm,u8 path)266 u8 _iqk_get_efuse_thermal_8822c(
267 struct dm_struct *dm,
268 u8 path)
269 {
270 u32 thermal_tmp;
271 u8 eeprom_thermal;
272
273 if (path == RF_PATH_A) /*path s0*/
274 odm_efuse_logical_map_read(dm, 1, 0xd0, &thermal_tmp);
275 else /*path s1*/
276 odm_efuse_logical_map_read(dm, 1, 0xd1, &thermal_tmp);
277 eeprom_thermal = (u8)thermal_tmp;
278
279 return eeprom_thermal;
280 }
281
282
283 /*---------------------------Define Local Constant---------------------------*/
phydm_get_read_counter_8822c(struct dm_struct * dm)284 void phydm_get_read_counter_8822c(struct dm_struct *dm)
285 {
286 u32 counter = 0x0;
287
288 while (1) {
289 if ((odm_get_rf_reg(dm, RF_PATH_A, RF_0x8, RFREGOFFSETMASK) == 0xabcde) || counter > 300)
290 break;
291 counter++;
292 ODM_delay_us(10);
293 };
294 odm_set_rf_reg(dm, RF_PATH_A, RF_0x8, RFREGOFFSETMASK, 0x0);
295 RF_DBG(dm, DBG_RF_IQK, "[IQK]counter = %d\n", counter);
296 }
297
298 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
do_iqk_8822c(void * dm_void,u8 delta_thermal_index,u8 thermal_value,u8 threshold)299 void do_iqk_8822c(
300 void *dm_void,
301 u8 delta_thermal_index,
302 u8 thermal_value,
303 u8 threshold)
304 {
305 struct dm_struct *dm = (struct dm_struct *)dm_void;
306 struct dm_iqk_info *iqk_info = &dm->IQK_info;
307
308 dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
309 halrf_segment_iqk_trigger(dm, true, false);
310 }
311 #else
312 /*Originally config->do_iqk is hooked phy_iq_calibrate_8822C, but do_iqk_8822C and phy_iq_calibrate_8822C have different arguments*/
do_iqk_8822c(void * dm_void,u8 delta_thermal_index,u8 thermal_value,u8 threshold)313 void do_iqk_8822c(
314 void *dm_void,
315 u8 delta_thermal_index,
316 u8 thermal_value,
317 u8 threshold)
318 {
319 struct dm_struct *dm = (struct dm_struct *)dm_void;
320 struct dm_iqk_info *iqk_info = &dm->IQK_info;
321 boolean is_recovery = (boolean)delta_thermal_index;
322
323 halrf_segment_iqk_trigger(dm, true, false);
324 }
325 #endif
326
iqk_power_save_8822c(void * dm_void,boolean is_power_save)327 void iqk_power_save_8822c(
328 void *dm_void,
329 boolean is_power_save)
330 {
331 struct dm_struct *dm = (struct dm_struct *)dm_void;
332 struct dm_iqk_info *iqk_info = &dm->IQK_info;
333 u8 path = 0;
334
335 for(path = 0; path < SS_8822C; path++) {
336 odm_set_bb_reg(dm, R_0x1b00, BIT(2)| BIT(1), path);
337 if (is_power_save)
338 odm_set_bb_reg(dm, R_0x1b08, BIT(7), 0x0);
339 else
340 odm_set_bb_reg(dm, R_0x1b08, BIT(7), 0x1);
341 }
342 }
343
iqk_info_rsvd_page_8822c(void * dm_void,u8 * buf,u32 * buf_size)344 void iqk_info_rsvd_page_8822c(
345 void *dm_void,
346 u8 *buf,
347 u32 *buf_size)
348 {
349 struct dm_struct *dm = (struct dm_struct *)dm_void;
350 struct dm_iqk_info *iqk = &dm->IQK_info;
351 u32 i = 0;
352
353 if (buf) {
354 odm_move_memory(dm, buf, iqk->iqk_channel,
355 sizeof(iqk->iqk_channel));
356 i += sizeof(iqk->iqk_channel);
357 odm_move_memory(dm, buf + i, &iqk->iqk_cfir_real[0][0],
358 sizeof(iqk->iqk_cfir_real[0][0]));
359 i += sizeof(iqk->iqk_cfir_real[0][0]);
360 odm_move_memory(dm, buf + i, &iqk->iqk_cfir_real[0][1],
361 sizeof(iqk->iqk_cfir_real[0][1]));
362 i += sizeof(iqk->iqk_cfir_real[0][1]);
363 odm_move_memory(dm, buf + i, &iqk->iqk_cfir_real[1][0],
364 sizeof(iqk->iqk_cfir_real[1][0]));
365 i += sizeof(iqk->iqk_cfir_real[1][0]);
366 odm_move_memory(dm, buf + i, &iqk->iqk_cfir_real[1][1],
367 sizeof(iqk->iqk_cfir_real[1][1]));
368 i += sizeof(iqk->iqk_cfir_real[1][1]);
369 odm_move_memory(dm, buf + i, &iqk->iqk_cfir_imag[0][0],
370 sizeof(iqk->iqk_cfir_imag[0][0]));
371 i += sizeof(iqk->iqk_cfir_imag[0][0]);
372 odm_move_memory(dm, buf + i, &iqk->iqk_cfir_imag[0][1],
373 sizeof(iqk->iqk_cfir_imag[0][1]));
374 i += sizeof(iqk->iqk_cfir_imag[0][1]);
375 odm_move_memory(dm, buf + i, &iqk->iqk_cfir_imag[1][0],
376 sizeof(iqk->iqk_cfir_imag[1][0]));
377 i += sizeof(iqk->iqk_cfir_imag[1][0]);
378 odm_move_memory(dm, buf + i, &iqk->iqk_cfir_imag[1][1],
379 sizeof(iqk->iqk_cfir_imag[1][1]));
380 i += sizeof(iqk->iqk_cfir_imag[1][1]);
381 odm_move_memory(dm, buf + i, &iqk->lok_idac[0][0],
382 sizeof(iqk->lok_idac[0][0]));
383 i += sizeof(iqk->lok_idac[0][0]);
384 odm_move_memory(dm, buf + i, &iqk->lok_idac[0][1],
385 sizeof(iqk->lok_idac[0][1]));
386 i += sizeof(iqk->lok_idac[0][1]);
387 odm_move_memory(dm, buf + i, &iqk->lok_idac[1][0],
388 sizeof(iqk->lok_idac[1][0]));
389 i += sizeof(iqk->lok_idac[1][0]);
390 odm_move_memory(dm, buf + i, &iqk->lok_idac[1][1],
391 sizeof(iqk->lok_idac[1][1]));
392 i += sizeof(iqk->lok_idac[1][1]);
393 }
394
395 if (buf_size)
396 *buf_size = IQK_INFO_RSVD_LEN_8822C;
397 }
398
_iqk_information_8822c(struct dm_struct * dm)399 void _iqk_information_8822c(
400 struct dm_struct *dm)
401 {
402 struct dm_iqk_info *iqk_info = &dm->IQK_info;
403
404 u32 reg_rf18;
405
406 if (odm_get_bb_reg(dm, R_0x1e7c, BIT(30)))
407 iqk_info->is_tssi_mode = true;
408 else
409 iqk_info->is_tssi_mode = false;
410
411 reg_rf18 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK);
412 iqk_info->iqk_band = (u8)((reg_rf18 & BIT(16)) >> 16); /*0/1:G/A*/
413 iqk_info->iqk_ch = (u8)reg_rf18 & 0xff;
414 iqk_info->iqk_bw = (u8)((reg_rf18 & 0x3000) >> 12); /*3/2/1:20/40/80*/
415
416 RF_DBG(dm, DBG_RF_DPK, "[IQK] TSSI/ Band/ CH/ BW = %d / %s / %d / %s\n",
417 iqk_info->is_tssi_mode, iqk_info->iqk_band == 0 ? "2G" : "5G",
418 iqk_info->iqk_ch,
419 iqk_info->iqk_bw == 3 ? "20M" : (iqk_info->iqk_bw == 2 ? "40M" : "80M"));
420 }
421
422
_iqk_xym_read_8822c(struct dm_struct * dm,u8 path)423 boolean _iqk_xym_read_8822c(struct dm_struct *dm, u8 path)
424 {
425 u32 i = 0x0;
426 u32 xym = 0x0;
427 boolean kfail = false;
428 u32 xvalue = 0x0;
429 u32 yvalue = 0x0;
430 u8 x_thr = 100, y_thr = 100;
431
432 odm_write_4byte(dm, 0x1b00, 0x8 | path << 1);
433 odm_set_bb_reg(dm, 0x1b1c, BIT(1) | BIT(0), 0x2);
434
435 for (i = 0x0; i < 24; i++ ) {
436 odm_set_bb_reg(dm, 0x1b14, MASKDWORD, 0x000000e0 + i);
437 odm_set_bb_reg(dm, 0x1b14, MASKDWORD, 0x0);
438 xym = odm_get_bb_reg(dm, 0x1b38, MASKDWORD);
439 xvalue = odm_get_bb_reg(dm, 0x1b38, 0xfff00000);
440 yvalue = odm_get_bb_reg(dm, 0x1b38, 0x000fff00);
441
442 if (xvalue < 0x400) {// "- vale
443 if ((0x400 - xvalue) > x_thr)
444 kfail = true;
445 } else { //"+" vale
446 if ((xvalue - 0x400) > x_thr)
447 kfail = true;
448 }
449
450 if (yvalue > 0x800) { // "- vale
451 if ((0xfff - yvalue) > y_thr)
452 kfail = true;
453 } else { // "+" vale
454 if (yvalue > y_thr)
455 kfail = true;
456 }
457
458 if (kfail == true) {
459 RF_DBG(dm, DBG_RF_IQK, "[IQK]S%d XYM > thr happen\n", path);
460 break;
461 }
462
463 }
464 odm_set_bb_reg(dm, 0x1b38, MASKDWORD, 0x40000000);
465 return kfail;
466 }
467
468
469 static u32
_iqk_btc_wait_indirect_reg_ready_8822c(struct dm_struct * dm)470 _iqk_btc_wait_indirect_reg_ready_8822c(struct dm_struct *dm)
471 {
472 u32 delay_count = 0;
473
474 /* wait for ready bit before access 0x1700 */
475 while (1) {
476 if ((odm_read_1byte(dm, 0x1703) & BIT(5)) == 0) {
477 rtw_mdelay_os(10);
478 if (++delay_count >= 10)
479 break;
480 } else {
481 break;
482 }
483 }
484
485 return delay_count;
486 }
487
488 static u32
_iqk_btc_read_indirect_reg_8822c(struct dm_struct * dm,u16 reg_addr)489 _iqk_btc_read_indirect_reg_8822c(struct dm_struct *dm, u16 reg_addr)
490 {
491 u32 delay_count = 0;
492
493 /* wait for ready bit before access 0x1700 */
494 _iqk_btc_wait_indirect_reg_ready_8822c(dm);
495
496 odm_write_4byte(dm, 0x1700, 0x800F0000 | reg_addr);
497
498 return odm_read_4byte(dm, 0x1708); /* get read data */
499 }
500
501 static void
_iqk_btc_write_indirect_reg_8822c(struct dm_struct * dm,u16 reg_addr,u32 bit_mask,u32 reg_value)502 _iqk_btc_write_indirect_reg_8822c(struct dm_struct *dm, u16 reg_addr,
503 u32 bit_mask, u32 reg_value)
504 {
505 u32 val, i = 0, bitpos = 0, delay_count = 0;
506
507 if (bit_mask == 0x0)
508 return;
509
510 if (bit_mask == 0xffffffff) {
511 /* wait for ready bit before access 0x1700 */
512 _iqk_btc_wait_indirect_reg_ready_8822c(dm);
513
514 /* put write data */
515 odm_write_4byte(dm, 0x1704, reg_value);
516
517 odm_write_4byte(dm, 0x1700, 0xc00F0000 | reg_addr);
518 } else {
519 for (i = 0; i <= 31; i++) {
520 if (((bit_mask >> i) & 0x1) == 0x1) {
521 bitpos = i;
522 break;
523 }
524 }
525
526 /* read back register value before write */
527 val = _iqk_btc_read_indirect_reg_8822c(dm, reg_addr);
528 val = (val & (~bit_mask)) | (reg_value << bitpos);
529
530 /* wait for ready bit before access 0x1700 */
531 _iqk_btc_wait_indirect_reg_ready_8822c(dm);
532
533 odm_write_4byte(dm, 0x1704, val); /* put write data */
534 odm_write_4byte(dm, 0x1700, 0xc00F0000 | reg_addr);
535 }
536 }
537
_iqk_set_gnt_wl_high_8822c(struct dm_struct * dm)538 void _iqk_set_gnt_wl_high_8822c(struct dm_struct *dm)
539 {
540 u32 val = 0;
541 u8 state = 0x1;
542
543 /*GNT_WL = 1*/
544 val = (state << 1) | 0x1;
545 _iqk_btc_write_indirect_reg_8822c(dm, 0x38, 0xff00, 0x77); /*0x38[13:12]*/
546 //_iqk_btc_write_indirect_reg_8822c(dm, 0x38, 0x0300, val); /*0x38[9:8]*/
547 }
548
_iqk_set_gnt_bt_low_8822c(struct dm_struct * dm)549 void _iqk_set_gnt_bt_low_8822c(struct dm_struct *dm)
550 {
551 #if 0
552 u32 val = 0;
553 u8 state = 0x0, sw_control = 0x1;
554
555 /*GNT_BT = 0*/
556 val = (sw_control) ? ((state << 1) | 0x1) : 0;
557 //_iqk_btc_write_indirect_reg_8822c(dm, 0x38, 0xc000, val); /*0x38[15:14]*/
558 //_iqk_btc_write_indirect_reg_8822c(dm, 0x38, 0x0c00, val); /*0x38[11:10]*/
559 #endif
560 return;
561 }
562
_iqk_set_gnt_wl_gnt_bt_8822c(struct dm_struct * dm,boolean beforeK)563 void _iqk_set_gnt_wl_gnt_bt_8822c(struct dm_struct *dm, boolean beforeK)
564 {
565 struct dm_iqk_info *iqk_info = &dm->IQK_info;
566
567 if (beforeK) {
568 _iqk_set_gnt_wl_high_8822c(dm);
569 //_iqk_set_gnt_bt_low_8822c(dm);
570 } else {
571 _iqk_btc_write_indirect_reg_8822c(dm, 0x38, MASKDWORD, iqk_info->tmp_gntwl);
572 }
573 }
574
575
576
_iqk_nctl_8822c(struct dm_struct * dm)577 void _iqk_nctl_8822c(struct dm_struct *dm)
578 {
579 RF_DBG(dm, DBG_RF_IQK, "[IQK]==========IQK NCTL!!!!!========\n");
580 //odm_write_4byte(dm 0x1CD0, 0x7 [31:28]);
581 odm_set_bb_reg(dm, 0x1cd0, 0xf0000000, 0x7);
582 //====== Subpage 0 Init_Setting ======================= //
583 odm_write_4byte(dm, 0x1b00, 0x00000008);
584 odm_write_4byte(dm, 0x1b00, 0x00D70008);
585 odm_write_4byte(dm, 0x1b00, 0x00150008);
586 odm_write_4byte(dm, 0x1b00, 0x00000008);
587
588 odm_write_4byte(dm, 0x1b04, 0xE2462952);
589 odm_write_4byte(dm, 0x1b08, 0x00000080);
590 odm_write_4byte(dm, 0x1b0c, 0x00000000);
591 odm_write_4byte(dm, 0x1b10, 0x00011800);
592 odm_write_4byte(dm, 0x1b14, 0x00000000);
593 odm_write_4byte(dm, 0x1b18, 0x00292903);
594 odm_write_4byte(dm, 0x1b1c, 0xA2193C32);
595 odm_write_4byte(dm, 0x1b20, 0x03040008);
596 odm_write_4byte(dm, 0x1b24, 0x00060008);
597 odm_write_4byte(dm, 0x1b28, 0x00060300);
598 odm_write_4byte(dm, 0x1b2C, 0x00180018);
599 odm_write_4byte(dm, 0x1b30, 0x40000000);
600 odm_write_4byte(dm, 0x1b34, 0x00000800);
601 odm_write_4byte(dm, 0x1b38, 0x40000000 );
602 odm_write_4byte(dm, 0x1b3C, 0x40000000 );
603 // TxGainGapK
604 odm_write_4byte(dm, 0x1b98, 0x00000000);
605 odm_write_4byte(dm, 0x1b9c, 0x00000000);
606 odm_write_4byte(dm, 0x1bc0, 0x01000000);
607 odm_write_4byte(dm, 0x1bcc, 0x00000000);
608 //odm_write_4byte(dm, 0x1be4, 0x0 [1:0]);
609 odm_set_bb_reg(dm, 0x1be4, BIT(1) | BIT(0), 0x0);
610 odm_write_4byte(dm, 0x1bec, 0x40000000);
611 // ---------------------------------- DPD -------------------------- //
612 //DPD associated settings
613 odm_write_4byte(dm, 0x1b40, 0x40000000);
614 odm_write_4byte(dm, 0x1b44, 0x20001064);
615 odm_write_4byte(dm, 0x1b48, 0x0005002D);
616 odm_write_4byte(dm, 0x1b4c, 0x00000000);
617 odm_write_4byte(dm, 0x1b54, 0x00009802);
618 odm_write_4byte(dm, 0x1b60, 0x1F150000);
619 odm_write_4byte(dm, 0x1b64, 0x19140000);
620 odm_write_4byte(dm, 0x1b58, 0x00008F00);
621 odm_write_4byte(dm, 0x1b5C, 0x00000000);
622 //0dB amp
623 odm_write_4byte(dm, 0x1b4c, 0x00000000);
624 odm_write_4byte(dm, 0x1b4c, 0x008a0000);
625 odm_write_4byte(dm, 0x1b50, 0x000003BE);
626 odm_write_4byte(dm, 0x1b4c, 0x018a0000);
627 odm_write_4byte(dm, 0x1b50, 0x0000057A);
628 odm_write_4byte(dm, 0x1b4c, 0x028a0000);
629 odm_write_4byte(dm, 0x1b50, 0x000006C8);
630 odm_write_4byte(dm, 0x1b4c, 0x038a0000);
631 odm_write_4byte(dm, 0x1b50, 0x000007E0);
632 odm_write_4byte(dm, 0x1b4c, 0x048a0000);
633 odm_write_4byte(dm, 0x1b50, 0x000008D5);
634 odm_write_4byte(dm, 0x1b4c, 0x058a0000);
635 odm_write_4byte(dm, 0x1b50, 0x000009B2);
636 odm_write_4byte(dm, 0x1b4c, 0x068a0000);
637 odm_write_4byte(dm, 0x1b50, 0x00000A7D);
638 odm_write_4byte(dm, 0x1b4c, 0x078a0000);
639 odm_write_4byte(dm, 0x1b50, 0x00000B3A);
640 odm_write_4byte(dm, 0x1b4c, 0x088a0000);
641 odm_write_4byte(dm, 0x1b50, 0x00000BEB);
642 odm_write_4byte(dm, 0x1b4c, 0x098a0000);
643 odm_write_4byte(dm, 0x1b50, 0x00000C92);
644 odm_write_4byte(dm, 0x1b4c, 0x0A8a0000);
645 odm_write_4byte(dm, 0x1b50, 0x00000D31);
646 odm_write_4byte(dm, 0x1b4c, 0x0B8a0000);
647 odm_write_4byte(dm, 0x1b50, 0x00000DC9);
648 odm_write_4byte(dm, 0x1b4c, 0x0C8a0000);
649 odm_write_4byte(dm, 0x1b50, 0x00000E5A);
650 odm_write_4byte(dm, 0x1b4c, 0x0D8a0000);
651 odm_write_4byte(dm, 0x1b50, 0x00000EE6);
652 odm_write_4byte(dm, 0x1b4c, 0x0E8a0000);
653 odm_write_4byte(dm, 0x1b50, 0x00000F6D);
654 odm_write_4byte(dm, 0x1b4c, 0x0F8a0000);
655 odm_write_4byte(dm, 0x1b50, 0x00000FF0);
656 odm_write_4byte(dm, 0x1b4c, 0x108a0000);
657 odm_write_4byte(dm, 0x1b50, 0x0000106F);
658 odm_write_4byte(dm, 0x1b4c, 0x118a0000);
659 odm_write_4byte(dm, 0x1b50, 0x000010E9);
660 odm_write_4byte(dm, 0x1b4c, 0x128a0000);
661 odm_write_4byte(dm, 0x1b50, 0x00001161);
662 odm_write_4byte(dm, 0x1b4c, 0x138a0000);
663 odm_write_4byte(dm, 0x1b50, 0x000011D5);
664 odm_write_4byte(dm, 0x1b4c, 0x148a0000);
665 odm_write_4byte(dm, 0x1b50, 0x00001247);
666 odm_write_4byte(dm, 0x1b4c, 0x158a0000);
667 odm_write_4byte(dm, 0x1b50, 0x000012B5);
668 odm_write_4byte(dm, 0x1b4c, 0x168a0000);
669 odm_write_4byte(dm, 0x1b50, 0x00001322);
670 odm_write_4byte(dm, 0x1b4c, 0x178a0000);
671 odm_write_4byte(dm, 0x1b50, 0x0000138B);
672 odm_write_4byte(dm, 0x1b4c, 0x188a0000);
673 odm_write_4byte(dm, 0x1b50, 0x000013F3);
674 odm_write_4byte(dm, 0x1b4c, 0x198a0000);
675 odm_write_4byte(dm, 0x1b50, 0x00001459);
676 odm_write_4byte(dm, 0x1b4c, 0x1A8a0000);
677 odm_write_4byte(dm, 0x1b50, 0x000014BD);
678 odm_write_4byte(dm, 0x1b4c, 0x1B8a0000);
679 odm_write_4byte(dm, 0x1b50, 0x0000151E);
680 odm_write_4byte(dm, 0x1b4c, 0x1C8a0000);
681 odm_write_4byte(dm, 0x1b50, 0x0000157F);
682 odm_write_4byte(dm, 0x1b4c, 0x1D8a0000);
683 odm_write_4byte(dm, 0x1b50, 0x000015DD);
684 odm_write_4byte(dm, 0x1b4c, 0x1E8a0000);
685 odm_write_4byte(dm, 0x1b50, 0x0000163A);
686 odm_write_4byte(dm, 0x1b4c, 0x1F8a0000);
687 odm_write_4byte(dm, 0x1b50, 0x00001695);
688 odm_write_4byte(dm, 0x1b4c, 0x208a0000);
689 odm_write_4byte(dm, 0x1b50, 0x000016EF);
690 odm_write_4byte(dm, 0x1b4c, 0x218a0000);
691 odm_write_4byte(dm, 0x1b50, 0x00001748);
692 odm_write_4byte(dm, 0x1b4c, 0x228a0000);
693 odm_write_4byte(dm, 0x1b50, 0x0000179F);
694 odm_write_4byte(dm, 0x1b4c, 0x238a0000);
695 odm_write_4byte(dm, 0x1b50, 0x000017F5);
696 odm_write_4byte(dm, 0x1b4c, 0x248a0000);
697 odm_write_4byte(dm, 0x1b50, 0x0000184A);
698 odm_write_4byte(dm, 0x1b4c, 0x258a0000);
699 odm_write_4byte(dm, 0x1b50, 0x0000189E);
700 odm_write_4byte(dm, 0x1b4c, 0x268a0000);
701 odm_write_4byte(dm, 0x1b50, 0x000018F1);
702 odm_write_4byte(dm, 0x1b4c, 0x278a0000);
703 odm_write_4byte(dm, 0x1b50, 0x00001942);
704 odm_write_4byte(dm, 0x1b4c, 0x288a0000);
705 odm_write_4byte(dm, 0x1b50, 0x00001993);
706 odm_write_4byte(dm, 0x1b4c, 0x298a0000);
707 odm_write_4byte(dm, 0x1b50, 0x000019E2);
708 odm_write_4byte(dm, 0x1b4c, 0x2A8a0000);
709 odm_write_4byte(dm, 0x1b50, 0x00001A31);
710 odm_write_4byte(dm, 0x1b4c, 0x2B8a0000);
711 odm_write_4byte(dm, 0x1b50, 0x00001A7F);
712 odm_write_4byte(dm, 0x1b4c, 0x2C8a0000);
713 odm_write_4byte(dm, 0x1b50, 0x00001ACC);
714 odm_write_4byte(dm, 0x1b4c, 0x2D8a0000);
715 odm_write_4byte(dm, 0x1b50, 0x00001B18);
716 odm_write_4byte(dm, 0x1b4c, 0x2E8a0000);
717 odm_write_4byte(dm, 0x1b50, 0x00001B63);
718 odm_write_4byte(dm, 0x1b4c, 0x2F8a0000);
719 odm_write_4byte(dm, 0x1b50, 0x00001BAD);
720 odm_write_4byte(dm, 0x1b4c, 0x308a0000);
721 odm_write_4byte(dm, 0x1b50, 0x00001BF7);
722 odm_write_4byte(dm, 0x1b4c, 0x318a0000);
723 odm_write_4byte(dm, 0x1b50, 0x00001C40);
724 odm_write_4byte(dm, 0x1b4c, 0x328a0000);
725 odm_write_4byte(dm, 0x1b50, 0x00001C88);
726 odm_write_4byte(dm, 0x1b4c, 0x338a0000);
727 odm_write_4byte(dm, 0x1b50, 0x00001CCF);
728 odm_write_4byte(dm, 0x1b4c, 0x348a0000);
729 odm_write_4byte(dm, 0x1b50, 0x00001D16);
730 odm_write_4byte(dm, 0x1b4c, 0x358a0000);
731 odm_write_4byte(dm, 0x1b50, 0x00001D5C);
732 odm_write_4byte(dm, 0x1b4c, 0x368a0000);
733 odm_write_4byte(dm, 0x1b50, 0x00001DA2);
734 odm_write_4byte(dm, 0x1b4c, 0x378a0000);
735 odm_write_4byte(dm, 0x1b50, 0x00001DE6);
736 odm_write_4byte(dm, 0x1b4c, 0x388a0000);
737 odm_write_4byte(dm, 0x1b50, 0x00001E2B);
738 odm_write_4byte(dm, 0x1b4c, 0x398a0000);
739 odm_write_4byte(dm, 0x1b50, 0x00001E6E);
740 odm_write_4byte(dm, 0x1b4c, 0x3A8a0000);
741 odm_write_4byte(dm, 0x1b50, 0x00001EB1);
742 odm_write_4byte(dm, 0x1b4c, 0x3B8a0000);
743 odm_write_4byte(dm, 0x1b50, 0x00001EF4);
744 odm_write_4byte(dm, 0x1b4c, 0x3C8a0000);
745 odm_write_4byte(dm, 0x1b50, 0x00001F35);
746 odm_write_4byte(dm, 0x1b4c, 0x3D8a0000);
747 odm_write_4byte(dm, 0x1b50, 0x00001F77);
748 odm_write_4byte(dm, 0x1b4c, 0x3E8a0000);
749 odm_write_4byte(dm, 0x1b50, 0x00001FB8);
750 odm_write_4byte(dm, 0x1b4c, 0x3F8a0000);
751 odm_write_4byte(dm, 0x1b50, 0x00001FF8);
752 odm_write_4byte(dm, 0x1b4c, 0x00000000);
753 odm_write_4byte(dm, 0x1b50, 0x00000000);
754 // write pwsf table
755 odm_write_4byte(dm, 0x1b58, 0x00890000);
756 odm_write_4byte(dm, 0x1b5C, 0x3C6B3FFF);
757 odm_write_4byte(dm, 0x1b58, 0x02890000);
758 odm_write_4byte(dm, 0x1b5C, 0x35D9390A);
759 odm_write_4byte(dm, 0x1b58, 0x04890000);
760 odm_write_4byte(dm, 0x1b5C, 0x2FFE32D6);
761 odm_write_4byte(dm, 0x1b58, 0x06890000);
762 odm_write_4byte(dm, 0x1b5C, 0x2AC62D4F);
763 odm_write_4byte(dm, 0x1b58, 0x08890000);
764 odm_write_4byte(dm, 0x1b5C, 0x261F2862);
765 odm_write_4byte(dm, 0x1b58, 0x0A890000);
766 odm_write_4byte(dm, 0x1b5C, 0x21FA23FD);
767 odm_write_4byte(dm, 0x1b58, 0x0C890000);
768 odm_write_4byte(dm, 0x1b5C, 0x1E482013);
769 odm_write_4byte(dm, 0x1b58, 0x0E890000);
770 odm_write_4byte(dm, 0x1b5C, 0x1AFD1C96);
771 odm_write_4byte(dm, 0x1b58, 0x10890000);
772 odm_write_4byte(dm, 0x1b5C, 0x180E197B);
773 odm_write_4byte(dm, 0x1b58, 0x12890000);
774 odm_write_4byte(dm, 0x1b5C, 0x157016B5);
775 odm_write_4byte(dm, 0x1b58, 0x14890000);
776 odm_write_4byte(dm, 0x1b5C, 0x131B143D);
777 odm_write_4byte(dm, 0x1b58, 0x16890000);
778 odm_write_4byte(dm, 0x1b5C, 0x1107120A);
779 odm_write_4byte(dm, 0x1b58, 0x18890000);
780 odm_write_4byte(dm, 0x1b5C, 0x0F2D1013);
781 odm_write_4byte(dm, 0x1b58, 0x1A890000);
782 odm_write_4byte(dm, 0x1b5C, 0x0D870E54);
783 odm_write_4byte(dm, 0x1b58, 0x1C890000);
784 odm_write_4byte(dm, 0x1b5C, 0x0C0E0CC5);
785 odm_write_4byte(dm, 0x1b58, 0x1E890000);
786 odm_write_4byte(dm, 0x1b5C, 0x0ABF0B62);
787 odm_write_4byte(dm, 0x1b58, 0x20890000);
788 odm_write_4byte(dm, 0x1b5C, 0x09930A25);
789 odm_write_4byte(dm, 0x1b58, 0x22890000);
790 odm_write_4byte(dm, 0x1b5C, 0x0889090A);
791 odm_write_4byte(dm, 0x1b58, 0x24890000);
792 odm_write_4byte(dm, 0x1b5C, 0x079B080F);
793 odm_write_4byte(dm, 0x1b58, 0x26890000);
794 odm_write_4byte(dm, 0x1b5C, 0x06C7072E);
795 odm_write_4byte(dm, 0x1b58, 0x28890000);
796 odm_write_4byte(dm, 0x1b5C, 0x060B0666);
797 odm_write_4byte(dm, 0x1b58, 0x2A890000);
798 odm_write_4byte(dm, 0x1b5C, 0x056305B4);
799 odm_write_4byte(dm, 0x1b58, 0x2C890000);
800 odm_write_4byte(dm, 0x1b5C, 0x04CD0515);
801 odm_write_4byte(dm, 0x1b58, 0x2E890000);
802 odm_write_4byte(dm, 0x1b5C, 0x04470488);
803 odm_write_4byte(dm, 0x1b58, 0x30890000);
804 odm_write_4byte(dm, 0x1b5C, 0x03D0040A);
805 odm_write_4byte(dm, 0x1b58, 0x32890000);
806 odm_write_4byte(dm, 0x1b5C, 0x03660399);
807 odm_write_4byte(dm, 0x1b58, 0x34890000);
808 odm_write_4byte(dm, 0x1b5C, 0x03070335);
809 odm_write_4byte(dm, 0x1b58, 0x36890000);
810 odm_write_4byte(dm, 0x1b5C, 0x02B302DC);
811 odm_write_4byte(dm, 0x1b58, 0x38890000);
812 odm_write_4byte(dm, 0x1b5C, 0x0268028C);
813 odm_write_4byte(dm, 0x1b58, 0x3A890000);
814 odm_write_4byte(dm, 0x1b5C, 0x02250245);
815 odm_write_4byte(dm, 0x1b58, 0x3C890000);
816 odm_write_4byte(dm, 0x1b5C, 0x01E90206);
817 odm_write_4byte(dm, 0x1b58, 0x3E890000);
818 odm_write_4byte(dm, 0x1b5C, 0x01B401CE);
819 odm_write_4byte(dm, 0x1b58, 0x40890000);
820 odm_write_4byte(dm, 0x1b5C, 0x0185019C);
821 odm_write_4byte(dm, 0x1b58, 0x42890000);
822 odm_write_4byte(dm, 0x1b5C, 0x015A016F);
823 odm_write_4byte(dm, 0x1b58, 0x44890000);
824 odm_write_4byte(dm, 0x1b5C, 0x01350147);
825 odm_write_4byte(dm, 0x1b58, 0x46890000);
826 odm_write_4byte(dm, 0x1b5C, 0x01130123);
827 odm_write_4byte(dm, 0x1b58, 0x48890000);
828 odm_write_4byte(dm, 0x1b5C, 0x00F50104);
829 odm_write_4byte(dm, 0x1b58, 0x4A890000);
830 odm_write_4byte(dm, 0x1b5C, 0x00DA00E7);
831 odm_write_4byte(dm, 0x1b58, 0x4C890000);
832 odm_write_4byte(dm, 0x1b5C, 0x00C300CE);
833 odm_write_4byte(dm, 0x1b58, 0x4E890000);
834 odm_write_4byte(dm, 0x1b5C, 0x00AE00B8);
835 odm_write_4byte(dm, 0x1b58, 0x50890000);
836 odm_write_4byte(dm, 0x1b5C, 0x009B00A4);
837 odm_write_4byte(dm, 0x1b58, 0x52890000);
838 odm_write_4byte(dm, 0x1b5C, 0x008A0092);
839 odm_write_4byte(dm, 0x1b58, 0x54890000);
840 odm_write_4byte(dm, 0x1b5C, 0x007B0082);
841 odm_write_4byte(dm, 0x1b58, 0x56890000);
842 odm_write_4byte(dm, 0x1b5C, 0x006E0074);
843 odm_write_4byte(dm, 0x1b58, 0x58890000);
844 odm_write_4byte(dm, 0x1b5C, 0x00620067);
845 odm_write_4byte(dm, 0x1b58, 0x5A890000);
846 odm_write_4byte(dm, 0x1b5C, 0x0057005C);
847 odm_write_4byte(dm, 0x1b58, 0x5C890000);
848 odm_write_4byte(dm, 0x1b5C, 0x004E0052);
849 odm_write_4byte(dm, 0x1b58, 0x5E890000);
850 odm_write_4byte(dm, 0x1b5C, 0x00450049);
851 odm_write_4byte(dm, 0x1b58, 0x60890000);
852 odm_write_4byte(dm, 0x1b5C, 0x003E0041);
853 odm_write_4byte(dm, 0x1b58, 0x62890000);
854 odm_write_4byte(dm, 0x1b5C, 0x0037003A);
855 odm_write_4byte(dm, 0x1b58, 0x62010000);
856 // ======================= Subpage 1 Init_Setting ===============
857 odm_write_4byte(dm, 0x1b00, 0x0000000A);
858 // --------------------------- WIQK --------------------------- //
859 odm_write_4byte(dm, 0x1b00, 0x00D7000A);
860 odm_write_4byte(dm, 0x1b00, 0x0015000A);
861 odm_write_4byte(dm, 0x1b00, 0x0000000A);
862 odm_write_4byte(dm, 0x1b04, 0xE2462952);
863 odm_write_4byte(dm, 0x1b08, 0x00000080);
864 odm_write_4byte(dm, 0x1b0c, 0x00000000);
865 odm_write_4byte(dm, 0x1b10, 0x00011800);
866 odm_write_4byte(dm, 0x1b14, 0x00000000);
867 odm_write_4byte(dm, 0x1b18, 0x00292903);
868 odm_write_4byte(dm, 0x1b1c, 0xA2193C32);
869 odm_write_4byte(dm, 0x1b20, 0x03040008);
870 odm_write_4byte(dm, 0x1b24, 0x00060008);
871 odm_write_4byte(dm, 0x1b28, 0x00060300);
872 odm_write_4byte(dm, 0x1b2C, 0x00180018);
873 odm_write_4byte(dm, 0x1b30, 0x40000000);
874 odm_write_4byte(dm, 0x1b34, 0x00000800);
875 odm_write_4byte(dm, 0x1b38, 0x40000000 );
876 odm_write_4byte(dm, 0x1b3C, 0x40000000 );
877 // TxGainGapK
878 odm_write_4byte(dm, 0x1b98, 0x00000000);
879 odm_write_4byte(dm, 0x1b9c, 0x00000000);
880 odm_write_4byte(dm, 0x1bc0, 0x01000000);
881 odm_write_4byte(dm, 0x1bcc, 0x00000000);
882 //odm_write_4byte(dm, 0x1be4, 0x0 [1:0]);
883 odm_set_bb_reg(dm, 0x1be4, BIT(1) | BIT(0), 0x0);
884 odm_write_4byte(dm, 0x1bec, 0x40000000);
885 // --------------------------- DPD --------------------------- //
886 //DPD associated settings
887 odm_write_4byte(dm, 0x1b54, 0x00009802 );
888 odm_write_4byte(dm, 0x1b60, 0x1F150000);
889 odm_write_4byte(dm, 0x1b64, 0x19140000);
890 odm_write_4byte(dm, 0x1b58, 0x00008F00);
891 odm_write_4byte(dm, 0x1b5C, 0x00000000);
892 // write pwsf table );
893 odm_write_4byte(dm, 0x1b58, 0x00890000);
894 odm_write_4byte(dm, 0x1b5C, 0x3C6B3FFF);
895 odm_write_4byte(dm, 0x1b58, 0x02890000);
896 odm_write_4byte(dm, 0x1b5C, 0x35D9390A);
897 odm_write_4byte(dm, 0x1b58, 0x04890000);
898 odm_write_4byte(dm, 0x1b5C, 0x2FFE32D6);
899 odm_write_4byte(dm, 0x1b58, 0x06890000);
900 odm_write_4byte(dm, 0x1b5C, 0x2AC62D4F);
901 odm_write_4byte(dm, 0x1b58, 0x08890000);
902 odm_write_4byte(dm, 0x1b5C, 0x261F2862);
903 odm_write_4byte(dm, 0x1b58, 0x0A890000);
904 odm_write_4byte(dm, 0x1b5C, 0x21FA23FD);
905 odm_write_4byte(dm, 0x1b58, 0x0C890000);
906 odm_write_4byte(dm, 0x1b5C, 0x1E482013);
907 odm_write_4byte(dm, 0x1b58, 0x0E890000);
908 odm_write_4byte(dm, 0x1b5C, 0x1AFD1C96);
909 odm_write_4byte(dm, 0x1b58, 0x10890000);
910 odm_write_4byte(dm, 0x1b5C, 0x180E197B);
911 odm_write_4byte(dm, 0x1b58, 0x12890000);
912 odm_write_4byte(dm, 0x1b5C, 0x157016B5);
913 odm_write_4byte(dm, 0x1b58, 0x14890000);
914 odm_write_4byte(dm, 0x1b5C, 0x131B143D);
915 odm_write_4byte(dm, 0x1b58, 0x16890000);
916 odm_write_4byte(dm, 0x1b5C, 0x1107120A);
917 odm_write_4byte(dm, 0x1b58, 0x18890000);
918 odm_write_4byte(dm, 0x1b5C, 0x0F2D1013);
919 odm_write_4byte(dm, 0x1b58, 0x1A890000);
920 odm_write_4byte(dm, 0x1b5C, 0x0D870E54);
921 odm_write_4byte(dm, 0x1b58, 0x1C890000);
922 odm_write_4byte(dm, 0x1b5C, 0x0C0E0CC5);
923 odm_write_4byte(dm, 0x1b58, 0x1E890000);
924 odm_write_4byte(dm, 0x1b5C, 0x0ABF0B62);
925 odm_write_4byte(dm, 0x1b58, 0x20890000);
926 odm_write_4byte(dm, 0x1b5C, 0x09930A25);
927 odm_write_4byte(dm, 0x1b58, 0x22890000);
928 odm_write_4byte(dm, 0x1b5C, 0x0889090A);
929 odm_write_4byte(dm, 0x1b58, 0x24890000);
930 odm_write_4byte(dm, 0x1b5C, 0x079B080F);
931 odm_write_4byte(dm, 0x1b58, 0x26890000);
932 odm_write_4byte(dm, 0x1b5C, 0x06C7072E);
933 odm_write_4byte(dm, 0x1b58, 0x28890000);
934 odm_write_4byte(dm, 0x1b5C, 0x060B0666);
935 odm_write_4byte(dm, 0x1b58, 0x2A890000);
936 odm_write_4byte(dm, 0x1b5C, 0x056305B4);
937 odm_write_4byte(dm, 0x1b58, 0x2C890000);
938 odm_write_4byte(dm, 0x1b5C, 0x04CD0515);
939 odm_write_4byte(dm, 0x1b58, 0x2E890000);
940 odm_write_4byte(dm, 0x1b5C, 0x04470488);
941 odm_write_4byte(dm, 0x1b58, 0x30890000);
942 odm_write_4byte(dm, 0x1b5C, 0x03D0040A);
943 odm_write_4byte(dm, 0x1b58, 0x32890000);
944 odm_write_4byte(dm, 0x1b5C, 0x03660399);
945 odm_write_4byte(dm, 0x1b58, 0x34890000);
946 odm_write_4byte(dm, 0x1b5C, 0x03070335);
947 odm_write_4byte(dm, 0x1b58, 0x36890000);
948 odm_write_4byte(dm, 0x1b5C, 0x02B302DC);
949 odm_write_4byte(dm, 0x1b58, 0x38890000);
950 odm_write_4byte(dm, 0x1b5C, 0x0268028C);
951 odm_write_4byte(dm, 0x1b58, 0x3A890000);
952 odm_write_4byte(dm, 0x1b5C, 0x02250245);
953 odm_write_4byte(dm, 0x1b58, 0x3C890000);
954 odm_write_4byte(dm, 0x1b5C, 0x01E90206);
955 odm_write_4byte(dm, 0x1b58, 0x3E890000);
956 odm_write_4byte(dm, 0x1b5C, 0x01B401CE);
957 odm_write_4byte(dm, 0x1b58, 0x40890000);
958 odm_write_4byte(dm, 0x1b5C, 0x0185019C);
959 odm_write_4byte(dm, 0x1b58, 0x42890000);
960 odm_write_4byte(dm, 0x1b5C, 0x015A016F);
961 odm_write_4byte(dm, 0x1b58, 0x44890000);
962 odm_write_4byte(dm, 0x1b5C, 0x01350147);
963 odm_write_4byte(dm, 0x1b58, 0x46890000);
964 odm_write_4byte(dm, 0x1b5C, 0x01130123);
965 odm_write_4byte(dm, 0x1b58, 0x48890000);
966 odm_write_4byte(dm, 0x1b5C, 0x00F50104);
967 odm_write_4byte(dm, 0x1b58, 0x4A890000);
968 odm_write_4byte(dm, 0x1b5C, 0x00DA00E7);
969 odm_write_4byte(dm, 0x1b58, 0x4C890000);
970 odm_write_4byte(dm, 0x1b5C, 0x00C300CE);
971 odm_write_4byte(dm, 0x1b58, 0x4E890000);
972 odm_write_4byte(dm, 0x1b5C, 0x00AE00B8);
973 odm_write_4byte(dm, 0x1b58, 0x50890000);
974 odm_write_4byte(dm, 0x1b5C, 0x009B00A4);
975 odm_write_4byte(dm, 0x1b58, 0x52890000);
976 odm_write_4byte(dm, 0x1b5C, 0x008A0092);
977 odm_write_4byte(dm, 0x1b58, 0x54890000);
978 odm_write_4byte(dm, 0x1b5C, 0x007B0082);
979 odm_write_4byte(dm, 0x1b58, 0x56890000);
980 odm_write_4byte(dm, 0x1b5C, 0x006E0074);
981 odm_write_4byte(dm, 0x1b58, 0x58890000);
982 odm_write_4byte(dm, 0x1b5C, 0x00620067);
983 odm_write_4byte(dm, 0x1b58, 0x5A890000);
984 odm_write_4byte(dm, 0x1b5C, 0x0057005C);
985 odm_write_4byte(dm, 0x1b58, 0x5C890000);
986 odm_write_4byte(dm, 0x1b5C, 0x004E0052);
987 odm_write_4byte(dm, 0x1b58, 0x5E890000);
988 odm_write_4byte(dm, 0x1b5C, 0x00450049);
989 odm_write_4byte(dm, 0x1b58, 0x60890000);
990 odm_write_4byte(dm, 0x1b5C, 0x003E0041);
991 odm_write_4byte(dm, 0x1b58, 0x62890000);
992 odm_write_4byte(dm, 0x1b5C, 0x0037003A);
993 odm_write_4byte(dm, 0x1b58, 0x62010000);
994 // ============== Subpage 2 Init_Setting =========== //);
995 odm_write_4byte(dm, 0x1b00, 0x0000000C);
996 // set LMS parameters
997 odm_write_4byte(dm, 0x1bB8, 0x20202020);
998 odm_write_4byte(dm, 0x1bBC, 0x20202020);
999 odm_write_4byte(dm, 0x1bC0, 0x20202020);
1000 odm_write_4byte(dm, 0x1bC4, 0x20202020);
1001 odm_write_4byte(dm, 0x1bC8, 0x20202020);
1002 odm_write_4byte(dm, 0x1bCC, 0x20202020);
1003 odm_write_4byte(dm, 0x1bD0, 0x20202020);
1004 odm_write_4byte(dm, 0x1bD8, 0x20202020);
1005 odm_write_4byte(dm, 0x1bDC, 0x20202020);
1006 odm_write_4byte(dm, 0x1bE0, 0x20202020);
1007 odm_write_4byte(dm, 0x1bE4, 0x09050301);
1008 odm_write_4byte(dm, 0x1bE8, 0x130F0D0B);
1009 odm_write_4byte(dm, 0x1bEC, 0x00000000);
1010 odm_write_4byte(dm, 0x1bF0, 0x00000000);
1011 // MDPK init reg settings
1012 odm_write_4byte(dm, 0x1b04, 0x30000080);
1013 odm_write_4byte(dm, 0x1b08, 0x00004000);
1014 odm_write_4byte(dm, 0x1b5C, 0x30000080);
1015 odm_write_4byte(dm, 0x1b60, 0x00004000);
1016 odm_write_4byte(dm, 0x1bb4, 0x20000000);
1017 // ================= NCTL ============ //
1018 // nctl_8822C_20180626_wi_iqk_dpk_v1_driver
1019 odm_write_4byte(dm, 0x1b00, 0x00000008);
1020 odm_write_4byte(dm, 0x1b80, 0x00000007);
1021 odm_write_4byte(dm, 0x1b80, 0x00080005);
1022 odm_write_4byte(dm, 0x1b80, 0x00080007);
1023 odm_write_4byte(dm, 0x1b80, 0x80000015);
1024 odm_write_4byte(dm, 0x1b80, 0x80000017);
1025 odm_write_4byte(dm, 0x1b80, 0x09080025);
1026 odm_write_4byte(dm, 0x1b80, 0x09080027);
1027 odm_write_4byte(dm, 0x1b80, 0x0f020035);
1028 odm_write_4byte(dm, 0x1b80, 0x0f020037);
1029 odm_write_4byte(dm, 0x1b80, 0x00220045);
1030 odm_write_4byte(dm, 0x1b80, 0x00220047);
1031 odm_write_4byte(dm, 0x1b80, 0x00040055);
1032 odm_write_4byte(dm, 0x1b80, 0x00040057);
1033 odm_write_4byte(dm, 0x1b80, 0x05c00065);
1034 odm_write_4byte(dm, 0x1b80, 0x05c00067);
1035 odm_write_4byte(dm, 0x1b80, 0x00070075);
1036 odm_write_4byte(dm, 0x1b80, 0x00070077);
1037 odm_write_4byte(dm, 0x1b80, 0x64020085);
1038 odm_write_4byte(dm, 0x1b80, 0x64020087);
1039 odm_write_4byte(dm, 0x1b80, 0x00020095);
1040 odm_write_4byte(dm, 0x1b80, 0x00020097);
1041 odm_write_4byte(dm, 0x1b80, 0x000400a5);
1042 odm_write_4byte(dm, 0x1b80, 0x000400a7);
1043 odm_write_4byte(dm, 0x1b80, 0x4a0000b5);
1044 odm_write_4byte(dm, 0x1b80, 0x4a0000b7);
1045 odm_write_4byte(dm, 0x1b80, 0x4b0400c5);
1046 odm_write_4byte(dm, 0x1b80, 0x4b0400c7);
1047 odm_write_4byte(dm, 0x1b80, 0x860300d5);
1048 odm_write_4byte(dm, 0x1b80, 0x860300d7);
1049 odm_write_4byte(dm, 0x1b80, 0x400900e5);
1050 odm_write_4byte(dm, 0x1b80, 0x400900e7);
1051 odm_write_4byte(dm, 0x1b80, 0xe02700f5);
1052 odm_write_4byte(dm, 0x1b80, 0xe02700f7);
1053 odm_write_4byte(dm, 0x1b80, 0x4b050105);
1054 odm_write_4byte(dm, 0x1b80, 0x4b050107);
1055 odm_write_4byte(dm, 0x1b80, 0x87030115);
1056 odm_write_4byte(dm, 0x1b80, 0x87030117);
1057 odm_write_4byte(dm, 0x1b80, 0x400b0125);
1058 odm_write_4byte(dm, 0x1b80, 0x400b0127);
1059 odm_write_4byte(dm, 0x1b80, 0xe0270135);
1060 odm_write_4byte(dm, 0x1b80, 0xe0270137);
1061 odm_write_4byte(dm, 0x1b80, 0x4b060145);
1062 odm_write_4byte(dm, 0x1b80, 0x4b060147);
1063 odm_write_4byte(dm, 0x1b80, 0x88030155);
1064 odm_write_4byte(dm, 0x1b80, 0x88030157);
1065 odm_write_4byte(dm, 0x1b80, 0x400d0165);
1066 odm_write_4byte(dm, 0x1b80, 0x400d0167);
1067 odm_write_4byte(dm, 0x1b80, 0xe0270175);
1068 odm_write_4byte(dm, 0x1b80, 0xe0270177);
1069 odm_write_4byte(dm, 0x1b80, 0x4b000185);
1070 odm_write_4byte(dm, 0x1b80, 0x4b000187);
1071 odm_write_4byte(dm, 0x1b80, 0x00070195);
1072 odm_write_4byte(dm, 0x1b80, 0x00070197);
1073 odm_write_4byte(dm, 0x1b80, 0x4c0001a5);
1074 odm_write_4byte(dm, 0x1b80, 0x4c0001a7);
1075 odm_write_4byte(dm, 0x1b80, 0x000401b5);
1076 odm_write_4byte(dm, 0x1b80, 0x000401b7);
1077 odm_write_4byte(dm, 0x1b80, 0x400801c5);
1078 odm_write_4byte(dm, 0x1b80, 0x400801c7);
1079 odm_write_4byte(dm, 0x1b80, 0x505501d5);
1080 odm_write_4byte(dm, 0x1b80, 0x505501d7);
1081 odm_write_4byte(dm, 0x1b80, 0x090a01e5);
1082 odm_write_4byte(dm, 0x1b80, 0x090a01e7);
1083 odm_write_4byte(dm, 0x1b80, 0x0ffe01f5);
1084 odm_write_4byte(dm, 0x1b80, 0x0ffe01f7);
1085 odm_write_4byte(dm, 0x1b80, 0x00220205);
1086 odm_write_4byte(dm, 0x1b80, 0x00220207);
1087 odm_write_4byte(dm, 0x1b80, 0x00040215);
1088 odm_write_4byte(dm, 0x1b80, 0x00040217);
1089 odm_write_4byte(dm, 0x1b80, 0x05c00225);
1090 odm_write_4byte(dm, 0x1b80, 0x05c00227);
1091 odm_write_4byte(dm, 0x1b80, 0x00070235);
1092 odm_write_4byte(dm, 0x1b80, 0x00070237);
1093 odm_write_4byte(dm, 0x1b80, 0x64000245);
1094 odm_write_4byte(dm, 0x1b80, 0x64000247);
1095 odm_write_4byte(dm, 0x1b80, 0x00020255);
1096 odm_write_4byte(dm, 0x1b80, 0x00020257);
1097 odm_write_4byte(dm, 0x1b80, 0x30000265);
1098 odm_write_4byte(dm, 0x1b80, 0x30000267);
1099 odm_write_4byte(dm, 0x1b80, 0xa50d0275);
1100 odm_write_4byte(dm, 0x1b80, 0xa50d0277);
1101 odm_write_4byte(dm, 0x1b80, 0xe2a60285);
1102 odm_write_4byte(dm, 0x1b80, 0xe2a60287);
1103 odm_write_4byte(dm, 0x1b80, 0xf0180295);
1104 odm_write_4byte(dm, 0x1b80, 0xf0180297);
1105 odm_write_4byte(dm, 0x1b80, 0xf11802a5);
1106 odm_write_4byte(dm, 0x1b80, 0xf11802a7);
1107 odm_write_4byte(dm, 0x1b80, 0xf21802b5);
1108 odm_write_4byte(dm, 0x1b80, 0xf21802b7);
1109 odm_write_4byte(dm, 0x1b80, 0xf31802c5);
1110 odm_write_4byte(dm, 0x1b80, 0xf31802c7);
1111 odm_write_4byte(dm, 0x1b80, 0xf41802d5);
1112 odm_write_4byte(dm, 0x1b80, 0xf41802d7);
1113 odm_write_4byte(dm, 0x1b80, 0xf51802e5);
1114 odm_write_4byte(dm, 0x1b80, 0xf51802e7);
1115 odm_write_4byte(dm, 0x1b80, 0xf61802f5);
1116 odm_write_4byte(dm, 0x1b80, 0xf61802f7);
1117 odm_write_4byte(dm, 0x1b80, 0xf7180305);
1118 odm_write_4byte(dm, 0x1b80, 0xf7180307);
1119 odm_write_4byte(dm, 0x1b80, 0xf8180315);
1120 odm_write_4byte(dm, 0x1b80, 0xf8180317);
1121 odm_write_4byte(dm, 0x1b80, 0xf9180325);
1122 odm_write_4byte(dm, 0x1b80, 0xf9180327);
1123 odm_write_4byte(dm, 0x1b80, 0xfa180335);
1124 odm_write_4byte(dm, 0x1b80, 0xfa180337);
1125 odm_write_4byte(dm, 0x1b80, 0xf2180345);
1126 odm_write_4byte(dm, 0x1b80, 0xf2180347);
1127 odm_write_4byte(dm, 0x1b80, 0xf3180355);
1128 odm_write_4byte(dm, 0x1b80, 0xf3180357);
1129 odm_write_4byte(dm, 0x1b80, 0xf6180365);
1130 odm_write_4byte(dm, 0x1b80, 0xf6180367);
1131 odm_write_4byte(dm, 0x1b80, 0xf7180375);
1132 odm_write_4byte(dm, 0x1b80, 0xf7180377);
1133 odm_write_4byte(dm, 0x1b80, 0xf8180385);
1134 odm_write_4byte(dm, 0x1b80, 0xf8180387);
1135 odm_write_4byte(dm, 0x1b80, 0xf9180395);
1136 odm_write_4byte(dm, 0x1b80, 0xf9180397);
1137 odm_write_4byte(dm, 0x1b80, 0xfa1803a5);
1138 odm_write_4byte(dm, 0x1b80, 0xfa1803a7);
1139 odm_write_4byte(dm, 0x1b80, 0xfb1803b5);
1140 odm_write_4byte(dm, 0x1b80, 0xfb1803b7);
1141 odm_write_4byte(dm, 0x1b80, 0xfc1803c5);
1142 odm_write_4byte(dm, 0x1b80, 0xfc1803c7);
1143 odm_write_4byte(dm, 0x1b80, 0xfd1803d5);
1144 odm_write_4byte(dm, 0x1b80, 0xfd1803d7);
1145 odm_write_4byte(dm, 0x1b80, 0xfe1803e5);
1146 odm_write_4byte(dm, 0x1b80, 0xfe1803e7);
1147 odm_write_4byte(dm, 0x1b80, 0xff1803f5);
1148 odm_write_4byte(dm, 0x1b80, 0xff1803f7);
1149 odm_write_4byte(dm, 0x1b80, 0x00010405);
1150 odm_write_4byte(dm, 0x1b80, 0x00010407);
1151 odm_write_4byte(dm, 0x1b80, 0x30610415);
1152 odm_write_4byte(dm, 0x1b80, 0x30610417);
1153 odm_write_4byte(dm, 0x1b80, 0x30790425);
1154 odm_write_4byte(dm, 0x1b80, 0x30790427);
1155 odm_write_4byte(dm, 0x1b80, 0x30e20435);
1156 odm_write_4byte(dm, 0x1b80, 0x30e20437);
1157 odm_write_4byte(dm, 0x1b80, 0x307b0445);
1158 odm_write_4byte(dm, 0x1b80, 0x307b0447);
1159 odm_write_4byte(dm, 0x1b80, 0x30860455);
1160 odm_write_4byte(dm, 0x1b80, 0x30860457);
1161 odm_write_4byte(dm, 0x1b80, 0x30910465);
1162 odm_write_4byte(dm, 0x1b80, 0x30910467);
1163 odm_write_4byte(dm, 0x1b80, 0x30e60475);
1164 odm_write_4byte(dm, 0x1b80, 0x30e60477);
1165 odm_write_4byte(dm, 0x1b80, 0x30f10485);
1166 odm_write_4byte(dm, 0x1b80, 0x30f10487);
1167 odm_write_4byte(dm, 0x1b80, 0x30fc0495);
1168 odm_write_4byte(dm, 0x1b80, 0x30fc0497);
1169 odm_write_4byte(dm, 0x1b80, 0x316104a5);
1170 odm_write_4byte(dm, 0x1b80, 0x316104a7);
1171 odm_write_4byte(dm, 0x1b80, 0x305804b5);
1172 odm_write_4byte(dm, 0x1b80, 0x305804b7);
1173 odm_write_4byte(dm, 0x1b80, 0x307904c5);
1174 odm_write_4byte(dm, 0x1b80, 0x307904c7);
1175 odm_write_4byte(dm, 0x1b80, 0x30e004d5);
1176 odm_write_4byte(dm, 0x1b80, 0x30e004d7);
1177 odm_write_4byte(dm, 0x1b80, 0x317e04e5);
1178 odm_write_4byte(dm, 0x1b80, 0x317e04e7);
1179 odm_write_4byte(dm, 0x1b80, 0x318504f5);
1180 odm_write_4byte(dm, 0x1b80, 0x318504f7);
1181 odm_write_4byte(dm, 0x1b80, 0x318c0505);
1182 odm_write_4byte(dm, 0x1b80, 0x318c0507);
1183 odm_write_4byte(dm, 0x1b80, 0x31930515);
1184 odm_write_4byte(dm, 0x1b80, 0x31930517);
1185 odm_write_4byte(dm, 0x1b80, 0x319a0525);
1186 odm_write_4byte(dm, 0x1b80, 0x319a0527);
1187 odm_write_4byte(dm, 0x1b80, 0x31a30535);
1188 odm_write_4byte(dm, 0x1b80, 0x31a30537);
1189 odm_write_4byte(dm, 0x1b80, 0x31ac0545);
1190 odm_write_4byte(dm, 0x1b80, 0x31ac0547);
1191 odm_write_4byte(dm, 0x1b80, 0x31b20555);
1192 odm_write_4byte(dm, 0x1b80, 0x31b20557);
1193 odm_write_4byte(dm, 0x1b80, 0x31b80565);
1194 odm_write_4byte(dm, 0x1b80, 0x31b80567);
1195 odm_write_4byte(dm, 0x1b80, 0x31be0575);
1196 odm_write_4byte(dm, 0x1b80, 0x31be0577);
1197 odm_write_4byte(dm, 0x1b80, 0x4d040585);
1198 odm_write_4byte(dm, 0x1b80, 0x4d040587);
1199 odm_write_4byte(dm, 0x1b80, 0x20810595);
1200 odm_write_4byte(dm, 0x1b80, 0x20810597);
1201 odm_write_4byte(dm, 0x1b80, 0x234505a5);
1202 odm_write_4byte(dm, 0x1b80, 0x234505a7);
1203 odm_write_4byte(dm, 0x1b80, 0x200405b5);
1204 odm_write_4byte(dm, 0x1b80, 0x200405b7);
1205 odm_write_4byte(dm, 0x1b80, 0x001705c5);
1206 odm_write_4byte(dm, 0x1b80, 0x001705c7);
1207 odm_write_4byte(dm, 0x1b80, 0x234605d5);
1208 odm_write_4byte(dm, 0x1b80, 0x234605d7);
1209 odm_write_4byte(dm, 0x1b80, 0x789a05e5);
1210 odm_write_4byte(dm, 0x1b80, 0x789a05e7);
1211 odm_write_4byte(dm, 0x1b80, 0x4d0005f5);
1212 odm_write_4byte(dm, 0x1b80, 0x4d0005f7);
1213 odm_write_4byte(dm, 0x1b80, 0x00010605);
1214 odm_write_4byte(dm, 0x1b80, 0x00010607);
1215 odm_write_4byte(dm, 0x1b80, 0xe23f0615);
1216 odm_write_4byte(dm, 0x1b80, 0xe23f0617);
1217 odm_write_4byte(dm, 0x1b80, 0x4d040625);
1218 odm_write_4byte(dm, 0x1b80, 0x4d040627);
1219 odm_write_4byte(dm, 0x1b80, 0x20800635);
1220 odm_write_4byte(dm, 0x1b80, 0x20800637);
1221 odm_write_4byte(dm, 0x1b80, 0x00000645);
1222 odm_write_4byte(dm, 0x1b80, 0x00000647);
1223 odm_write_4byte(dm, 0x1b80, 0x4d000655);
1224 odm_write_4byte(dm, 0x1b80, 0x4d000657);
1225 odm_write_4byte(dm, 0x1b80, 0x55070665);
1226 odm_write_4byte(dm, 0x1b80, 0x55070667);
1227 odm_write_4byte(dm, 0x1b80, 0xe2370675);
1228 odm_write_4byte(dm, 0x1b80, 0xe2370677);
1229 odm_write_4byte(dm, 0x1b80, 0xe2370685);
1230 odm_write_4byte(dm, 0x1b80, 0xe2370687);
1231 odm_write_4byte(dm, 0x1b80, 0x4d040695);
1232 odm_write_4byte(dm, 0x1b80, 0x4d040697);
1233 odm_write_4byte(dm, 0x1b80, 0x208806a5);
1234 odm_write_4byte(dm, 0x1b80, 0x208806a7);
1235 odm_write_4byte(dm, 0x1b80, 0x020006b5);
1236 odm_write_4byte(dm, 0x1b80, 0x020006b7);
1237 odm_write_4byte(dm, 0x1b80, 0x4d0006c5);
1238 odm_write_4byte(dm, 0x1b80, 0x4d0006c7);
1239 odm_write_4byte(dm, 0x1b80, 0x550f06d5);
1240 odm_write_4byte(dm, 0x1b80, 0x550f06d7);
1241 odm_write_4byte(dm, 0x1b80, 0xe23706e5);
1242 odm_write_4byte(dm, 0x1b80, 0xe23706e7);
1243 odm_write_4byte(dm, 0x1b80, 0x4f0206f5);
1244 odm_write_4byte(dm, 0x1b80, 0x4f0206f7);
1245 odm_write_4byte(dm, 0x1b80, 0x4e000705);
1246 odm_write_4byte(dm, 0x1b80, 0x4e000707);
1247 odm_write_4byte(dm, 0x1b80, 0x53020715);
1248 odm_write_4byte(dm, 0x1b80, 0x53020717);
1249 odm_write_4byte(dm, 0x1b80, 0x52010725);
1250 odm_write_4byte(dm, 0x1b80, 0x52010727);
1251 odm_write_4byte(dm, 0x1b80, 0xe23b0735);
1252 odm_write_4byte(dm, 0x1b80, 0xe23b0737);
1253 odm_write_4byte(dm, 0x1b80, 0x4d080745);
1254 odm_write_4byte(dm, 0x1b80, 0x4d080747);
1255 odm_write_4byte(dm, 0x1b80, 0x57100755);
1256 odm_write_4byte(dm, 0x1b80, 0x57100757);
1257 odm_write_4byte(dm, 0x1b80, 0x57000765);
1258 odm_write_4byte(dm, 0x1b80, 0x57000767);
1259 odm_write_4byte(dm, 0x1b80, 0x4d000775);
1260 odm_write_4byte(dm, 0x1b80, 0x4d000777);
1261 odm_write_4byte(dm, 0x1b80, 0x00010785);
1262 odm_write_4byte(dm, 0x1b80, 0x00010787);
1263 odm_write_4byte(dm, 0x1b80, 0xe23f0795);
1264 odm_write_4byte(dm, 0x1b80, 0xe23f0797);
1265 odm_write_4byte(dm, 0x1b80, 0x000107a5);
1266 odm_write_4byte(dm, 0x1b80, 0x000107a7);
1267 odm_write_4byte(dm, 0x1b80, 0x30a607b5);
1268 odm_write_4byte(dm, 0x1b80, 0x30a607b7);
1269 odm_write_4byte(dm, 0x1b80, 0x002607c5);
1270 odm_write_4byte(dm, 0x1b80, 0x002607c7);
1271 odm_write_4byte(dm, 0x1b80, 0xe29907d5);
1272 odm_write_4byte(dm, 0x1b80, 0xe29907d7);
1273 odm_write_4byte(dm, 0x1b80, 0x000207e5);
1274 odm_write_4byte(dm, 0x1b80, 0x000207e7);
1275 odm_write_4byte(dm, 0x1b80, 0x54ec07f5);
1276 odm_write_4byte(dm, 0x1b80, 0x54ec07f7);
1277 odm_write_4byte(dm, 0x1b80, 0x0ba60805);
1278 odm_write_4byte(dm, 0x1b80, 0x0ba60807);
1279 odm_write_4byte(dm, 0x1b80, 0x00260815);
1280 odm_write_4byte(dm, 0x1b80, 0x00260817);
1281 odm_write_4byte(dm, 0x1b80, 0xe2990825);
1282 odm_write_4byte(dm, 0x1b80, 0xe2990827);
1283 odm_write_4byte(dm, 0x1b80, 0x00020835);
1284 odm_write_4byte(dm, 0x1b80, 0x00020837);
1285 odm_write_4byte(dm, 0x1b80, 0x63c30845);
1286 odm_write_4byte(dm, 0x1b80, 0x63c30847);
1287 odm_write_4byte(dm, 0x1b80, 0x30d00855);
1288 odm_write_4byte(dm, 0x1b80, 0x30d00857);
1289 odm_write_4byte(dm, 0x1b80, 0x309e0865);
1290 odm_write_4byte(dm, 0x1b80, 0x309e0867);
1291 odm_write_4byte(dm, 0x1b80, 0x00240875);
1292 odm_write_4byte(dm, 0x1b80, 0x00240877);
1293 odm_write_4byte(dm, 0x1b80, 0xe2990885);
1294 odm_write_4byte(dm, 0x1b80, 0xe2990887);
1295 odm_write_4byte(dm, 0x1b80, 0x00020895);
1296 odm_write_4byte(dm, 0x1b80, 0x00020897);
1297 odm_write_4byte(dm, 0x1b80, 0x54ea08a5);
1298 odm_write_4byte(dm, 0x1b80, 0x54ea08a7);
1299 odm_write_4byte(dm, 0x1b80, 0x0ba608b5);
1300 odm_write_4byte(dm, 0x1b80, 0x0ba608b7);
1301 odm_write_4byte(dm, 0x1b80, 0x002408c5);
1302 odm_write_4byte(dm, 0x1b80, 0x002408c7);
1303 odm_write_4byte(dm, 0x1b80, 0xe29908d5);
1304 odm_write_4byte(dm, 0x1b80, 0xe29908d7);
1305 odm_write_4byte(dm, 0x1b80, 0x000208e5);
1306 odm_write_4byte(dm, 0x1b80, 0x000208e7);
1307 odm_write_4byte(dm, 0x1b80, 0x63c308f5);
1308 odm_write_4byte(dm, 0x1b80, 0x63c308f7);
1309 odm_write_4byte(dm, 0x1b80, 0x30d00905);
1310 odm_write_4byte(dm, 0x1b80, 0x30d00907);
1311 odm_write_4byte(dm, 0x1b80, 0x6c100915);
1312 odm_write_4byte(dm, 0x1b80, 0x6c100917);
1313 odm_write_4byte(dm, 0x1b80, 0x6d0f0925);
1314 odm_write_4byte(dm, 0x1b80, 0x6d0f0927);
1315 odm_write_4byte(dm, 0x1b80, 0xe23f0935);
1316 odm_write_4byte(dm, 0x1b80, 0xe23f0937);
1317 odm_write_4byte(dm, 0x1b80, 0xe2990945);
1318 odm_write_4byte(dm, 0x1b80, 0xe2990947);
1319 odm_write_4byte(dm, 0x1b80, 0x6c240955);
1320 odm_write_4byte(dm, 0x1b80, 0x6c240957);
1321 odm_write_4byte(dm, 0x1b80, 0xe23f0965);
1322 odm_write_4byte(dm, 0x1b80, 0xe23f0967);
1323 odm_write_4byte(dm, 0x1b80, 0xe2990975);
1324 odm_write_4byte(dm, 0x1b80, 0xe2990977);
1325 odm_write_4byte(dm, 0x1b80, 0x6c440985);
1326 odm_write_4byte(dm, 0x1b80, 0x6c440987);
1327 odm_write_4byte(dm, 0x1b80, 0xe23f0995);
1328 odm_write_4byte(dm, 0x1b80, 0xe23f0997);
1329 odm_write_4byte(dm, 0x1b80, 0xe29909a5);
1330 odm_write_4byte(dm, 0x1b80, 0xe29909a7);
1331 odm_write_4byte(dm, 0x1b80, 0x6c6409b5);
1332 odm_write_4byte(dm, 0x1b80, 0x6c6409b7);
1333 odm_write_4byte(dm, 0x1b80, 0xe23f09c5);
1334 odm_write_4byte(dm, 0x1b80, 0xe23f09c7);
1335 odm_write_4byte(dm, 0x1b80, 0xe29909d5);
1336 odm_write_4byte(dm, 0x1b80, 0xe29909d7);
1337 odm_write_4byte(dm, 0x1b80, 0x0baa09e5);
1338 odm_write_4byte(dm, 0x1b80, 0x0baa09e7);
1339 odm_write_4byte(dm, 0x1b80, 0x6c8409f5);
1340 odm_write_4byte(dm, 0x1b80, 0x6c8409f7);
1341 odm_write_4byte(dm, 0x1b80, 0x6d0f0a05);
1342 odm_write_4byte(dm, 0x1b80, 0x6d0f0a07);
1343 odm_write_4byte(dm, 0x1b80, 0xe23f0a15);
1344 odm_write_4byte(dm, 0x1b80, 0xe23f0a17);
1345 odm_write_4byte(dm, 0x1b80, 0xe2990a25);
1346 odm_write_4byte(dm, 0x1b80, 0xe2990a27);
1347 odm_write_4byte(dm, 0x1b80, 0x6ca40a35);
1348 odm_write_4byte(dm, 0x1b80, 0x6ca40a37);
1349 odm_write_4byte(dm, 0x1b80, 0xe23f0a45);
1350 odm_write_4byte(dm, 0x1b80, 0xe23f0a47);
1351 odm_write_4byte(dm, 0x1b80, 0xe2990a55);
1352 odm_write_4byte(dm, 0x1b80, 0xe2990a57);
1353 odm_write_4byte(dm, 0x1b80, 0x0bac0a65);
1354 odm_write_4byte(dm, 0x1b80, 0x0bac0a67);
1355 odm_write_4byte(dm, 0x1b80, 0x6cc40a75);
1356 odm_write_4byte(dm, 0x1b80, 0x6cc40a77);
1357 odm_write_4byte(dm, 0x1b80, 0x6d0f0a85);
1358 odm_write_4byte(dm, 0x1b80, 0x6d0f0a87);
1359 odm_write_4byte(dm, 0x1b80, 0xe23f0a95);
1360 odm_write_4byte(dm, 0x1b80, 0xe23f0a97);
1361 odm_write_4byte(dm, 0x1b80, 0xe2990aa5);
1362 odm_write_4byte(dm, 0x1b80, 0xe2990aa7);
1363 odm_write_4byte(dm, 0x1b80, 0x6ce40ab5);
1364 odm_write_4byte(dm, 0x1b80, 0x6ce40ab7);
1365 odm_write_4byte(dm, 0x1b80, 0xe23f0ac5);
1366 odm_write_4byte(dm, 0x1b80, 0xe23f0ac7);
1367 odm_write_4byte(dm, 0x1b80, 0xe2990ad5);
1368 odm_write_4byte(dm, 0x1b80, 0xe2990ad7);
1369 odm_write_4byte(dm, 0x1b80, 0x6cf40ae5);
1370 odm_write_4byte(dm, 0x1b80, 0x6cf40ae7);
1371 odm_write_4byte(dm, 0x1b80, 0xe23f0af5);
1372 odm_write_4byte(dm, 0x1b80, 0xe23f0af7);
1373 odm_write_4byte(dm, 0x1b80, 0xe2990b05);
1374 odm_write_4byte(dm, 0x1b80, 0xe2990b07);
1375 odm_write_4byte(dm, 0x1b80, 0x6c0c0b15);
1376 odm_write_4byte(dm, 0x1b80, 0x6c0c0b17);
1377 odm_write_4byte(dm, 0x1b80, 0x6d000b25);
1378 odm_write_4byte(dm, 0x1b80, 0x6d000b27);
1379 odm_write_4byte(dm, 0x1b80, 0xe23f0b35);
1380 odm_write_4byte(dm, 0x1b80, 0xe23f0b37);
1381 odm_write_4byte(dm, 0x1b80, 0xe2990b45);
1382 odm_write_4byte(dm, 0x1b80, 0xe2990b47);
1383 odm_write_4byte(dm, 0x1b80, 0x6c1c0b55);
1384 odm_write_4byte(dm, 0x1b80, 0x6c1c0b57);
1385 odm_write_4byte(dm, 0x1b80, 0xe23f0b65);
1386 odm_write_4byte(dm, 0x1b80, 0xe23f0b67);
1387 odm_write_4byte(dm, 0x1b80, 0xe2990b75);
1388 odm_write_4byte(dm, 0x1b80, 0xe2990b77);
1389 odm_write_4byte(dm, 0x1b80, 0x6c3c0b85);
1390 odm_write_4byte(dm, 0x1b80, 0x6c3c0b87);
1391 odm_write_4byte(dm, 0x1b80, 0xe23f0b95);
1392 odm_write_4byte(dm, 0x1b80, 0xe23f0b97);
1393 odm_write_4byte(dm, 0x1b80, 0xe2990ba5);
1394 odm_write_4byte(dm, 0x1b80, 0xe2990ba7);
1395 odm_write_4byte(dm, 0x1b80, 0xf3c10bb5);
1396 odm_write_4byte(dm, 0x1b80, 0xf3c10bb7);
1397 odm_write_4byte(dm, 0x1b80, 0x6c5c0bc5);
1398 odm_write_4byte(dm, 0x1b80, 0x6c5c0bc7);
1399 odm_write_4byte(dm, 0x1b80, 0xe23f0bd5);
1400 odm_write_4byte(dm, 0x1b80, 0xe23f0bd7);
1401 odm_write_4byte(dm, 0x1b80, 0xe2990be5);
1402 odm_write_4byte(dm, 0x1b80, 0xe2990be7);
1403 odm_write_4byte(dm, 0x1b80, 0x6c7c0bf5);
1404 odm_write_4byte(dm, 0x1b80, 0x6c7c0bf7);
1405 odm_write_4byte(dm, 0x1b80, 0xe23f0c05);
1406 odm_write_4byte(dm, 0x1b80, 0xe23f0c07);
1407 odm_write_4byte(dm, 0x1b80, 0xe2990c15);
1408 odm_write_4byte(dm, 0x1b80, 0xe2990c17);
1409 odm_write_4byte(dm, 0x1b80, 0xf4c50c25);
1410 odm_write_4byte(dm, 0x1b80, 0xf4c50c27);
1411 odm_write_4byte(dm, 0x1b80, 0x6c9c0c35);
1412 odm_write_4byte(dm, 0x1b80, 0x6c9c0c37);
1413 odm_write_4byte(dm, 0x1b80, 0xe23f0c45);
1414 odm_write_4byte(dm, 0x1b80, 0xe23f0c47);
1415 odm_write_4byte(dm, 0x1b80, 0xe2990c55);
1416 odm_write_4byte(dm, 0x1b80, 0xe2990c57);
1417 odm_write_4byte(dm, 0x1b80, 0x6cbc0c65);
1418 odm_write_4byte(dm, 0x1b80, 0x6cbc0c67);
1419 odm_write_4byte(dm, 0x1b80, 0xe23f0c75);
1420 odm_write_4byte(dm, 0x1b80, 0xe23f0c77);
1421 odm_write_4byte(dm, 0x1b80, 0xe2990c85);
1422 odm_write_4byte(dm, 0x1b80, 0xe2990c87);
1423 odm_write_4byte(dm, 0x1b80, 0x6cdc0c95);
1424 odm_write_4byte(dm, 0x1b80, 0x6cdc0c97);
1425 odm_write_4byte(dm, 0x1b80, 0xe23f0ca5);
1426 odm_write_4byte(dm, 0x1b80, 0xe23f0ca7);
1427 odm_write_4byte(dm, 0x1b80, 0xe2990cb5);
1428 odm_write_4byte(dm, 0x1b80, 0xe2990cb7);
1429 odm_write_4byte(dm, 0x1b80, 0x6cf00cc5);
1430 odm_write_4byte(dm, 0x1b80, 0x6cf00cc7);
1431 odm_write_4byte(dm, 0x1b80, 0xe23f0cd5);
1432 odm_write_4byte(dm, 0x1b80, 0xe23f0cd7);
1433 odm_write_4byte(dm, 0x1b80, 0xe2990ce5);
1434 odm_write_4byte(dm, 0x1b80, 0xe2990ce7);
1435 odm_write_4byte(dm, 0x1b80, 0x63c30cf5);
1436 odm_write_4byte(dm, 0x1b80, 0x63c30cf7);
1437 odm_write_4byte(dm, 0x1b80, 0x55010d05);
1438 odm_write_4byte(dm, 0x1b80, 0x55010d07);
1439 odm_write_4byte(dm, 0x1b80, 0x57040d15);
1440 odm_write_4byte(dm, 0x1b80, 0x57040d17);
1441 odm_write_4byte(dm, 0x1b80, 0x57000d25);
1442 odm_write_4byte(dm, 0x1b80, 0x57000d27);
1443 odm_write_4byte(dm, 0x1b80, 0x96000d35);
1444 odm_write_4byte(dm, 0x1b80, 0x96000d37);
1445 odm_write_4byte(dm, 0x1b80, 0x57080d45);
1446 odm_write_4byte(dm, 0x1b80, 0x57080d47);
1447 odm_write_4byte(dm, 0x1b80, 0x57000d55);
1448 odm_write_4byte(dm, 0x1b80, 0x57000d57);
1449 odm_write_4byte(dm, 0x1b80, 0x95000d65);
1450 odm_write_4byte(dm, 0x1b80, 0x95000d67);
1451 odm_write_4byte(dm, 0x1b80, 0x4d000d75);
1452 odm_write_4byte(dm, 0x1b80, 0x4d000d77);
1453 odm_write_4byte(dm, 0x1b80, 0x63070d85);
1454 odm_write_4byte(dm, 0x1b80, 0x63070d87);
1455 odm_write_4byte(dm, 0x1b80, 0x7b400d95);
1456 odm_write_4byte(dm, 0x1b80, 0x7b400d97);
1457 odm_write_4byte(dm, 0x1b80, 0x7a000da5);
1458 odm_write_4byte(dm, 0x1b80, 0x7a000da7);
1459 odm_write_4byte(dm, 0x1b80, 0x79000db5);
1460 odm_write_4byte(dm, 0x1b80, 0x79000db7);
1461 odm_write_4byte(dm, 0x1b80, 0x7f400dc5);
1462 odm_write_4byte(dm, 0x1b80, 0x7f400dc7);
1463 odm_write_4byte(dm, 0x1b80, 0x7e000dd5);
1464 odm_write_4byte(dm, 0x1b80, 0x7e000dd7);
1465 odm_write_4byte(dm, 0x1b80, 0x7d000de5);
1466 odm_write_4byte(dm, 0x1b80, 0x7d000de7);
1467 odm_write_4byte(dm, 0x1b80, 0x00010df5);
1468 odm_write_4byte(dm, 0x1b80, 0x00010df7);
1469 odm_write_4byte(dm, 0x1b80, 0xe26b0e05);
1470 odm_write_4byte(dm, 0x1b80, 0xe26b0e07);
1471 odm_write_4byte(dm, 0x1b80, 0x00010e15);
1472 odm_write_4byte(dm, 0x1b80, 0x00010e17);
1473 odm_write_4byte(dm, 0x1b80, 0x5c320e25);
1474 odm_write_4byte(dm, 0x1b80, 0x5c320e27);
1475 odm_write_4byte(dm, 0x1b80, 0xe2950e35);
1476 odm_write_4byte(dm, 0x1b80, 0xe2950e37);
1477 odm_write_4byte(dm, 0x1b80, 0xe26b0e45);
1478 odm_write_4byte(dm, 0x1b80, 0xe26b0e47);
1479 odm_write_4byte(dm, 0x1b80, 0x00010e55);
1480 odm_write_4byte(dm, 0x1b80, 0x00010e57);
1481 odm_write_4byte(dm, 0x1b80, 0x311d0e65);
1482 odm_write_4byte(dm, 0x1b80, 0x311d0e67);
1483 odm_write_4byte(dm, 0x1b80, 0x00260e75);
1484 odm_write_4byte(dm, 0x1b80, 0x00260e77);
1485 odm_write_4byte(dm, 0x1b80, 0xe29e0e85);
1486 odm_write_4byte(dm, 0x1b80, 0xe29e0e87);
1487 odm_write_4byte(dm, 0x1b80, 0x00020e95);
1488 odm_write_4byte(dm, 0x1b80, 0x00020e97);
1489 odm_write_4byte(dm, 0x1b80, 0x54ec0ea5);
1490 odm_write_4byte(dm, 0x1b80, 0x54ec0ea7);
1491 odm_write_4byte(dm, 0x1b80, 0x0ba60eb5);
1492 odm_write_4byte(dm, 0x1b80, 0x0ba60eb7);
1493 odm_write_4byte(dm, 0x1b80, 0x00260ec5);
1494 odm_write_4byte(dm, 0x1b80, 0x00260ec7);
1495 odm_write_4byte(dm, 0x1b80, 0xe29e0ed5);
1496 odm_write_4byte(dm, 0x1b80, 0xe29e0ed7);
1497 odm_write_4byte(dm, 0x1b80, 0x00020ee5);
1498 odm_write_4byte(dm, 0x1b80, 0x00020ee7);
1499 odm_write_4byte(dm, 0x1b80, 0x63830ef5);
1500 odm_write_4byte(dm, 0x1b80, 0x63830ef7);
1501 odm_write_4byte(dm, 0x1b80, 0x30d00f05);
1502 odm_write_4byte(dm, 0x1b80, 0x30d00f07);
1503 odm_write_4byte(dm, 0x1b80, 0x31110f15);
1504 odm_write_4byte(dm, 0x1b80, 0x31110f17);
1505 odm_write_4byte(dm, 0x1b80, 0x00240f25);
1506 odm_write_4byte(dm, 0x1b80, 0x00240f27);
1507 odm_write_4byte(dm, 0x1b80, 0xe29e0f35);
1508 odm_write_4byte(dm, 0x1b80, 0xe29e0f37);
1509 odm_write_4byte(dm, 0x1b80, 0x00020f45);
1510 odm_write_4byte(dm, 0x1b80, 0x00020f47);
1511 odm_write_4byte(dm, 0x1b80, 0x54ea0f55);
1512 odm_write_4byte(dm, 0x1b80, 0x54ea0f57);
1513 odm_write_4byte(dm, 0x1b80, 0x0ba60f65);
1514 odm_write_4byte(dm, 0x1b80, 0x0ba60f67);
1515 odm_write_4byte(dm, 0x1b80, 0x00240f75);
1516 odm_write_4byte(dm, 0x1b80, 0x00240f77);
1517 odm_write_4byte(dm, 0x1b80, 0xe29e0f85);
1518 odm_write_4byte(dm, 0x1b80, 0xe29e0f87);
1519 odm_write_4byte(dm, 0x1b80, 0x00020f95);
1520 odm_write_4byte(dm, 0x1b80, 0x00020f97);
1521 odm_write_4byte(dm, 0x1b80, 0x63830fa5);
1522 odm_write_4byte(dm, 0x1b80, 0x63830fa7);
1523 odm_write_4byte(dm, 0x1b80, 0x30d00fb5);
1524 odm_write_4byte(dm, 0x1b80, 0x30d00fb7);
1525 odm_write_4byte(dm, 0x1b80, 0x5c320fc5);
1526 odm_write_4byte(dm, 0x1b80, 0x5c320fc7);
1527 odm_write_4byte(dm, 0x1b80, 0x54e60fd5);
1528 odm_write_4byte(dm, 0x1b80, 0x54e60fd7);
1529 odm_write_4byte(dm, 0x1b80, 0x6e100fe5);
1530 odm_write_4byte(dm, 0x1b80, 0x6e100fe7);
1531 odm_write_4byte(dm, 0x1b80, 0x6f0f0ff5);
1532 odm_write_4byte(dm, 0x1b80, 0x6f0f0ff7);
1533 odm_write_4byte(dm, 0x1b80, 0xe26b1005);
1534 odm_write_4byte(dm, 0x1b80, 0xe26b1007);
1535 odm_write_4byte(dm, 0x1b80, 0xe29e1015);
1536 odm_write_4byte(dm, 0x1b80, 0xe29e1017);
1537 odm_write_4byte(dm, 0x1b80, 0x5c321025);
1538 odm_write_4byte(dm, 0x1b80, 0x5c321027);
1539 odm_write_4byte(dm, 0x1b80, 0x54e71035);
1540 odm_write_4byte(dm, 0x1b80, 0x54e71037);
1541 odm_write_4byte(dm, 0x1b80, 0x6e241045);
1542 odm_write_4byte(dm, 0x1b80, 0x6e241047);
1543 odm_write_4byte(dm, 0x1b80, 0xe26b1055);
1544 odm_write_4byte(dm, 0x1b80, 0xe26b1057);
1545 odm_write_4byte(dm, 0x1b80, 0xe29e1065);
1546 odm_write_4byte(dm, 0x1b80, 0xe29e1067);
1547 odm_write_4byte(dm, 0x1b80, 0x5c321075);
1548 odm_write_4byte(dm, 0x1b80, 0x5c321077);
1549 odm_write_4byte(dm, 0x1b80, 0x54e81085);
1550 odm_write_4byte(dm, 0x1b80, 0x54e81087);
1551 odm_write_4byte(dm, 0x1b80, 0x6e441095);
1552 odm_write_4byte(dm, 0x1b80, 0x6e441097);
1553 odm_write_4byte(dm, 0x1b80, 0xe26b10a5);
1554 odm_write_4byte(dm, 0x1b80, 0xe26b10a7);
1555 odm_write_4byte(dm, 0x1b80, 0xe29e10b5);
1556 odm_write_4byte(dm, 0x1b80, 0xe29e10b7);
1557 odm_write_4byte(dm, 0x1b80, 0x5c3210c5);
1558 odm_write_4byte(dm, 0x1b80, 0x5c3210c7);
1559 odm_write_4byte(dm, 0x1b80, 0x54e910d5);
1560 odm_write_4byte(dm, 0x1b80, 0x54e910d7);
1561 odm_write_4byte(dm, 0x1b80, 0x6e6410e5);
1562 odm_write_4byte(dm, 0x1b80, 0x6e6410e7);
1563 odm_write_4byte(dm, 0x1b80, 0xe26b10f5);
1564 odm_write_4byte(dm, 0x1b80, 0xe26b10f7);
1565 odm_write_4byte(dm, 0x1b80, 0xe29e1105);
1566 odm_write_4byte(dm, 0x1b80, 0xe29e1107);
1567 odm_write_4byte(dm, 0x1b80, 0x5c321115);
1568 odm_write_4byte(dm, 0x1b80, 0x5c321117);
1569 odm_write_4byte(dm, 0x1b80, 0x54ea1125);
1570 odm_write_4byte(dm, 0x1b80, 0x54ea1127);
1571 odm_write_4byte(dm, 0x1b80, 0x0baa1135);
1572 odm_write_4byte(dm, 0x1b80, 0x0baa1137);
1573 odm_write_4byte(dm, 0x1b80, 0x6e841145);
1574 odm_write_4byte(dm, 0x1b80, 0x6e841147);
1575 odm_write_4byte(dm, 0x1b80, 0x6f0f1155);
1576 odm_write_4byte(dm, 0x1b80, 0x6f0f1157);
1577 odm_write_4byte(dm, 0x1b80, 0xe26b1165);
1578 odm_write_4byte(dm, 0x1b80, 0xe26b1167);
1579 odm_write_4byte(dm, 0x1b80, 0xe29e1175);
1580 odm_write_4byte(dm, 0x1b80, 0xe29e1177);
1581 odm_write_4byte(dm, 0x1b80, 0x5c321185);
1582 odm_write_4byte(dm, 0x1b80, 0x5c321187);
1583 odm_write_4byte(dm, 0x1b80, 0x54eb1195);
1584 odm_write_4byte(dm, 0x1b80, 0x54eb1197);
1585 odm_write_4byte(dm, 0x1b80, 0x6ea411a5);
1586 odm_write_4byte(dm, 0x1b80, 0x6ea411a7);
1587 odm_write_4byte(dm, 0x1b80, 0xe26b11b5);
1588 odm_write_4byte(dm, 0x1b80, 0xe26b11b7);
1589 odm_write_4byte(dm, 0x1b80, 0xe29e11c5);
1590 odm_write_4byte(dm, 0x1b80, 0xe29e11c7);
1591 odm_write_4byte(dm, 0x1b80, 0x5c3211d5);
1592 odm_write_4byte(dm, 0x1b80, 0x5c3211d7);
1593 odm_write_4byte(dm, 0x1b80, 0x54ec11e5);
1594 odm_write_4byte(dm, 0x1b80, 0x54ec11e7);
1595 odm_write_4byte(dm, 0x1b80, 0x0bac11f5);
1596 odm_write_4byte(dm, 0x1b80, 0x0bac11f7);
1597 odm_write_4byte(dm, 0x1b80, 0x6ec41205);
1598 odm_write_4byte(dm, 0x1b80, 0x6ec41207);
1599 odm_write_4byte(dm, 0x1b80, 0x6f0f1215);
1600 odm_write_4byte(dm, 0x1b80, 0x6f0f1217);
1601 odm_write_4byte(dm, 0x1b80, 0xe26b1225);
1602 odm_write_4byte(dm, 0x1b80, 0xe26b1227);
1603 odm_write_4byte(dm, 0x1b80, 0xe29e1235);
1604 odm_write_4byte(dm, 0x1b80, 0xe29e1237);
1605 odm_write_4byte(dm, 0x1b80, 0x5c321245);
1606 odm_write_4byte(dm, 0x1b80, 0x5c321247);
1607 odm_write_4byte(dm, 0x1b80, 0x54ed1255);
1608 odm_write_4byte(dm, 0x1b80, 0x54ed1257);
1609 odm_write_4byte(dm, 0x1b80, 0x6ee41265);
1610 odm_write_4byte(dm, 0x1b80, 0x6ee41267);
1611 odm_write_4byte(dm, 0x1b80, 0xe26b1275);
1612 odm_write_4byte(dm, 0x1b80, 0xe26b1277);
1613 odm_write_4byte(dm, 0x1b80, 0xe29e1285);
1614 odm_write_4byte(dm, 0x1b80, 0xe29e1287);
1615 odm_write_4byte(dm, 0x1b80, 0x5c321295);
1616 odm_write_4byte(dm, 0x1b80, 0x5c321297);
1617 odm_write_4byte(dm, 0x1b80, 0x54ee12a5);
1618 odm_write_4byte(dm, 0x1b80, 0x54ee12a7);
1619 odm_write_4byte(dm, 0x1b80, 0x6ef412b5);
1620 odm_write_4byte(dm, 0x1b80, 0x6ef412b7);
1621 odm_write_4byte(dm, 0x1b80, 0xe26b12c5);
1622 odm_write_4byte(dm, 0x1b80, 0xe26b12c7);
1623 odm_write_4byte(dm, 0x1b80, 0xe29e12d5);
1624 odm_write_4byte(dm, 0x1b80, 0xe29e12d7);
1625 odm_write_4byte(dm, 0x1b80, 0x5c3212e5);
1626 odm_write_4byte(dm, 0x1b80, 0x5c3212e7);
1627 odm_write_4byte(dm, 0x1b80, 0x54ef12f5);
1628 odm_write_4byte(dm, 0x1b80, 0x54ef12f7);
1629 odm_write_4byte(dm, 0x1b80, 0x6e0c1305);
1630 odm_write_4byte(dm, 0x1b80, 0x6e0c1307);
1631 odm_write_4byte(dm, 0x1b80, 0x6f001315);
1632 odm_write_4byte(dm, 0x1b80, 0x6f001317);
1633 odm_write_4byte(dm, 0x1b80, 0xe26b1325);
1634 odm_write_4byte(dm, 0x1b80, 0xe26b1327);
1635 odm_write_4byte(dm, 0x1b80, 0xe29e1335);
1636 odm_write_4byte(dm, 0x1b80, 0xe29e1337);
1637 odm_write_4byte(dm, 0x1b80, 0x5c321345);
1638 odm_write_4byte(dm, 0x1b80, 0x5c321347);
1639 odm_write_4byte(dm, 0x1b80, 0x54f01355);
1640 odm_write_4byte(dm, 0x1b80, 0x54f01357);
1641 odm_write_4byte(dm, 0x1b80, 0x6e1c1365);
1642 odm_write_4byte(dm, 0x1b80, 0x6e1c1367);
1643 odm_write_4byte(dm, 0x1b80, 0xe26b1375);
1644 odm_write_4byte(dm, 0x1b80, 0xe26b1377);
1645 odm_write_4byte(dm, 0x1b80, 0xe29e1385);
1646 odm_write_4byte(dm, 0x1b80, 0xe29e1387);
1647 odm_write_4byte(dm, 0x1b80, 0x5c321395);
1648 odm_write_4byte(dm, 0x1b80, 0x5c321397);
1649 odm_write_4byte(dm, 0x1b80, 0x54f113a5);
1650 odm_write_4byte(dm, 0x1b80, 0x54f113a7);
1651 odm_write_4byte(dm, 0x1b80, 0x6e3c13b5);
1652 odm_write_4byte(dm, 0x1b80, 0x6e3c13b7);
1653 odm_write_4byte(dm, 0x1b80, 0xe26b13c5);
1654 odm_write_4byte(dm, 0x1b80, 0xe26b13c7);
1655 odm_write_4byte(dm, 0x1b80, 0xe29e13d5);
1656 odm_write_4byte(dm, 0x1b80, 0xe29e13d7);
1657 odm_write_4byte(dm, 0x1b80, 0xf6a913e5);
1658 odm_write_4byte(dm, 0x1b80, 0xf6a913e7);
1659 odm_write_4byte(dm, 0x1b80, 0x5c3213f5);
1660 odm_write_4byte(dm, 0x1b80, 0x5c3213f7);
1661 odm_write_4byte(dm, 0x1b80, 0x54f21405);
1662 odm_write_4byte(dm, 0x1b80, 0x54f21407);
1663 odm_write_4byte(dm, 0x1b80, 0x6e5c1415);
1664 odm_write_4byte(dm, 0x1b80, 0x6e5c1417);
1665 odm_write_4byte(dm, 0x1b80, 0xe26b1425);
1666 odm_write_4byte(dm, 0x1b80, 0xe26b1427);
1667 odm_write_4byte(dm, 0x1b80, 0xe29e1435);
1668 odm_write_4byte(dm, 0x1b80, 0xe29e1437);
1669 odm_write_4byte(dm, 0x1b80, 0x5c321445);
1670 odm_write_4byte(dm, 0x1b80, 0x5c321447);
1671 odm_write_4byte(dm, 0x1b80, 0x54f31455);
1672 odm_write_4byte(dm, 0x1b80, 0x54f31457);
1673 odm_write_4byte(dm, 0x1b80, 0x6e7c1465);
1674 odm_write_4byte(dm, 0x1b80, 0x6e7c1467);
1675 odm_write_4byte(dm, 0x1b80, 0xe26b1475);
1676 odm_write_4byte(dm, 0x1b80, 0xe26b1477);
1677 odm_write_4byte(dm, 0x1b80, 0xe29e1485);
1678 odm_write_4byte(dm, 0x1b80, 0xe29e1487);
1679 odm_write_4byte(dm, 0x1b80, 0xf7a91495);
1680 odm_write_4byte(dm, 0x1b80, 0xf7a91497);
1681 odm_write_4byte(dm, 0x1b80, 0x5c3214a5);
1682 odm_write_4byte(dm, 0x1b80, 0x5c3214a7);
1683 odm_write_4byte(dm, 0x1b80, 0x54f414b5);
1684 odm_write_4byte(dm, 0x1b80, 0x54f414b7);
1685 odm_write_4byte(dm, 0x1b80, 0x6e9c14c5);
1686 odm_write_4byte(dm, 0x1b80, 0x6e9c14c7);
1687 odm_write_4byte(dm, 0x1b80, 0xe26b14d5);
1688 odm_write_4byte(dm, 0x1b80, 0xe26b14d7);
1689 odm_write_4byte(dm, 0x1b80, 0xe29e14e5);
1690 odm_write_4byte(dm, 0x1b80, 0xe29e14e7);
1691 odm_write_4byte(dm, 0x1b80, 0x5c3214f5);
1692 odm_write_4byte(dm, 0x1b80, 0x5c3214f7);
1693 odm_write_4byte(dm, 0x1b80, 0x54f51505);
1694 odm_write_4byte(dm, 0x1b80, 0x54f51507);
1695 odm_write_4byte(dm, 0x1b80, 0x6ebc1515);
1696 odm_write_4byte(dm, 0x1b80, 0x6ebc1517);
1697 odm_write_4byte(dm, 0x1b80, 0xe26b1525);
1698 odm_write_4byte(dm, 0x1b80, 0xe26b1527);
1699 odm_write_4byte(dm, 0x1b80, 0xe29e1535);
1700 odm_write_4byte(dm, 0x1b80, 0xe29e1537);
1701 odm_write_4byte(dm, 0x1b80, 0x5c321545);
1702 odm_write_4byte(dm, 0x1b80, 0x5c321547);
1703 odm_write_4byte(dm, 0x1b80, 0x54f61555);
1704 odm_write_4byte(dm, 0x1b80, 0x54f61557);
1705 odm_write_4byte(dm, 0x1b80, 0x6edc1565);
1706 odm_write_4byte(dm, 0x1b80, 0x6edc1567);
1707 odm_write_4byte(dm, 0x1b80, 0xe26b1575);
1708 odm_write_4byte(dm, 0x1b80, 0xe26b1577);
1709 odm_write_4byte(dm, 0x1b80, 0xe29e1585);
1710 odm_write_4byte(dm, 0x1b80, 0xe29e1587);
1711 odm_write_4byte(dm, 0x1b80, 0x5c321595);
1712 odm_write_4byte(dm, 0x1b80, 0x5c321597);
1713 odm_write_4byte(dm, 0x1b80, 0x54f715a5);
1714 odm_write_4byte(dm, 0x1b80, 0x54f715a7);
1715 odm_write_4byte(dm, 0x1b80, 0x6ef015b5);
1716 odm_write_4byte(dm, 0x1b80, 0x6ef015b7);
1717 odm_write_4byte(dm, 0x1b80, 0xe26b15c5);
1718 odm_write_4byte(dm, 0x1b80, 0xe26b15c7);
1719 odm_write_4byte(dm, 0x1b80, 0xe29e15d5);
1720 odm_write_4byte(dm, 0x1b80, 0xe29e15d7);
1721 odm_write_4byte(dm, 0x1b80, 0x638315e5);
1722 odm_write_4byte(dm, 0x1b80, 0x638315e7);
1723 odm_write_4byte(dm, 0x1b80, 0x30d015f5);
1724 odm_write_4byte(dm, 0x1b80, 0x30d015f7);
1725 odm_write_4byte(dm, 0x1b80, 0x00011605);
1726 odm_write_4byte(dm, 0x1b80, 0x00011607);
1727 odm_write_4byte(dm, 0x1b80, 0x00041615);
1728 odm_write_4byte(dm, 0x1b80, 0x00041617);
1729 odm_write_4byte(dm, 0x1b80, 0x55011625);
1730 odm_write_4byte(dm, 0x1b80, 0x55011627);
1731 odm_write_4byte(dm, 0x1b80, 0x5c311635);
1732 odm_write_4byte(dm, 0x1b80, 0x5c311637);
1733 odm_write_4byte(dm, 0x1b80, 0x5f821645);
1734 odm_write_4byte(dm, 0x1b80, 0x5f821647);
1735 odm_write_4byte(dm, 0x1b80, 0x66051655);
1736 odm_write_4byte(dm, 0x1b80, 0x66051657);
1737 odm_write_4byte(dm, 0x1b80, 0x00061665);
1738 odm_write_4byte(dm, 0x1b80, 0x00061667);
1739 odm_write_4byte(dm, 0x1b80, 0x5d801675);
1740 odm_write_4byte(dm, 0x1b80, 0x5d801677);
1741 odm_write_4byte(dm, 0x1b80, 0x09001685);
1742 odm_write_4byte(dm, 0x1b80, 0x09001687);
1743 odm_write_4byte(dm, 0x1b80, 0x0a011695);
1744 odm_write_4byte(dm, 0x1b80, 0x0a011697);
1745 odm_write_4byte(dm, 0x1b80, 0x0b4016a5);
1746 odm_write_4byte(dm, 0x1b80, 0x0b4016a7);
1747 odm_write_4byte(dm, 0x1b80, 0x0d0016b5);
1748 odm_write_4byte(dm, 0x1b80, 0x0d0016b7);
1749 odm_write_4byte(dm, 0x1b80, 0x0f0116c5);
1750 odm_write_4byte(dm, 0x1b80, 0x0f0116c7);
1751 odm_write_4byte(dm, 0x1b80, 0x002a16d5);
1752 odm_write_4byte(dm, 0x1b80, 0x002a16d7);
1753 odm_write_4byte(dm, 0x1b80, 0x055a16e5);
1754 odm_write_4byte(dm, 0x1b80, 0x055a16e7);
1755 odm_write_4byte(dm, 0x1b80, 0x05db16f5);
1756 odm_write_4byte(dm, 0x1b80, 0x05db16f7);
1757 odm_write_4byte(dm, 0x1b80, 0xe2891705);
1758 odm_write_4byte(dm, 0x1b80, 0xe2891707);
1759 odm_write_4byte(dm, 0x1b80, 0xe2371715);
1760 odm_write_4byte(dm, 0x1b80, 0xe2371717);
1761 odm_write_4byte(dm, 0x1b80, 0x00061725);
1762 odm_write_4byte(dm, 0x1b80, 0x00061727);
1763 odm_write_4byte(dm, 0x1b80, 0x06da1735);
1764 odm_write_4byte(dm, 0x1b80, 0x06da1737);
1765 odm_write_4byte(dm, 0x1b80, 0x07db1745);
1766 odm_write_4byte(dm, 0x1b80, 0x07db1747);
1767 odm_write_4byte(dm, 0x1b80, 0xe2891755);
1768 odm_write_4byte(dm, 0x1b80, 0xe2891757);
1769 odm_write_4byte(dm, 0x1b80, 0xe2371765);
1770 odm_write_4byte(dm, 0x1b80, 0xe2371767);
1771 odm_write_4byte(dm, 0x1b80, 0xe2801775);
1772 odm_write_4byte(dm, 0x1b80, 0xe2801777);
1773 odm_write_4byte(dm, 0x1b80, 0x00021785);
1774 odm_write_4byte(dm, 0x1b80, 0x00021787);
1775 odm_write_4byte(dm, 0x1b80, 0xe2851795);
1776 odm_write_4byte(dm, 0x1b80, 0xe2851797);
1777 odm_write_4byte(dm, 0x1b80, 0x5d0017a5);
1778 odm_write_4byte(dm, 0x1b80, 0x5d0017a7);
1779 odm_write_4byte(dm, 0x1b80, 0x000417b5);
1780 odm_write_4byte(dm, 0x1b80, 0x000417b7);
1781 odm_write_4byte(dm, 0x1b80, 0x5fa217c5);
1782 odm_write_4byte(dm, 0x1b80, 0x5fa217c7);
1783 odm_write_4byte(dm, 0x1b80, 0x000117d5);
1784 odm_write_4byte(dm, 0x1b80, 0x000117d7);
1785 odm_write_4byte(dm, 0x1b80, 0xe1c417e5);
1786 odm_write_4byte(dm, 0x1b80, 0xe1c417e7);
1787 odm_write_4byte(dm, 0x1b80, 0x740817f5);
1788 odm_write_4byte(dm, 0x1b80, 0x740817f7);
1789 odm_write_4byte(dm, 0x1b80, 0xe2021805);
1790 odm_write_4byte(dm, 0x1b80, 0xe2021807);
1791 odm_write_4byte(dm, 0x1b80, 0xe1e41815);
1792 odm_write_4byte(dm, 0x1b80, 0xe1e41817);
1793 odm_write_4byte(dm, 0x1b80, 0xe2161825);
1794 odm_write_4byte(dm, 0x1b80, 0xe2161827);
1795 odm_write_4byte(dm, 0x1b80, 0xe2221835);
1796 odm_write_4byte(dm, 0x1b80, 0xe2221837);
1797 odm_write_4byte(dm, 0x1b80, 0x00011845);
1798 odm_write_4byte(dm, 0x1b80, 0x00011847);
1799 odm_write_4byte(dm, 0x1b80, 0xe1c41855);
1800 odm_write_4byte(dm, 0x1b80, 0xe1c41857);
1801 odm_write_4byte(dm, 0x1b80, 0x74081865);
1802 odm_write_4byte(dm, 0x1b80, 0x74081867);
1803 odm_write_4byte(dm, 0x1b80, 0xe20c1875);
1804 odm_write_4byte(dm, 0x1b80, 0xe20c1877);
1805 odm_write_4byte(dm, 0x1b80, 0xe1e41885);
1806 odm_write_4byte(dm, 0x1b80, 0xe1e41887);
1807 odm_write_4byte(dm, 0x1b80, 0xe21c1895);
1808 odm_write_4byte(dm, 0x1b80, 0xe21c1897);
1809 odm_write_4byte(dm, 0x1b80, 0xe22218a5);
1810 odm_write_4byte(dm, 0x1b80, 0xe22218a7);
1811 odm_write_4byte(dm, 0x1b80, 0x000118b5);
1812 odm_write_4byte(dm, 0x1b80, 0x000118b7);
1813 odm_write_4byte(dm, 0x1b80, 0xe1d418c5);
1814 odm_write_4byte(dm, 0x1b80, 0xe1d418c7);
1815 odm_write_4byte(dm, 0x1b80, 0x740018d5);
1816 odm_write_4byte(dm, 0x1b80, 0x740018d7);
1817 odm_write_4byte(dm, 0x1b80, 0xe20218e5);
1818 odm_write_4byte(dm, 0x1b80, 0xe20218e7);
1819 odm_write_4byte(dm, 0x1b80, 0xe1f318f5);
1820 odm_write_4byte(dm, 0x1b80, 0xe1f318f7);
1821 odm_write_4byte(dm, 0x1b80, 0xe2161905);
1822 odm_write_4byte(dm, 0x1b80, 0xe2161907);
1823 odm_write_4byte(dm, 0x1b80, 0xe2221915);
1824 odm_write_4byte(dm, 0x1b80, 0xe2221917);
1825 odm_write_4byte(dm, 0x1b80, 0x00011925);
1826 odm_write_4byte(dm, 0x1b80, 0x00011927);
1827 odm_write_4byte(dm, 0x1b80, 0xe1d41935);
1828 odm_write_4byte(dm, 0x1b80, 0xe1d41937);
1829 odm_write_4byte(dm, 0x1b80, 0x74001945);
1830 odm_write_4byte(dm, 0x1b80, 0x74001947);
1831 odm_write_4byte(dm, 0x1b80, 0xe20c1955);
1832 odm_write_4byte(dm, 0x1b80, 0xe20c1957);
1833 odm_write_4byte(dm, 0x1b80, 0xe1f31965);
1834 odm_write_4byte(dm, 0x1b80, 0xe1f31967);
1835 odm_write_4byte(dm, 0x1b80, 0xe21c1975);
1836 odm_write_4byte(dm, 0x1b80, 0xe21c1977);
1837 odm_write_4byte(dm, 0x1b80, 0xe2221985);
1838 odm_write_4byte(dm, 0x1b80, 0xe2221987);
1839 odm_write_4byte(dm, 0x1b80, 0x00011995);
1840 odm_write_4byte(dm, 0x1b80, 0x00011997);
1841 odm_write_4byte(dm, 0x1b80, 0x000419a5);
1842 odm_write_4byte(dm, 0x1b80, 0x000419a7);
1843 odm_write_4byte(dm, 0x1b80, 0x445b19b5);
1844 odm_write_4byte(dm, 0x1b80, 0x445b19b7);
1845 odm_write_4byte(dm, 0x1b80, 0x470019c5);
1846 odm_write_4byte(dm, 0x1b80, 0x470019c7);
1847 odm_write_4byte(dm, 0x1b80, 0x000619d5);
1848 odm_write_4byte(dm, 0x1b80, 0x000619d7);
1849 odm_write_4byte(dm, 0x1b80, 0x772819e5);
1850 odm_write_4byte(dm, 0x1b80, 0x772819e7);
1851 odm_write_4byte(dm, 0x1b80, 0x000419f5);
1852 odm_write_4byte(dm, 0x1b80, 0x000419f7);
1853 odm_write_4byte(dm, 0x1b80, 0x4b801a05);
1854 odm_write_4byte(dm, 0x1b80, 0x4b801a07);
1855 odm_write_4byte(dm, 0x1b80, 0x40081a15);
1856 odm_write_4byte(dm, 0x1b80, 0x40081a17);
1857 odm_write_4byte(dm, 0x1b80, 0x00011a25);
1858 odm_write_4byte(dm, 0x1b80, 0x00011a27);
1859 odm_write_4byte(dm, 0x1b80, 0x00051a35);
1860 odm_write_4byte(dm, 0x1b80, 0x00051a37);
1861 odm_write_4byte(dm, 0x1b80, 0x5c5b1a45);
1862 odm_write_4byte(dm, 0x1b80, 0x5c5b1a47);
1863 odm_write_4byte(dm, 0x1b80, 0x5f001a55);
1864 odm_write_4byte(dm, 0x1b80, 0x5f001a57);
1865 odm_write_4byte(dm, 0x1b80, 0x00061a65);
1866 odm_write_4byte(dm, 0x1b80, 0x00061a67);
1867 odm_write_4byte(dm, 0x1b80, 0x77291a75);
1868 odm_write_4byte(dm, 0x1b80, 0x77291a77);
1869 odm_write_4byte(dm, 0x1b80, 0x00041a85);
1870 odm_write_4byte(dm, 0x1b80, 0x00041a87);
1871 odm_write_4byte(dm, 0x1b80, 0x63801a95);
1872 odm_write_4byte(dm, 0x1b80, 0x63801a97);
1873 odm_write_4byte(dm, 0x1b80, 0x40081aa5);
1874 odm_write_4byte(dm, 0x1b80, 0x40081aa7);
1875 odm_write_4byte(dm, 0x1b80, 0x00011ab5);
1876 odm_write_4byte(dm, 0x1b80, 0x00011ab7);
1877 odm_write_4byte(dm, 0x1b80, 0xe1c41ac5);
1878 odm_write_4byte(dm, 0x1b80, 0xe1c41ac7);
1879 odm_write_4byte(dm, 0x1b80, 0x74081ad5);
1880 odm_write_4byte(dm, 0x1b80, 0x74081ad7);
1881 odm_write_4byte(dm, 0x1b80, 0xe2021ae5);
1882 odm_write_4byte(dm, 0x1b80, 0xe2021ae7);
1883 odm_write_4byte(dm, 0x1b80, 0x00041af5);
1884 odm_write_4byte(dm, 0x1b80, 0x00041af7);
1885 odm_write_4byte(dm, 0x1b80, 0x40081b05);
1886 odm_write_4byte(dm, 0x1b80, 0x40081b07);
1887 odm_write_4byte(dm, 0x1b80, 0x00011b15);
1888 odm_write_4byte(dm, 0x1b80, 0x00011b17);
1889 odm_write_4byte(dm, 0x1b80, 0xe1c41b25);
1890 odm_write_4byte(dm, 0x1b80, 0xe1c41b27);
1891 odm_write_4byte(dm, 0x1b80, 0x74081b35);
1892 odm_write_4byte(dm, 0x1b80, 0x74081b37);
1893 odm_write_4byte(dm, 0x1b80, 0xe20c1b45);
1894 odm_write_4byte(dm, 0x1b80, 0xe20c1b47);
1895 odm_write_4byte(dm, 0x1b80, 0x00041b55);
1896 odm_write_4byte(dm, 0x1b80, 0x00041b57);
1897 odm_write_4byte(dm, 0x1b80, 0x40081b65);
1898 odm_write_4byte(dm, 0x1b80, 0x40081b67);
1899 odm_write_4byte(dm, 0x1b80, 0x00011b75);
1900 odm_write_4byte(dm, 0x1b80, 0x00011b77);
1901 odm_write_4byte(dm, 0x1b80, 0xe1d41b85);
1902 odm_write_4byte(dm, 0x1b80, 0xe1d41b87);
1903 odm_write_4byte(dm, 0x1b80, 0x74001b95);
1904 odm_write_4byte(dm, 0x1b80, 0x74001b97);
1905 odm_write_4byte(dm, 0x1b80, 0xe2021ba5);
1906 odm_write_4byte(dm, 0x1b80, 0xe2021ba7);
1907 odm_write_4byte(dm, 0x1b80, 0x00041bb5);
1908 odm_write_4byte(dm, 0x1b80, 0x00041bb7);
1909 odm_write_4byte(dm, 0x1b80, 0x40081bc5);
1910 odm_write_4byte(dm, 0x1b80, 0x40081bc7);
1911 odm_write_4byte(dm, 0x1b80, 0x00011bd5);
1912 odm_write_4byte(dm, 0x1b80, 0x00011bd7);
1913 odm_write_4byte(dm, 0x1b80, 0xe1d41be5);
1914 odm_write_4byte(dm, 0x1b80, 0xe1d41be7);
1915 odm_write_4byte(dm, 0x1b80, 0x74001bf5);
1916 odm_write_4byte(dm, 0x1b80, 0x74001bf7);
1917 odm_write_4byte(dm, 0x1b80, 0xe20c1c05);
1918 odm_write_4byte(dm, 0x1b80, 0xe20c1c07);
1919 odm_write_4byte(dm, 0x1b80, 0x00041c15);
1920 odm_write_4byte(dm, 0x1b80, 0x00041c17);
1921 odm_write_4byte(dm, 0x1b80, 0x40081c25);
1922 odm_write_4byte(dm, 0x1b80, 0x40081c27);
1923 odm_write_4byte(dm, 0x1b80, 0x00011c35);
1924 odm_write_4byte(dm, 0x1b80, 0x00011c37);
1925 odm_write_4byte(dm, 0x1b80, 0x00071c45);
1926 odm_write_4byte(dm, 0x1b80, 0x00071c47);
1927 odm_write_4byte(dm, 0x1b80, 0x780c1c55);
1928 odm_write_4byte(dm, 0x1b80, 0x780c1c57);
1929 odm_write_4byte(dm, 0x1b80, 0x79191c65);
1930 odm_write_4byte(dm, 0x1b80, 0x79191c67);
1931 odm_write_4byte(dm, 0x1b80, 0x7a001c75);
1932 odm_write_4byte(dm, 0x1b80, 0x7a001c77);
1933 odm_write_4byte(dm, 0x1b80, 0x7b821c85);
1934 odm_write_4byte(dm, 0x1b80, 0x7b821c87);
1935 odm_write_4byte(dm, 0x1b80, 0x7b021c95);
1936 odm_write_4byte(dm, 0x1b80, 0x7b021c97);
1937 odm_write_4byte(dm, 0x1b80, 0x78141ca5);
1938 odm_write_4byte(dm, 0x1b80, 0x78141ca7);
1939 odm_write_4byte(dm, 0x1b80, 0x79ee1cb5);
1940 odm_write_4byte(dm, 0x1b80, 0x79ee1cb7);
1941 odm_write_4byte(dm, 0x1b80, 0x7a011cc5);
1942 odm_write_4byte(dm, 0x1b80, 0x7a011cc7);
1943 odm_write_4byte(dm, 0x1b80, 0x7b831cd5);
1944 odm_write_4byte(dm, 0x1b80, 0x7b831cd7);
1945 odm_write_4byte(dm, 0x1b80, 0x7b031ce5);
1946 odm_write_4byte(dm, 0x1b80, 0x7b031ce7);
1947 odm_write_4byte(dm, 0x1b80, 0x780f1cf5);
1948 odm_write_4byte(dm, 0x1b80, 0x780f1cf7);
1949 odm_write_4byte(dm, 0x1b80, 0x79b41d05);
1950 odm_write_4byte(dm, 0x1b80, 0x79b41d07);
1951 odm_write_4byte(dm, 0x1b80, 0x7a001d15);
1952 odm_write_4byte(dm, 0x1b80, 0x7a001d17);
1953 odm_write_4byte(dm, 0x1b80, 0x7b001d25);
1954 odm_write_4byte(dm, 0x1b80, 0x7b001d27);
1955 odm_write_4byte(dm, 0x1b80, 0x00011d35);
1956 odm_write_4byte(dm, 0x1b80, 0x00011d37);
1957 odm_write_4byte(dm, 0x1b80, 0x00071d45);
1958 odm_write_4byte(dm, 0x1b80, 0x00071d47);
1959 odm_write_4byte(dm, 0x1b80, 0x78101d55);
1960 odm_write_4byte(dm, 0x1b80, 0x78101d57);
1961 odm_write_4byte(dm, 0x1b80, 0x79131d65);
1962 odm_write_4byte(dm, 0x1b80, 0x79131d67);
1963 odm_write_4byte(dm, 0x1b80, 0x7a001d75);
1964 odm_write_4byte(dm, 0x1b80, 0x7a001d77);
1965 odm_write_4byte(dm, 0x1b80, 0x7b801d85);
1966 odm_write_4byte(dm, 0x1b80, 0x7b801d87);
1967 odm_write_4byte(dm, 0x1b80, 0x7b001d95);
1968 odm_write_4byte(dm, 0x1b80, 0x7b001d97);
1969 odm_write_4byte(dm, 0x1b80, 0x78db1da5);
1970 odm_write_4byte(dm, 0x1b80, 0x78db1da7);
1971 odm_write_4byte(dm, 0x1b80, 0x79001db5);
1972 odm_write_4byte(dm, 0x1b80, 0x79001db7);
1973 odm_write_4byte(dm, 0x1b80, 0x7a001dc5);
1974 odm_write_4byte(dm, 0x1b80, 0x7a001dc7);
1975 odm_write_4byte(dm, 0x1b80, 0x7b811dd5);
1976 odm_write_4byte(dm, 0x1b80, 0x7b811dd7);
1977 odm_write_4byte(dm, 0x1b80, 0x7b011de5);
1978 odm_write_4byte(dm, 0x1b80, 0x7b011de7);
1979 odm_write_4byte(dm, 0x1b80, 0x780f1df5);
1980 odm_write_4byte(dm, 0x1b80, 0x780f1df7);
1981 odm_write_4byte(dm, 0x1b80, 0x79b41e05);
1982 odm_write_4byte(dm, 0x1b80, 0x79b41e07);
1983 odm_write_4byte(dm, 0x1b80, 0x7a001e15);
1984 odm_write_4byte(dm, 0x1b80, 0x7a001e17);
1985 odm_write_4byte(dm, 0x1b80, 0x7b001e25);
1986 odm_write_4byte(dm, 0x1b80, 0x7b001e27);
1987 odm_write_4byte(dm, 0x1b80, 0x00011e35);
1988 odm_write_4byte(dm, 0x1b80, 0x00011e37);
1989 odm_write_4byte(dm, 0x1b80, 0x00071e45);
1990 odm_write_4byte(dm, 0x1b80, 0x00071e47);
1991 odm_write_4byte(dm, 0x1b80, 0x783e1e55);
1992 odm_write_4byte(dm, 0x1b80, 0x783e1e57);
1993 odm_write_4byte(dm, 0x1b80, 0x79f91e65);
1994 odm_write_4byte(dm, 0x1b80, 0x79f91e67);
1995 odm_write_4byte(dm, 0x1b80, 0x7a011e75);
1996 odm_write_4byte(dm, 0x1b80, 0x7a011e77);
1997 odm_write_4byte(dm, 0x1b80, 0x7b821e85);
1998 odm_write_4byte(dm, 0x1b80, 0x7b821e87);
1999 odm_write_4byte(dm, 0x1b80, 0x7b021e95);
2000 odm_write_4byte(dm, 0x1b80, 0x7b021e97);
2001 odm_write_4byte(dm, 0x1b80, 0x78a91ea5);
2002 odm_write_4byte(dm, 0x1b80, 0x78a91ea7);
2003 odm_write_4byte(dm, 0x1b80, 0x79ed1eb5);
2004 odm_write_4byte(dm, 0x1b80, 0x79ed1eb7);
2005 odm_write_4byte(dm, 0x1b80, 0x7b831ec5);
2006 odm_write_4byte(dm, 0x1b80, 0x7b831ec7);
2007 odm_write_4byte(dm, 0x1b80, 0x7b031ed5);
2008 odm_write_4byte(dm, 0x1b80, 0x7b031ed7);
2009 odm_write_4byte(dm, 0x1b80, 0x780f1ee5);
2010 odm_write_4byte(dm, 0x1b80, 0x780f1ee7);
2011 odm_write_4byte(dm, 0x1b80, 0x79b41ef5);
2012 odm_write_4byte(dm, 0x1b80, 0x79b41ef7);
2013 odm_write_4byte(dm, 0x1b80, 0x7a001f05);
2014 odm_write_4byte(dm, 0x1b80, 0x7a001f07);
2015 odm_write_4byte(dm, 0x1b80, 0x7b001f15);
2016 odm_write_4byte(dm, 0x1b80, 0x7b001f17);
2017 odm_write_4byte(dm, 0x1b80, 0x00011f25);
2018 odm_write_4byte(dm, 0x1b80, 0x00011f27);
2019 odm_write_4byte(dm, 0x1b80, 0x00071f35);
2020 odm_write_4byte(dm, 0x1b80, 0x00071f37);
2021 odm_write_4byte(dm, 0x1b80, 0x78ae1f45);
2022 odm_write_4byte(dm, 0x1b80, 0x78ae1f47);
2023 odm_write_4byte(dm, 0x1b80, 0x79fa1f55);
2024 odm_write_4byte(dm, 0x1b80, 0x79fa1f57);
2025 odm_write_4byte(dm, 0x1b80, 0x7a011f65);
2026 odm_write_4byte(dm, 0x1b80, 0x7a011f67);
2027 odm_write_4byte(dm, 0x1b80, 0x7b801f75);
2028 odm_write_4byte(dm, 0x1b80, 0x7b801f77);
2029 odm_write_4byte(dm, 0x1b80, 0x7b001f85);
2030 odm_write_4byte(dm, 0x1b80, 0x7b001f87);
2031 odm_write_4byte(dm, 0x1b80, 0x787a1f95);
2032 odm_write_4byte(dm, 0x1b80, 0x787a1f97);
2033 odm_write_4byte(dm, 0x1b80, 0x79f11fa5);
2034 odm_write_4byte(dm, 0x1b80, 0x79f11fa7);
2035 odm_write_4byte(dm, 0x1b80, 0x7b811fb5);
2036 odm_write_4byte(dm, 0x1b80, 0x7b811fb7);
2037 odm_write_4byte(dm, 0x1b80, 0x7b011fc5);
2038 odm_write_4byte(dm, 0x1b80, 0x7b011fc7);
2039 odm_write_4byte(dm, 0x1b80, 0x780f1fd5);
2040 odm_write_4byte(dm, 0x1b80, 0x780f1fd7);
2041 odm_write_4byte(dm, 0x1b80, 0x79b41fe5);
2042 odm_write_4byte(dm, 0x1b80, 0x79b41fe7);
2043 odm_write_4byte(dm, 0x1b80, 0x7a001ff5);
2044 odm_write_4byte(dm, 0x1b80, 0x7a001ff7);
2045 odm_write_4byte(dm, 0x1b80, 0x7b002005);
2046 odm_write_4byte(dm, 0x1b80, 0x7b002007);
2047 odm_write_4byte(dm, 0x1b80, 0x00012015);
2048 odm_write_4byte(dm, 0x1b80, 0x00012017);
2049 odm_write_4byte(dm, 0x1b80, 0x77102025);
2050 odm_write_4byte(dm, 0x1b80, 0x77102027);
2051 odm_write_4byte(dm, 0x1b80, 0x00062035);
2052 odm_write_4byte(dm, 0x1b80, 0x00062037);
2053 odm_write_4byte(dm, 0x1b80, 0x74002045);
2054 odm_write_4byte(dm, 0x1b80, 0x74002047);
2055 odm_write_4byte(dm, 0x1b80, 0x76002055);
2056 odm_write_4byte(dm, 0x1b80, 0x76002057);
2057 odm_write_4byte(dm, 0x1b80, 0x77002065);
2058 odm_write_4byte(dm, 0x1b80, 0x77002067);
2059 odm_write_4byte(dm, 0x1b80, 0x75102075);
2060 odm_write_4byte(dm, 0x1b80, 0x75102077);
2061 odm_write_4byte(dm, 0x1b80, 0x75002085);
2062 odm_write_4byte(dm, 0x1b80, 0x75002087);
2063 odm_write_4byte(dm, 0x1b80, 0xb3002095);
2064 odm_write_4byte(dm, 0x1b80, 0xb3002097);
2065 odm_write_4byte(dm, 0x1b80, 0x930020a5);
2066 odm_write_4byte(dm, 0x1b80, 0x930020a7);
2067 odm_write_4byte(dm, 0x1b80, 0x000120b5);
2068 odm_write_4byte(dm, 0x1b80, 0x000120b7);
2069 odm_write_4byte(dm, 0x1b80, 0x772020c5);
2070 odm_write_4byte(dm, 0x1b80, 0x772020c7);
2071 odm_write_4byte(dm, 0x1b80, 0x000620d5);
2072 odm_write_4byte(dm, 0x1b80, 0x000620d7);
2073 odm_write_4byte(dm, 0x1b80, 0x740020e5);
2074 odm_write_4byte(dm, 0x1b80, 0x740020e7);
2075 odm_write_4byte(dm, 0x1b80, 0x760020f5);
2076 odm_write_4byte(dm, 0x1b80, 0x760020f7);
2077 odm_write_4byte(dm, 0x1b80, 0x77012105);
2078 odm_write_4byte(dm, 0x1b80, 0x77012107);
2079 odm_write_4byte(dm, 0x1b80, 0x75102115);
2080 odm_write_4byte(dm, 0x1b80, 0x75102117);
2081 odm_write_4byte(dm, 0x1b80, 0x75002125);
2082 odm_write_4byte(dm, 0x1b80, 0x75002127);
2083 odm_write_4byte(dm, 0x1b80, 0xb3002135);
2084 odm_write_4byte(dm, 0x1b80, 0xb3002137);
2085 odm_write_4byte(dm, 0x1b80, 0x93002145);
2086 odm_write_4byte(dm, 0x1b80, 0x93002147);
2087 odm_write_4byte(dm, 0x1b80, 0x00012155);
2088 odm_write_4byte(dm, 0x1b80, 0x00012157);
2089 odm_write_4byte(dm, 0x1b80, 0x00042165);
2090 odm_write_4byte(dm, 0x1b80, 0x00042167);
2091 odm_write_4byte(dm, 0x1b80, 0x44802175);
2092 odm_write_4byte(dm, 0x1b80, 0x44802177);
2093 odm_write_4byte(dm, 0x1b80, 0x47302185);
2094 odm_write_4byte(dm, 0x1b80, 0x47302187);
2095 odm_write_4byte(dm, 0x1b80, 0x00062195);
2096 odm_write_4byte(dm, 0x1b80, 0x00062197);
2097 odm_write_4byte(dm, 0x1b80, 0x776c21a5);
2098 odm_write_4byte(dm, 0x1b80, 0x776c21a7);
2099 odm_write_4byte(dm, 0x1b80, 0x000121b5);
2100 odm_write_4byte(dm, 0x1b80, 0x000121b7);
2101 odm_write_4byte(dm, 0x1b80, 0x000521c5);
2102 odm_write_4byte(dm, 0x1b80, 0x000521c7);
2103 odm_write_4byte(dm, 0x1b80, 0x5c8021d5);
2104 odm_write_4byte(dm, 0x1b80, 0x5c8021d7);
2105 odm_write_4byte(dm, 0x1b80, 0x5f3021e5);
2106 odm_write_4byte(dm, 0x1b80, 0x5f3021e7);
2107 odm_write_4byte(dm, 0x1b80, 0x000621f5);
2108 odm_write_4byte(dm, 0x1b80, 0x000621f7);
2109 odm_write_4byte(dm, 0x1b80, 0x776d2205);
2110 odm_write_4byte(dm, 0x1b80, 0x776d2207);
2111 odm_write_4byte(dm, 0x1b80, 0x00012215);
2112 odm_write_4byte(dm, 0x1b80, 0x00012217);
2113 odm_write_4byte(dm, 0x1b80, 0xb9002225);
2114 odm_write_4byte(dm, 0x1b80, 0xb9002227);
2115 odm_write_4byte(dm, 0x1b80, 0x99002235);
2116 odm_write_4byte(dm, 0x1b80, 0x99002237);
2117 odm_write_4byte(dm, 0x1b80, 0x77202245);
2118 odm_write_4byte(dm, 0x1b80, 0x77202247);
2119 odm_write_4byte(dm, 0x1b80, 0x00042255);
2120 odm_write_4byte(dm, 0x1b80, 0x00042257);
2121 odm_write_4byte(dm, 0x1b80, 0x40082265);
2122 odm_write_4byte(dm, 0x1b80, 0x40082267);
2123 odm_write_4byte(dm, 0x1b80, 0x98032275);
2124 odm_write_4byte(dm, 0x1b80, 0x98032277);
2125 odm_write_4byte(dm, 0x1b80, 0x4a022285);
2126 odm_write_4byte(dm, 0x1b80, 0x4a022287);
2127 odm_write_4byte(dm, 0x1b80, 0x30192295);
2128 odm_write_4byte(dm, 0x1b80, 0x30192297);
2129 odm_write_4byte(dm, 0x1b80, 0x000122a5);
2130 odm_write_4byte(dm, 0x1b80, 0x000122a7);
2131 odm_write_4byte(dm, 0x1b80, 0x7b4822b5);
2132 odm_write_4byte(dm, 0x1b80, 0x7b4822b7);
2133 odm_write_4byte(dm, 0x1b80, 0x7a9022c5);
2134 odm_write_4byte(dm, 0x1b80, 0x7a9022c7);
2135 odm_write_4byte(dm, 0x1b80, 0x790022d5);
2136 odm_write_4byte(dm, 0x1b80, 0x790022d7);
2137 odm_write_4byte(dm, 0x1b80, 0x550322e5);
2138 odm_write_4byte(dm, 0x1b80, 0x550322e7);
2139 odm_write_4byte(dm, 0x1b80, 0x323722f5);
2140 odm_write_4byte(dm, 0x1b80, 0x323722f7);
2141 odm_write_4byte(dm, 0x1b80, 0x7b382305);
2142 odm_write_4byte(dm, 0x1b80, 0x7b382307);
2143 odm_write_4byte(dm, 0x1b80, 0x7a802315);
2144 odm_write_4byte(dm, 0x1b80, 0x7a802317);
2145 odm_write_4byte(dm, 0x1b80, 0x550b2325);
2146 odm_write_4byte(dm, 0x1b80, 0x550b2327);
2147 odm_write_4byte(dm, 0x1b80, 0x32372335);
2148 odm_write_4byte(dm, 0x1b80, 0x32372337);
2149 odm_write_4byte(dm, 0x1b80, 0x7b402345);
2150 odm_write_4byte(dm, 0x1b80, 0x7b402347);
2151 odm_write_4byte(dm, 0x1b80, 0x7a002355);
2152 odm_write_4byte(dm, 0x1b80, 0x7a002357);
2153 odm_write_4byte(dm, 0x1b80, 0x55132365);
2154 odm_write_4byte(dm, 0x1b80, 0x55132367);
2155 odm_write_4byte(dm, 0x1b80, 0x74012375);
2156 odm_write_4byte(dm, 0x1b80, 0x74012377);
2157 odm_write_4byte(dm, 0x1b80, 0x74002385);
2158 odm_write_4byte(dm, 0x1b80, 0x74002387);
2159 odm_write_4byte(dm, 0x1b80, 0x8e002395);
2160 odm_write_4byte(dm, 0x1b80, 0x8e002397);
2161 odm_write_4byte(dm, 0x1b80, 0x000123a5);
2162 odm_write_4byte(dm, 0x1b80, 0x000123a7);
2163 odm_write_4byte(dm, 0x1b80, 0x570223b5);
2164 odm_write_4byte(dm, 0x1b80, 0x570223b7);
2165 odm_write_4byte(dm, 0x1b80, 0x570023c5);
2166 odm_write_4byte(dm, 0x1b80, 0x570023c7);
2167 odm_write_4byte(dm, 0x1b80, 0x970023d5);
2168 odm_write_4byte(dm, 0x1b80, 0x970023d7);
2169 odm_write_4byte(dm, 0x1b80, 0x000123e5);
2170 odm_write_4byte(dm, 0x1b80, 0x000123e7);
2171 odm_write_4byte(dm, 0x1b80, 0x4f7823f5);
2172 odm_write_4byte(dm, 0x1b80, 0x4f7823f7);
2173 odm_write_4byte(dm, 0x1b80, 0x53882405);
2174 odm_write_4byte(dm, 0x1b80, 0x53882407);
2175 odm_write_4byte(dm, 0x1b80, 0xe24b2415);
2176 odm_write_4byte(dm, 0x1b80, 0xe24b2417);
2177 odm_write_4byte(dm, 0x1b80, 0x54802425);
2178 odm_write_4byte(dm, 0x1b80, 0x54802427);
2179 odm_write_4byte(dm, 0x1b80, 0x54002435);
2180 odm_write_4byte(dm, 0x1b80, 0x54002437);
2181 odm_write_4byte(dm, 0x1b80, 0x54812445);
2182 odm_write_4byte(dm, 0x1b80, 0x54812447);
2183 odm_write_4byte(dm, 0x1b80, 0x54002455);
2184 odm_write_4byte(dm, 0x1b80, 0x54002457);
2185 odm_write_4byte(dm, 0x1b80, 0x54822465);
2186 odm_write_4byte(dm, 0x1b80, 0x54822467);
2187 odm_write_4byte(dm, 0x1b80, 0x54002475);
2188 odm_write_4byte(dm, 0x1b80, 0x54002477);
2189 odm_write_4byte(dm, 0x1b80, 0xe2562485);
2190 odm_write_4byte(dm, 0x1b80, 0xe2562487);
2191 odm_write_4byte(dm, 0x1b80, 0xbf1d2495);
2192 odm_write_4byte(dm, 0x1b80, 0xbf1d2497);
2193 odm_write_4byte(dm, 0x1b80, 0x301924a5);
2194 odm_write_4byte(dm, 0x1b80, 0x301924a7);
2195 odm_write_4byte(dm, 0x1b80, 0xe22b24b5);
2196 odm_write_4byte(dm, 0x1b80, 0xe22b24b7);
2197 odm_write_4byte(dm, 0x1b80, 0xe23024c5);
2198 odm_write_4byte(dm, 0x1b80, 0xe23024c7);
2199 odm_write_4byte(dm, 0x1b80, 0xe23424d5);
2200 odm_write_4byte(dm, 0x1b80, 0xe23424d7);
2201 odm_write_4byte(dm, 0x1b80, 0xe23b24e5);
2202 odm_write_4byte(dm, 0x1b80, 0xe23b24e7);
2203 odm_write_4byte(dm, 0x1b80, 0xe29524f5);
2204 odm_write_4byte(dm, 0x1b80, 0xe29524f7);
2205 odm_write_4byte(dm, 0x1b80, 0x55132505);
2206 odm_write_4byte(dm, 0x1b80, 0x55132507);
2207 odm_write_4byte(dm, 0x1b80, 0xe2372515);
2208 odm_write_4byte(dm, 0x1b80, 0xe2372517);
2209 odm_write_4byte(dm, 0x1b80, 0x55152525);
2210 odm_write_4byte(dm, 0x1b80, 0x55152527);
2211 odm_write_4byte(dm, 0x1b80, 0xe23b2535);
2212 odm_write_4byte(dm, 0x1b80, 0xe23b2537);
2213 odm_write_4byte(dm, 0x1b80, 0xe2952545);
2214 odm_write_4byte(dm, 0x1b80, 0xe2952547);
2215 odm_write_4byte(dm, 0x1b80, 0x00012555);
2216 odm_write_4byte(dm, 0x1b80, 0x00012557);
2217 odm_write_4byte(dm, 0x1b80, 0x54bf2565);
2218 odm_write_4byte(dm, 0x1b80, 0x54bf2567);
2219 odm_write_4byte(dm, 0x1b80, 0x54c02575);
2220 odm_write_4byte(dm, 0x1b80, 0x54c02577);
2221 odm_write_4byte(dm, 0x1b80, 0x54a32585);
2222 odm_write_4byte(dm, 0x1b80, 0x54a32587);
2223 odm_write_4byte(dm, 0x1b80, 0x54c12595);
2224 odm_write_4byte(dm, 0x1b80, 0x54c12597);
2225 odm_write_4byte(dm, 0x1b80, 0x54a425a5);
2226 odm_write_4byte(dm, 0x1b80, 0x54a425a7);
2227 odm_write_4byte(dm, 0x1b80, 0x4c1825b5);
2228 odm_write_4byte(dm, 0x1b80, 0x4c1825b7);
2229 odm_write_4byte(dm, 0x1b80, 0xbf0725c5);
2230 odm_write_4byte(dm, 0x1b80, 0xbf0725c7);
2231 odm_write_4byte(dm, 0x1b80, 0x54c225d5);
2232 odm_write_4byte(dm, 0x1b80, 0x54c225d7);
2233 odm_write_4byte(dm, 0x1b80, 0x54a425e5);
2234 odm_write_4byte(dm, 0x1b80, 0x54a425e7);
2235 odm_write_4byte(dm, 0x1b80, 0xbf0425f5);
2236 odm_write_4byte(dm, 0x1b80, 0xbf0425f7);
2237 odm_write_4byte(dm, 0x1b80, 0x54c12605);
2238 odm_write_4byte(dm, 0x1b80, 0x54c12607);
2239 odm_write_4byte(dm, 0x1b80, 0x54a32615);
2240 odm_write_4byte(dm, 0x1b80, 0x54a32617);
2241 odm_write_4byte(dm, 0x1b80, 0xbf012625);
2242 odm_write_4byte(dm, 0x1b80, 0xbf012627);
2243 odm_write_4byte(dm, 0x1b80, 0xe2a32635);
2244 odm_write_4byte(dm, 0x1b80, 0xe2a32637);
2245 odm_write_4byte(dm, 0x1b80, 0x54df2645);
2246 odm_write_4byte(dm, 0x1b80, 0x54df2647);
2247 odm_write_4byte(dm, 0x1b80, 0x00012655);
2248 odm_write_4byte(dm, 0x1b80, 0x00012657);
2249 odm_write_4byte(dm, 0x1b80, 0x54bf2665);
2250 odm_write_4byte(dm, 0x1b80, 0x54bf2667);
2251 odm_write_4byte(dm, 0x1b80, 0x54e52675);
2252 odm_write_4byte(dm, 0x1b80, 0x54e52677);
2253 odm_write_4byte(dm, 0x1b80, 0x050a2685);
2254 odm_write_4byte(dm, 0x1b80, 0x050a2687);
2255 odm_write_4byte(dm, 0x1b80, 0x54df2695);
2256 odm_write_4byte(dm, 0x1b80, 0x54df2697);
2257 odm_write_4byte(dm, 0x1b80, 0x000126a5);
2258 odm_write_4byte(dm, 0x1b80, 0x000126a7);
2259 odm_write_4byte(dm, 0x1b80, 0x7f4026b5);
2260 odm_write_4byte(dm, 0x1b80, 0x7f4026b7);
2261 odm_write_4byte(dm, 0x1b80, 0x7e0026c5);
2262 odm_write_4byte(dm, 0x1b80, 0x7e0026c7);
2263 odm_write_4byte(dm, 0x1b80, 0x7d0026d5);
2264 odm_write_4byte(dm, 0x1b80, 0x7d0026d7);
2265 odm_write_4byte(dm, 0x1b80, 0x550126e5);
2266 odm_write_4byte(dm, 0x1b80, 0x550126e7);
2267 odm_write_4byte(dm, 0x1b80, 0x5c3126f5);
2268 odm_write_4byte(dm, 0x1b80, 0x5c3126f7);
2269 odm_write_4byte(dm, 0x1b80, 0xe2372705);
2270 odm_write_4byte(dm, 0x1b80, 0xe2372707);
2271 odm_write_4byte(dm, 0x1b80, 0xe23b2715);
2272 odm_write_4byte(dm, 0x1b80, 0xe23b2717);
2273 odm_write_4byte(dm, 0x1b80, 0x54802725);
2274 odm_write_4byte(dm, 0x1b80, 0x54802727);
2275 odm_write_4byte(dm, 0x1b80, 0x54002735);
2276 odm_write_4byte(dm, 0x1b80, 0x54002737);
2277 odm_write_4byte(dm, 0x1b80, 0x54812745);
2278 odm_write_4byte(dm, 0x1b80, 0x54812747);
2279 odm_write_4byte(dm, 0x1b80, 0x54002755);
2280 odm_write_4byte(dm, 0x1b80, 0x54002757);
2281 odm_write_4byte(dm, 0x1b80, 0x54822765);
2282 odm_write_4byte(dm, 0x1b80, 0x54822767);
2283 odm_write_4byte(dm, 0x1b80, 0x54002775);
2284 odm_write_4byte(dm, 0x1b80, 0x54002777);
2285 odm_write_4byte(dm, 0x1b80, 0xe2562785);
2286 odm_write_4byte(dm, 0x1b80, 0xe2562787);
2287 odm_write_4byte(dm, 0x1b80, 0xbfed2795);
2288 odm_write_4byte(dm, 0x1b80, 0xbfed2797);
2289 odm_write_4byte(dm, 0x1b80, 0x301927a5);
2290 odm_write_4byte(dm, 0x1b80, 0x301927a7);
2291 odm_write_4byte(dm, 0x1b80, 0x740227b5);
2292 odm_write_4byte(dm, 0x1b80, 0x740227b7);
2293 odm_write_4byte(dm, 0x1b80, 0x003f27c5);
2294 odm_write_4byte(dm, 0x1b80, 0x003f27c7);
2295 odm_write_4byte(dm, 0x1b80, 0x740027d5);
2296 odm_write_4byte(dm, 0x1b80, 0x740027d7);
2297 odm_write_4byte(dm, 0x1b80, 0x000227e5);
2298 odm_write_4byte(dm, 0x1b80, 0x000227e7);
2299 odm_write_4byte(dm, 0x1b80, 0x000127f5);
2300 odm_write_4byte(dm, 0x1b80, 0x000127f7);
2301 odm_write_4byte(dm, 0x1b80, 0x00062805);
2302 odm_write_4byte(dm, 0x1b80, 0x00062807);
2303 odm_write_4byte(dm, 0x1b80, 0x5a802815);
2304 odm_write_4byte(dm, 0x1b80, 0x5a802817);
2305 odm_write_4byte(dm, 0x1b80, 0x5a002825);
2306 odm_write_4byte(dm, 0x1b80, 0x5a002827);
2307 odm_write_4byte(dm, 0x1b80, 0x92002835);
2308 odm_write_4byte(dm, 0x1b80, 0x92002837);
2309 odm_write_4byte(dm, 0x1b80, 0x00012845);
2310 odm_write_4byte(dm, 0x1b80, 0x00012847);
2311 odm_write_4byte(dm, 0x1b80, 0x5b8f2855);
2312 odm_write_4byte(dm, 0x1b80, 0x5b8f2857);
2313 odm_write_4byte(dm, 0x1b80, 0x5b0f2865);
2314 odm_write_4byte(dm, 0x1b80, 0x5b0f2867);
2315 odm_write_4byte(dm, 0x1b80, 0x91002875);
2316 odm_write_4byte(dm, 0x1b80, 0x91002877);
2317 odm_write_4byte(dm, 0x1b80, 0x00012885);
2318 odm_write_4byte(dm, 0x1b80, 0x00012887);
2319 odm_write_4byte(dm, 0x1b80, 0x00062895);
2320 odm_write_4byte(dm, 0x1b80, 0x00062897);
2321 odm_write_4byte(dm, 0x1b80, 0x5d8028a5);
2322 odm_write_4byte(dm, 0x1b80, 0x5d8028a7);
2323 odm_write_4byte(dm, 0x1b80, 0x5e5628b5);
2324 odm_write_4byte(dm, 0x1b80, 0x5e5628b7);
2325 odm_write_4byte(dm, 0x1b80, 0x000428c5);
2326 odm_write_4byte(dm, 0x1b80, 0x000428c7);
2327 odm_write_4byte(dm, 0x1b80, 0x4d0828d5);
2328 odm_write_4byte(dm, 0x1b80, 0x4d0828d7);
2329 odm_write_4byte(dm, 0x1b80, 0x571028e5);
2330 odm_write_4byte(dm, 0x1b80, 0x571028e7);
2331 odm_write_4byte(dm, 0x1b80, 0x570028f5);
2332 odm_write_4byte(dm, 0x1b80, 0x570028f7);
2333 odm_write_4byte(dm, 0x1b80, 0x4d002905);
2334 odm_write_4byte(dm, 0x1b80, 0x4d002907);
2335 odm_write_4byte(dm, 0x1b80, 0x00062915);
2336 odm_write_4byte(dm, 0x1b80, 0x00062917);
2337 odm_write_4byte(dm, 0x1b80, 0x5d002925);
2338 odm_write_4byte(dm, 0x1b80, 0x5d002927);
2339 odm_write_4byte(dm, 0x1b80, 0x00042935);
2340 odm_write_4byte(dm, 0x1b80, 0x00042937);
2341 odm_write_4byte(dm, 0x1b80, 0x00012945);
2342 odm_write_4byte(dm, 0x1b80, 0x00012947);
2343 odm_write_4byte(dm, 0x1b80, 0x549f2955);
2344 odm_write_4byte(dm, 0x1b80, 0x549f2957);
2345 odm_write_4byte(dm, 0x1b80, 0x54ff2965);
2346 odm_write_4byte(dm, 0x1b80, 0x54ff2967);
2347 odm_write_4byte(dm, 0x1b80, 0x54002975);
2348 odm_write_4byte(dm, 0x1b80, 0x54002977);
2349 odm_write_4byte(dm, 0x1b80, 0x00012985);
2350 odm_write_4byte(dm, 0x1b80, 0x00012987);
2351 odm_write_4byte(dm, 0x1b80, 0x5c312995);
2352 odm_write_4byte(dm, 0x1b80, 0x5c312997);
2353 odm_write_4byte(dm, 0x1b80, 0x071429a5);
2354 odm_write_4byte(dm, 0x1b80, 0x071429a7);
2355 odm_write_4byte(dm, 0x1b80, 0x540029b5);
2356 odm_write_4byte(dm, 0x1b80, 0x540029b7);
2357 odm_write_4byte(dm, 0x1b80, 0x5c3229c5);
2358 odm_write_4byte(dm, 0x1b80, 0x5c3229c7);
2359 odm_write_4byte(dm, 0x1b80, 0x000129d5);
2360 odm_write_4byte(dm, 0x1b80, 0x000129d7);
2361 odm_write_4byte(dm, 0x1b80, 0x5c3229e5);
2362 odm_write_4byte(dm, 0x1b80, 0x5c3229e7);
2363 odm_write_4byte(dm, 0x1b80, 0x071429f5);
2364 odm_write_4byte(dm, 0x1b80, 0x071429f7);
2365 odm_write_4byte(dm, 0x1b80, 0x54002a05);
2366 odm_write_4byte(dm, 0x1b80, 0x54002a07);
2367 odm_write_4byte(dm, 0x1b80, 0x5c312a15);
2368 odm_write_4byte(dm, 0x1b80, 0x5c312a17);
2369 odm_write_4byte(dm, 0x1b80, 0x00012a25);
2370 odm_write_4byte(dm, 0x1b80, 0x00012a27);
2371 odm_write_4byte(dm, 0x1b80, 0x4c982a35);
2372 odm_write_4byte(dm, 0x1b80, 0x4c982a37);
2373 odm_write_4byte(dm, 0x1b80, 0x4c182a45);
2374 odm_write_4byte(dm, 0x1b80, 0x4c182a47);
2375 odm_write_4byte(dm, 0x1b80, 0x00012a55);
2376 odm_write_4byte(dm, 0x1b80, 0x00012a57);
2377 odm_write_4byte(dm, 0x1b80, 0x5c322a65);
2378 odm_write_4byte(dm, 0x1b80, 0x5c322a67);
2379 odm_write_4byte(dm, 0x1b80, 0x62042a75);
2380 odm_write_4byte(dm, 0x1b80, 0x62042a77);
2381 odm_write_4byte(dm, 0x1b80, 0x63032a85);
2382 odm_write_4byte(dm, 0x1b80, 0x63032a87);
2383 odm_write_4byte(dm, 0x1b80, 0x66072a95);
2384 odm_write_4byte(dm, 0x1b80, 0x66072a97);
2385 odm_write_4byte(dm, 0x1b80, 0x7b402aa5);
2386 odm_write_4byte(dm, 0x1b80, 0x7b402aa7);
2387 odm_write_4byte(dm, 0x1b80, 0x7a002ab5);
2388 odm_write_4byte(dm, 0x1b80, 0x7a002ab7);
2389 odm_write_4byte(dm, 0x1b80, 0x79002ac5);
2390 odm_write_4byte(dm, 0x1b80, 0x79002ac7);
2391 odm_write_4byte(dm, 0x1b80, 0x7f402ad5);
2392 odm_write_4byte(dm, 0x1b80, 0x7f402ad7);
2393 odm_write_4byte(dm, 0x1b80, 0x7e002ae5);
2394 odm_write_4byte(dm, 0x1b80, 0x7e002ae7);
2395 odm_write_4byte(dm, 0x1b80, 0x7d002af5);
2396 odm_write_4byte(dm, 0x1b80, 0x7d002af7);
2397 odm_write_4byte(dm, 0x1b80, 0x09012b05);
2398 odm_write_4byte(dm, 0x1b80, 0x09012b07);
2399 odm_write_4byte(dm, 0x1b80, 0x0c012b15);
2400 odm_write_4byte(dm, 0x1b80, 0x0c012b17);
2401 odm_write_4byte(dm, 0x1b80, 0x0ba62b25);
2402 odm_write_4byte(dm, 0x1b80, 0x0ba62b27);
2403 odm_write_4byte(dm, 0x1b80, 0x00012b35);
2404 odm_write_4byte(dm, 0x1b80, 0x00012b37);
2405 odm_write_4byte(dm, 0x1b80, 0x00000006);
2406 odm_write_4byte(dm, 0x1b80, 0x00000002);
2407
2408 }
2409
2410
_iqk_cal_path_off_8822c(struct dm_struct * dm)2411 void _iqk_cal_path_off_8822c(struct dm_struct *dm)
2412 {
2413 u8 path;
2414
2415 odm_set_bb_reg(dm, 0x1bb8, BIT(20), 0x0);
2416 for(path = 0; path < SS_8822C; path++) {
2417 //odm_set_rf_reg(dm, (enum rf_path)path, 0x0, 0xfffff, 0x10000);
2418 //odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x8 | path << 1);
2419 odm_set_bb_reg(dm, R_0x1b00, BIT(2)| BIT(1), path);
2420 odm_set_bb_reg(dm, 0x1bcc, 0x3f, 0x3f);
2421 }
2422 }
2423
_iqk_con_tx_8822c(struct dm_struct * dm,boolean is_contx)2424 void _iqk_con_tx_8822c(
2425 struct dm_struct *dm,
2426 boolean is_contx)
2427 {
2428 if (is_contx) {
2429 odm_set_bb_reg(dm, 0x180c, 0x3, 0x0);
2430 odm_set_bb_reg(dm, 0x410c, 0x3, 0x0);
2431 //odm_set_bb_reg(dm, 0x520c, 0x3, 0x0);
2432 //odm_set_bb_reg(dm, 0x530c, 0x3, 0x0);
2433 odm_set_bb_reg(dm, 0x1d08, BIT(0), 0x1);
2434 odm_set_bb_reg(dm, 0x1ca4, BIT(0), 0x1);
2435 odm_set_bb_reg(dm, 0x1e70, BIT(1), 0x1);
2436 odm_set_bb_reg(dm, 0x1e70, BIT(1), 0x0);
2437 odm_set_bb_reg(dm, 0x1e70, BIT(2), 0x0);
2438 odm_set_bb_reg(dm, 0x1e70, BIT(2), 0x1);
2439 } else {
2440 odm_set_bb_reg(dm, 0x1d08, BIT(0), 0x0);
2441 odm_set_bb_reg(dm, 0x1ca4, BIT(0), 0x0);
2442 }
2443 }
2444
_iqk_rf_set_check_8822c(struct dm_struct * dm,u8 path,u16 add,u32 data)2445 void _iqk_rf_set_check_8822c(
2446 struct dm_struct *dm,
2447 u8 path,
2448 u16 add,
2449 u32 data)
2450 {
2451 u32 i;
2452
2453 odm_set_rf_reg(dm, (enum rf_path)path, add, RFREGOFFSETMASK, data);
2454
2455 for (i = 0; i < 100; i++) {
2456 if (odm_get_rf_reg(dm, (enum rf_path)path, add, RFREGOFFSETMASK) == data)
2457 break;
2458 else {
2459 ODM_delay_us(10);
2460 odm_set_rf_reg(dm, (enum rf_path)path, add, RFREGOFFSETMASK, data);
2461 }
2462 }
2463 }
2464
_iqk_rf0xb0_workaround_8822c(struct dm_struct * dm)2465 void _iqk_rf0xb0_workaround_8822c(
2466 struct dm_struct *dm)
2467 {
2468 /*add 0xb8 control for the bad phase noise after switching channel*/
2469 odm_set_rf_reg(dm, (enum rf_path)0x0, RF_0xb8, RFREGOFFSETMASK, 0x00a00);
2470 odm_set_rf_reg(dm, (enum rf_path)0x0, RF_0xb8, RFREGOFFSETMASK, 0x80a00);
2471 }
2472
_iqk_fill_iqk_report_8822c(void * dm_void,u8 ch)2473 void _iqk_fill_iqk_report_8822c(
2474 void *dm_void,
2475 u8 ch)
2476 {
2477 struct dm_struct *dm = (struct dm_struct *)dm_void;
2478 struct dm_iqk_info *iqk = &dm->IQK_info;
2479 u32 tmp1 = 0x0, tmp2 = 0x0, tmp3 = 0x0, data;
2480 u8 i;
2481
2482 for (i = 0; i < SS_8822C; i++) {
2483 tmp1 += ((iqk->iqk_fail_report[ch][i][TX_IQK] & 1) << i);
2484 tmp2 += ((iqk->iqk_fail_report[ch][i][RX_IQK] & 1) << (i + 4));
2485 tmp3 += ((iqk->rxiqk_fail_code[ch][i] & 0x3) << (i * 2 + 8));
2486 data = iqk->rxiqk_agc[ch][i];
2487
2488 odm_write_4byte(dm, R_0x1b00, IQK_CMD_8822C | i << 1 );
2489 odm_set_bb_reg(dm, R_0x1bf0, 0x0000ffff, tmp1 | tmp2 | tmp3);
2490 odm_write_4byte(dm, R_0x1be8, data);
2491 RF_DBG(dm, DBG_RF_IQK, "[IQK]S%d 0x1bf0 =0x%x,0x1be8=0x%x\n", i,
2492 odm_read_4byte(dm, 0x1bf0), odm_read_4byte(dm, 0x1be8));
2493 }
2494
2495
2496 }
2497
_iqk_fail_count_8822c(void * dm_void)2498 void _iqk_fail_count_8822c(
2499 void *dm_void)
2500 {
2501 struct dm_struct *dm = (struct dm_struct *)dm_void;
2502 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2503 u8 i;
2504
2505 dm->n_iqk_cnt++;
2506 if (odm_get_rf_reg(dm, RF_PATH_A, RF_0x1bf0, BIT(16)) == 1)
2507 iqk_info->is_reload = true;
2508 else
2509 iqk_info->is_reload = false;
2510
2511 if (!iqk_info->is_reload) {
2512 for (i = 0; i < 8; i++) {
2513 if (odm_get_bb_reg(dm, R_0x1bf0, BIT(i)) == 1)
2514 dm->n_iqk_fail_cnt++;
2515 }
2516 }
2517 RF_DBG(dm, DBG_RF_IQK, "[IQK]All/Fail = %d %d\n", dm->n_iqk_cnt, dm->n_iqk_fail_cnt);
2518 }
2519
_iqk_iqk_fail_report_8822c(struct dm_struct * dm)2520 void _iqk_iqk_fail_report_8822c(
2521 struct dm_struct *dm)
2522 {
2523 u32 tmp1bf0 = 0x0;
2524 u8 i;
2525
2526 tmp1bf0 = odm_read_4byte(dm, 0x1bf0);
2527
2528 for (i = 0; i < 4; i++) {
2529 if (tmp1bf0 & (0x1 << i))
2530 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2531 RF_DBG(dm, DBG_RF_IQK, "[IQK] please check S%d TXIQK\n", i);
2532 #else
2533 panic_printk("[IQK] please check S%d TXIQK\n", i);
2534 #endif
2535 if (tmp1bf0 & (0x1 << (i + 12)))
2536 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2537 RF_DBG(dm, DBG_RF_IQK, "[IQK] please check S%d RXIQK\n", i);
2538 #else
2539 panic_printk("[IQK] please check S%d RXIQK\n", i);
2540 #endif
2541 }
2542 }
2543
_iqk_backup_mac_bb_8822c(struct dm_struct * dm,u32 * MAC_backup,u32 * BB_backup,u32 * backup_mac_reg,u32 * backup_bb_reg)2544 void _iqk_backup_mac_bb_8822c(
2545 struct dm_struct *dm,
2546 u32 *MAC_backup,
2547 u32 *BB_backup,
2548 u32 *backup_mac_reg,
2549 u32 *backup_bb_reg)
2550 {
2551 u32 i;
2552 for (i = 0; i < MAC_REG_NUM_8822C; i++){
2553 MAC_backup[i] = odm_read_4byte(dm, backup_mac_reg[i]);
2554 //RF_DBG(dm, DBG_RF_IQK, "[IQK]Backup mac addr = %x, value =% x\n", backup_mac_reg[i], MAC_backup[i]);
2555 }
2556 for (i = 0; i < BB_REG_NUM_8822C; i++){
2557 BB_backup[i] = odm_read_4byte(dm, backup_bb_reg[i]);
2558 //RF_DBG(dm, DBG_RF_IQK, "[IQK]Backup bbaddr = %x, value =% x\n", backup_bb_reg[i], BB_backup[i]);
2559 }
2560 RF_DBG(dm, DBG_RF_IQK, "[IQK]BackupMacBB Success!!!!\n");
2561 }
2562
_iqk_backup_rf_8822c(struct dm_struct * dm,u32 RF_backup[][SS_8822C],u32 * backup_rf_reg)2563 void _iqk_backup_rf_8822c(
2564 struct dm_struct *dm,
2565 u32 RF_backup[][SS_8822C],
2566 u32 *backup_rf_reg)
2567 {
2568 u32 i;
2569
2570 for (i = 0; i < RF_REG_NUM_8822C; i++) {
2571 RF_backup[i][RF_PATH_A] = odm_get_rf_reg(dm, RF_PATH_A, backup_rf_reg[i], RFREGOFFSETMASK);
2572 RF_backup[i][RF_PATH_B] = odm_get_rf_reg(dm, RF_PATH_B, backup_rf_reg[i], RFREGOFFSETMASK);
2573 //RF_backup[i][RF_PATH_C] = odm_get_rf_reg(dm, RF_PATH_C, backup_rf_reg[i], RFREGOFFSETMASK);
2574 //RF_backup[i][RF_PATH_D] = odm_get_rf_reg(dm, RF_PATH_D, backup_rf_reg[i], RFREGOFFSETMASK);
2575 }
2576 RF_DBG(dm, DBG_RF_IQK, "[IQK]BackupRF Success!!!!\n");
2577 }
2578
_iqk_agc_bnd_int_8822c(struct dm_struct * dm)2579 void _iqk_agc_bnd_int_8822c(
2580 struct dm_struct *dm)
2581 {
2582 return;
2583 #if 0
2584 /*initialize RX AGC bnd, it must do after bbreset*/
2585 odm_write_4byte(dm, 0x1b00, 0x8);
2586 odm_write_4byte(dm, 0x1b00, 0x00A70008);
2587 odm_write_4byte(dm, 0x1b00, 0x00150008);
2588 odm_write_4byte(dm, 0x1b00, 0x8);
2589 RF_DBG(dm, DBG_RF_IQK, "[IQK]init. rx agc bnd\n");
2590 #endif
2591 }
2592
_iqk_bb_reset_8822c(struct dm_struct * dm)2593 void _iqk_bb_reset_8822c(
2594 struct dm_struct *dm)
2595 {
2596 boolean cca_ing = false;
2597 u32 count = 0;
2598
2599 odm_set_rf_reg(dm, RF_PATH_A, RF_0x0, RFREGOFFSETMASK, 0x10000);
2600 odm_set_rf_reg(dm, RF_PATH_B, RF_0x0, RFREGOFFSETMASK, 0x10000);
2601 /*reset BB report*/
2602 odm_set_bb_reg(dm, R_0x8f8, 0x0ff00000, 0x0);
2603
2604 while (1) {
2605 odm_write_4byte(dm, 0x8fc, 0x0);
2606 odm_set_bb_reg(dm, R_0x198c, 0x7, 0x7);
2607 cca_ing = (boolean)odm_get_bb_reg(dm, R_0xfa0, BIT(3));
2608
2609 if (count > 30)
2610 cca_ing = false;
2611
2612 if (cca_ing) {
2613 ODM_delay_us(10);
2614 count++;
2615 } else {
2616 odm_write_1byte(dm, 0x808, 0x0); /*RX ant off*/
2617 odm_set_bb_reg(dm, R_0xa04, BIT(27) | BIT(26) | BIT(25) | BIT(24), 0x0); /*CCK RX path off*/
2618
2619 /*BBreset*/
2620 odm_set_bb_reg(dm, R_0x0, BIT(16), 0x0);
2621 odm_set_bb_reg(dm, R_0x0, BIT(16), 0x1);
2622
2623 if (odm_get_bb_reg(dm, R_0x660, BIT(16)))
2624 odm_write_4byte(dm, 0x6b4, 0x89000006);
2625 /*RF_DBG(dm, DBG_RF_IQK, "[IQK]BBreset!!!!\n");*/
2626 break;
2627 }
2628 }
2629 }
_iqk_bb_for_dpk_setting_8822c(struct dm_struct * dm)2630 void _iqk_bb_for_dpk_setting_8822c(struct dm_struct *dm)
2631 {
2632 odm_set_bb_reg(dm, R_0x1e24, BIT(17), 0x1);
2633 odm_set_bb_reg(dm, R_0x1cd0, BIT(28), 0x1);
2634 odm_set_bb_reg(dm, R_0x1cd0, BIT(29), 0x1);
2635 odm_set_bb_reg(dm, R_0x1cd0, BIT(30), 0x1);
2636 odm_set_bb_reg(dm, R_0x1cd0, BIT(31), 0x0);
2637 //odm_set_bb_reg(dm, R_0x1c68, 0x0f000000, 0xf);
2638 odm_set_bb_reg(dm, 0x1d58, 0xff8, 0x1ff);
2639 odm_set_bb_reg(dm, 0x1864, BIT(31), 0x1);
2640 odm_set_bb_reg(dm, 0x4164, BIT(31), 0x1);
2641 odm_set_bb_reg(dm, R_0x180c, BIT(27), 0x1);
2642 odm_set_bb_reg(dm, R_0x410c, BIT(27), 0x1);
2643 odm_set_bb_reg(dm, R_0x186c, BIT(7), 0x1);
2644 odm_set_bb_reg(dm, 0x416c, BIT(7), 0x1);
2645 odm_set_bb_reg(dm, R_0x180c, 0x3, 0x0); //S0 -3 wire
2646 odm_set_bb_reg(dm, R_0x410c, 0x3, 0x0); //S1 -3wire
2647 odm_set_bb_reg(dm, 0x1a00, BIT(1) | BIT(0), 0x2);
2648 RF_DBG(dm, DBG_RF_IQK, "[IQK]_iqk_bb_for_dpk_setting_8822c!!!!\n");
2649 }
2650
_iqk_rf_setting_8822c(struct dm_struct * dm)2651 void _iqk_rf_setting_8822c(struct dm_struct *dm)
2652 {
2653 odm_set_bb_reg(dm, 0x1bb8, BIT(20), 0x0);
2654 /*TxIQK mode S0,RF0x00[19:16]=0x4*/
2655 odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0xfffff, 0x80000);
2656 odm_set_rf_reg(dm, RF_PATH_A, 0x33, 0x0000f, 0x4);
2657 odm_set_rf_reg(dm, RF_PATH_A, 0x3e, 0xfffff, 0x00003);
2658 odm_set_rf_reg(dm, RF_PATH_A, 0x3f, 0xfffff, 0xF60FF);//3F[15]=0, iPA off
2659 odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0xfffff, 0x00000);
2660
2661 /*TxIQK mode S1,RF0x00[19:16]=0x4*/
2662 odm_set_rf_reg(dm, RF_PATH_B, 0xef, 0xfffff, 0x80000);
2663 odm_set_rf_reg(dm, RF_PATH_B, 0x33, 0x0000f, 0x4);
2664 odm_set_rf_reg(dm, RF_PATH_B, 0x3f, 0xfffff, 0xFD83F);//3F[15]=0, iPA off
2665 odm_set_rf_reg(dm, RF_PATH_B, 0xef, 0xfffff, 0x00000);
2666
2667 // RxIQK1 mode S0, RF0x00[19:16]=0x6
2668 odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0xfffff, 0x80000); //[19]: WE_LUT_RFMODE
2669 odm_set_rf_reg(dm, RF_PATH_A, 0x33, 0x0000f, 0x6); //RFMODE
2670 odm_set_rf_reg(dm, RF_PATH_A, 0x3e, 0xfffff, 0x00003);
2671 odm_set_rf_reg(dm, RF_PATH_A, 0x3f, 0xfffff, 0x760FF);//3F[15]=0, iPA off , 3F[19]=0, POW_TXBB off
2672 odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0xfffff, 0x00000);
2673
2674 // RxIQK1 mode S1, RF0x00[19:16]=0x6
2675 odm_set_rf_reg(dm, RF_PATH_B, 0xef, 0xfffff, 0x80000);
2676 odm_set_rf_reg(dm, RF_PATH_B, 0x33, 0x0000f, 0x6);
2677 odm_set_rf_reg(dm, RF_PATH_B, 0x3f, 0xfffff, 0xDD83F);//3F[15]=0, iPA off
2678 odm_set_rf_reg(dm, RF_PATH_B, 0xef, 0xfffff, 0x00000);
2679
2680 // RxIQK2 mode S0, RF0x00[19:16]=0x7
2681 odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0xfffff, 0x80000); //[19]: WE_LUT_RFMODE
2682 odm_set_rf_reg(dm, RF_PATH_A, 0x33, 0x0000f, 0x7); //RFMODE
2683 odm_set_rf_reg(dm, RF_PATH_A, 0x3e, 0xfffff, 0x00003);
2684 odm_set_rf_reg(dm, RF_PATH_A, 0x3f, 0xfffff, 0x7DEFF);//3F[15]=1, iPA on ,3F[19]=0, POW_TXBB off
2685 odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0xfffff, 0x00000);
2686
2687 // RxIQK2 mode S1, RF0x00[19:16]=0x7
2688 odm_set_rf_reg(dm, RF_PATH_B, 0xef, 0xfffff, 0x80000); //[19]: WE_LUT_RFMODE
2689 odm_set_rf_reg(dm, RF_PATH_B, 0x33, 0x0000f, 0x7); //RFMODE
2690 odm_set_rf_reg(dm, RF_PATH_B, 0x3f, 0xfffff, 0xDF7BF);//3F[13]=1, iPA on ,3F[17]=0, POW_TXBB off
2691 odm_set_rf_reg(dm, RF_PATH_B, 0xef, 0xfffff, 0x00000);
2692
2693 odm_set_rf_reg(dm, RF_PATH_A, RF_0x19, RFREG_MASK, 0x0);
2694 odm_set_rf_reg(dm, RF_PATH_B, RF_0x19, RFREG_MASK, 0x0);
2695
2696
2697 RF_DBG(dm, DBG_RF_IQK, "[IQK]_iqk_rf_setting_8822c RF01!!!!\n");
2698 }
2699
_iqk_set_afe_8822c(struct dm_struct * dm)2700 void _iqk_set_afe_8822c(struct dm_struct *dm)
2701 {
2702 odm_set_bb_reg(dm, 0x1830, BIT(30), 0x0);
2703 odm_set_bb_reg(dm, 0x1860, 0xfffff000, 0xf0001);
2704 odm_set_bb_reg(dm, 0x4130, BIT(30), 0x0);
2705 odm_set_bb_reg(dm, 0x4160, 0xfffff000, 0xf0001);
2706 /*ADDA FIFO reset*/
2707 odm_write_4byte(dm, 0x1c38, 0x0);
2708 ODM_delay_us(10);
2709 odm_write_4byte(dm, 0x1c38, 0xffffffff);
2710 RF_DBG(dm, DBG_RF_IQK, "[IQK]AFE setting for IQK mode!!!!\n");
2711 }
2712
2713
_iqk_afe_setting_8822c(struct dm_struct * dm,boolean do_iqk)2714 void _iqk_afe_setting_8822c(
2715 struct dm_struct *dm,
2716 boolean do_iqk)
2717 {
2718 u8 i;
2719 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2720
2721 if (do_iqk) {
2722 /*03_8822C_AFE_for_DPK.txt*/
2723 // AFE on Settings
2724 odm_write_4byte(dm, 0x1830, 0x700f0001);
2725 odm_write_4byte(dm, 0x1830, 0x700f0001);
2726 odm_write_4byte(dm, 0x1830, 0x701f0001);
2727 odm_write_4byte(dm, 0x1830, 0x702f0001);
2728 odm_write_4byte(dm, 0x1830, 0x703f0001);
2729 odm_write_4byte(dm, 0x1830, 0x704f0001);
2730 odm_write_4byte(dm, 0x1830, 0x705f0001);
2731 odm_write_4byte(dm, 0x1830, 0x706f0001);
2732 odm_write_4byte(dm, 0x1830, 0x707f0001);
2733 odm_write_4byte(dm, 0x1830, 0x708f0001);
2734 odm_write_4byte(dm, 0x1830, 0x709f0001);
2735 odm_write_4byte(dm, 0x1830, 0x70af0001);
2736 odm_write_4byte(dm, 0x1830, 0x70bf0001);
2737 odm_write_4byte(dm, 0x1830, 0x70cf0001);
2738 odm_write_4byte(dm, 0x1830, 0x70df0001);
2739 odm_write_4byte(dm, 0x1830, 0x70ef0001);
2740 odm_write_4byte(dm, 0x1830, 0x70ff0001);
2741 odm_write_4byte(dm, 0x1830, 0x70ff0001);
2742 odm_write_4byte(dm, 0x4130, 0x700f0001);
2743 odm_write_4byte(dm, 0x4130, 0x700f0001);
2744 odm_write_4byte(dm, 0x4130, 0x701f0001);
2745 odm_write_4byte(dm, 0x4130, 0x702f0001);
2746 odm_write_4byte(dm, 0x4130, 0x703f0001);
2747 odm_write_4byte(dm, 0x4130, 0x704f0001);
2748 odm_write_4byte(dm, 0x4130, 0x705f0001);
2749 odm_write_4byte(dm, 0x4130, 0x706f0001);
2750 odm_write_4byte(dm, 0x4130, 0x707f0001);
2751 odm_write_4byte(dm, 0x4130, 0x708f0001);
2752 odm_write_4byte(dm, 0x4130, 0x709f0001);
2753 odm_write_4byte(dm, 0x4130, 0x70af0001);
2754 odm_write_4byte(dm, 0x4130, 0x70bf0001);
2755 odm_write_4byte(dm, 0x4130, 0x70cf0001);
2756 odm_write_4byte(dm, 0x4130, 0x70df0001);
2757 odm_write_4byte(dm, 0x4130, 0x70ef0001);
2758 odm_write_4byte(dm, 0x4130, 0x70ff0001);
2759 odm_write_4byte(dm, 0x4130, 0x70ff0001);
2760 /*ADDA FIFO reset*/
2761 odm_write_4byte(dm, 0x1c38, 0x0);
2762 ODM_delay_us(10);
2763 odm_write_4byte(dm, 0x1c38, 0xffffffff);
2764 RF_DBG(dm, DBG_RF_IQK, "[IQK]AFE setting for IQK mode!!!!\n");
2765 } else {
2766 if (iqk_info->is_tssi_mode) {
2767 odm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xf7d5005e);
2768 odm_set_bb_reg(dm, R_0x1860, 0x00007000, 0x4 >> iqk_info->iqk_band);
2769 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x700b8041);
2770 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x701f0040 | (0x4 >> iqk_info->iqk_band));
2771 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x702f0040 | (0x4 >> iqk_info->iqk_band));
2772 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x703f0040 | (0x4 >> iqk_info->iqk_band));
2773 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x704f0040 | (0x4 >> iqk_info->iqk_band));
2774 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x705b8041);
2775 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x706f0040 | (0x4 >> iqk_info->iqk_band));
2776
2777 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x700b8041);
2778 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x701f0040 | (0x4 >> iqk_info->iqk_band));
2779 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x702f0040 | (0x4 >> iqk_info->iqk_band));
2780 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x703f0040 | (0x4 >> iqk_info->iqk_band));
2781 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x704f0040 | (0x4 >> iqk_info->iqk_band));
2782 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x705b8041);
2783 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x706f0040 | (0x4 >> iqk_info->iqk_band));
2784
2785 RF_DBG(dm, DBG_RF_IQK, "[IQK]AFE for TSSI mode\n");
2786
2787 } else {
2788 // AFE Restore Settings
2789 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x700b8041);
2790 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70144041);
2791 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70244041);
2792 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70344041);
2793 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70444041);
2794 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x705b8041);
2795 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70644041);
2796 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x707b8041);
2797 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x708b8041);
2798 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x709b8041);
2799 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70ab8041);
2800 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70bb8041);
2801 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70cb8041);
2802 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70db8041);
2803 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70eb8041);
2804 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70fb8041);
2805
2806 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x700b8041);
2807 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70144041);
2808 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70244041);
2809 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70344041);
2810 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70444041);
2811 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x705b8041);
2812 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70644041);
2813 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x707b8041);
2814 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x708b8041);
2815 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x709b8041);
2816 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70ab8041);
2817 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70bb8041);
2818 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70cb8041);
2819 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70db8041);
2820 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70eb8041);
2821 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70fb8041);
2822 RF_DBG(dm, DBG_RF_IQK, "[IQK]AFE for non-TSSI mode\n");
2823 }
2824 #if 0
2825 /*11_8822C_BB_for_DPK_restore*/
2826 odm_set_bb_reg(dm, 0x1d0c, BIT(16), 0x1);
2827 odm_set_bb_reg(dm, 0x1d0c, BIT(16), 0x0);
2828 odm_set_bb_reg(dm, 0x1d0c, BIT(16), 0x1);
2829 #endif
2830 odm_set_bb_reg(dm, 0x1bb8, BIT(20), 0x0);
2831 odm_set_bb_reg(dm, 0x1bcc, 0x000000ff, 0x0);
2832
2833 // BB Restore Settings
2834 //odm_set_bb_reg(dm, 0x1c68, 0x0f000000, 0x0);
2835 odm_set_bb_reg(dm, 0x1d58, 0xff8, 0x0);
2836 //odm_set_bb_reg(dm, 0x1c3c, BIT(0), 0x1);
2837 //odm_set_bb_reg(dm, 0x1c3c, BIT(1), 0x1);
2838 odm_set_bb_reg(dm, 0x1864, BIT(31), 0x0);
2839 odm_set_bb_reg(dm, 0x4164, BIT(31), 0x0);
2840 odm_set_bb_reg(dm, 0x180c, BIT(27), 0x0);
2841 odm_set_bb_reg(dm, 0x410c, BIT(27), 0x0);
2842 odm_set_bb_reg(dm, 0x186c, BIT(7), 0x0);
2843 odm_set_bb_reg(dm, 0x416c, BIT(7), 0x0);
2844 odm_set_bb_reg(dm, 0x180c, BIT(1) | BIT(0), 0x3);
2845 odm_set_bb_reg(dm, 0x410c, BIT(1) | BIT(0), 0x3);
2846 odm_set_bb_reg(dm, 0x1a00, BIT(1) | BIT(0), 0x0);
2847
2848
2849 RF_DBG(dm, DBG_RF_IQK, "[IQK]AFE setting for Normal mode!!!!\n");
2850 }
2851 }
2852
_iqk_restore_mac_bb_8822c(struct dm_struct * dm,u32 * MAC_backup,u32 * BB_backup,u32 * backup_mac_reg,u32 * backup_bb_reg)2853 void _iqk_restore_mac_bb_8822c(
2854 struct dm_struct *dm,
2855 u32 *MAC_backup,
2856 u32 *BB_backup,
2857 u32 *backup_mac_reg,
2858 u32 *backup_bb_reg)
2859 {
2860 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2861 u32 i;
2862
2863 /*toggle IGI*/
2864 odm_write_4byte(dm, 0x1d70, 0x50505050);
2865
2866 for (i = 0; i < MAC_REG_NUM_8822C; i++){
2867 odm_write_4byte(dm, backup_mac_reg[i], MAC_backup[i]);
2868 //RF_DBG(dm, DBG_RF_IQK, "[IQK]restore mac = %x, value = %x\n",backup_mac_reg[i],MAC_backup[i]);
2869 }
2870 for (i = 0; i < BB_REG_NUM_8822C; i++){
2871 odm_write_4byte(dm, backup_bb_reg[i], BB_backup[i]);
2872 //RF_DBG(dm, DBG_RF_IQK, "[IQK]restore bb = %x, value = %x\n",backup_bb_reg[i],BB_backup[i]);
2873 }
2874 /*rx go throughput IQK*/
2875 #if 0
2876 odm_set_bb_reg(dm, 0x180c, BIT(31), 0x1);
2877 odm_set_bb_reg(dm, 0x410c, BIT(31), 0x1);
2878 #else
2879 if (iqk_info->iqk_fail_report[0][0][RXIQK] == true)
2880 odm_set_bb_reg(dm, 0x180c, BIT(31), 0x0);
2881 else
2882 odm_set_bb_reg(dm, 0x180c, BIT(31), 0x1);
2883
2884 if (iqk_info->iqk_fail_report[0][1][RXIQK] == true)
2885 odm_set_bb_reg(dm, 0x410c, BIT(31), 0x0);
2886 else
2887 odm_set_bb_reg(dm, 0x410c, BIT(31), 0x1);
2888 #endif
2889 //odm_set_bb_reg(dm, 0x520c, BIT(31), 0x1);
2890 //odm_set_bb_reg(dm, 0x530c, BIT(31), 0x1);
2891 /* RF_DBG(dm, DBG_RF_IQK, "[IQK]RestoreMacBB Success!!!!\n"); */
2892 }
2893
_iqk_restore_rf_8822c(struct dm_struct * dm,u32 * rf_reg,u32 temp[][SS_8822C])2894 void _iqk_restore_rf_8822c(
2895 struct dm_struct *dm,
2896 u32 *rf_reg,
2897 u32 temp[][SS_8822C])
2898 {
2899 u32 i;
2900
2901 odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0xfffff, 0x0);
2902 odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0xfffff, 0x0);
2903 /*0xdf[4]=0*/
2904 //_iqk_rf_set_check_8822c(dm, RF_PATH_A, 0xdf, temp[0][RF_PATH_A] & (~BIT(4)));
2905 //_iqk_rf_set_check_8822c(dm, RF_PATH_B, 0xdf, temp[0][RF_PATH_B] & (~BIT(4)));
2906
2907 for (i = 0; i < RF_REG_NUM_8822C; i++) {
2908 odm_set_rf_reg(dm, RF_PATH_A, rf_reg[i],
2909 0xfffff, temp[i][RF_PATH_A]);
2910 odm_set_rf_reg(dm, RF_PATH_B, rf_reg[i],
2911 0xfffff, temp[i][RF_PATH_B]);
2912 }
2913
2914 odm_set_rf_reg(dm, RF_PATH_A, RF_0xde, BIT(16), 0x0);
2915 odm_set_rf_reg(dm, RF_PATH_B, RF_0xde, BIT(16), 0x0);
2916 RF_DBG(dm, DBG_RF_IQK, "[IQK]RestoreRF Success!!!!\n");
2917 }
2918
_iqk_backup_iqk_8822c(struct dm_struct * dm,u8 step,u8 path)2919 void _iqk_backup_iqk_8822c(
2920 struct dm_struct *dm,
2921 u8 step,
2922 u8 path)
2923 {
2924 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2925 u8 i, j, k;
2926
2927 switch (step) {
2928 case 0:
2929 iqk_info->iqk_channel[1] = iqk_info->iqk_channel[0];
2930 //RF_DBG(dm, DBG_RF_IQK, "[IQK](0)iqk_info->iqk_channel[1] = %2x\n",iqk_info->iqk_channel[1]);
2931 for (i = 0; i < SS_8822C; i++) {
2932 iqk_info->lok_idac[1][i] = iqk_info->lok_idac[0][i];
2933 iqk_info->rxiqk_agc[1][i] = iqk_info->rxiqk_agc[0][i];
2934 iqk_info->bypass_iqk[1][i] = iqk_info->bypass_iqk[0][i];
2935 iqk_info->rxiqk_fail_code[1][i] = iqk_info->rxiqk_fail_code[0][i];
2936 for (j = 0; j < 2; j++) {
2937 iqk_info->iqk_fail_report[1][i][j] = iqk_info->iqk_fail_report[0][i][j];
2938 //RF_DBG(dm, DBG_RF_IQK, "[IQK](2)iqk_info->iqk_fail_report[0][%x][%x] = %2x\n",i,j,iqk_info->iqk_fail_report[1][i][j] );
2939 for (k = 0; k <= 16; k++) {
2940 iqk_info->iqk_cfir_real[1][i][j][k] = iqk_info->iqk_cfir_real[0][i][j][k];
2941 iqk_info->iqk_cfir_imag[1][i][j][k] = iqk_info->iqk_cfir_imag[0][i][j][k];
2942 }
2943 }
2944 }
2945
2946 for (i = 0; i < SS_8822C; i++) {
2947 iqk_info->rxiqk_fail_code[0][i] = 0x0;
2948 iqk_info->rxiqk_agc[0][i] = 0x0;
2949 for (j = 0; j < 2; j++) {
2950 iqk_info->iqk_fail_report[0][i][j] = true;
2951 iqk_info->gs_retry_count[0][i][j] = 0x0;
2952 }
2953 for (j = 0; j < 3; j++)
2954 iqk_info->retry_count[0][i][j] = 0x0;
2955 }
2956 /*backup channel*/
2957 iqk_info->iqk_channel[0] = iqk_info->rf_reg18;
2958 break;
2959 case 1: /*LOK backup*/
2960 iqk_info->lok_idac[0][path] = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x58, RFREGOFFSETMASK);
2961 //RF_DBG(dm, DBG_RF_IQK, "[IQK](4) iqk_info->lok_idac[0][%d]= %2x\n", path, iqk_info->lok_idac[0][path]);
2962 break;
2963 case 2: /*TXIQK backup*/
2964 iqk_get_cfir_8822c(dm, TX_IQK, path, false);
2965 break;
2966 case 3: /*RXIQK backup*/
2967 iqk_get_cfir_8822c(dm, RX_IQK, path, false);
2968 break;
2969 }
2970 }
2971
_iqk_reload_iqk_setting_8822c(struct dm_struct * dm,u8 ch,u8 reload_idx)2972 void _iqk_reload_iqk_setting_8822c(
2973 struct dm_struct *dm,
2974 u8 ch,
2975 u8 reload_idx /*1: reload TX, 2: reload LO, TX, RX*/
2976 )
2977 {
2978 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2979 #if 1
2980 u8 i, path, idx;
2981 u16 iqk_apply[2] = {0x180c, 0x410c};
2982 u32 tmp = 0x0, tmp1 = 0x0, tmp2 = 0x0;
2983 boolean is_NB_IQK = false;
2984
2985 if ((*dm->band_width == CHANNEL_WIDTH_5) ||(*dm->band_width == CHANNEL_WIDTH_10))
2986 is_NB_IQK = true;
2987
2988 for (path = 0; path < SS_8822C; path++) {
2989 if (reload_idx == 2) {
2990 /*odm_set_rf_reg(dm, (enum rf_path)path, RF_0xdf, BIT(4), 0x1);*/
2991 tmp = odm_get_rf_reg(dm, (enum rf_path)path, RF_0xdf, RFREGOFFSETMASK) | BIT(4);
2992 _iqk_rf_set_check_8822c(dm, (enum rf_path)path, 0xdf, tmp);
2993 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x58, RFREGOFFSETMASK, iqk_info->lok_idac[ch][path]);
2994 }
2995
2996 for (idx = 0; idx < reload_idx; idx++) {
2997 odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x8 | path << 1);
2998 odm_write_1byte(dm, 0x1bcc, 0x0);
2999 if (is_NB_IQK) {
3000 odm_set_bb_reg(dm, R_0x1b20, BIT(26), 0x0);
3001 odm_set_bb_reg(dm, 0x1b38, MASKDWORD, iqk_info->nbtxk_1b38[path]);
3002 odm_set_bb_reg(dm, 0x1b3c, MASKDWORD, iqk_info->nbrxk_1b3c[path]);
3003 } else {
3004 odm_set_bb_reg(dm, R_0x1b20, BIT(26), 0x1);
3005 odm_set_bb_reg(dm, R_0x1b38, MASKDWORD, 0x40000000);
3006 odm_set_bb_reg(dm, R_0x1b3c, MASKDWORD, 0x40000000);
3007 }
3008 if (idx == TX_IQK) {//TXCFIR
3009 odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x3);
3010 tmp1 = 0xc0000001;
3011 } else {//RXCFIR
3012 odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x1);
3013 tmp1 = 0x60000001;
3014 }
3015 for (i = 0; i <= 16; i++) {
3016 tmp2 = tmp1 | iqk_info->iqk_cfir_real[ch][path][idx][i] << 8;
3017 tmp2 = (tmp2 | i << 2) + 2;
3018 odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, tmp2);
3019 }
3020 for (i = 0; i <= 16; i++) {
3021 tmp2 = tmp1 | iqk_info->iqk_cfir_imag[ch][path][idx][i] << 8;
3022 tmp2 = (tmp2 | i << 2);
3023 odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, tmp2);
3024 }
3025 if (idx == RX_IQK) {
3026 odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x1);
3027 odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0xe0000001);
3028 odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x0);
3029 //odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);
3030 }
3031 }
3032 // end for write CFIR SRAM
3033 // odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0xe0000000);
3034 odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x0);
3035 // odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);
3036 }
3037 #endif
3038 }
3039
3040 boolean
_iqk_reload_iqk_8822c(struct dm_struct * dm,boolean reset)3041 _iqk_reload_iqk_8822c(
3042 struct dm_struct *dm,
3043 boolean reset)
3044 {
3045 struct dm_iqk_info *iqk_info = &dm->IQK_info;
3046 u8 i;
3047 iqk_info->is_reload = false;
3048
3049 if (reset) {
3050 for (i = 0; i < 2; i++)
3051 iqk_info->iqk_channel[i] = 0x0;
3052 } else {
3053 iqk_info->rf_reg18 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREGOFFSETMASK);
3054
3055 for (i = 0; i < 2; i++) {
3056 if (iqk_info->rf_reg18 == iqk_info->iqk_channel[i]) {
3057 _iqk_reload_iqk_setting_8822c(dm, i, 2);
3058 _iqk_fill_iqk_report_8822c(dm, i);
3059 RF_DBG(dm, DBG_RF_IQK, "[IQK]reload IQK result before!!!!\n");
3060 iqk_info->is_reload = true;
3061 }
3062 }
3063 }
3064 /*report*/
3065 odm_set_bb_reg(dm, R_0x1bf0, BIT(16), (u8)iqk_info->is_reload);
3066 odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, BIT(4), 0x0);
3067 odm_set_rf_reg(dm, RF_PATH_B, RF_0xdf, BIT(4), 0x0);
3068 return iqk_info->is_reload;
3069 }
3070
_iqk_rfe_setting_8822c(struct dm_struct * dm,boolean ext_pa_on)3071 void _iqk_rfe_setting_8822c(
3072 struct dm_struct *dm,
3073 boolean ext_pa_on)
3074 {
3075 /*TBD*/
3076 return;
3077 #if 0
3078 if (ext_pa_on) {
3079 /*RFE setting*/
3080 odm_write_4byte(dm, 0xcb0, 0x77777777);
3081 odm_write_4byte(dm, 0xcb4, 0x00007777);
3082 odm_write_4byte(dm, 0xcbc, 0x0000083B);
3083 odm_write_4byte(dm, 0xeb0, 0x77777777);
3084 odm_write_4byte(dm, 0xeb4, 0x00007777);
3085 odm_write_4byte(dm, 0xebc, 0x0000083B);
3086 /*odm_write_4byte(dm, 0x1990, 0x00000c30);*/
3087 RF_DBG(dm, DBG_RF_IQK, "[IQK]external PA on!!!!\n");
3088 } else {
3089 /*RFE setting*/
3090 odm_write_4byte(dm, 0xcb0, 0x77777777);
3091 odm_write_4byte(dm, 0xcb4, 0x00007777);
3092 odm_write_4byte(dm, 0xcbc, 0x00000100);
3093 odm_write_4byte(dm, 0xeb0, 0x77777777);
3094 odm_write_4byte(dm, 0xeb4, 0x00007777);
3095 odm_write_4byte(dm, 0xebc, 0x00000100);
3096 /*odm_write_4byte(dm, 0x1990, 0x00000c30);*/
3097 /*RF_DBG(dm, DBG_RF_IQK, "[IQK]external PA off!!!!\n");*/
3098 }
3099 #endif
3100 }
3101
_iqk_setrf_bypath_8822c(struct dm_struct * dm)3102 void _iqk_setrf_bypath_8822c(
3103 struct dm_struct *dm)
3104 {
3105 u8 path;
3106 u32 tmp;
3107
3108 /*TBD*/
3109 }
_iqk_rf_direct_access_8822c(struct dm_struct * dm,u8 path,boolean direct_access)3110 void _iqk_rf_direct_access_8822c(
3111 struct dm_struct *dm,
3112 u8 path,
3113 boolean direct_access)
3114 {
3115 if(!direct_access) {//PI
3116 if ((enum rf_path)path == RF_PATH_A)
3117 odm_set_bb_reg(dm, 0x1c, BIT(31) | BIT(30), 0x0);
3118 else if((enum rf_path)path == RF_PATH_B)
3119 odm_set_bb_reg(dm, 0xec, BIT(31) | BIT(30), 0x0);
3120 //odm_set_bb_reg(dm, 0x1c, BIT(31) | BIT(30), 0x0);
3121 //odm_set_bb_reg(dm, 0xec, BIT(31) | BIT(30), 0x0);
3122 } else {//direct access
3123 if ((enum rf_path)path == RF_PATH_A)
3124 odm_set_bb_reg(dm, 0x1c, BIT(31) | BIT(30), 0x2);
3125 else if((enum rf_path)path == RF_PATH_B)
3126 odm_set_bb_reg(dm, 0xec, BIT(31) | BIT(30), 0x2);
3127 //odm_set_bb_reg(dm, 0x1c, BIT(31) | BIT(30), 0x2);
3128 //odm_set_bb_reg(dm, 0xec, BIT(31) | BIT(30), 0x2);
3129 }
3130 /*
3131 RF_DBG(dm, DBG_RF_IQK, "[IQK]0x1c = 0x%x, 0xec = 0x%x\n",
3132 odm_read_4byte(dm, 0x1c), odm_read_4byte(dm, 0xec));
3133 */
3134 }
3135
_iqk_bbtx_path_8822c(struct dm_struct * dm,u8 path)3136 void _iqk_bbtx_path_8822c(
3137 struct dm_struct *dm,
3138 u8 path)
3139 {
3140 u32 temp1 = 0, temp2 = 0;
3141
3142 switch (path) {
3143 case RF_PATH_A:
3144 temp1 = 0x11111111;
3145 temp2 = 0x1;
3146 break;
3147 case RF_PATH_B:
3148 temp1 = 0x22222222;
3149 temp2 = 0x2;
3150 break;
3151 }
3152 odm_write_4byte(dm, 0x820, temp1);
3153 odm_set_bb_reg(dm, 0x824, 0xf0000, temp2);
3154 }
3155
_iqk_iqk_mode_8822c(struct dm_struct * dm,boolean is_iqkmode)3156 void _iqk_iqk_mode_8822c(
3157 struct dm_struct *dm,
3158 boolean is_iqkmode)
3159 {
3160 u32 temp1, temp2;
3161 /*RF can't be write in iqk mode*/
3162 /*page 1b can't */
3163 if (is_iqkmode)
3164 odm_set_bb_reg(dm, 0x1cd0, BIT(31), 0x1);
3165 else
3166 odm_set_bb_reg(dm, 0x1cd0, BIT(31), 0x0);
3167 }
3168
_iqk_macbb_8822c(struct dm_struct * dm)3169 void _iqk_macbb_8822c(
3170 struct dm_struct *dm)
3171 {
3172 struct dm_iqk_info *iqk_info = &dm->IQK_info;
3173
3174 if (iqk_info->is_tssi_mode) {
3175 odm_set_bb_reg(dm, R_0x1e7c, BIT(30), 0x0);
3176 odm_set_bb_reg(dm, R_0x18a4, BIT(28), 0x0);
3177 odm_set_bb_reg(dm, R_0x41a4, BIT(28), 0x0);
3178 }
3179
3180 /*MACBB register setting*/
3181 odm_write_1byte(dm, REG_TXPAUSE, 0xff);
3182 //0x73[2] = 1 (PTA control path is at WLAN)
3183 odm_set_bb_reg(dm, 0x70, 0xff000000, 0x06);
3184 /*BB CCA off*/
3185 //odm_set_bb_reg(dm, 0x1c68, BIT(27) | BIT(26) | BIT(25) | BIT(24), 0xf);
3186 //odm_set_bb_reg(dm, 0x1d58, 0xff8, 0x1ff);
3187 //odm_set_bb_reg(dm, 0x1c68, 0xff8, 0x1ff);
3188 /*tx go throughput IQK*/
3189 odm_set_bb_reg(dm, 0x1e24, BIT(17), 0x1);
3190 /*enable IQK block*/
3191 odm_set_bb_reg(dm, 0x1cd0, BIT(30) | BIT(29) | BIT(28), 0x7);
3192 /*enable IQK loop back in BB*/
3193 odm_set_bb_reg(dm, 0x1d60, BIT(31), 0x1);
3194 /*ADDA FIFO reset*/
3195 odm_write_4byte(dm, 0x1c38, 0xffffffff);
3196 /*CCK off*/
3197 //odm_set_bb_reg(dm, 0x1c3c, BIT(0), 0x0);
3198 //odm_set_bb_reg(dm, 0x1c3c, BIT(1), 0x0);
3199 odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);
3200
3201 /*r_iqk_dpk_clock_src*/
3202 //odm_set_bb_reg(dm, R_0x1cd0, 0xf0000000, 0x7);
3203
3204 /*rx path on*/
3205 odm_set_bb_reg(dm, 0x824, 0x30000, 0x3);
3206
3207 RF_DBG(dm, DBG_RF_IQK, "[IQK]_iqk_macbb_8822c!!!!\n");
3208 }
3209
_iqk_lok_setting_8822c(struct dm_struct * dm,u8 path,u8 idac_bs)3210 void _iqk_lok_setting_8822c(
3211 struct dm_struct *dm,
3212 u8 path,
3213 u8 idac_bs)
3214 {
3215 struct dm_iqk_info *iqk_info = &dm->IQK_info;
3216
3217 boolean is_NB_IQK = false;
3218 u32 temp;
3219
3220 if ((*dm->band_width == CHANNEL_WIDTH_5) ||(*dm->band_width == CHANNEL_WIDTH_10))
3221 is_NB_IQK = true;
3222
3223 _iqk_cal_path_off_8822c(dm);
3224 //_iqk_bbtx_path_8822c(dm, path);
3225 odm_write_4byte(dm, 0x1b00, 0x8 | path << 1);
3226 odm_set_bb_reg(dm, 0x1b20, BIT(31) | BIT(30), 0x0);
3227 odm_set_bb_reg(dm, 0x1b20, 0x3e0, 0x12);// 12dB
3228
3229 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xdf, BIT(4), 0x0);
3230 // Disable bypass TXBB @ RF0x0[19:16]=0x6 and 0x7
3231 odm_set_rf_reg(dm, (enum rf_path)path, 0x9e, BIT(5), 0x0);
3232 odm_set_rf_reg(dm, (enum rf_path)path, 0x9e, BIT(10), 0x0);
3233
3234
3235 //LOK_RES Table
3236 if (*dm->band_type == ODM_BAND_2_4G) {
3237 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xde, BIT(16), 0x1);
3238 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x56, 0xfff, 0x887);
3239 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(2), 0x1);
3240 //odm_set_rf_reg(dm, (enum rf_path)path, RF_0x18, BIT(16), 0x0);
3241 //odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, BIT(0), 0x0);
3242 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x08, 0x70, idac_bs);
3243 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(2), 0x0);
3244 } else {
3245 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xde, BIT(16), 0x1);
3246 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x56, 0xfff, 0x868);
3247 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(2), 0x1);
3248 //odm_set_rf_reg(dm, (enum rf_path)path, RF_0x18, BIT(16), 0x1);
3249 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, BIT(0), 0x0);
3250 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x08, 0x70, idac_bs);
3251 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(2), 0x0);
3252 }
3253 odm_set_rf_reg(dm, (enum rf_path)path, 0x57, BIT(0), 0x0);
3254
3255 //TX_LOK
3256 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(4), 0x1);
3257 if (*dm->band_type == ODM_BAND_2_4G) {
3258 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, 0x7f, 0x00);
3259 odm_write_1byte(dm, 0x1bcc, 0x09);
3260 } else {
3261 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, 0x7f, 0x20);
3262 odm_write_1byte(dm, 0x1bcc, 0x09);
3263 }
3264 odm_write_1byte(dm, 0x1b10, 0x0);
3265
3266 if(is_NB_IQK)
3267 odm_set_bb_reg(dm, 0x1b2c, 0xfff, 0x08);
3268 else
3269 odm_set_bb_reg(dm, 0x1b2c, 0xfff, 0x38);
3270 }
3271
_iqk_reload_lok_setting_8822c(struct dm_struct * dm,u8 path)3272 void _iqk_reload_lok_setting_8822c(
3273 struct dm_struct *dm,
3274 u8 path)
3275 {
3276 #if 1
3277 struct dm_iqk_info *iqk_info = &dm->IQK_info;
3278 u32 tmp;
3279 u8 idac_i, idac_q;
3280 u8 i;
3281
3282 idac_i = (u8)((iqk_info->rf_reg58 & 0xfc000) >> 14);
3283 idac_q = (u8)((iqk_info->rf_reg58 & 0x3f00) >> 8);
3284 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xdf, BIT(4), 0x0);//W LOK table
3285 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(4), 0x1);
3286
3287 if (*dm->band_type == ODM_BAND_2_4G)
3288 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, 0x7f, 0x00);
3289 else
3290 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, 0x7f, 0x20);
3291
3292 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x08, 0xfc000, idac_i);
3293 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x08, 0x003f0, idac_q);
3294 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(4), 0x0);// stop write
3295
3296 tmp = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x58, 0xfffff);
3297 RF_DBG(dm, DBG_RF_IQK, "[IQK]S%d,reload 0x58 = 0x%x\n", path, tmp);
3298 #endif
3299 }
3300
_iqk_txk_setting_8822c(struct dm_struct * dm,u8 path)3301 void _iqk_txk_setting_8822c(
3302 struct dm_struct *dm,
3303 u8 path)
3304 {
3305 u32 rf_reg64 = 0x0;
3306 u32 curr_thermal = 0x0, ee_thermal = 0x0;
3307 u32 rf_0x56 = 0x0;
3308 boolean flag = false;
3309 u8 threshold = 0x10;
3310 boolean is_NB_IQK = false;
3311
3312 if ((*dm->band_width == CHANNEL_WIDTH_5) ||(*dm->band_width == CHANNEL_WIDTH_10))
3313 is_NB_IQK = true;
3314
3315 odm_write_4byte(dm, 0x1b00, 0x8 | path << 1);
3316 odm_set_bb_reg(dm, 0x1bb8, BIT(20), 0x0);
3317 odm_write_4byte(dm, 0x1b20, 0x00040008);
3318
3319 path = (enum rf_path)path;
3320 if (*dm->band_type == ODM_BAND_2_4G) {
3321 rf_0x56 = 0x887;
3322 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x56, 0xfff, rf_0x56);
3323 odm_write_1byte(dm, 0x1bcc, 0x09);
3324 } else {
3325 rf_0x56 = 0x8c6;
3326 #if 1
3327 //TANK
3328 rf_reg64 = odm_get_rf_reg(dm, path, RF_0x64, MASK20BITS);
3329 rf_reg64 = (rf_reg64 & 0xfff0f) | 0x010;
3330 odm_set_rf_reg(dm, path, RF_0xdf, BIT(6), 0x1);
3331 odm_set_rf_reg(dm, path, RF_0x64, MASK20BITS, rf_reg64);
3332 #endif
3333 #if 1
3334 /*get thermal meter*/
3335 ee_thermal = _iqk_get_efuse_thermal_8822c(dm, path);
3336 odm_set_rf_reg(dm, path, 0x42, BIT(17) | BIT(16), 0x3);
3337 halrf_delay_10us(20);
3338 curr_thermal = (u8)odm_get_rf_reg(dm, path, 0x42, 0xfc00);
3339 if (ee_thermal > curr_thermal)
3340 flag = ee_thermal - curr_thermal > threshold ? true : false;
3341 if (flag)
3342 rf_0x56 = 0x886;
3343 odm_set_rf_reg(dm, path, RF_0x56, 0xfff, rf_0x56);
3344 #endif
3345 odm_write_1byte(dm, 0x1bcc, 0x09);
3346 }
3347
3348 if(is_NB_IQK)
3349 odm_set_bb_reg(dm, 0x1b2c, 0xfff, 0x08);
3350 else
3351 odm_set_bb_reg(dm, 0x1b2c, 0xfff, 0x38);
3352 }
3353
_iqk_lok_for_rxk_setting_8822c(struct dm_struct * dm,u8 path)3354 void _iqk_lok_for_rxk_setting_8822c(
3355 struct dm_struct *dm,
3356 u8 path)
3357 {
3358 struct dm_iqk_info *iqk_info = &dm->IQK_info;
3359
3360 boolean is_NB_IQK = false;
3361
3362 if ((*dm->band_width == CHANNEL_WIDTH_5) ||(*dm->band_width == CHANNEL_WIDTH_10))
3363 is_NB_IQK = true;
3364
3365 _iqk_cal_path_off_8822c(dm);
3366 odm_write_4byte(dm, 0x1b00, 0x8 | path << 1);
3367 odm_set_bb_reg(dm, 0x1bb8, BIT(20), 0x0);
3368 odm_set_bb_reg(dm, 0x1b20, BIT(31) | BIT(30), 0x0);
3369
3370 //force 0x53[0]=1, force PA on
3371 odm_set_rf_reg(dm, (enum rf_path)path, 0x53, BIT(0), 0x1);
3372
3373 //LOK_RES Table
3374 if (*dm->band_type == ODM_BAND_2_4G) {
3375 odm_set_rf_reg(dm, (enum rf_path)path, 0x00, 0xf0000, 0x7);
3376 odm_set_rf_reg(dm, (enum rf_path)path, 0x9e, BIT(5), 0x1);
3377 odm_set_rf_reg(dm, (enum rf_path)path, 0x9e, BIT(10), 0x1);
3378 odm_set_bb_reg(dm, 0x1b20, 0x3e0, 0x12);// 12dB
3379 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xde, BIT(16), 0x1);
3380 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x56, 0xfff, 020);
3381 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(2), 0x1);
3382 //odm_set_rf_reg(dm, (enum rf_path)path, RF_0x18, BIT(16), 0x0);
3383 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, BIT(0), 0x0);
3384 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x08, 0x70, 0x4);
3385 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(2), 0x0);
3386 } else {
3387 odm_set_rf_reg(dm, (enum rf_path)path, 0x00, 0xf0000, 0x7);
3388 odm_set_rf_reg(dm, (enum rf_path)path, 0x9e, BIT(5), 0x1);
3389 odm_set_rf_reg(dm, (enum rf_path)path, 0x9e, BIT(10), 0x1);
3390 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xde, BIT(16), 0x1);
3391 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x56, 0xfff, 0x000);
3392 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(2), 0x1);
3393 //odm_set_rf_reg(dm, (enum rf_path)path, RF_0x18, BIT(16), 0x1);
3394 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, BIT(0), 0x1);
3395 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x08, 0x70, 0x4);
3396 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(2), 0x0);
3397 }
3398 odm_set_rf_reg(dm, (enum rf_path)path, 0x57, BIT(0), 0x0);
3399
3400 //TX_LOK
3401 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(4), 0x1);
3402 if (*dm->band_type == ODM_BAND_2_4G) {
3403 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, 0x7f, 0x00);
3404 odm_write_1byte(dm, 0x1bcc, 0x09);
3405 } else {
3406 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, 0x7f, 0x20);
3407 odm_write_1byte(dm, 0x1bcc, 0x09);
3408 }
3409 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(4), 0x1); //LOK _Write_en
3410 odm_write_1byte(dm, 0x1b10, 0x0);
3411 odm_write_1byte(dm, 0x1bcc, 0x12);
3412 if(is_NB_IQK)
3413 odm_set_bb_reg(dm, 0x1b2c, 0xfff, 0x008);
3414 else
3415 odm_set_bb_reg(dm, 0x1b2c, 0xfff, 0x038);
3416 }
3417
3418 //static u8 wlg_lna[5] = {0x0, 0x1, 0x2, 0x3, 0x5};
3419 //static u8 wla_lna[5] = {0x0, 0x1, 0x3, 0x4, 0x5};
_iqk_rxk1_setting_8822c(struct dm_struct * dm,u8 path)3420 void _iqk_rxk1_setting_8822c(
3421 struct dm_struct *dm,
3422 u8 path)
3423 {
3424 struct dm_iqk_info *iqk = &dm->IQK_info;
3425 boolean is_NB_IQK = false;
3426
3427 if ((*dm->band_width == CHANNEL_WIDTH_5) ||(*dm->band_width == CHANNEL_WIDTH_10))
3428 is_NB_IQK = true;
3429
3430 _iqk_cal_path_off_8822c(dm);
3431 odm_write_4byte(dm, 0x1b00, 0x8 | path << 1);
3432 odm_set_bb_reg(dm, 0x1bb8, BIT(20), 0x0);
3433 odm_set_bb_reg(dm, 0x1b20, BIT(31) | BIT(30), 0x0);
3434 //odm_write_4byte(dm, 0x1bd8, 0x0);
3435
3436 odm_set_bb_reg(dm, 0x1b20, 0x3e0, 0x12); // 12dB
3437 if (*dm->band_type == ODM_BAND_2_4G) {
3438 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xde, BIT(16), 0x1);
3439 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x56, 0xfff, 0x020);
3440 odm_write_1byte(dm, 0x1bcc, 0x12);
3441 } else {
3442 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xde, BIT(16), 0x1);
3443 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x56, 0xfff, 0x000);
3444 odm_write_1byte(dm, 0x1bcc, 0x12);
3445 }
3446
3447 if(is_NB_IQK)
3448 odm_set_bb_reg(dm, 0x1b2c, 0xfff, 0x008);
3449 else
3450 odm_set_bb_reg(dm, 0x1b2c, 0xfff, 0x038);
3451 }
3452
_iqk_rxk2_setting_8822c(struct dm_struct * dm,u8 path,boolean is_gs)3453 void _iqk_rxk2_setting_8822c(
3454 struct dm_struct *dm,
3455 u8 path,
3456 boolean is_gs)
3457 {
3458 struct dm_iqk_info *iqk = &dm->IQK_info;
3459 boolean is_NB_IQK = false;
3460
3461 if ((*dm->band_width == CHANNEL_WIDTH_5) ||(*dm->band_width == CHANNEL_WIDTH_10))
3462 is_NB_IQK = true;
3463 odm_write_4byte(dm, 0x1b00, 0x8 | path << 1);
3464 odm_set_bb_reg(dm, 0x1b20, BIT(31) | BIT(30), 0x0);
3465 //odm_write_4byte(dm, 0x1bd8, 0x0);
3466
3467 if (*dm->band_type == ODM_BAND_2_4G) {
3468 if (is_gs) {
3469 iqk->tmp1bcc = 0x12;
3470 }
3471 odm_write_1byte(dm, 0x1bcc, iqk->tmp1bcc);
3472 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xde, BIT(16), 0x1);
3473 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x56, 0xfff, 0x020);
3474 odm_set_bb_reg(dm, 0x1b18, BIT(1), 0x1);
3475 odm_write_4byte(dm, 0x1b24, 0x00071808); //LNA=0110, RXBB=00000
3476 odm_write_1byte(dm, 0x1b10, 0x0);
3477 } else {
3478
3479 if (is_gs) {
3480 iqk->tmp1bcc = 0x12;
3481 }
3482 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xde, BIT(16), 0x1);
3483 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x56, 0xfff, 0x000);
3484 odm_write_1byte(dm, 0x1bcc, iqk->tmp1bcc);
3485 odm_set_bb_reg(dm, 0x1b18, BIT(1), 0x1);
3486 odm_write_4byte(dm, 0x1b24, 0x00070c08); //LNA=011
3487 odm_write_1byte(dm, 0x1b10, 0x0);
3488 }
3489
3490 if(is_NB_IQK)
3491 odm_set_bb_reg(dm, 0x1b2c, 0xfff, 0x008);
3492 else
3493 odm_set_bb_reg(dm, 0x1b2c, 0xfff, 0x038);
3494 }
3495
3496
3497
3498 void
_iqk_set_lok_lut_8822c(struct dm_struct * dm,u8 path)3499 _iqk_set_lok_lut_8822c(
3500 struct dm_struct *dm,
3501 u8 path)
3502 {
3503 #if 0
3504 u32 temp;
3505 u8 idac_i, idac_q;
3506 u8 i;
3507
3508 temp = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x58, 0xfffff);
3509 RF_DBG(dm, DBG_RF_IQK, "[IQK]setlut_0x58 = 0x%x\n", temp);
3510 idac_i = (u8)((temp & 0xfc000) >> 14);
3511 idac_q = (u8)((temp & 0x3f0) >> 4);
3512 temp = (idac_i << 6) | idac_q;
3513 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xdf, BIT(4), 0x0);
3514 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(4), 0x1);
3515 for (i = 0; i < 8; i++) {
3516 temp = (i << 14) | (temp & 0xfff);
3517 if (*dm->band_type == ODM_BAND_2_4G)
3518 odm_set_rf_reg(dm, (enum rf_path)path, 0x33, 0xfffff, temp);
3519 else
3520 odm_set_rf_reg(dm, (enum rf_path)path, 0x33, 0xfffff, 0x20 | temp);
3521 RF_DBG(dm, DBG_RF_IQK, "[IQK]path =%d,0x33 = 0x%x!!!\n", path, temp);
3522 }
3523 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(4), 0x0);
3524 #endif
3525 }
3526
3527 boolean
_iqk_rx_iqk_gain_search_fail_8822c(struct dm_struct * dm,u8 path,u8 step)3528 _iqk_rx_iqk_gain_search_fail_8822c(
3529 struct dm_struct *dm,
3530 u8 path,
3531 u8 step)
3532 {
3533
3534
3535 struct dm_iqk_info *iqk = &dm->IQK_info;
3536 boolean fail = true, k2fail = true;
3537 u32 IQK_CMD = 0x0, rf_reg0 = 0x0, tmp = 0x0, bb_idx = 0x0;
3538 u8 IQMUX[5] = {0x9, 0x12, 0x1b, 0x24, 0x24};
3539 u8 idx;
3540
3541 RF_DBG(dm, DBG_RF_IQK, "[IQK]============ S%d RXIQK GainSearch ============\n", path);
3542
3543 if (step == RXIQK1) {
3544 IQK_CMD = (0x208 | (1 << (path + 4)) | (path << 1));
3545 RF_DBG(dm, DBG_RF_IQK, "[IQK]S%d GS%d_Trigger = 0x%x\n", path,
3546 step, IQK_CMD);
3547
3548 if(dm->cut_version == ODM_CUT_E) {
3549 odm_set_rf_reg(dm, (enum rf_path)path, 0x0, 0xf0000, 0x4);
3550 odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, BIT(14), 0x1);
3551 }
3552 halrf_delay_10us(1);
3553 odm_write_4byte(dm, 0x1b00, IQK_CMD);
3554 odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);
3555 fail = _iqk_check_cal_8822c(dm, path, 0x1);
3556 } else if (step == RXIQK2) {
3557 for (idx = 0; idx < 4; idx++) {
3558 if (iqk->tmp1bcc == IQMUX[idx])
3559 break;
3560 }
3561 if (idx == 4)
3562 RF_DBG(dm, DBG_RF_IQK, "[IQK] rx_gs overflow\n");
3563
3564 odm_write_4byte(dm, 0x1b00, 0x8 | path << 1);
3565 odm_write_4byte(dm, 0x1bcc, iqk->tmp1bcc);
3566
3567 IQK_CMD = (0x308 | (1 << (path + 4)) | (path << 1));
3568 RF_DBG(dm, DBG_RF_IQK, "[IQK]S%d GS%d_Trigger = 0x%x\n", path,
3569 step, IQK_CMD);
3570
3571 if(dm->cut_version == ODM_CUT_E) {
3572 odm_set_rf_reg(dm, (enum rf_path)path, 0x0, 0xf0000, 0x7);
3573 odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, BIT(14), 0x0);
3574 }
3575 halrf_delay_10us(1);
3576 odm_write_4byte(dm, 0x1b00, IQK_CMD);
3577 odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);
3578 halrf_delay_10us(2);
3579 rf_reg0 = odm_get_rf_reg(dm, (enum rf_path)path,
3580 RF_0x0, MASK20BITS);
3581
3582 k2fail = _iqk_check_cal_8822c(dm, path, 0x1);
3583
3584 if (k2fail == true) {
3585 iqk->tmp1bcc = IQMUX[idx++];
3586 return true;
3587 }
3588 odm_write_4byte(dm, 0x1b00, 0x00000008 | path << 1);
3589
3590 tmp = (rf_reg0 & 0x1fe0) >> 5;
3591 iqk->lna_idx = tmp >> 5; // lna value
3592 bb_idx = tmp & 0x1f;
3593 if (bb_idx <= 0x1) {
3594 if (idx != 3)
3595 idx++;
3596 else
3597 iqk->isbnd = true;
3598 fail = true;
3599 } else if (bb_idx >= 0xa) {
3600 if (idx != 0)
3601 idx--;
3602 else
3603 iqk->isbnd = true;
3604 fail = true;
3605 } else {
3606 fail = false;
3607 iqk->isbnd = false;
3608 }
3609
3610 if (iqk->isbnd)
3611 fail = false;
3612
3613 iqk->tmp1bcc = IQMUX[idx];
3614
3615 if (fail == false){
3616 tmp = (iqk->tmp1bcc << 8) | bb_idx ;
3617 odm_write_4byte(dm, 0x1be8, tmp);
3618 RF_DBG(dm, DBG_RF_IQK, "[IQK]S%d 0x1be8 = %x\n",path, tmp);
3619 }
3620 }
3621
3622 return fail;
3623
3624
3625 }
3626
3627 boolean
_lok_check_8822c(void * dm_void,u8 path)3628 _lok_check_8822c(void *dm_void, u8 path)
3629 {
3630 struct dm_struct *dm = (struct dm_struct *)dm_void;
3631 struct dm_iqk_info *iqk_info = &dm->IQK_info;
3632 struct _hal_rf_ *rf = &dm->rf_table;
3633 u32 temp;
3634 u8 idac_i, idac_q;
3635 u8 i;
3636
3637 _iqk_cal_path_off_8822c(dm);
3638 odm_write_4byte(dm, 0x1b00, 0x8 | path << 1);
3639
3640 temp = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x58, 0xfffff);
3641 //RF_DBG(dm, DBG_RF_IQK, "[IQK](1)setlut_0x58 = 0x%x\n", temp);
3642 idac_i = (u8)((temp & 0xfc000) >> 14);
3643 idac_q = (u8)((temp & 0x03f00) >> 8);
3644
3645 if (idac_i <= 0x3 || idac_i >= 0x3c || idac_q <= 0x3 || idac_q >= 0x3c)
3646 return false;
3647 else
3648 return true;
3649
3650 }
3651
3652
3653 boolean
_lok_one_shot_8822c(void * dm_void,u8 path,boolean for_rxk)3654 _lok_one_shot_8822c(
3655 void *dm_void,
3656 u8 path,
3657 boolean for_rxk)
3658 {
3659 struct dm_struct *dm = (struct dm_struct *)dm_void;
3660 struct dm_iqk_info *iqk_info = &dm->IQK_info;
3661 struct _hal_rf_ *rf = &dm->rf_table;
3662
3663 u8 delay_count = 0;
3664 boolean LOK_notready = false;
3665 u32 temp = 0;
3666 u32 IQK_CMD = 0x0;
3667 u8 idac_i, idac_q;
3668
3669 _iqk_set_gnt_wl_gnt_bt_8822c(dm, true);
3670 if (for_rxk) {
3671 RF_DBG(dm, DBG_RF_IQK,
3672 "[IQK]======S%d LOK for RXK======\n", path);
3673 IQK_CMD = 0x8 | (1 << (4 + path)) | (path << 1);
3674 if(dm->cut_version == ODM_CUT_E) {
3675 odm_set_rf_reg(dm, (enum rf_path)path, 0x0, 0xf0000, 0x6);
3676 odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, BIT(14), 0x1);
3677 RF_DBG(dm, DBG_RF_IQK, "[IQK]0x00 =%x, 0x8f = 0x%x\n", odm_get_rf_reg(dm, path, 0x0, 0xfffff), odm_get_rf_reg(dm, path, 0x8f, 0xfffff));
3678 RF_DBG(dm, DBG_RF_IQK, "[IQK]0x38 =%x, 0x8f = 0x%x\n", _iqk_btc_read_indirect_reg_8822c(dm, 0x38), odm_get_bb_reg(dm, 0x70, 0xff000000));
3679
3680 }
3681 halrf_delay_10us(1);
3682 } else {
3683 RF_DBG(dm, DBG_RF_IQK,
3684 "[IQK]======S%d LOK======\n", path);
3685 IQK_CMD = 0x8 | (1 << (4 + path)) | (path << 1);
3686
3687 if(dm->cut_version == ODM_CUT_E) {
3688 odm_set_rf_reg(dm, (enum rf_path)path, 0x0, 0xf0000, 0x4);
3689 odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, BIT(14), 0x1);
3690 RF_DBG(dm, DBG_RF_IQK, "[IQK]0x00 =%x, 0x8f = 0x%x\n", odm_get_rf_reg(dm, path, 0x0, 0xfffff), odm_get_rf_reg(dm, path, 0x8f, 0xfffff));
3691 RF_DBG(dm, DBG_RF_IQK, "[IQK]0x38 =%x, 0x8f = 0x%x\n", _iqk_btc_read_indirect_reg_8822c(dm, 0x38), odm_get_bb_reg(dm, 0x70, 0xff000000));
3692
3693 }
3694 halrf_delay_10us(1);
3695 }
3696 RF_DBG(dm, DBG_RF_IQK, "[IQK]LOK_Trigger = 0x%x\n", IQK_CMD);
3697
3698 RF_DBG(dm, DBG_RF_IQK, "[IQK]0x00 =%x, 0x8f = 0x%x\n", odm_get_rf_reg(dm, path, 0x0, 0xfffff), odm_get_rf_reg(dm, path, 0x8f, 0xfffff));
3699 RF_DBG(dm, DBG_RF_IQK, "[IQK]0x38 =%x, 0x8f = 0x%x\n", _iqk_btc_read_indirect_reg_8822c(dm, 0x38), odm_get_bb_reg(dm, 0x70, 0xff000000));
3700
3701
3702 _iqk_rf_direct_access_8822c(dm, (enum rf_path)path, false);
3703 odm_write_4byte(dm, 0x1b00, IQK_CMD);
3704 odm_write_4byte(dm, 0x1b00, IQK_CMD + 1);
3705 halrf_delay_10us(200);
3706 _iqk_rf_direct_access_8822c(dm, (enum rf_path)path, true);
3707 /*LOK: CMD ID = 0 {0xf8000018, 0xf8000028}*/
3708 /*LOK: CMD ID = 0 {0xf8000019, 0xf8000029}*/
3709
3710 // idx of LOK LUT table, EF[4]:WE_LUT_TX_LOK
3711 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(4), 0x0);
3712
3713 LOK_notready = _iqk_check_cal_8822c(dm, path, 0x0);
3714 #if 1
3715 if (path == RF_PATH_B)
3716 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x00, 0xf0000, 0x1);
3717 #endif
3718
3719 _iqk_set_gnt_wl_gnt_bt_8822c(dm, false);
3720 if(!for_rxk)
3721 iqk_info->rf_reg58 = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x58, 0xfffff);
3722
3723 if (!LOK_notready) {
3724 RF_DBG(dm, DBG_RF_IQK, "[IQK]0x58 = 0x%x\n",
3725 odm_get_rf_reg(dm, (enum rf_path)path, RF_0x58, 0xfffff));
3726 _iqk_backup_iqk_8822c(dm, 0x1, path);
3727 } else
3728 RF_DBG(dm, DBG_RF_IQK, "[IQK]==>S%d LOK Fail!!!\n", path);
3729 iqk_info->lok_fail[path] = LOK_notready;
3730 return LOK_notready;
3731 }
3732
3733 boolean
_iqk_one_shot_8822c(void * dm_void,u8 path,u8 idx)3734 _iqk_one_shot_8822c(
3735 void *dm_void,
3736 u8 path,
3737 u8 idx)
3738 {
3739 struct dm_struct *dm = (struct dm_struct *)dm_void;
3740 struct dm_iqk_info *iqk_info = &dm->IQK_info;
3741 struct _hal_rf_ *rf = &dm->rf_table;
3742 boolean notready = true, fail = true, is_NB_IQK = false;
3743 u32 iqk_cmd = 0x0 , temp = 0x0;
3744
3745 if (idx == TXIQK)
3746 RF_DBG(dm, DBG_RF_IQK, "[IQK]============ S%d WBTXIQK ============\n", path);
3747 else if (idx == RXIQK1)
3748 RF_DBG(dm, DBG_RF_IQK, "[IQK]============ S%d WBRXIQK STEP1============\n", path);
3749 else
3750 RF_DBG(dm, DBG_RF_IQK, "[IQK]============ S%d WBRXIQK STEP2============\n", path);
3751
3752 if ((*dm->band_width == CHANNEL_WIDTH_5) ||(*dm->band_width == CHANNEL_WIDTH_10))
3753 is_NB_IQK = true;
3754
3755 _iqk_set_gnt_wl_gnt_bt_8822c(dm, true);
3756
3757 if (idx == TXIQK) {
3758 if (is_NB_IQK)
3759 temp = (0x1 << 8) | (1 << (path + 4)) | (path << 1);
3760 else
3761 temp = ((*dm->band_width + 4) << 8) | (1 << (path + 4)) | (path << 1);
3762 iqk_cmd = 0x8 | temp;
3763 RF_DBG(dm, DBG_RF_IQK, "[IQK]TXK_Trigger = 0x%x\n", iqk_cmd);
3764
3765 if(dm->cut_version == ODM_CUT_E){
3766 odm_set_rf_reg(dm, (enum rf_path)path, 0x0, 0xf0000, 0x4);
3767 odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, BIT(14), 0x1);
3768 }
3769 halrf_delay_10us(1);
3770 /*{0xf8000118, 0xf800012a} ==> NB TXK (CMD = 1)*/
3771 /*{0xf8000418, 0xf800042a} ==> 20 WBTXK (CMD = 3)*/
3772 /*{0xf8000518, 0xf800052a} ==> 40 WBTXK (CMD = 4)*/
3773 /*{0xf8000618, 0xf800062a} ==> 80 WBTXK (CMD = 5)*/
3774 } else if (idx == RXIQK1) {
3775 if (is_NB_IQK)
3776 temp = (0x2 << 8) | (1 << (path + 4)) | (path << 1);
3777 else
3778 temp = ((*dm->band_width + 7) << 8) | (1 << (path + 4)) | (path << 1);
3779 iqk_cmd = 0x8 | temp;
3780 RF_DBG(dm, DBG_RF_IQK, "[IQK]RXK1_Trigger = 0x%x\n", iqk_cmd);
3781
3782 if(dm->cut_version == ODM_CUT_E){
3783 odm_set_rf_reg(dm, (enum rf_path)path, 0x0, 0xf0000, 0x6);
3784 odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, BIT(14), 0x1);
3785 }
3786 halrf_delay_10us(1);
3787 /*{0xf8000218, 0xf800021a} ==> NB RXK1 (CMD = 1)*/
3788 /*{0xf8000718, 0xf800071a} ==> 20 WBRXK1 (CMD = 7)*/
3789 /*{0xf8000718, 0xf800081a} ==> 40 WBRXK1 (CMD = 8)*/
3790 /*{0xf8000818, 0xf800091a} ==> 80 WBRXK1 (CMD = 9)*/
3791 } else if (idx == RXIQK2) {
3792 if (is_NB_IQK)
3793 temp = (0x3 << 8) | (1 << (path + 4)) | (path << 1);
3794 else
3795 temp = ((*dm->band_width + 0xa) << 8) | (1 << (path + 4)) | (path << 1);
3796 iqk_cmd = 0x8 | temp;
3797 RF_DBG(dm, DBG_RF_IQK, "[IQK]RXK2_Trigger = 0x%x\n", iqk_cmd);
3798
3799 if(dm->cut_version == ODM_CUT_E) {
3800 odm_set_rf_reg(dm, (enum rf_path)path, 0x0, 0xf0000, 0x7);
3801 odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, BIT(14), 0x0);
3802 }
3803 halrf_delay_10us(1);
3804 /*{0xf8000318, 0xf800031a} ==> NB RXK2 (CMD = 3)*/
3805 /*{0xf8000918, 0xf8000a1a} ==> 20 WBRXK2 (CMD = a)*/
3806 /*{0xf8000a18, 0xf8000b1a} ==> 40 WBRXK2 (CMD = b)*/
3807 /*{0xf8000b18, 0xf8000c1a} ==> 80 WBRXK2 (CMD = c)*/
3808 }
3809
3810 RF_DBG(dm, DBG_RF_IQK, "[IQK]0x0 =%x, 0x8f = 0x%x\n", odm_get_rf_reg(dm, path, 0x0, 0xfffff), odm_get_rf_reg(dm, path, 0x8f, 0xfffff));
3811 RF_DBG(dm, DBG_RF_IQK, "[IQK]0x38 =%x, 0x73 = 0x%x\n", _iqk_btc_read_indirect_reg_8822c(dm, 0x38), odm_get_bb_reg(dm, 0x70, 0xff000000));
3812
3813 if (rf->rf_dbg_comp & DBG_RF_IQK) {
3814 if (idx != TXIQK) {
3815 odm_write_4byte(dm, 0x1b00, 0x8 | path << 1);
3816 RF_DBG(dm, DBG_RF_IQK, "[IQK]0x1bcc =0x%x\n", odm_read_1byte(dm, 0x1bcc));
3817 }
3818 }
3819 //_iqk_set_gnt_wl_gnt_bt_8822c(dm, true);
3820 odm_write_4byte(dm, 0x1b00, iqk_cmd);
3821 odm_write_4byte(dm, 0x1b00, iqk_cmd + 0x1);
3822 fail = _iqk_check_cal_8822c(dm, path, 0x1);
3823
3824 #if 1
3825 if (path == RF_PATH_B)
3826 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x00, 0xf0000, 0x1);
3827 #endif
3828 _iqk_set_gnt_wl_gnt_bt_8822c(dm, false);
3829
3830 if (idx == TXIQK) {
3831 odm_write_4byte(dm, 0x1b00, 0x8 | path << 1);
3832 iqk_info->iqk_fail_report[0][path][TXIQK] = fail;
3833 if (!fail){
3834 if (is_NB_IQK)
3835 iqk_info->nbtxk_1b38[path] = odm_read_4byte(dm, 0x1b38);
3836 else
3837 _iqk_backup_iqk_8822c(dm, 0x2, path);
3838 }
3839 }
3840 if (idx == RXIQK2) {
3841 odm_write_4byte(dm, 0x1b00, 0x8 | path << 1);
3842 temp = odm_get_rf_reg(dm,(enum rf_path)path, RF_0x0, MASK20BITS) >> 5;
3843 temp = temp & 0xff;
3844 temp = temp | (iqk_info->tmp1bcc << 8);
3845 iqk_info->rxiqk_agc[0][path] = (u16)temp;
3846 iqk_info->iqk_fail_report[0][path][RXIQK] = fail;
3847 if (!fail) {
3848 if (is_NB_IQK)
3849 iqk_info->nbrxk_1b3c[path] = odm_read_4byte(dm, 0x1b3c);
3850 else
3851 _iqk_backup_iqk_8822c(dm, 0x3, path);
3852 }
3853 }
3854 return fail;
3855 }
3856
3857 boolean
_iqk_rx_iqk_by_path_8822c(void * dm_void,u8 path)3858 _iqk_rx_iqk_by_path_8822c(
3859 void *dm_void,
3860 u8 path)
3861 {
3862 struct dm_struct *dm = (struct dm_struct *)dm_void;
3863 struct dm_iqk_info *iqk_info = &dm->IQK_info;
3864 boolean KFAIL = false, gonext;
3865 u32 tmp;
3866
3867 //RF_DBG(dm, DBG_RF_IQK, "[IQK]rx_iqk_step = 0x%x\n", iqk_info->rxiqk_step);
3868
3869 #if 1
3870 switch (iqk_info->rxiqk_step) {
3871 case 0: //LOK for RXK
3872 #if 1
3873 _iqk_lok_for_rxk_setting_8822c(dm, path);
3874 _lok_one_shot_8822c(dm, path, true);
3875 #endif
3876 iqk_info->rxiqk_step++;
3877 break;
3878 case 1: /*gain search_RXK1*/
3879 #if 0
3880 _iqk_rxk1_setting_8822c(dm, path);
3881 gonext = false;
3882 while (1) {
3883 KFAIL = _iqk_rx_iqk_gain_search_fail_8822c(dm, path, RXIQK1);
3884 if (KFAIL && iqk_info->gs_retry_count[0][path][0] < 2)
3885 iqk_info->gs_retry_count[0][path][0]++;
3886 else if (KFAIL) {
3887 iqk_info->rxiqk_fail_code[0][path] = 0;
3888 iqk_info->rxiqk_step = RXK_STEP_8822C;
3889 gonext = true;
3890 } else {
3891 iqk_info->rxiqk_step++;
3892 gonext = true;
3893 }
3894 if (gonext)
3895 break;
3896 }
3897 //halrf_iqk_xym_read(dm, path, 0x2);
3898 #else
3899 iqk_info->rxiqk_step++;
3900 #endif
3901 break;
3902 case 2: /*RXK1*/
3903 #if 1
3904 _iqk_rxk1_setting_8822c(dm, path);
3905 gonext = false;
3906 while (1) {
3907 KFAIL = _iqk_one_shot_8822c(dm, path, RXIQK1);
3908 if (KFAIL && iqk_info->retry_count[0][path][RXIQK1] < 2)
3909 iqk_info->retry_count[0][path][RXIQK1]++;
3910 else if (KFAIL) {
3911 iqk_info->rxiqk_fail_code[0][path] = 1;
3912 iqk_info->rxiqk_step = RXK_STEP_8822C;
3913 gonext = true;
3914 } else {
3915 iqk_info->rxiqk_step++;
3916 gonext = true;
3917 }
3918 if (gonext)
3919 break;
3920 }
3921 #else
3922 iqk_info->rxiqk_step++;
3923 #endif
3924 break;
3925
3926 case 3: /*gain search_RXK2*/
3927 #if 1
3928 _iqk_rxk2_setting_8822c(dm, path, true);
3929 iqk_info->isbnd = false;
3930 while (1) {
3931 RF_DBG(dm, DBG_RF_IQK, "[IQK]gs2_retry = %d\n", iqk_info->gs_retry_count[0][path][1]);
3932 KFAIL = _iqk_rx_iqk_gain_search_fail_8822c(dm, path, RXIQK2);
3933 if (KFAIL && (iqk_info->gs_retry_count[0][path][1] < rxiqk_gs_limit))
3934 iqk_info->gs_retry_count[0][path][1]++;
3935 else {
3936 iqk_info->rxiqk_step++;
3937 break;
3938 }
3939 }
3940 //halrf_iqk_xym_read(dm, path, 0x3);
3941 #else
3942 iqk_info->rxiqk_step++;
3943 #endif
3944 break;
3945 case 4: /*RXK2*/
3946 #if 1
3947 _iqk_rxk2_setting_8822c(dm, path, false);
3948 gonext = false;
3949 while (1) {
3950 KFAIL = _iqk_one_shot_8822c(dm, path, RXIQK2);
3951 if (KFAIL && iqk_info->retry_count[0][path][RXIQK2] < 2)
3952 iqk_info->retry_count[0][path][RXIQK2]++;
3953 else if (KFAIL) {
3954 iqk_info->rxiqk_fail_code[0][path] = 2;
3955 iqk_info->rxiqk_step = RXK_STEP_8822C;
3956 gonext = true;
3957 } else {
3958 iqk_info->rxiqk_step++;
3959 gonext = true;
3960 }
3961 if (gonext)
3962 break;
3963 }
3964 #else
3965 iqk_info->rxiqk_step++;
3966 #endif
3967 break;
3968 case 5: /*check RX XYM*/
3969 #if 0
3970 RF_DBG(dm, DBG_RF_IQK, "[IQK] check RX XYM step =%d\n", iqk_info->rxiqk_step);
3971 KFAIL = _iqk_xym_read_8822c(dm, path);
3972 if (KFAIL)
3973 iqk_info->rxiqk_step = 0x0;
3974 else
3975 iqk_info->rxiqk_step++;
3976
3977 iqk_info->iqk_fail_report[0][path][RXIQK] = KFAIL;
3978 #else
3979 iqk_info->rxiqk_step++;
3980 #endif
3981 break;
3982
3983 }
3984 return KFAIL;
3985 #endif
3986 }
3987
_iqk_lok_tune_8822c(void * dm_void,u8 path)3988 void _iqk_lok_tune_8822c(void *dm_void, u8 path)
3989 {
3990 struct dm_struct *dm = (struct dm_struct *)dm_void;
3991 u8 idac_bs = 0x4;
3992
3993 while (1) {
3994 _iqk_lok_setting_8822c(dm, path, idac_bs);
3995 _lok_one_shot_8822c(dm, path, false);
3996 //RF_DBG(dm, DBG_RF_IQK, "[IQK]ibs = %d\n", idac_bs);
3997 if(!_lok_check_8822c(dm, path)) {
3998 if(idac_bs == 0x6)
3999 break;
4000 else
4001 idac_bs++;
4002 } else {
4003 break;
4004 }
4005 }
4006 }
4007
4008 boolean
_lok_load_default_8822c(void * dm_void,u8 path)4009 _lok_load_default_8822c(void *dm_void, u8 path)
4010 {
4011 struct dm_struct *dm = (struct dm_struct *)dm_void;
4012 struct dm_iqk_info *iqk_info = &dm->IQK_info;
4013 struct _hal_rf_ *rf = &dm->rf_table;
4014 u32 temp;
4015 u8 idac_i, idac_q;
4016 u8 i;
4017
4018 _iqk_cal_path_off_8822c(dm);
4019 odm_write_4byte(dm, 0x1b00, 0x8 | path << 1);
4020
4021 temp = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x58, 0xfffff);
4022 //RF_DBG(dm, DBG_RF_IQK, "[IQK](1)setlut_0x58 = 0x%x\n", temp);
4023 idac_i = (u8)((temp & 0xfc000) >> 14);
4024 idac_q = (u8)((temp & 0x3f00) >> 8);
4025
4026 if (!(idac_i == 0x0 || idac_i == 0x3f || idac_q == 0x0 || idac_q == 0x3f)) {
4027 RF_DBG(dm, DBG_RF_IQK, "[IQK]LOK 0x58 = 0x%x\n", temp);
4028 return false;
4029 }
4030
4031 idac_i = 0x20;
4032 idac_q = 0x20;
4033
4034 odm_set_rf_reg(dm, (enum rf_path)path, 0x57, BIT(0), 0x0);
4035 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(4), 0x1);
4036
4037 if (*dm->band_type == ODM_BAND_2_4G)
4038 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, 0x7f, 0x0);
4039 else
4040 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, 0x7f, 0x20);
4041
4042 //_iqk_rf_direct_access_8822c(dm, (enum rf_path)path, false);
4043
4044 odm_set_rf_reg(dm, (enum rf_path)path, 0x08, 0x003f0, idac_i);
4045 odm_set_rf_reg(dm, (enum rf_path)path, 0x08, 0xfc000, idac_q);
4046
4047 temp = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x08, 0xfffff);
4048 RF_DBG(dm, DBG_RF_IQK, "[IQK](2)setlut_0x08 = 0x%x\n", temp);
4049
4050 temp = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x58, 0xfffff);
4051 RF_DBG(dm, DBG_RF_IQK, "[IQK](2)setlut_0x58 = 0x%x\n", temp);
4052
4053 //_iqk_rf_direct_access_8822c(dm, (enum rf_path)path, true);
4054
4055 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(4), 0x0);
4056
4057 return true;
4058
4059 }
4060
_iqk_iqk_by_path_8822c(void * dm_void,boolean segment_iqk)4061 void _iqk_iqk_by_path_8822c(
4062 void *dm_void,
4063 boolean segment_iqk)
4064 {
4065 struct dm_struct *dm = (struct dm_struct *)dm_void;
4066 struct dm_iqk_info *iqk_info = &dm->IQK_info;
4067 boolean KFAIL = true, is_NB_IQK = false;
4068 u8 i= 0x0, kcount_limit, path;
4069 u32 counter = 0x0;
4070
4071 if ((*dm->band_width == CHANNEL_WIDTH_5) ||(*dm->band_width == CHANNEL_WIDTH_10))
4072 is_NB_IQK = true;
4073
4074 #if 1
4075 switch (iqk_info->iqk_step) {
4076 case 0: /*S0 RXIQK*/
4077 #if 1
4078 counter = 0x0;
4079 while (1) {
4080 counter++;
4081 KFAIL = _iqk_rx_iqk_by_path_8822c(dm, RF_PATH_A);
4082 //RF_DBG(dm, DBG_RF_IQK, "[IQK]S0RXK KFail = 0x%x\n", KFAIL);
4083 if ((!KFAIL) && (iqk_info->rxiqk_step == RXK_STEP_8822C)){ //do lok
4084 iqk_info->iqk_step++;
4085 iqk_info->rxiqk_step = 0;
4086 if (KFAIL)
4087 RF_DBG(dm, DBG_RF_IQK, "[IQK]S0RXK fail code: %d!!!\n", iqk_info->rxiqk_fail_code[0][RF_PATH_A]);
4088 break;
4089 }
4090
4091 if ((counter > 60) && (iqk_info->rxiqk_step == 0x0)) { // do lok
4092 iqk_info->iqk_step++;
4093 RF_DBG(dm, DBG_RF_IQK, "[IQK] counter > 10\n");
4094 break;
4095 }
4096 }
4097 //_iqk_get_rxcfir_8822c(dm, RF_PATH_A, 0);
4098 //_iqk_rx_cfir_8822c(dm, RF_PATH_A);
4099 iqk_info->kcount++;
4100 #else
4101 iqk_info->iqk_step++;
4102 #endif
4103 break;
4104
4105 case 1: /*S0 LOK*/
4106 #if 1
4107 _iqk_lok_tune_8822c(dm, RF_PATH_A);
4108 //if(_lok_load_default_8822c(dm, RF_PATH_A))
4109 // RF_DBG(dm, DBG_RF_IQK, "[IQK]S1 Load LOK to default\n");
4110
4111 #endif
4112 iqk_info->iqk_step++;
4113 break;
4114 case 2: /*S0 TXIQK*/
4115 #if 1
4116 _iqk_txk_setting_8822c(dm, RF_PATH_A);
4117 KFAIL = _iqk_one_shot_8822c(dm, RF_PATH_A, TXIQK);
4118 odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(4), 0x0);
4119 iqk_info->kcount++;
4120 RF_DBG(dm, DBG_RF_IQK, "[IQK]S0TXK KFail = 0x%x\n", KFAIL);
4121 iqk_info->iqk_step++;
4122
4123 //RF_DBG(dm, DBG_RF_IQK, "[CC]CFIR after S0 TXIQK\n");
4124 //_iqk_rx_cfir_8822c(dm, RF_PATH_A);
4125
4126 #else
4127 iqk_info->iqk_step++;
4128 #endif
4129 break;
4130 case 3: /*S1 RXIQK*/
4131 #if 1
4132 counter = 0x0;
4133 while (1) {
4134 counter++;
4135 KFAIL = _iqk_rx_iqk_by_path_8822c(dm, RF_PATH_B);
4136 //_DBG(dm, DBG_RF_IQK, "[IQK]S1RXK KFail = 0x%x\n", KFAIL);
4137
4138 if ((!KFAIL) && (iqk_info->rxiqk_step == RXK_STEP_8822C)){ //do lok
4139 iqk_info->iqk_step++;
4140 iqk_info->rxiqk_step = 0;
4141 if (KFAIL)
4142 RF_DBG(dm, DBG_RF_IQK, "[IQK]S1RXK fail code: %d!!!\n", iqk_info->rxiqk_fail_code[0][RF_PATH_B]);
4143 break;
4144 }
4145
4146 if ((counter > 60) && (iqk_info->rxiqk_step == 0x0)) { // do lok
4147 iqk_info->iqk_step++;
4148 RF_DBG(dm, DBG_RF_IQK, "[IQK] counter > 10\n");
4149 break;
4150 }
4151 }
4152 iqk_info->kcount++;
4153 //RF_DBG(dm, DBG_RF_IQK, "[CC]CFIR after S1 RXIQK\n");
4154 //_iqk_get_rxcfir_8822c(dm, RF_PATH_B, 0);
4155 //_iqk_rx_cfir_8822c(dm,RF_PATH_B);
4156 #else
4157 iqk_info->iqk_step++;
4158 #endif
4159 break;
4160
4161 case 4: /*S1 LOK*/
4162 #if 1
4163 _iqk_lok_tune_8822c(dm, RF_PATH_B);
4164 //if(_lok_load_default_8822c(dm, RF_PATH_B))
4165 // RF_DBG(dm, DBG_RF_IQK, "[IQK]S1 Load LOK to default\n");
4166
4167 #endif
4168 iqk_info->iqk_step++;
4169 break;
4170
4171 case 5: /*S1 TXIQK*/
4172 #if 1
4173 _iqk_txk_setting_8822c(dm, RF_PATH_B);
4174 KFAIL = _iqk_one_shot_8822c(dm, RF_PATH_B, TXIQK);
4175 odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(4), 0x0);
4176 iqk_info->kcount++;
4177 RF_DBG(dm, DBG_RF_IQK, "[IQK]S1TXK KFail = 0x%x\n", KFAIL);
4178 if (KFAIL && iqk_info->retry_count[0][RF_PATH_B][TXIQK] < 3)
4179 iqk_info->retry_count[0][RF_PATH_B][TXIQK]++;
4180 else
4181 iqk_info->iqk_step++;
4182 //RF_DBG(dm, DBG_RF_IQK, "[CC]CFIR after S1 TXIQK\n");
4183 //_iqk_rx_cfir_8822c(dm, RF_PATH_B);
4184 #else
4185 iqk_info->iqk_step++;
4186 #endif
4187 break;
4188 case 6: /*IDFT*/
4189 #if 0
4190 RF_DBG(dm, DBG_RF_IQK, "[CC]IDFT\n");
4191 _iqk_idft(dm);
4192 iqk_info->iqk_step++;
4193 #else
4194 iqk_info->iqk_step++;
4195 #endif
4196 break;
4197 }
4198
4199 if (iqk_info->iqk_step == IQK_STEP_8822C) {
4200 RF_DBG(dm, DBG_RF_IQK, "[IQK]========LOK summary =========\n");
4201 RF_DBG(dm, DBG_RF_IQK, "[IQK]S0_LOK_fail= %d, S1_LOK_fail= %d\n",
4202 iqk_info->lok_fail[RF_PATH_A],
4203 iqk_info->lok_fail[RF_PATH_B]);
4204 RF_DBG(dm, DBG_RF_IQK, "[IQK]========IQK summary ==========\n");
4205 RF_DBG(dm, DBG_RF_IQK, "[IQK]S0_TXIQK_fail = %d, S1_TXIQK_fail = %d\n"
4206 ,iqk_info->iqk_fail_report[0][RF_PATH_A][TXIQK],
4207 iqk_info->iqk_fail_report[0][RF_PATH_B][TXIQK]);
4208 RF_DBG(dm, DBG_RF_IQK, "[IQK]S0_RXIQK_fail= %d, S1_RXIQK_fail= %d\n"
4209 ,iqk_info->iqk_fail_report[0][RF_PATH_A][RXIQK],
4210 iqk_info->iqk_fail_report[0][RF_PATH_B][RXIQK]);
4211 RF_DBG(dm, DBG_RF_IQK, "[IQK]S0_TK_retry = %d, S1_TXIQK_retry = %d\n"
4212 ,iqk_info->retry_count[0][RF_PATH_A][TXIQK],
4213 iqk_info->retry_count[0][RF_PATH_B][TXIQK]);
4214 RF_DBG(dm, DBG_RF_IQK, "[IQK]S0_RXK1_retry = %d, S0_RXK2_retry = %d\n"
4215 ,iqk_info->retry_count[0][RF_PATH_A][RXIQK1],
4216 iqk_info->retry_count[0][RF_PATH_A][RXIQK2]);
4217 RF_DBG(dm, DBG_RF_IQK, "[IQK]S2_RXK1_retry = %d, S2_RXK2_retry = %d\n"
4218 ,iqk_info->retry_count[0][RF_PATH_B][RXIQK1],
4219 iqk_info->retry_count[0][RF_PATH_B][RXIQK2]);
4220 RF_DBG(dm, DBG_RF_IQK, "[IQK]S0_GS1_retry = %d, S0_GS2_retry = %d, S1_GS1_retry = %d, S1_GS2_retry = %d\n"
4221 ,iqk_info->gs_retry_count[0][RF_PATH_A][0],
4222 iqk_info->gs_retry_count[0][RF_PATH_A][1],
4223 iqk_info->gs_retry_count[0][RF_PATH_B][0],
4224 iqk_info->gs_retry_count[0][RF_PATH_B][1]);
4225
4226 for (path = 0; path < SS_8822C; path++) {
4227 odm_set_bb_reg(dm, 0x1b00, bMaskDWord, 0x8 | path << 1);
4228 odm_set_bb_reg(dm, 0x1bb8, BIT(20), 0x0);
4229 odm_set_bb_reg(dm, 0x1bcc, MASKBYTE0, 0x0);
4230 if (is_NB_IQK) {
4231 odm_set_bb_reg(dm, R_0x1b20, BIT(26), 0x0);
4232 odm_set_bb_reg(dm, 0x1b38, MASKDWORD, iqk_info->nbtxk_1b38[path]);
4233 odm_set_bb_reg(dm, 0x1b3c, MASKDWORD, iqk_info->nbrxk_1b3c[path]);
4234 } else {
4235 odm_set_bb_reg(dm, R_0x1b20, BIT(26), 0x1);
4236 odm_set_bb_reg(dm, 0x1b38, MASKDWORD, 0x40000000);
4237 odm_set_bb_reg(dm, 0x1b3c, MASKDWORD, 0x40000000);
4238 }
4239 // force return to rx mode
4240 odm_set_rf_reg(dm, path, RF_0x0, 0xf0000, 0x3);
4241
4242 RF_DBG(dm, DBG_RF_IQK, "[IQK]1b38= 0x%x, 1b3c= 0x%x\n",
4243 iqk_info->nbtxk_1b38[path],
4244 iqk_info->nbrxk_1b3c[path]);
4245 }
4246
4247
4248 }
4249 #endif
4250
4251 }
4252
_iqk_dpd_in_sel(struct dm_struct * dm,u8 input)4253 void _iqk_dpd_in_sel(
4254 struct dm_struct *dm,
4255 u8 input)
4256 {
4257 u8 path;
4258 /*input =1: DPD input = single tone, 0: DPD input = OFDM*/
4259 for (path = 0; path < SS_8822C; path++) {
4260 odm_write_4byte(dm, 0x1b00, IQK_CMD_8822C | (path << 1));
4261 /*dpd_in_sel*/
4262 odm_set_bb_reg(dm, 0x1bcc, BIT(13), input);
4263 }
4264
4265 }
4266
_iqk_start_iqk_8822c(struct dm_struct * dm,boolean segment_iqk)4267 void _iqk_start_iqk_8822c(
4268 struct dm_struct *dm,
4269 boolean segment_iqk)
4270 {
4271 struct dm_iqk_info *iqk_info = &dm->IQK_info;
4272 u8 i = 0;
4273 u8 kcount_limit;
4274
4275 if (*dm->band_width == 2)
4276 kcount_limit = kcount_limit_80m;
4277 else
4278 kcount_limit = kcount_limit_others;
4279
4280 while (i < 100) {
4281 _iqk_iqk_by_path_8822c(dm, segment_iqk);
4282
4283 if (iqk_info->iqk_step == IQK_STEP_8822C)
4284 break;
4285 if (segment_iqk && (iqk_info->kcount == kcount_limit))
4286 break;
4287 i++;
4288 }
4289 }
4290
_iq_calibrate_8822c_init(struct dm_struct * dm)4291 void _iq_calibrate_8822c_init(
4292 struct dm_struct *dm)
4293 {
4294 struct dm_iqk_info *iqk_info = &dm->IQK_info;
4295 u8 i, j, k, m;
4296 static boolean firstrun = true;
4297
4298 if (firstrun) {
4299 firstrun = false;
4300 RF_DBG(dm, DBG_RF_IQK, "[IQK]=====>PHY_IQCalibrate_8822c_Init\n");
4301
4302 for (i = 0; i < SS_8822C; i++) {
4303 for (j = 0; j < 2; j++) {
4304 iqk_info->lok_fail[i] = true;
4305 iqk_info->iqk_fail[j][i] = true;
4306 iqk_info->iqc_matrix[j][i] = 0x20000000;
4307 }
4308 }
4309
4310 for (i = 0; i < 2; i++) {
4311 iqk_info->iqk_channel[i] = 0x0;
4312
4313 for (j = 0; j < SS_8822C; j++) {
4314 iqk_info->lok_idac[i][j] = 0x0;
4315 iqk_info->rxiqk_agc[i][j] = 0x0;
4316 iqk_info->bypass_iqk[i][j] = 0x0;
4317
4318 for (k = 0; k < 2; k++) {
4319 iqk_info->iqk_fail_report[i][j][k] = true;
4320 for (m = 0; m <= 16; m++) {
4321 iqk_info->iqk_cfir_real[i][j][k][m] = 0x0;
4322 iqk_info->iqk_cfir_imag[i][j][k][m] = 0x0;
4323 }
4324 }
4325
4326 for (k = 0; k < 3; k++)
4327 iqk_info->retry_count[i][j][k] = 0x0;
4328 }
4329 }
4330 }
4331
4332 }
4333
4334 boolean
_iqk_rximr_rxk1_test_8822c(struct dm_struct * dm,u8 path,u32 tone_index)4335 _iqk_rximr_rxk1_test_8822c(
4336 struct dm_struct *dm,
4337 u8 path,
4338 u32 tone_index)
4339 {
4340 struct dm_iqk_info *iqk_info = &dm->IQK_info;
4341 boolean fail = true;
4342 u32 IQK_CMD;
4343
4344 odm_write_4byte(dm, 0x1b00, 0x8 | path << 1);
4345 odm_write_4byte(dm, 0x1b20, (odm_read_4byte(dm, 0x1b20) & 0x000fffff) | ((tone_index & 0xfff) << 20));
4346 odm_write_4byte(dm, 0x1b24, (odm_read_4byte(dm, 0x1b24) & 0x000fffff) | ((tone_index & 0xfff) << 20));
4347
4348 IQK_CMD = 0xf8000208 | (1 << (path + 4));
4349 odm_write_4byte(dm, 0x1b00, IQK_CMD);
4350 odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);
4351
4352 fail = _iqk_check_cal_8822c(dm, path, 0x1);
4353 return fail;
4354 }
4355
_iqk_tximr_selfcheck_8822c(void * dm_void,u8 tone_index,u8 path)4356 u32 _iqk_tximr_selfcheck_8822c(
4357 void *dm_void,
4358 u8 tone_index,
4359 u8 path)
4360 {
4361 u32 tx_ini_power_H[2], tx_ini_power_L[2];
4362 u32 tmp1, tmp2, tmp3, tmp4, tmp5;
4363 u32 IQK_CMD;
4364 u32 tximr = 0x0;
4365 u8 i;
4366
4367 struct dm_struct *dm = (struct dm_struct *)dm_void;
4368 /*backup*/
4369 odm_write_4byte(dm, 0x1b00, 0x8 | path << 1);
4370 odm_write_4byte(dm, 0x1bc8, 0x80000000);
4371 odm_write_4byte(dm, 0x8f8, 0x41400080);
4372 tmp1 = odm_read_4byte(dm, 0x1b0c);
4373 tmp2 = odm_read_4byte(dm, 0x1b14);
4374 tmp3 = odm_read_4byte(dm, 0x1b1c);
4375 tmp4 = odm_read_4byte(dm, 0x1b20);
4376 tmp5 = odm_read_4byte(dm, 0x1b24);
4377 /*setup*/
4378 odm_write_4byte(dm, 0x1b0c, 0x00003000);
4379 odm_write_4byte(dm, 0x1b1c, 0xA2193C32);
4380 odm_write_1byte(dm, 0x1b15, 0x00);
4381 odm_write_4byte(dm, 0x1b20, (u32)(tone_index << 20 | 0x00040008));
4382 odm_write_4byte(dm, 0x1b24, (u32)(tone_index << 20 | 0x00060008));
4383 odm_write_4byte(dm, 0x1b2c, 0x07);
4384 odm_write_4byte(dm, 0x1b38, 0x40000000);
4385 odm_write_4byte(dm, 0x1b3c, 0x40000000);
4386 /* ======derive pwr1========*/
4387 for (i = 0; i < 2; i++) {
4388 odm_write_4byte(dm, 0x1b00, 0x8 | path << 1);
4389 if (i == 0)
4390 odm_write_1byte(dm, 0x1bcc, 0x0f);
4391 else
4392 odm_write_1byte(dm, 0x1bcc, 0x09);
4393 /* One Shot*/
4394 IQK_CMD = 0x00000800;
4395 odm_write_4byte(dm, 0x1b34, IQK_CMD + 1);
4396 odm_write_4byte(dm, 0x1b34, IQK_CMD);
4397 halrf_delay_10us(100);
4398 odm_write_4byte(dm, 0x1bd4, 0x00040001);
4399 tx_ini_power_H[i] = odm_read_4byte(dm, 0x1bfc);
4400 odm_write_4byte(dm, 0x1bd4, 0x000C0001);
4401 tx_ini_power_L[i] = odm_read_4byte(dm, 0x1bfc);
4402 }
4403 /*restore*/
4404 odm_write_4byte(dm, 0x1b00, 0x8 | path << 1);
4405 odm_write_4byte(dm, 0x1b0c, tmp1);
4406 odm_write_4byte(dm, 0x1b14, tmp2);
4407 odm_write_4byte(dm, 0x1b1c, tmp3);
4408 odm_write_4byte(dm, 0x1b20, tmp4);
4409 odm_write_4byte(dm, 0x1b24, tmp5);
4410
4411 if (tx_ini_power_H[1] == tx_ini_power_H[0])
4412 tximr = (3 * (halrf_psd_log2base(tx_ini_power_L[0] << 2) - halrf_psd_log2base(tx_ini_power_L[1]))) / 100;
4413 else
4414 tximr = 0;
4415 return tximr;
4416 }
4417
_iqk_start_tximr_test_8822c(struct dm_struct * dm,u8 imr_limit)4418 void _iqk_start_tximr_test_8822c(
4419 struct dm_struct *dm,
4420 u8 imr_limit)
4421 {
4422 boolean KFAIL;
4423 u8 path, i, tone_index;
4424 u32 imr_result;
4425
4426 for (path = 0; path < SS_8822C; path++) {
4427 _iqk_txk_setting_8822c(dm, path);
4428 KFAIL = _iqk_one_shot_8822c(dm, path, TXIQK);
4429 for (i = 0x0; i < imr_limit; i++) {
4430 tone_index = (u8)(0x08 | i << 4);
4431 imr_result = _iqk_tximr_selfcheck_8822c(dm, tone_index, path);
4432 RF_DBG(dm, DBG_RF_IQK, "[IQK]path=%x, toneindex = %x, TXIMR = %d\n", path, tone_index, imr_result);
4433 }
4434 RF_DBG(dm, DBG_RF_IQK, "\n");
4435 }
4436 }
4437
_iqk_rximr_selfcheck_8822c(void * dm_void,u32 tone_index,u8 path,u32 tmp1b38)4438 u32 _iqk_rximr_selfcheck_8822c(
4439 void *dm_void,
4440 u32 tone_index,
4441 u8 path,
4442 u32 tmp1b38)
4443 {
4444 u32 rx_ini_power_H[2], rx_ini_power_L[2]; /*[0]: psd tone; [1]: image tone*/
4445 u32 tmp1, tmp2, tmp3, tmp4, tmp5;
4446 u32 IQK_CMD, tmp1bcc;
4447 u8 i, num_k1, rximr_step, count = 0x0;
4448 u32 rximr = 0x0;
4449 boolean KFAIL = true;
4450
4451 struct dm_struct *dm = (struct dm_struct *)dm_void;
4452 struct dm_iqk_info *iqk_info = &dm->IQK_info;
4453
4454 /*backup*/
4455 odm_write_4byte(dm, 0x1b00, 0x8 | path << 1);
4456 tmp1 = odm_read_4byte(dm, 0x1b0c);
4457 tmp2 = odm_read_4byte(dm, 0x1b14);
4458 tmp3 = odm_read_4byte(dm, 0x1b1c);
4459 tmp4 = odm_read_4byte(dm, 0x1b20);
4460 tmp5 = odm_read_4byte(dm, 0x1b24);
4461
4462 odm_write_4byte(dm, 0x1b0c, 0x00001000);
4463 odm_write_1byte(dm, 0x1b15, 0x00);
4464 odm_write_4byte(dm, 0x1b1c, 0x82193d31);
4465 odm_write_4byte(dm, 0x1b20, (u32)(tone_index << 20 | 0x00040008));
4466 odm_write_4byte(dm, 0x1b24, (u32)(tone_index << 20 | 0x00060048));
4467 odm_write_4byte(dm, 0x1b2c, 0x07);
4468 odm_write_4byte(dm, 0x1b38, tmp1b38);
4469 odm_write_4byte(dm, 0x1b3c, 0x40000000);
4470
4471 for (i = 0; i < 2; i++) {
4472 if (i == 0)
4473 odm_write_4byte(dm, 0x1b1c, 0x82193d31);
4474 else
4475 odm_write_4byte(dm, 0x1b1c, 0xa2193d31);
4476 IQK_CMD = 0x00000800;
4477 odm_write_4byte(dm, 0x1b34, IQK_CMD + 1);
4478 odm_write_4byte(dm, 0x1b34, IQK_CMD);
4479 halrf_delay_10us(100);
4480 odm_write_1byte(dm, 0x1bd6, 0xb);
4481 while (count < 100) {
4482 count++;
4483 if (odm_get_bb_reg(dm, R_0x1bfc, BIT(1)) == 1)
4484 break;
4485 else
4486 halrf_delay_10us(100);
4487 }
4488 if (1) {
4489 odm_write_1byte(dm, 0x1bd6, 0x5);
4490 rx_ini_power_H[i] = odm_read_4byte(dm, 0x1bfc);
4491 odm_write_1byte(dm, 0x1bd6, 0xe);
4492 rx_ini_power_L[i] = odm_read_4byte(dm, 0x1bfc);
4493 } else {
4494 rx_ini_power_H[i] = 0x0;
4495 rx_ini_power_L[i] = 0x0;
4496 }
4497 }
4498 /*restore*/
4499 odm_write_4byte(dm, 0x1b0c, tmp1);
4500 odm_write_4byte(dm, 0x1b14, tmp2);
4501 odm_write_4byte(dm, 0x1b1c, tmp3);
4502 odm_write_4byte(dm, 0x1b20, tmp4);
4503 odm_write_4byte(dm, 0x1b24, tmp5);
4504 for (i = 0; i < 2; i++)
4505 rx_ini_power_H[i] = (rx_ini_power_H[i] & 0xf8000000) >> 27;
4506
4507 if (rx_ini_power_H[0] != rx_ini_power_H[1])
4508 switch (rx_ini_power_H[0]) {
4509 case 1:
4510 rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 1) | 0x80000000);
4511 rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 1;
4512 break;
4513 case 2:
4514 rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 2) | 0x80000000);
4515 rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 2;
4516 break;
4517 case 3:
4518 rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 2) | 0xc0000000);
4519 rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 2;
4520 break;
4521 case 4:
4522 rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 3) | 0x80000000);
4523 rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 3;
4524 break;
4525 case 5:
4526 rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 3) | 0xa0000000);
4527 rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 3;
4528 break;
4529 case 6:
4530 rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 3) | 0xc0000000);
4531 rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 3;
4532 break;
4533 case 7:
4534 rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 3) | 0xe0000000);
4535 rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 3;
4536 break;
4537 default:
4538 break;
4539 }
4540 rximr = (u32)(3 * ((halrf_psd_log2base(rx_ini_power_L[0] / 100) - halrf_psd_log2base(rx_ini_power_L[1] / 100))) / 100);
4541 /*
4542 RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%x, 0x%x, 0x%x, 0x%x,0x%x, tone_index=%x, rximr= %d\n",
4543 (path == 0) ? "PATH A RXIMR ": "PATH B RXIMR",
4544 rx_ini_power_H[0], rx_ini_power_L[0], rx_ini_power_H[1], rx_ini_power_L[1], tmp1bcc, tone_index, rximr);
4545 */
4546 return rximr;
4547 }
4548
_iqk_rximr_test_8822c(struct dm_struct * dm,u8 path,u8 imr_limit)4549 void _iqk_rximr_test_8822c(
4550 struct dm_struct *dm,
4551 u8 path,
4552 u8 imr_limit)
4553 {
4554 struct dm_iqk_info *iqk_info = &dm->IQK_info;
4555 boolean kfail;
4556 u8 i, step, count, side;
4557 u32 imr_result = 0, tone_index;
4558 u32 temp = 0, temp1b38[2][15];
4559 char *freq[15] = {"1.25MHz", "3.75MHz", "6.25MHz", "8.75MHz", "11.25MHz",
4560 "13.75MHz", "16.25MHz", "18.75MHz", "21.25MHz", "23.75MHz",
4561 "26.25MHz", "28.75MHz", "31.25MHz", "33.75MHz", "36.25MHz"};
4562
4563 for (step = 1; step < 5; step++) {
4564 count = 0;
4565 switch (step) {
4566 case 1: /*gain search_RXK1*/
4567 _iqk_rxk1_setting_8822c(dm, path);
4568 while (count < 3) {
4569 kfail = _iqk_rx_iqk_gain_search_fail_8822c(dm, path, RXIQK1);
4570 RF_DBG(dm, DBG_RF_IQK, "[IQK]path = %x, kfail = %x\n", path, kfail);
4571 if (kfail) {
4572 count++;
4573 if (count == 3)
4574 step = 5;
4575 } else {
4576 break;
4577 }
4578 }
4579 break;
4580 case 2: /*gain search_RXK2*/
4581 _iqk_rxk2_setting_8822c(dm, path, true);
4582 iqk_info->isbnd = false;
4583 while (count < 8) {
4584 kfail = _iqk_rx_iqk_gain_search_fail_8822c(dm, path, RXIQK2);
4585 RF_DBG(dm, DBG_RF_IQK, "[IQK]path = %x, kfail = %x\n", path, kfail);
4586 if (kfail) {
4587 count++;
4588 if (count == 8)
4589 step = 5;
4590 } else {
4591 break;
4592 }
4593 }
4594 break;
4595 case 3: /*get RXK1 IQC*/
4596 odm_write_4byte(dm, 0x1b00, 0x8 | path << 1);
4597 temp = odm_read_4byte(dm, 0x1b1c);
4598 for (side = 0; side < 2; side++) {
4599 for (i = 0; i < imr_limit; i++) {
4600 if (side == 0)
4601 tone_index = 0xff8 - (i << 4);
4602 else
4603 tone_index = 0x08 | (i << 4);
4604 while (count < 3) {
4605 _iqk_rxk1_setting_8822c(dm, path);
4606 kfail = _iqk_rximr_rxk1_test_8822c(dm, path, tone_index);
4607 RF_DBG(dm, DBG_RF_IQK, "[IQK]path = %x, kfail = %x\n", path, kfail);
4608 if (kfail) {
4609 count++;
4610 if (count == 3) {
4611 step = 5;
4612 temp1b38[side][i] = 0x20000000;
4613 RF_DBG(dm, DBG_RF_IQK, "[IQK]path = %x, toneindex = %x rxk1 fail\n", path, tone_index);
4614 }
4615 } else {
4616 odm_write_4byte(dm, 0x1b00, 0x8 | path << 1);
4617 odm_write_4byte(dm, 0x1b1c, 0xa2193c32);
4618 odm_write_4byte(dm, 0x1b14, 0xe5);
4619 odm_write_4byte(dm, 0x1b14, 0x0);
4620 temp1b38[side][i] = odm_read_4byte(dm, 0x1b38);
4621 RF_DBG(dm, DBG_RF_IQK, "[IQK]path = 0x%x, tone_idx = 0x%x, tmp1b38 = 0x%x\n", path, tone_index, temp1b38[side][i]);
4622 break;
4623 }
4624 }
4625 }
4626 }
4627 break;
4628 case 4: /*get RX IMR*/
4629 for (side = 0; side < 2; side++) {
4630 for (i = 0x0; i < imr_limit; i++) {
4631 if (side == 0)
4632 tone_index = 0xff8 - (i << 4);
4633 else
4634 tone_index = 0x08 | (i << 4);
4635 _iqk_rxk2_setting_8822c(dm, path, false);
4636 imr_result = _iqk_rximr_selfcheck_8822c(dm, tone_index, path, temp1b38[side][i]);
4637 RF_DBG(dm, DBG_RF_IQK, "[IQK]tone_idx = 0x%5x, freq = %s%10s, RXIMR = %5d dB\n", tone_index, (side == 0) ? "-" : " ", freq[i], imr_result);
4638 }
4639 odm_write_4byte(dm, 0x1b00, 0x8 | path << 1);
4640 odm_write_4byte(dm, 0x1b1c, temp);
4641 odm_write_4byte(dm, 0x1b38, 0x20000000);
4642 }
4643 break;
4644 }
4645 }
4646 }
4647
_iqk_start_rximr_test_8822c(struct dm_struct * dm,u8 imr_limit)4648 void _iqk_start_rximr_test_8822c(
4649 struct dm_struct *dm,
4650 u8 imr_limit)
4651 {
4652 u8 path;
4653
4654 for (path = 0; path < SS_8822C; path++)
4655 _iqk_rximr_test_8822c(dm, path, imr_limit);
4656 }
4657
_iqk_start_imr_test_8822c(void * dm_void)4658 void _iqk_start_imr_test_8822c(
4659 void *dm_void)
4660 {
4661 u8 imr_limit;
4662
4663 struct dm_struct *dm = (struct dm_struct *)dm_void;
4664 struct dm_iqk_info *iqk_info = &dm->IQK_info;
4665
4666 if (*dm->band_width == 2)
4667 imr_limit = 0xf;
4668 else if (*dm->band_width == 1)
4669 imr_limit = 0x8;
4670 else
4671 imr_limit = 0x4;
4672 // _iqk_start_tximr_test_8822c(dm, imr_limit);
4673 _iqk_start_rximr_test_8822c(dm, imr_limit);
4674 }
4675
4676
4677
_phy_iq_calibrate_8822c(struct dm_struct * dm,boolean reset,boolean segment_iqk)4678 void _phy_iq_calibrate_8822c(
4679 struct dm_struct *dm,
4680 boolean reset,
4681 boolean segment_iqk)
4682 {
4683 u32 MAC_backup[MAC_REG_NUM_8822C] = {0};
4684 u32 BB_backup[BB_REG_NUM_8822C] = {0};
4685 u32 RF_backup[RF_REG_NUM_8822C][SS_8822C] = {{0}};
4686 u32 backup_mac_reg[MAC_REG_NUM_8822C] = {0x520, 0x1c, 0x70};
4687 u32 backup_bb_reg[BB_REG_NUM_8822C] = {
4688 0x0820, 0x0824, 0x1c38, 0x1c68,
4689 0x1d60, 0x180c, 0x410c, 0x1c3c,
4690 0x1a14, 0x1d58, 0x1d70, R_0x1864,
4691 R_0x4164, R_0x186c, R_0x416c, R_0x1a14,
4692 R_0x1e70, R_0x80c, R_0x1e7c, R_0x18a4,
4693 R_0x41a4};
4694 u32 backup_rf_reg[RF_REG_NUM_8822C] = {0x19, 0xdf, 0x9e};
4695 boolean is_mp = false;
4696 u8 i = 0;
4697
4698 struct dm_iqk_info *iqk_info = &dm->IQK_info;
4699
4700 if (*dm->mp_mode)
4701 is_mp = true;
4702 else
4703 is_mp = false;
4704 #if 0
4705 if (!is_mp)
4706 if (_iqk_reload_iqk_8822c(dm, reset))
4707 return;
4708 #endif
4709 iqk_info->rf_reg18 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREGOFFSETMASK);
4710
4711 RF_DBG(dm, DBG_RF_IQK, "[IQK]==========IQK strat!!!!!==========\n");
4712 RF_DBG(dm, DBG_RF_IQK, "[IQK]band_type = %s, band_width = %d, ExtPA2G = %d, ext_pa_5g = %d\n", (*dm->band_type == ODM_BAND_5G) ? "5G" : "2G", *dm->band_width, dm->ext_pa, dm->ext_pa_5g);
4713 RF_DBG(dm, DBG_RF_IQK, "[IQK]Interface = %d, Cv = %x\n", dm->support_interface, dm->cut_version);
4714 RF_DBG(dm, DBG_RF_IQK, "[IQK] Test V15 \n");
4715 iqk_info->iqk_times++;
4716 iqk_info->kcount = 0;
4717 iqk_info->iqk_step = 0;
4718 iqk_info->rxiqk_step = 0;
4719 iqk_info->tmp_gntwl = _iqk_btc_read_indirect_reg_8822c(dm, 0x38);
4720
4721 _iqk_information_8822c(dm);
4722 _iqk_backup_iqk_8822c(dm, 0x0, 0x0);
4723 _iqk_backup_mac_bb_8822c(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg);
4724 _iqk_backup_rf_8822c(dm, RF_backup, backup_rf_reg);
4725
4726 while (i < 3) {
4727 i++;
4728 _iqk_macbb_8822c(dm);
4729 _iqk_bb_for_dpk_setting_8822c(dm);
4730 _iqk_afe_setting_8822c(dm, true);
4731 _iqk_agc_bnd_int_8822c(dm);
4732 _iqk_start_iqk_8822c(dm, segment_iqk);
4733 _iqk_afe_setting_8822c(dm, false);
4734 _iqk_restore_rf_8822c(dm, backup_rf_reg, RF_backup);
4735 _iqk_restore_mac_bb_8822c(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg);
4736 if (iqk_info->iqk_step == IQK_STEP_8822C)
4737 break;
4738 iqk_info->kcount = 0;
4739 RF_DBG(dm, DBG_RF_IQK, "[IQK]delay 50ms!!!\n");
4740 halrf_delay_10us(500);
4741 };
4742
4743 _iqk_fill_iqk_report_8822c(dm, 0);
4744 #if 0
4745 /*check cfir value*/
4746 _iqk_get_rxcfir_8822c(dm, RF_PATH_A , 1);
4747 _iqk_get_rxcfir_8822c(dm, RF_PATH_B , 1);
4748 _iqk_rx_cfir_check_8822c(dm, 1);
4749
4750 _iqk_rx_cfir_8822c(dm, RF_PATH_A);
4751 _iqk_rx_cfir_8822c(dm, RF_PATH_B);
4752 #endif
4753 RF_DBG(dm, DBG_RF_IQK, "[IQK]==========IQK end!!!!!==========\n");
4754 }
4755
_check_fwiqk_done_8822c(struct dm_struct * dm)4756 void _check_fwiqk_done_8822c(struct dm_struct *dm)
4757 {
4758 u32 counter = 0x0;
4759 #if 1
4760 while (1) {
4761 if (odm_read_1byte(dm, 0x2d9c) == 0xaa || counter > 300)
4762 break;
4763 counter++;
4764 halrf_delay_10us(100);
4765 };
4766 odm_write_1byte(dm, 0x1b10, 0x0);
4767 RF_DBG(dm, DBG_RF_IQK, "[IQK]counter = %d\n", counter);
4768 #else
4769 ODM_delay_ms(50);
4770 RF_DBG(dm, DBG_RF_IQK, "[IQK] delay 50ms\n");
4771
4772 #endif
4773 }
4774
4775
_phy_iq_calibrate_by_fw_8822c(void * dm_void,u8 clear,u8 segment_iqk)4776 void _phy_iq_calibrate_by_fw_8822c(
4777 void *dm_void,
4778 u8 clear,
4779 u8 segment_iqk)
4780 {
4781 struct dm_struct *dm = (struct dm_struct *)dm_void;
4782 struct dm_iqk_info *iqk_info = &dm->IQK_info;
4783 enum hal_status status = HAL_STATUS_FAILURE;
4784
4785 if (*dm->mp_mode)
4786 clear = 0x1;
4787 // else if (dm->is_linked)
4788 // segment_iqk = 0x1;
4789
4790 iqk_info->iqk_times++;
4791 status = odm_iq_calibrate_by_fw(dm, clear, segment_iqk);
4792
4793 if (status == HAL_STATUS_SUCCESS)
4794 RF_DBG(dm, DBG_RF_IQK, "[IQK]FWIQK OK!!!\n");
4795 else
4796 RF_DBG(dm, DBG_RF_IQK, "[IQK]FWIQK fail!!!\n");
4797 }
4798
4799 /*IQK_version:0x8, NCTL:0x5*/
4800 /*1.max tx pause while IQK*/
4801 /*2.CCK off while IQK*/
phy_iq_calibrate_8822c(void * dm_void,boolean clear,boolean segment_iqk)4802 void phy_iq_calibrate_8822c(
4803 void *dm_void,
4804 boolean clear,
4805 boolean segment_iqk)
4806 {
4807 struct dm_struct *dm = (struct dm_struct *)dm_void;
4808 struct _hal_rf_ *rf = &dm->rf_table;
4809
4810 if (!(rf->rf_supportability & HAL_RF_IQK))
4811 return;
4812
4813 //if (!(*dm->mp_mode))
4814 // _iqk_check_coex_status(dm, true);
4815
4816 dm->rf_calibrate_info.is_iqk_in_progress = true;
4817 /*FW IQK*/
4818 if (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) {
4819 _phy_iq_calibrate_by_fw_8822c(dm, clear, (u8)(segment_iqk));
4820 _check_fwiqk_done_8822c(dm);
4821 _iqk_check_if_reload(dm);
4822 RF_DBG(dm, DBG_RF_IQK, "!!!!! FW IQK !!!!!\n");
4823 } else {
4824 _iq_calibrate_8822c_init(dm);
4825 _phy_iq_calibrate_8822c(dm, clear, segment_iqk);
4826 }
4827 _iqk_fail_count_8822c(dm);
4828 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
4829 _iqk_iqk_fail_report_8822c(dm);
4830 #endif
4831 halrf_iqk_dbg(dm);
4832
4833 dm->rf_calibrate_info.is_iqk_in_progress = false;
4834
4835 }
4836
iqk_reload_iqk_8822c(void * dm_void,boolean reset)4837 void iqk_reload_iqk_8822c(void *dm_void, boolean reset)
4838 {
4839 struct dm_struct *dm = (struct dm_struct *)dm_void;
4840 struct dm_iqk_info *iqk_info = &dm->IQK_info;
4841
4842 _iqk_reload_iqk_8822c(dm, reset);
4843
4844 }
4845
iqk_get_cfir_8822c(void * dm_void,u8 idx,u8 path,boolean debug)4846 void iqk_get_cfir_8822c(void *dm_void, u8 idx, u8 path, boolean debug)
4847 {
4848 struct dm_struct *dm = (struct dm_struct *)dm_void;
4849 struct dm_iqk_info *iqk_info = &dm->IQK_info;
4850
4851 u8 i, ch;
4852 u32 tmp;
4853 u32 bit_mask_20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
4854
4855 if (debug)
4856 ch = 2;
4857 else
4858 ch = 0;
4859
4860 odm_write_4byte(dm, 0x1b00, 0x8 | path << 1);
4861 #if 0
4862 for (i = 0; i < 0x100/4; i++)
4863 RF_DBG(dm, DBG_RF_DPK, "[IQK] (1) 1b%x = 0x%x\n",
4864 i*4, odm_read_4byte(dm, (0x1b00 + i*4)));
4865 #endif
4866 if (idx == TX_IQK) {//TXCFIR
4867 odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x3);
4868 } else {//RXCFIR
4869 odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x1);
4870 }
4871 odm_set_bb_reg(dm, R_0x1bd4, BIT(21), 0x1);
4872 odm_set_bb_reg(dm, R_0x1bd4, bit_mask_20_16, 0x10);
4873 for (i = 0; i <= 16; i++) {
4874 odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0xe0000001 | i << 2);
4875 tmp = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
4876 iqk_info->iqk_cfir_real[ch][path][idx][i] =
4877 (u16)((tmp & 0x0fff0000) >> 16);
4878 iqk_info->iqk_cfir_imag[ch][path][idx][i] = (u16)(tmp & 0x0fff);
4879 }
4880 #if 0
4881 for (i = 0; i <= 16; i++)
4882 RF_DBG(dm, DBG_RF_IQK, "[IQK](7) cfir_real[0][%d][%d][%x] = %2x\n", path, idx, i, iqk_info->iqk_cfir_real[0][path][idx][i]);
4883 for (i = 0; i <= 16; i++)
4884 RF_DBG(dm, DBG_RF_IQK, "[IQK](7) cfir_imag[0][%d][%d][%x] = %2x\n", path, idx, i, iqk_info->iqk_cfir_imag[0][path][idx][i]);
4885 #endif
4886 odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x0);
4887 //odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);
4888 }
4889
iqk_set_cfir_8822c(void * dm_void,u8 idx,u8 path,boolean debug)4890 void iqk_set_cfir_8822c(void *dm_void, u8 idx, u8 path, boolean debug)
4891 {
4892 struct dm_struct *dm = (struct dm_struct *)dm_void;
4893 struct dm_iqk_info *iqk_info = &dm->IQK_info;
4894
4895 u8 i = 0x0, ch = 0x0;
4896 u32 tmp1 = 0x0, tmp2 = 0x0;
4897 //u32 bit_mask_20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
4898
4899 if (debug)
4900 ch = 2;
4901 else
4902 ch = 0;
4903
4904 odm_write_4byte(dm, 0x1b00, 0x8 | path << 1);
4905
4906 if (idx == TX_IQK) {//TXCFIR
4907 odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x3);
4908 tmp1 = 0xc0000001;
4909 } else {//RXCFIR
4910 odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x1);
4911 tmp1 = 0x60000001;
4912 }
4913
4914 for (i = 0; i <= 16; i++) {
4915 tmp2 = tmp1 | iqk_info->iqk_cfir_real[ch][path][idx][i]<< 8;
4916 tmp2 = (tmp2 | i << 2) + 2;
4917 odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, tmp2);
4918 //RF_DBG(dm, DBG_RF_IQK, "[IQK]iqk_cfir_real = 0x%x\n", tmp2);
4919 }
4920 for (i = 0; i <= 16; i++) {
4921 tmp2 = tmp1 | iqk_info->iqk_cfir_imag[ch][path][idx][i]<< 8;
4922 tmp2 = (tmp2 | i << 2);
4923 odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, tmp2);
4924 //RF_DBG(dm, DBG_RF_IQK, "[IQK]iqk_cfir_imag = 0x%x\n", tmp2);
4925 }
4926
4927 // end for write CFIR SRAM
4928 //odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0xe0000001);
4929 odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x0);
4930 //odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);
4931 }
4932
4933
iqk_clean_cfir_8822c(void * dm_void,u8 mode,u8 path)4934 void iqk_clean_cfir_8822c(void *dm_void, u8 mode, u8 path)
4935 {
4936 struct dm_struct *dm = (struct dm_struct *)dm_void;
4937 struct dm_iqk_info *iqk_info = &dm->IQK_info;
4938 u32 bit_mask_6_2 = 0x7c;
4939 u32 bit_mask_19_8 = 0xfff00;
4940 u8 i = 0x0;
4941 u32 tmp = 0x0;
4942
4943 odm_write_4byte(dm, 0x1b00, 0x8 | path << 1);
4944 //TX_IQK
4945 odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x3);
4946 // clear real part
4947 tmp = 0xc0000003;
4948 for (i =0x0; i<= 16; i++)
4949 odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, tmp | i << 2);
4950 //clear img part
4951 tmp = 0xc0000001;
4952 for (i =0x0; i<= 16; i++)
4953 odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, tmp | i << 2);
4954 //RX_IQK
4955 odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x1);
4956 // clear real part
4957 tmp = 0x60000003;
4958 for (i =0x0; i<= 16; i++)
4959 odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, tmp | i << 2);
4960 //clear img part
4961 tmp = 0x60000001;
4962 for (i =0x0; i<= 16; i++)
4963 odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, tmp | i << 2);
4964
4965 // end for write CFIR SRAM
4966 odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0xe0000001);
4967
4968 }
phy_get_iqk_cfir_8822c(void * dm_void,u8 idx,u8 path,boolean debug)4969 void phy_get_iqk_cfir_8822c(void *dm_void, u8 idx, u8 path, boolean debug)
4970 {
4971 struct dm_struct *dm = (struct dm_struct *)dm_void;
4972 struct dm_iqk_info *iqk_info = &dm->IQK_info;
4973
4974 iqk_get_cfir_8822c(dm, idx, path, debug);
4975 }
4976
4977
phy_iqk_dbg_cfir_backup_8822c(void * dm_void)4978 void phy_iqk_dbg_cfir_backup_8822c(void *dm_void)
4979 {
4980 struct dm_struct *dm = (struct dm_struct *)dm_void;
4981 struct dm_iqk_info *iqk_info = &dm->IQK_info;
4982 u8 path, idx, i;
4983
4984 RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "backup TX/RX CFIR");
4985
4986 for (path = 0; path < SS_8822C; path++)
4987 for (idx = 0; idx < 2; idx++)
4988 phydm_get_iqk_cfir(dm, idx, path, true);
4989
4990 for (path = 0; path < SS_8822C; path++) {
4991 for (idx = 0; idx < 2; idx++) {
4992 for (i = 0; i <= 16; i++) {
4993 RF_DBG(dm, DBG_RF_IQK,
4994 "[IQK]%-7s %-3s CFIR_real: %-2d: 0x%x\n",
4995 (path == 0) ? "PATH A" : "PATH B",
4996 (idx == 0) ? "TX" : "RX", i,
4997 iqk_info->iqk_cfir_real[2][path][idx][i])
4998 ;
4999 }
5000 for (i = 0; i <= 16; i++) {
5001 RF_DBG(dm, DBG_RF_IQK,
5002 "[IQK]%-7s %-3s CFIR_img:%-2d: 0x%x\n",
5003 (path == 0) ? "PATH A" : "PATH B",
5004 (idx == 0) ? "TX" : "RX", i,
5005 iqk_info->iqk_cfir_imag[2][path][idx][i])
5006 ;
5007 }
5008 }
5009 }
5010 }
5011
phy_iqk_dbg_cfir_backup_update_8822c(void * dm_void)5012 void phy_iqk_dbg_cfir_backup_update_8822c(void *dm_void)
5013 {
5014 struct dm_struct *dm = (struct dm_struct *)dm_void;
5015 struct dm_iqk_info *iqk = &dm->IQK_info;
5016 u8 i, path, idx;
5017 u32 bmask13_12 = BIT(13) | BIT(12);
5018 u32 bmask20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
5019 u32 data;
5020
5021 if (iqk->iqk_cfir_real[2][0][0][0] == 0) {
5022 RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "CFIR is invalid");
5023 return;
5024 }
5025 for (path = 0; path < SS_8822C; path++) {
5026 for (idx = 0; idx < 2; idx++) {
5027 odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x8 | path << 1);
5028 odm_set_bb_reg(dm, R_0x1b2c, MASKDWORD, 0x7);
5029 odm_set_bb_reg(dm, R_0x1b38, MASKDWORD, 0x40000000);
5030 odm_set_bb_reg(dm, R_0x1b3c, MASKDWORD, 0x40000000);
5031 odm_set_bb_reg(dm, R_0x1bcc, MASKDWORD, 0x00000000);
5032 iqk_get_cfir_8822c(dm, idx, path, false);
5033 }
5034 }
5035 RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "update new CFIR");
5036 }
5037
phy_iqk_dbg_cfir_reload_8822c(void * dm_void)5038 void phy_iqk_dbg_cfir_reload_8822c(void *dm_void)
5039 {
5040 struct dm_struct *dm = (struct dm_struct *)dm_void;
5041 struct dm_iqk_info *iqk = &dm->IQK_info;
5042 u8 i, path, idx;
5043 u32 bmask13_12 = BIT(13) | BIT(12);
5044 u32 bmask20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
5045 u32 data;
5046
5047 if (iqk->iqk_cfir_real[0][0][0][0] == 0) {
5048 RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "CFIR is invalid");
5049 return;
5050 }
5051 for (path = 0; path < SS_8822C; path++) {
5052 for (idx = 0; idx < 2; idx++) {
5053 odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x8 | path << 1);
5054 odm_set_bb_reg(dm, R_0x1b2c, MASKDWORD, 0x7);
5055 odm_set_bb_reg(dm, R_0x1b38, MASKDWORD, 0x40000000);
5056 odm_set_bb_reg(dm, R_0x1b3c, MASKDWORD, 0x40000000);
5057 odm_set_bb_reg(dm, R_0x1bcc, MASKDWORD, 0x00000000);
5058 iqk_set_cfir_8822c(dm, idx, path, false);
5059 }
5060 }
5061 RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "write CFIR with default value");
5062 }
5063
phy_iqk_dbg_cfir_write_8822c(void * dm_void,u8 type,u32 path,u32 idx,u32 i,u32 data)5064 void phy_iqk_dbg_cfir_write_8822c(void *dm_void, u8 type, u32 path, u32 idx,
5065 u32 i, u32 data)
5066 {
5067 struct dm_struct *dm = (struct dm_struct *)dm_void;
5068 struct dm_iqk_info *iqk_info = &dm->IQK_info;
5069
5070 if (type == 0)
5071 iqk_info->iqk_cfir_real[2][path][idx][i] = (u16)data;
5072 else
5073 iqk_info->iqk_cfir_imag[2][path][idx][i] = (u16)data;
5074 }
5075
phy_iqk_dbg_cfir_backup_show_8822c(void * dm_void)5076 void phy_iqk_dbg_cfir_backup_show_8822c(void *dm_void)
5077 {
5078 struct dm_struct *dm = (struct dm_struct *)dm_void;
5079 struct dm_iqk_info *iqk_info = &dm->IQK_info;
5080 u8 path, idx, i;
5081
5082 RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "backup TX/RX CFIR");
5083
5084 for (path = 0; path < SS_8822C; path++) {
5085 for (idx = 0; idx < 2; idx++) {
5086 for (i = 0; i <= 16; i++) {
5087 RF_DBG(dm, DBG_RF_IQK,
5088 "[IQK]%-10s %-3s CFIR_real:%-2d: 0x%x\n",
5089 (path == 0) ? "PATH A" : "PATH B",
5090 (idx == 0) ? "TX" : "RX", i,
5091 iqk_info->iqk_cfir_real[2][path][idx][i])
5092 ;
5093 }
5094 for (i = 0; i <= 16; i++) {
5095 RF_DBG(dm, DBG_RF_IQK,
5096 "[IQK]%-10s %-3s CFIR_img:%-2d: 0x%x\n",
5097 (path == 0) ? "PATH A" : "PATH B",
5098 (idx == 0) ? "TX" : "RX", i,
5099 iqk_info->iqk_cfir_imag[2][path][idx][i])
5100 ;
5101 }
5102 }
5103 }
5104 }
5105
5106 #endif
5107