1 // Copyright (C) 2022 Beken Corporation 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 #include "hal_config.h" 18 #include "spi_config.h" 19 #include "spi_hw.h" 20 #include "spi_ll.h" 21 #include <driver/hal/hal_spi_types.h> 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 typedef struct { 28 spi_hw_t *hw; 29 spi_unit_t id; 30 } spi_hal_t; 31 32 #define spi_hal_set_role(hal, role) spi_ll_set_role((hal)->hw, role) 33 #define spi_hal_set_bit_width(hal, bit_width) spi_ll_set_bit_width((hal)->hw, bit_width) 34 #define spi_hal_set_wire_mode(hal, wire_mode) spi_ll_set_wire_mode((hal)->hw, wire_mode) 35 #define spi_hal_set_first_bit(hal, first_bit) spi_ll_set_first_bit((hal)->hw, first_bit) 36 #define spi_hal_set_cpol(hal, cpol) spi_ll_set_cpol((hal)->hw, cpol) 37 #define spi_hal_set_cpha(hal, cpha) spi_ll_set_cpha((hal)->hw, cpha) 38 #define spi_hal_is_master(hal) spi_ll_is_role_master((hal)->hw) 39 #define spi_hal_is_slave(hal) spi_ll_is_role_slave((hal)->hw) 40 #define spi_hal_get_tx_fifo_int_level(hal) spi_ll_get_tx_fifo_int_level((hal)->hw) 41 #define spi_hal_get_rx_fifo_int_level(hal) spi_ll_get_rx_fifo_int_level((hal)->hw) 42 43 #define spi_hal_enable_tx(hal) spi_ll_enable_tx((hal)->hw) 44 #define spi_hal_disable_tx(hal) spi_ll_disable_tx((hal)->hw) 45 #define spi_hal_enable_rx(hal) spi_ll_enable_rx((hal)->hw) 46 #define spi_hal_disable_rx(hal) spi_ll_disable_rx((hal)->hw) 47 #define spi_hal_enable_tx_finish_int(hal) spi_ll_enable_tx_finish_int((hal)->hw) 48 #define spi_hal_disable_tx_finish_int(hal) spi_ll_disable_tx_finish_int((hal)->hw) 49 #define spi_hal_enable_rx_finish_int(hal) spi_ll_enable_rx_finish_int((hal)->hw) 50 #define spi_hal_disable_rx_finish_int(hal) spi_ll_disable_rx_finish_int((hal)->hw) 51 #define spi_hal_set_tx_trans_len(hal, len) spi_ll_set_tx_trans_len((hal)->hw, len) 52 #define spi_hal_set_rx_trans_len(hal, len) spi_ll_set_rx_trans_len((hal)->hw, len) 53 54 #define spi_hal_enable_tx_fifo_int(hal) spi_ll_enable_tx_fifo_int((hal)->hw) 55 #define spi_hal_disable_tx_fifo_int(hal) spi_ll_disable_tx_fifo_int((hal)->hw) 56 #define spi_hal_enable_rx_fifo_int(hal) spi_ll_enable_rx_fifo_int((hal)->hw) 57 #define spi_hal_disable_rx_fifo_int(hal) spi_ll_disable_rx_fifo_int((hal)->hw) 58 #define spi_hal_enable_tx_underflow_int(hal) spi_ll_enable_tx_underflow_int((hal)->hw) 59 #define spi_hal_disable_tx_underflow_int(hal) spi_ll_disable_tx_underflow_int((hal)->hw) 60 #define spi_hal_enable_rx_overflow_int(hal) spi_ll_enable_rx_overflow_int((hal)->hw) 61 #define spi_hal_disable_rx_overflow_int(hal) spi_ll_disable_rx_overflow_int((hal)->hw) 62 #define spi_hal_enable_slave_release_int(hal) spi_ll_enable_slave_release_int((hal)->hw) 63 #define spi_hal_disable_slave_release_int(hal) spi_ll_disable_slave_release_int((hal)->hw) 64 65 #define spi_hal_get_interrupt_status(hal) spi_ll_get_interrupt_status((hal)->hw) 66 #define spi_hal_clear_interrupt_status(hal, status) spi_ll_clear_interrupt_status((hal)->hw, status) 67 #define spi_hal_clear_tx_fifo_int_status(hal) spi_ll_clear_tx_fifo_int_status((hal)->hw) 68 #define spi_hal_clear_rx_fifo_int_status(hal) spi_ll_clear_rx_fifo_int_status((hal)->hw) 69 #define spi_hal_clear_tx_finish_int_status(hal) spi_ll_clear_tx_finish_int_status((hal)->hw) 70 #define spi_hal_clear_rx_finish_int_status(hal) spi_ll_clear_rx_finish_int_status((hal)->hw) 71 #define spi_hal_is_tx_fifo_wr_ready(hal) spi_ll_is_tx_fifo_wr_ready((hal)->hw) 72 #define spi_hal_is_rx_fifo_rd_ready(hal) spi_ll_is_rx_fifo_rd_ready((hal)->hw) 73 #define spi_hal_is_tx_fifo_int_triggered(hal) spi_ll_is_tx_fifo_int_triggered((hal)->hw) 74 #define spi_hal_is_rx_fifo_int_triggered(hal) spi_ll_is_rx_fifo_int_triggered((hal)->hw) 75 #define spi_hal_is_tx_fifo_int_triggered_with_status(hal, status) spi_ll_is_tx_fifo_int_triggered_with_status((hal)->hw, status) 76 #define spi_hal_is_rx_fifo_int_triggered_with_status(hal, status) spi_ll_is_rx_fifo_int_triggered_with_status((hal)->hw, status) 77 #define spi_hal_is_tx_finish_int_triggered(hal, status) spi_ll_is_tx_finish_int_triggered((hal)->hw, status) 78 #define spi_hal_is_rx_finish_int_triggered(hal, status) spi_ll_is_rx_finish_int_triggered((hal)->hw, status) 79 #define spi_hal_is_slave_release_int_triggered(hal, status) spi_ll_is_slave_release_int_triggered((hal)->hw, status) 80 #define spi_hal_is_rx_overflow_int_triggered(hal, status) spi_ll_is_rx_overflow_int_triggered((hal)->hw, status) 81 #define spi_hal_is_tx_underflow_int_triggered(hal, status) spi_ll_is_tx_underflow_int_triggered((hal)->hw, status) 82 #define spi_hal_clear_tx_fifo(hal) spi_ll_clear_tx_fifo((hal)->hw) 83 #define spi_hal_clear_rx_fifo(hal) spi_ll_clear_rx_fifo((hal)->hw) 84 #define spi_hal_is_rx_fifo_empty(hal) spi_ll_is_rx_fifo_empty((hal)->hw) 85 86 #define spi_hal_write_byte(hal, data) spi_ll_write_byte((hal)->hw, data) 87 88 bk_err_t spi_hal_init(spi_hal_t *hal); 89 bk_err_t spi_hal_configure(spi_hal_t *hal, const spi_config_t *config); 90 bk_err_t spi_hal_start_common(spi_hal_t *hal); 91 bk_err_t spi_hal_stop_common(spi_hal_t *hal); 92 bk_err_t spi_hal_set_baud_rate(spi_hal_t *hal, uint32_t baud_rate); 93 bk_err_t spi_hal_read_byte(spi_hal_t *hal, uint8_t *data); 94 95 #if CFG_HAL_DEBUG_SPI 96 void spi_struct_dump(spi_id_t id); 97 #else 98 #define spi_struct_dump(id) 99 #endif 100 101 #ifdef __cplusplus 102 } 103 #endif 104 105