1 // Copyright (C) 2022 Beken Corporation 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 #include <common/bk_err.h> 18 #include <driver/hal/hal_dma_types.h> 19 20 #ifdef __cplusplus 21 extern "C" { 22 #endif 23 24 #define BK_ERR_SPI_NOT_INIT (BK_ERR_SPI_BASE - 1) /**< SPI driver not init */ 25 #define BK_ERR_SPI_INVALID_ID (BK_ERR_SPI_BASE - 2) /**< SPI id number is invalid */ 26 #define BK_ERR_SPI_ID_NOT_INIT (BK_ERR_SPI_BASE - 3) /**< SPI ID not init */ 27 #define BK_ERR_SPI_RX_TIMEOUT (BK_ERR_SPI_BASE - 4) /**< SPI receive data timeout */ 28 #define BK_ERR_SPI_TX_TIMEOUT (BK_ERR_SPI_BASE - 5) /**< SPI send data timeout */ 29 #define BK_ERR_SPI_FIFO_WR_NOT_READY (BK_ERR_SPI_BASE - 6) /**< SPI tx fifo write not ready */ 30 #define BK_ERR_SPI_FIFO_RD_NOT_READY (BK_ERR_SPI_BASE - 6) /**< SPI rx fifo read not ready */ 31 32 typedef uint8_t spi_unit_t; /**< spi uint id */ 33 34 typedef enum { 35 SPI_ID_0 = 0, /**< SPI id 1 */ 36 #if (SOC_SPI_UNIT_NUM > 1) 37 SPI_ID_1, /**< SPI id 2 */ 38 #endif 39 #if (SOC_SPI_UNIT_NUM > 2) 40 SPI_ID_2, /**< SPI id 3 */ 41 #endif 42 SPI_ID_MAX /**< SPI id max */ 43 } spi_id_t; 44 45 typedef enum { 46 SPI_ROLE_SLAVE = 0, /**< SPI as slave */ 47 SPI_ROLE_MASTER, /**< SPI as master */ 48 } spi_role_t; 49 50 typedef enum { 51 SPI_BIT_WIDTH_8BITS = 0, /**< SPI bit width 8bits */ 52 SPI_BIT_WIDTH_16BITS, /**< SPI bit width 16bits */ 53 } spi_bit_width_t; 54 55 typedef enum { 56 SPI_POLARITY_LOW = 0, /**< SPI clock polarity low */ 57 SPI_POLARITY_HIGH, /**< SPI clock polarity high */ 58 } spi_polarity_t; 59 60 typedef enum { 61 SPI_PHASE_1ST_EDGE = 0, /**< SPI clock phase the first edge */ 62 SPI_PHASE_2ND_EDGE, /**< SPI clock phase the second edge */ 63 } spi_phase_t; 64 65 typedef enum { 66 SPI_POL_MODE_0 = 0, /**< SPI mode 0 */ 67 SPI_POL_MODE_1, /**< SPI mode 1 */ 68 SPI_POL_MODE_2, /**< SPI mode 2 */ 69 SPI_POL_MODE_3, /**< SPI mode 3 */ 70 } spi_mode_t; 71 72 typedef enum { 73 SPI_4WIRE_MODE = 0, /**< SPI four wire mode */ 74 SPI_3WIRE_MODE, /**< SPI three wire mode */ 75 } spi_wire_mode_t; 76 77 typedef enum { 78 SPI_MSB_FIRST = 0, /**< SPI MSB first */ 79 SPI_LSB_FIRST, /**< SPI LSB first */ 80 } spi_bit_order_t; 81 82 typedef enum { 83 SPI_FIFO_INT_LEVEL_1 = 0, /**< SPI fifo int level 1 */ 84 SPI_FIFO_INT_LEVEL_16, /**< SPI fifo int level 16 */ 85 SPI_FIFO_INT_LEVEL_32, /**< SPI fifo int level 32 */ 86 SPI_FIFO_INT_LEVEL_48, /**< SPI fifo int level 48 */ 87 } spi_fifo_int_level; 88 89 typedef enum { 90 SPI_CLK_XTAL = 0, 91 SPI_CLK_APLL, 92 SPI_CLK_UNKNOW = 0xff 93 } spi_src_clk_t; 94 95 #if (CONFIG_SPI_DMA) 96 97 typedef enum { 98 SPI_DMA_MODE_DISABLE = 0, /**< SPI disable dma */ 99 SPI_DMA_MODE_ENABLE, /**< SPI enable dma */ 100 } spi_dma_mode_t; 101 102 #endif 103 104 typedef struct { 105 spi_role_t role; /**< SPI as master or slave */ 106 spi_bit_width_t bit_width; /**< SPI data bit witdth */ 107 spi_polarity_t polarity; /**< SPI clock polarity */ 108 spi_phase_t phase; /**< SPI clock phase */ 109 spi_wire_mode_t wire_mode; /**< SPI wire mode */ 110 uint32_t baud_rate; /**< SPI transmit and receive SCK clock */ 111 spi_bit_order_t bit_order; /**< SPI bit order, MSB/LSB */ 112 #if (CONFIG_SPI_DMA) 113 spi_dma_mode_t dma_mode; /**< SPI whether use dma */ 114 dma_id_t spi_tx_dma_chan; /**< SPI tx dma channel */ 115 dma_id_t spi_rx_dma_chan; /**< SPI rx dma channel */ 116 #endif 117 } spi_config_t; 118 119 #ifdef __cplusplus 120 } 121 #endif 122 123