Searched defs:spierrstats_t (Results 1 – 3 of 3) sorted by relevance
| /device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/include/ |
| D | sdiovar.h | 58 struct spierrstats_t { struct
59 uint32 dna; /* The requested data is not available. */
60 uint32 rdunderflow; /* FIFO underflow happened due to current (F2, F3) rd command */
61 uint32 wroverflow; /* FIFO underflow happened due to current (F1, F2, F3) wr command */
63 uint32 f2interrupt; /* OR of all F2 related intr status bits. */
64 uint32 f3interrupt; /* OR of all F3 related intr status bits. */
66 uint32 f2rxnotready; /* F2 FIFO is not ready to receive data (FIFO empty) */
67 uint32 f3rxnotready; /* F3 FIFO is not ready to receive data (FIFO empty) */
69 uint32 hostcmddataerr; /* Error in command or host data, detected by CRC/checksum
72 uint32 f2pktavailable; /* Packet is available in F2 TX FIFO */
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| /device/board/kaihong/khdvk_3566b/wifi/bcmdhd_hdf/bcmdhd/include/ |
| D | sdiovar.h | 57 struct spierrstats_t { struct
58 uint32 dna; /* The requested data is not available. */
59 uint32 rdunderflow; /* FIFO underflow happened due to current (F2, F3) rd
61 uint32 wroverflow; /* FIFO underflow happened due to current (F1, F2, F3) wr
64 uint32 f2interrupt; /* OR of all F2 related intr status bits. */
65 uint32 f3interrupt; /* OR of all F3 related intr status bits. */
67 uint32 f2rxnotready; /* F2 FIFO is not ready to receive data (FIFO empty) */
68 uint32 f3rxnotready; /* F3 FIFO is not ready to receive data (FIFO empty) */
70 uint32 hostcmddataerr; /* Error in command or host data, detected by
73 uint32 f2pktavailable; /* Packet is available in F2 TX FIFO */
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| /device/board/isoftstone/yangfan/kernel/src/driv/net/rockchip_wlan/rkwifi/bcmdhd/include/ |
| D | sdiovar.h | 57 struct spierrstats_t { struct
58 uint32 dna; /* The requested data is not available. */
59 uint32 rdunderflow; /* FIFO underflow happened due to current (F2, F3) rd command */
60 uint32 wroverflow; /* FIFO underflow happened due to current (F1, F2, F3) wr command */
62 uint32 f2interrupt; /* OR of all F2 related intr status bits. */
63 uint32 f3interrupt; /* OR of all F3 related intr status bits. */
65 uint32 f2rxnotready; /* F2 FIFO is not ready to receive data (FIFO empty) */
66 uint32 f3rxnotready; /* F3 FIFO is not ready to receive data (FIFO empty) */
68 uint32 hostcmddataerr; /* Error in command or host data, detected by CRC/checksum
71 uint32 f2pktavailable; /* Packet is available in F2 TX FIFO */
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