1 2 /* 3 * isp500_reg.h 4 * 5 * Copyright (c) 2007-2017 Allwinnertech Co., Ltd. 6 * 7 * This software is licensed under the terms of the GNU General Public 8 * License version 2, as published by the Free Software Foundation, and 9 * may be copied, distributed, and modified under those terms. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 */ 17 18 #ifndef _ISP500_REG_H_ 19 #define _ISP500_REG_H_ 20 21 /*FOR ISP500*/ 22 23 #define ISP_FE_CFG_REG_OFF 0x000 24 #define ISP_FE_CTRL_REG_OFF 0x004 25 #define ISP_FE_INT_EN_REG_OFF 0x008 26 #define ISP_FE_INT_STA_REG_OFF 0x00c 27 #define ISP_DBG_OUTPUT_REG_OFF 0x010 28 #define ISP_LINE_INT_NUM_REG_OFF 0x018 29 #define ISP_ROT_OF_CFG_REG_OFF 0x01c 30 31 #define ISP_REG_LOAD_ADDR_REG_OFF 0x020 32 #define ISP_REG_SAVED_ADDR_REG_OFF 0x024 33 #define ISP_LUT_LENS_GAMMA_ADDR_REG_OFF 0x028 34 #define ISP_DRC_ADDR_REG_OFF 0x02c 35 #define ISP_STATISTICS_ADDR_REG_OFF 0x030 36 #define ISP_VER_CFG_REG_OFF 0x034 37 #define ISP_SRAM_RW_OFFSET_REG_OFF 0x038 38 #define ISP_SRAM_RW_DATA_REG_OFF 0x03c 39 40 #define ISP_EN_REG_OFF 0x040 41 #define ISP_MODE_REG_OFF 0x044 42 #define ISP_OB_SIZE_REG_OFF 0x078 43 #define ISP_OB_VALID_REG_OFF 0x07c 44 #define ISP_OB_VALID_START_REG_OFF 0x080 45 46 #define ISP_WDR_EXP_ADDR0_REG 0x0a0 47 #define ISP_WDR_EXP_ADDR1_REG 0x0a4 48 #define ISP_D3D_REC_ADDR0_REG 0x0c8 49 #define ISP_D3D_REC_ADDR1_REG 0x0cc 50 51 typedef union { 52 unsigned int dwval; 53 struct { 54 unsigned int isp_enable:1; 55 unsigned int res0:7; 56 unsigned int isp_ch0_en:1; 57 unsigned int isp_ch1_en:1; 58 unsigned int isp_ch2_en:1; 59 unsigned int isp_ch3_en:1; 60 unsigned int res1:4; 61 unsigned int wdr_ch_seq:1; 62 unsigned int wdr_exp_seq:1; 63 unsigned int isp_ver_read_en:1; 64 unsigned int res2:13; 65 } bits; 66 } ISP_FE_CFG_REG_t; 67 68 typedef union { 69 unsigned int dwval; 70 struct { 71 unsigned int cap_en:1; 72 unsigned int res0:1; 73 unsigned int para_ready:1; 74 unsigned int linear_update:1; 75 unsigned int lens_update:1; 76 unsigned int gamma_update:1; 77 unsigned int drc_update:1; 78 unsigned int disc_update:1; 79 unsigned int satu_update:1; 80 unsigned int wdr_update:1; 81 unsigned int tdnf_update:1; 82 unsigned int pltm_update:1; 83 unsigned int cem_update:1; 84 unsigned int contrast_update:1; 85 unsigned int res1:18; 86 } bits; 87 } ISP_FE_CTRL_REG_t; 88 89 typedef union { 90 unsigned int dwval; 91 struct { 92 unsigned int finish_int_en:1; 93 unsigned int start_int_en:1; 94 unsigned int para_save_int_en:1; 95 unsigned int para_load_int_en:1; 96 unsigned int src0_fifo_int_en:1; 97 unsigned int res0:2; 98 unsigned int n_line_start_int_en:1; 99 unsigned int frame_error_int_en:1; 100 unsigned int res1:5; 101 unsigned int frame_lost_int_en:1; 102 unsigned int res2:17; 103 } bits; 104 } ISP_FE_INT_EN_REG_t; 105 106 typedef union { 107 unsigned int dwval; 108 struct { 109 unsigned int finish_pd:1; 110 unsigned int start_pd:1; 111 unsigned int para_saved_pd:1; 112 unsigned int para_load_pd:1; 113 unsigned int src0_fifo_of_pd:1; 114 unsigned int res0:2; 115 unsigned int n_line_start_pd:1; 116 unsigned int cin_fifo_pd:1; 117 unsigned int dpc_fifo_pd:1; 118 unsigned int d2d_fifo_pd:1; 119 unsigned int bis_fifo_pd:1; 120 unsigned int cnr_fifo_pd:1; 121 unsigned int frame_lost_pd:1; 122 unsigned int res1:7; 123 unsigned int d3d_w_finish_pd:1; 124 unsigned int wdr_w_finish_pd:1; 125 unsigned int d3d_hb_pd:1; 126 unsigned int pltm_fifo_pd:1; 127 unsigned int d3d_write_fifo_pd:1; 128 unsigned int d3d_read_fifo_pd:1; 129 unsigned int d3d_wt2cmp_fifo_pd:1; 130 unsigned int wdr_write_fifo_pd:1; 131 unsigned int wdr_wt2cmp_fifo_pd:1; 132 unsigned int wdr_read_fifo_pd:1; 133 } bits; 134 } ISP_FE_INT_STA_REG_t; 135 136 typedef union { 137 unsigned int dwval; 138 struct { 139 unsigned int top_ctrl_st:8; 140 unsigned int wdr_ctrl_st:3; 141 unsigned int res0:4; 142 unsigned int debug_sel:5; 143 unsigned int debug_en:1; 144 unsigned int res1:11; 145 } bits; 146 } ISP_DBG_OUTPUT_REG_t; 147 148 typedef union { 149 unsigned int dwval; 150 struct { 151 unsigned int line_int_num:14; 152 unsigned int res0:13; 153 unsigned int last_blank_cycle:3; 154 unsigned int res1:2; 155 } bits; 156 } ISP_LINE_INT_NUM_REG_t; 157 158 typedef union { 159 unsigned int dwval; 160 struct { 161 unsigned int res0:26; 162 unsigned int speed_mode:3; 163 unsigned int res1:3; 164 } bits; 165 } ISP_ROT_OF_CFG_REG_t; 166 167 typedef union { 168 unsigned int dwval; 169 struct { 170 unsigned int reg_load_addr; 171 } bits; 172 } ISP_REG_LOAD_ADDR_REG_t; 173 174 typedef union { 175 unsigned int dwval; 176 struct { 177 unsigned int reg_saved_addr; 178 } bits; 179 } ISP_REG_SAVED_ADDR_REG_t; 180 181 typedef union { 182 unsigned int dwval; 183 struct { 184 unsigned int lut_lens_gamma_addr; 185 } bits; 186 } ISP_LUT_LENS_GAMMA_ADDR_REG_t; 187 188 typedef union { 189 unsigned int dwval; 190 struct { 191 unsigned int rgb_yuv_drc_addr; 192 } bits; 193 } ISP_DRC_ADDR_REG_t; 194 195 typedef union { 196 unsigned int dwval; 197 struct { 198 unsigned int statistics_addr; 199 } bits; 200 } ISP_STATISTICS_ADDR_REG_t; 201 202 typedef union { 203 unsigned int dwval; 204 struct { 205 unsigned int minor_ver:12; 206 unsigned int major_ver:12; 207 unsigned int res0:8; 208 } bits; 209 } ISP_VER_CFG_REG_t; 210 211 typedef union { 212 unsigned int dwval; 213 struct { 214 unsigned int sram_addr:17; 215 unsigned int res0:14; 216 unsigned int sram_clear:1; 217 } bits; 218 } ISP_SRAM_RW_OFFSET_REG_t; 219 220 typedef union { 221 unsigned int dwval; 222 struct { 223 unsigned int sram_data; 224 } bits; 225 } ISP_SRAM_RW_DATA_REG_t; 226 227 typedef union { 228 unsigned int dwval; 229 struct { 230 unsigned int ae_en:1; 231 unsigned int lc_en:1; 232 unsigned int wdr_en:1; 233 unsigned int otf_dpc_en:1; 234 unsigned int bdnf_en:1; 235 unsigned int tdnf_en:1; 236 unsigned int awb_en:1; 237 unsigned int wb_en:1; 238 unsigned int lsc_en:1; 239 unsigned int bgc_en:1; 240 unsigned int sap_en:1; 241 unsigned int af_en:1; 242 unsigned int rgb2rgb_en:1; 243 unsigned int rgb_drc_en:1; 244 unsigned int pltm_en:1; 245 unsigned int cem_en:1; 246 unsigned int afs_en:1; 247 unsigned int hist_en:1; 248 unsigned int blc_en:1; 249 unsigned int dg_en:1; 250 unsigned int so_en:1; 251 unsigned int ctc_en:1; 252 unsigned int contrast_en:1; 253 unsigned int cnr_en:1; 254 unsigned int saturation_en:1; 255 unsigned int res2:6; 256 unsigned int src0_en:1; 257 } bits; 258 } ISP_EN_REG_t; 259 260 typedef union { 261 unsigned int dwval; 262 struct { 263 unsigned int input_fmt:3; 264 unsigned int res0:5; 265 unsigned int wdr_mode:1; 266 unsigned int wdr_dol_mode:1; 267 unsigned int res1:1; 268 unsigned int wdr_cmp_mode:1; 269 unsigned int res2:4; 270 unsigned int otf_dpc_mode:2; 271 unsigned int res3:1; 272 unsigned int saturation_mode:1; 273 unsigned int hist_mode:2; 274 unsigned int hist_sel:1; 275 unsigned int caf_mode:1; 276 unsigned int ae_mode:2; 277 unsigned int awb_mode:1; 278 unsigned int dg_mode:1; 279 unsigned int res4:4; 280 } bits; 281 } ISP_MODE_REG_t; 282 283 typedef union { 284 unsigned int dwval; 285 struct { 286 unsigned int ob_width:14; 287 unsigned int res0:2; 288 unsigned int ob_height:14; 289 unsigned int res1:2; 290 } bits; 291 } ISP_OB_SIZE_REG_t; 292 293 typedef union { 294 unsigned int dwval; 295 struct { 296 unsigned int ob_valid_width:13; 297 unsigned int res0:3; 298 unsigned int ob_valid_height:13; 299 unsigned int res1:3; 300 } bits; 301 } ISP_OB_VALID_REG_t; 302 303 typedef union { 304 unsigned int dwval; 305 struct { 306 unsigned int ob_hor_start:13; 307 unsigned int res0:3; 308 unsigned int ob_ver_start:13; 309 unsigned int res1:3; 310 } bits; 311 } ISP_OB_VALID_START_REG_t; 312 313 #endif 314