1 // Copyright (C) 2022 Beken Corporation 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 typedef volatile struct { 22 //REG_0x00~REG_0x5F 23 struct { 24 union { 25 struct { 26 uint32_t enable: 1; /**< bit[0] DMA enable */ 27 uint32_t finish_int_en: 1; /**< bit[1] transfer finish interrupt enable */ 28 uint32_t half_finish_int_en: 1; /**< bit[2] half transfer finish interrupt enable */ 29 uint32_t mode: 1; /**< bit[3] DMA work mode */ 30 uint32_t src_data_width: 2; /**< bit[4:5] source data width */ 31 uint32_t dest_data_width: 2; /**< bit[6:7] destination data width */ 32 uint32_t src_addr_inc_en: 1; /**< bit[8] source address increment enable */ 33 uint32_t dest_addr_inc_en: 1; /**< bit[9] dest address increment enable */ 34 uint32_t src_addr_loop_en: 1; /**< bit[10] source address loop enable */ 35 uint32_t dest_addr_loop_en: 1; /**< bit[11] dest address loop enable */ 36 uint32_t chan_prio: 3; /**< bit[12:14] channel prioprity */ 37 uint32_t reserved: 1; /**< bit[15] */ 38 uint32_t transfer_len: 16; /**< bit[16:31] DMA transfer length,unit is byte */ 39 }; 40 uint32_t v; 41 } ctrl; 42 43 uint32_t dest_start_addr; 44 uint32_t src_start_addr; 45 uint32_t dest_loop_end_addr; 46 uint32_t dest_loop_start_addr; 47 uint32_t src_loop_end_addr; 48 uint32_t src_loop_start_addr; 49 50 union { 51 struct { 52 /* Source Request Mux.(see dest_req_mux) 53 * 0x0: DTCM/AHB_MEM read Req 54 * 0x1: Uart0 rx Req 55 * 0x2: Spi0 rx Req 56 * 0x3: Sdio rx Req 57 * 0x4: Uart1 rx Req 58 * 0x5: Uart2 rx Req 59 * 0x6: Spi1 rx Req 60 * 0x7: Usb rx Req 61 * 0x8: Aud rx Req 62 * 0x9: I2S rx Req 63 * 0xa: Jpeg rx Req 64 * 0xb~0xf: Reserved 65 */ 66 uint32_t src_req_mux: 5; /**< bit[0:4] source request mux */ 67 68 /* Destination Request Mux: 69 * 0x0: DTCM/AHB_MEM Write Req 70 * 0x1: Uart0 tx Req 71 * 0x2: Spi0 tx Req 72 * 0x3: Sdio tx Req 73 * 0x4: Uart1 tx Req 74 * 0x5: Uart2 tx Req 75 * 0x6: Spi1 tx Req 76 * 0x7: Usb tx Req 77 * 0x8: Aud tx Req 78 * 0x9: I2S tx Req 79 * 0xa: lcd cmd tx Req 80 * 0xb: lcd data tx Req 81 * 0xc~0xf: Reserved 82 */ 83 uint32_t dest_req_mux: 5; /**< bit[5:9] dest request mux */ 84 uint32_t reserved0: 2; /**< bit[10:11] */ 85 uint32_t src_read_interval: 4; /**< bit[12:15] source read operate interval,unit is cycle */ 86 uint32_t dest_write_interval: 4; /**< bit[16:19] destination write operate interval,unit is cycle */ 87 uint32_t reserved1: 12; /**< bit[20:31] */ 88 }; 89 uint32_t v; 90 } req_mux; 91 } config_group[SOC_DMA_CHAN_NUM_PER_UNIT]; 92 93 uint32_t reserved1[0x80 - 0x5f - 1]; 94 //REG_0x80~REG_0x8b 95 uint32_t src_pause_addr[SOC_DMA_CHAN_NUM_PER_UNIT]; 96 97 uint32_t reserved2[0x90 - 0x8b - 1]; 98 //REG_0x90~REG_0x9b 99 uint32_t dest_pause_addr[SOC_DMA_CHAN_NUM_PER_UNIT]; 100 101 uint32_t reserved3[0xa0 - 0x9b - 1]; 102 //REG_0xa0~REG_0xab 103 uint32_t src_rd_addr[SOC_DMA_CHAN_NUM_PER_UNIT]; 104 105 uint32_t reserved4[0xb0 - 0xab - 1]; 106 //REG_0xb0~REG_0xbb 107 uint32_t dest_wr_addr[SOC_DMA_CHAN_NUM_PER_UNIT]; 108 109 uint32_t reserved5[0xc0 - 0xbb - 1]; 110 //REG_0xc0~REG_0xcb 111 struct { 112 union { 113 struct { 114 uint32_t remain_len: 17; /**< bit[0:16] remain length indication */ 115 uint32_t flush_src_buff: 1; /**< bit[17] flush source buffer */ 116 uint32_t reserved: 6; /**< bit[18:23] */ 117 uint32_t finish_int_counter: 4; /**< bit[24:27] finish interrupt counter */ 118 uint32_t half_finish_int_counter: 4; /**< bit[28:31] half finish interrupt counter*/ 119 }; 120 uint32_t v; 121 } status; 122 } status_group[SOC_DMA_CHAN_NUM_PER_UNIT]; 123 124 uint32_t reserved6[0xd0 - 0xcb - 1]; 125 //REG_0xd0 126 union { 127 struct { 128 uint32_t prio_mode: 1; /**< bit[0] prioprity mode */ 129 uint32_t reserved: 31; /**< bit[1:31] reserved */ 130 }; 131 uint32_t v; 132 } prio_mode; 133 134 //REG_0xd1 135 union { 136 struct { 137 uint32_t finish_int_status: 12; /**< bit[0:11] finish interrupt status */ 138 uint32_t reserved0: 4; /**< bit[12:15] */ 139 uint32_t half_finish_int_status: 12; /**< bit[16:27] half finish interrupt status */ 140 uint32_t reserved1: 4; /**< bit[28:31] */ 141 }; 142 uint32_t v; 143 } int_status; 144 145 146 } dma_hw_t; 147 148 #ifdef __cplusplus 149 } 150 #endif 151 152 153