1 /*
2 * Copyright (c) 2021 Chipsea Technologies (Shenzhen) Corp., Ltd. All rights reserved.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15 #ifndef _REG_STDIO_UART_H_
16 #define _REG_STDIO_UART_H_
17
18 #include <stdint.h>
19 #include "compiler.h"
20 #include "arch.h"
21 #include "dbg_assert.h"
22 #include "reg_access_wrapper.h"
23
24 #define REG_STDIO_UART_BASE_ADDR CS_UART0_BASE
25 /// UART index
26 #if REG_STDIO_UART_BASE_ADDR == CS_UART0_BASE
27 #define UART_INDEX 0
28 #elif REG_STDIO_UART_BASE_ADDR == CS_UART1_BASE
29 #define UART_INDEX 1
30 #elif REG_STDIO_UART_BASE_ADDR == CS_UART2_BASE
31 #define UART_INDEX 2
32 #else
33 #error "invalid uart"
34 #endif
35 #define UART_IRQn (UART0_IRQn + UART_INDEX)
36
37 /**
38 * @brief TXRXD register definition
39 * <pre>
40 * Bits Field Name Reset Value
41 * ----- ------------------ -----------
42 * 31:08 RSVD 0x0
43 * 07:00 TXRXDATA 0x0
44 * </pre>
45 */
46 #define STDIO_UART_TXRXD_ADDR (REG_STDIO_UART_BASE_ADDR + 0x0000)
47 #define STDIO_UART_TXRXD_OFFSET 0x00000000
48 #define STDIO_UART_TXRXD_INDEX 0x00000000
49 #define STDIO_UART_TXRXD_RESET 0x00000000
50
stdio_uart_txrxd_get(void)51 __STATIC_INLINE uint32_t stdio_uart_txrxd_get(void)
52 {
53 return PLATFORM_REG_READ(STDIO_UART_TXRXD_ADDR);
54 }
55
stdio_uart_txrxd_set(uint32_t value)56 __STATIC_INLINE void stdio_uart_txrxd_set(uint32_t value)
57 {
58 PLATFORM_REG_WRITE(STDIO_UART_TXRXD_ADDR, value);
59 }
60
61 // field definitions
62 #define STDIO_UART_RXDATA_MASK ((uint32_t)0x000000FF)
63 #define STDIO_UART_RXDATA_LSB 0
64 #define STDIO_UART_RXDATA_WIDTH ((uint32_t)0x00000008)
65 #define STDIO_UART_TXDATA_MASK ((uint32_t)0x000000FF)
66 #define STDIO_UART_TXDATA_LSB 0
67 #define STDIO_UART_TXDATA_WIDTH ((uint32_t)0x00000008)
68
69 #define STDIO_UART_RXDATA_RST 0x0
70 #define STDIO_UART_TXDATA_RST 0x0
71
stdio_uart_rxdata_getf(void)72 __STATIC_INLINE uint8_t stdio_uart_rxdata_getf(void)
73 {
74 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_TXRXD_ADDR);
75 return ((localVal & ((uint32_t)0x000000FF)) >> 0);
76 }
77
stdio_uart_txdata_setf(uint8_t txdata)78 __STATIC_INLINE void stdio_uart_txdata_setf(uint8_t txdata)
79 {
80 PLATFORM_REG_WRITE(STDIO_UART_TXRXD_ADDR, (uint32_t)txdata << 0);
81 }
82
83 /**
84 * @brief DIV0 register definition
85 * <pre>
86 * Bits Field Name Reset Value
87 * ----- ------------------ -----------
88 * 31:08 RSVD 0x0
89 * 07:00 DIV0 0x0
90 * </pre>
91 */
92 #define STDIO_UART_DIV0_ADDR (REG_STDIO_UART_BASE_ADDR + 0x0000)
93 #define STDIO_UART_DIV0_OFFSET 0x00000000
94 #define STDIO_UART_DIV0_INDEX 0x00000000
95 #define STDIO_UART_DIV0_RESET 0x00000000
96
stdio_uart_div0_get(void)97 __STATIC_INLINE uint32_t stdio_uart_div0_get(void)
98 {
99 return PLATFORM_REG_READ(STDIO_UART_DIV0_ADDR);
100 }
101
stdio_uart_div0_set(uint32_t value)102 __STATIC_INLINE void stdio_uart_div0_set(uint32_t value)
103 {
104 PLATFORM_REG_WRITE(STDIO_UART_DIV0_ADDR, value);
105 }
106
107 // field definitions
108 #define STDIO_UART_DIV0_MASK ((uint32_t)0x000000FF)
109 #define STDIO_UART_DIV0_LSB 0
110 #define STDIO_UART_DIV0_WIDTH ((uint32_t)0x00000008)
111
112 #define STDIO_UART_DIV0_RST 0x0
113
stdio_uart_div0_getf(void)114 __STATIC_INLINE uint8_t stdio_uart_div0_getf(void)
115 {
116 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_DIV0_ADDR);
117 return (localVal >> 0);
118 }
119
stdio_uart_div0_setf(uint8_t div0)120 __STATIC_INLINE void stdio_uart_div0_setf(uint8_t div0)
121 {
122 PLATFORM_REG_WRITE(STDIO_UART_DIV0_ADDR, (uint32_t)div0 << 0);
123 }
124
125 /**
126 * @brief IRQCTL register definition
127 * <pre>
128 * Bits Field Name Reset Value
129 * ----- ------------------ -----------
130 * 07 PTIRQEN 0
131 * 03 MSIRQEN 0
132 * 02 LSIRQEN 0
133 * 01 TXIRQEN 0
134 * 00 RXIRQEN 0
135 * </pre>
136 */
137 #define STDIO_UART_IRQCTL_ADDR (REG_STDIO_UART_BASE_ADDR + 0x0004)
138 #define STDIO_UART_IRQCTL_OFFSET 0x00000004
139 #define STDIO_UART_IRQCTL_INDEX 0x00000001
140 #define STDIO_UART_IRQCTL_RESET 0x00000000
141
stdio_uart_irqctl_get(void)142 __STATIC_INLINE uint32_t stdio_uart_irqctl_get(void)
143 {
144 return PLATFORM_REG_READ(STDIO_UART_IRQCTL_ADDR);
145 }
146
stdio_uart_irqctl_set(uint32_t value)147 __STATIC_INLINE void stdio_uart_irqctl_set(uint32_t value)
148 {
149 PLATFORM_REG_WRITE(STDIO_UART_IRQCTL_ADDR, value);
150 }
151
152 // field definitions
153 #define STDIO_UART_PTIRQEN_BIT ((uint32_t)0x00000080)
154 #define STDIO_UART_PTIRQEN_POS 7
155 #define STDIO_UART_MSIRQEN_BIT ((uint32_t)0x00000008)
156 #define STDIO_UART_MSIRQEN_POS 3
157 #define STDIO_UART_LSIRQEN_BIT ((uint32_t)0x00000004)
158 #define STDIO_UART_LSIRQEN_POS 2
159 #define STDIO_UART_TXIRQEN_BIT ((uint32_t)0x00000002)
160 #define STDIO_UART_TXIRQEN_POS 1
161 #define STDIO_UART_RXIRQEN_BIT ((uint32_t)0x00000001)
162 #define STDIO_UART_RXIRQEN_POS 0
163
164 #define STDIO_UART_PTIRQEN_RST 0x0
165 #define STDIO_UART_MSIRQEN_RST 0x0
166 #define STDIO_UART_LSIRQEN_RST 0x0
167 #define STDIO_UART_TXIRQEN_RST 0x0
168 #define STDIO_UART_RXIRQEN_RST 0x0
169
stdio_uart_irqctl_pack(uint8_t ptirqen,uint8_t msirqen,uint8_t lsirqen,uint8_t txirqen,uint8_t rxirqen)170 __STATIC_INLINE void stdio_uart_irqctl_pack(uint8_t ptirqen, uint8_t msirqen, uint8_t lsirqen, uint8_t txirqen, uint8_t rxirqen)
171 {
172 PLATFORM_REG_WRITE(STDIO_UART_IRQCTL_ADDR, ((uint32_t)ptirqen << 7) | ((uint32_t)msirqen << 3) | ((uint32_t)lsirqen << 2) | ((uint32_t)txirqen << 1) | ((uint32_t)rxirqen << 0));
173 }
174
stdio_uart_irqctl_unpack(uint8_t * ptirqen,uint8_t * msirqen,uint8_t * lsirqen,uint8_t * txirqen,uint8_t * rxirqen)175 __STATIC_INLINE void stdio_uart_irqctl_unpack(uint8_t* ptirqen, uint8_t* msirqen, uint8_t* lsirqen, uint8_t* txirqen, uint8_t* rxirqen)
176 {
177 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_IRQCTL_ADDR);
178
179 *ptirqen = (localVal & ((uint32_t)0x00000080)) >> 7;
180 *msirqen = (localVal & ((uint32_t)0x00000008)) >> 3;
181 *lsirqen = (localVal & ((uint32_t)0x00000004)) >> 2;
182 *txirqen = (localVal & ((uint32_t)0x00000002)) >> 1;
183 *rxirqen = (localVal & ((uint32_t)0x00000001)) >> 0;
184 }
185
stdio_uart_ptirqen_getf(void)186 __STATIC_INLINE uint8_t stdio_uart_ptirqen_getf(void)
187 {
188 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_IRQCTL_ADDR);
189 return ((localVal & ((uint32_t)0x00000080)) >> 7);
190 }
191
stdio_uart_ptirqen_setf(uint8_t ptirqen)192 __STATIC_INLINE void stdio_uart_ptirqen_setf(uint8_t ptirqen)
193 {
194 PLATFORM_REG_WRITE(STDIO_UART_IRQCTL_ADDR, (PLATFORM_REG_READ(STDIO_UART_IRQCTL_ADDR) & ~((uint32_t)0x00000080)) | ((uint32_t)ptirqen << 7));
195 }
196
stdio_uart_msirqen_getf(void)197 __STATIC_INLINE uint8_t stdio_uart_msirqen_getf(void)
198 {
199 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_IRQCTL_ADDR);
200 return ((localVal & ((uint32_t)0x00000008)) >> 3);
201 }
202
stdio_uart_msirqen_setf(uint8_t msirqen)203 __STATIC_INLINE void stdio_uart_msirqen_setf(uint8_t msirqen)
204 {
205 PLATFORM_REG_WRITE(STDIO_UART_IRQCTL_ADDR, (PLATFORM_REG_READ(STDIO_UART_IRQCTL_ADDR) & ~((uint32_t)0x00000008)) | ((uint32_t)msirqen << 3));
206 }
207
stdio_uart_lsirqen_getf(void)208 __STATIC_INLINE uint8_t stdio_uart_lsirqen_getf(void)
209 {
210 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_IRQCTL_ADDR);
211 return ((localVal & ((uint32_t)0x00000004)) >> 2);
212 }
213
stdio_uart_lsirqen_setf(uint8_t lsirqen)214 __STATIC_INLINE void stdio_uart_lsirqen_setf(uint8_t lsirqen)
215 {
216 PLATFORM_REG_WRITE(STDIO_UART_IRQCTL_ADDR, (PLATFORM_REG_READ(STDIO_UART_IRQCTL_ADDR) & ~((uint32_t)0x00000004)) | ((uint32_t)lsirqen << 2));
217 }
218
stdio_uart_txirqen_getf(void)219 __STATIC_INLINE uint8_t stdio_uart_txirqen_getf(void)
220 {
221 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_IRQCTL_ADDR);
222 return ((localVal & ((uint32_t)0x00000002)) >> 1);
223 }
224
stdio_uart_txirqen_setf(uint8_t txirqen)225 __STATIC_INLINE void stdio_uart_txirqen_setf(uint8_t txirqen)
226 {
227 PLATFORM_REG_WRITE(STDIO_UART_IRQCTL_ADDR, (PLATFORM_REG_READ(STDIO_UART_IRQCTL_ADDR) & ~((uint32_t)0x00000002)) | ((uint32_t)txirqen << 1));
228 }
229
stdio_uart_rxirqen_getf(void)230 __STATIC_INLINE uint8_t stdio_uart_rxirqen_getf(void)
231 {
232 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_IRQCTL_ADDR);
233 return ((localVal & ((uint32_t)0x00000001)) >> 0);
234 }
235
stdio_uart_rxirqen_setf(uint8_t rxirqen)236 __STATIC_INLINE void stdio_uart_rxirqen_setf(uint8_t rxirqen)
237 {
238 PLATFORM_REG_WRITE(STDIO_UART_IRQCTL_ADDR, (PLATFORM_REG_READ(STDIO_UART_IRQCTL_ADDR) & ~((uint32_t)0x00000001)) | ((uint32_t)rxirqen << 0));
239 }
240
241 /**
242 * @brief DIV1 register definition
243 * <pre>
244 * Bits Field Name Reset Value
245 * ----- ------------------ -----------
246 * 31:08 RSVD 0x0
247 * 07:00 DIV1 0x0
248 * </pre>
249 */
250 #define STDIO_UART_DIV1_ADDR (REG_STDIO_UART_BASE_ADDR + 0x0004)
251 #define STDIO_UART_DIV1_OFFSET 0x00000004
252 #define STDIO_UART_DIV1_INDEX 0x00000001
253 #define STDIO_UART_DIV1_RESET 0x00000000
254
stdio_uart_div1_get(void)255 __STATIC_INLINE uint32_t stdio_uart_div1_get(void)
256 {
257 return PLATFORM_REG_READ(STDIO_UART_DIV1_ADDR);
258 }
259
stdio_uart_div1_set(uint32_t value)260 __STATIC_INLINE void stdio_uart_div1_set(uint32_t value)
261 {
262 PLATFORM_REG_WRITE(STDIO_UART_DIV1_ADDR, value);
263 }
264
265 // field definitions
266 #define STDIO_UART_DIV1_MASK ((uint32_t)0x000000FF)
267 #define STDIO_UART_DIV1_LSB 0
268 #define STDIO_UART_DIV1_WIDTH ((uint32_t)0x00000008)
269
270 #define STDIO_UART_DIV1_RST 0x0
271
stdio_uart_div1_getf(void)272 __STATIC_INLINE uint8_t stdio_uart_div1_getf(void)
273 {
274 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_DIV1_ADDR);
275 return (localVal >> 0);
276 }
277
stdio_uart_div1_setf(uint8_t div1)278 __STATIC_INLINE void stdio_uart_div1_setf(uint8_t div1)
279 {
280 PLATFORM_REG_WRITE(STDIO_UART_DIV1_ADDR, (uint32_t)div1 << 0);
281 }
282
283 /**
284 * @brief IRQTYP register definition
285 * <pre>
286 * Bits Field Name Reset Value
287 * ----- ------------------ -----------
288 * 03:00 IRQTYP 0x1
289 * </pre>
290 */
291 #define STDIO_UART_IRQTYP_ADDR (REG_STDIO_UART_BASE_ADDR + 0x0008)
292 #define STDIO_UART_IRQTYP_OFFSET 0x00000008
293 #define STDIO_UART_IRQTYP_INDEX 0x00000002
294 #define STDIO_UART_IRQTYP_RESET 0x00000061
295
stdio_uart_irqtyp_get(void)296 __STATIC_INLINE uint32_t stdio_uart_irqtyp_get(void)
297 {
298 return PLATFORM_REG_READ(STDIO_UART_IRQTYP_ADDR);
299 }
300
301 // field definitions
302 #define STDIO_UART_IRQTYP_MASK ((uint32_t)0x0000000F)
303 #define STDIO_UART_IRQTYP_LSB 0
304 #define STDIO_UART_IRQTYP_WIDTH ((uint32_t)0x00000004)
305
306 #define STDIO_UART_IRQTYP_RST 0x1
307
stdio_uart_irqtyp_getf(void)308 __STATIC_INLINE uint8_t stdio_uart_irqtyp_getf(void)
309 {
310 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_IRQTYP_ADDR);
311 return ((localVal & ((uint32_t)0x0000000F)) >> 0);
312 }
313
314 /**
315 * @brief DBUFCFG register definition
316 * <pre>
317 * Bits Field Name Reset Value
318 * ----- ------------------ -----------
319 * 02 TXDRST 0
320 * 01 RXDRST 0
321 * 00 DBUFEN 0
322 * </pre>
323 */
324 #define STDIO_UART_DBUFCFG_ADDR (REG_STDIO_UART_BASE_ADDR + 0x0008)
325 #define STDIO_UART_DBUFCFG_OFFSET 0x00000008
326 #define STDIO_UART_DBUFCFG_INDEX 0x00000002
327 #define STDIO_UART_DBUFCFG_RESET 0x00000000
328
stdio_uart_dbufcfg_set(uint32_t value)329 __STATIC_INLINE void stdio_uart_dbufcfg_set(uint32_t value)
330 {
331 PLATFORM_REG_WRITE(STDIO_UART_DBUFCFG_ADDR, value);
332 }
333
334 // field definitions
335 #define STDIO_UART_TXDRST_BIT ((uint32_t)0x00000004)
336 #define STDIO_UART_TXDRST_POS 2
337 #define STDIO_UART_RXDRST_BIT ((uint32_t)0x00000002)
338 #define STDIO_UART_RXDRST_POS 1
339 #define STDIO_UART_DBUFEN_BIT ((uint32_t)0x00000001)
340 #define STDIO_UART_DBUFEN_POS 0
341
342 #define STDIO_UART_TXDRST_RST 0x0
343 #define STDIO_UART_RXDRST_RST 0x0
344 #define STDIO_UART_DBUFEN_RST 0x0
345
stdio_uart_dbufcfg_pack(uint8_t txdrst,uint8_t rxdrst,uint8_t dbufen)346 __STATIC_INLINE void stdio_uart_dbufcfg_pack(uint8_t txdrst, uint8_t rxdrst, uint8_t dbufen)
347 {
348 PLATFORM_REG_WRITE(STDIO_UART_DBUFCFG_ADDR, ((uint32_t)txdrst << 2) | ((uint32_t)rxdrst << 1) | ((uint32_t)dbufen << 0));
349 }
350
stdio_uart_txdrst_setf(uint8_t txdrst)351 __STATIC_INLINE void stdio_uart_txdrst_setf(uint8_t txdrst)
352 {
353 PLATFORM_REG_WRITE(STDIO_UART_DBUFCFG_ADDR, (PLATFORM_REG_READ(STDIO_UART_DBUFCFG_ADDR) & ~((uint32_t)0x00000004)) | ((uint32_t)txdrst << 2));
354 }
355
stdio_uart_rxdrst_setf(uint8_t rxdrst)356 __STATIC_INLINE void stdio_uart_rxdrst_setf(uint8_t rxdrst)
357 {
358 PLATFORM_REG_WRITE(STDIO_UART_DBUFCFG_ADDR, (PLATFORM_REG_READ(STDIO_UART_DBUFCFG_ADDR) & ~((uint32_t)0x00000002)) | ((uint32_t)rxdrst << 1));
359 }
360
stdio_uart_dbufen_setf(uint8_t dbufen)361 __STATIC_INLINE void stdio_uart_dbufen_setf(uint8_t dbufen)
362 {
363 PLATFORM_REG_WRITE(STDIO_UART_DBUFCFG_ADDR, (PLATFORM_REG_READ(STDIO_UART_DBUFCFG_ADDR) & ~((uint32_t)0x00000001)) | ((uint32_t)dbufen << 0));
364 }
365
366 /**
367 * @brief DFMTCFG register definition
368 * <pre>
369 * Bits Field Name Reset Value
370 * ----- ------------------ -----------
371 * 08 DIVMS 0
372 * 07 DIVAE 0
373 * 06 BRK 0
374 * 04 EPS 0
375 * 03 PEN 0
376 * 02 STOP 0
377 * 01:00 DLS 0x3
378 * </pre>
379 */
380 #define STDIO_UART_DFMTCFG_ADDR (REG_STDIO_UART_BASE_ADDR + 0x000C)
381 #define STDIO_UART_DFMTCFG_OFFSET 0x0000000C
382 #define STDIO_UART_DFMTCFG_INDEX 0x00000003
383 #define STDIO_UART_DFMTCFG_RESET 0x00000003
384
stdio_uart_dfmtcfg_get(void)385 __STATIC_INLINE uint32_t stdio_uart_dfmtcfg_get(void)
386 {
387 return PLATFORM_REG_READ(STDIO_UART_DFMTCFG_ADDR);
388 }
389
stdio_uart_dfmtcfg_set(uint32_t value)390 __STATIC_INLINE void stdio_uart_dfmtcfg_set(uint32_t value)
391 {
392 PLATFORM_REG_WRITE(STDIO_UART_DFMTCFG_ADDR, value);
393 }
394
395 // field definitions
396 #define STDIO_UART_DIVMS_BIT ((uint32_t)0x00000100)
397 #define STDIO_UART_DIVMS_POS 8
398 #define STDIO_UART_DIVAE_BIT ((uint32_t)0x00000080)
399 #define STDIO_UART_DIVAE_POS 7
400 #define STDIO_UART_BRK_BIT ((uint32_t)0x00000040)
401 #define STDIO_UART_BRK_POS 6
402 #define STDIO_UART_EPS_BIT ((uint32_t)0x00000010)
403 #define STDIO_UART_EPS_POS 4
404 #define STDIO_UART_PEN_BIT ((uint32_t)0x00000008)
405 #define STDIO_UART_PEN_POS 3
406 #define STDIO_UART_STOP_BIT ((uint32_t)0x00000004)
407 #define STDIO_UART_STOP_POS 2
408 #define STDIO_UART_DLS_MASK ((uint32_t)0x00000003)
409 #define STDIO_UART_DLS_LSB 0
410 #define STDIO_UART_DLS_WIDTH ((uint32_t)0x00000002)
411
412 #define STDIO_UART_DIVMS_RST 0x0
413 #define STDIO_UART_DIVAE_RST 0x0
414 #define STDIO_UART_BRK_RST 0x0
415 #define STDIO_UART_EPS_RST 0x0
416 #define STDIO_UART_PEN_RST 0x0
417 #define STDIO_UART_STOP_RST 0x0
418 #define STDIO_UART_DLS_RST 0x3
419
stdio_uart_dfmtcfg_pack(uint8_t divms,uint8_t divae,uint8_t brk,uint8_t eps,uint8_t pen,uint8_t stop,uint8_t dls)420 __STATIC_INLINE void stdio_uart_dfmtcfg_pack(uint8_t divms, uint8_t divae, uint8_t brk, uint8_t eps, uint8_t pen, uint8_t stop, uint8_t dls)
421 {
422 ASSERT_ERR((((uint32_t)divms << 8) & ~((uint32_t)0x00000100)) == 0);
423 ASSERT_ERR((((uint32_t)divae << 7) & ~((uint32_t)0x00000080)) == 0);
424 ASSERT_ERR((((uint32_t)brk << 6) & ~((uint32_t)0x00000040)) == 0);
425 ASSERT_ERR((((uint32_t)eps << 4) & ~((uint32_t)0x00000010)) == 0);
426 ASSERT_ERR((((uint32_t)pen << 3) & ~((uint32_t)0x00000008)) == 0);
427 ASSERT_ERR((((uint32_t)stop << 2) & ~((uint32_t)0x00000004)) == 0);
428 ASSERT_ERR((((uint32_t)dls << 0) & ~((uint32_t)0x00000003)) == 0);
429 PLATFORM_REG_WRITE(STDIO_UART_DFMTCFG_ADDR, ((uint32_t)divms << 8) | ((uint32_t)divae << 7) | ((uint32_t)brk << 6) | ((uint32_t)eps << 4) | ((uint32_t)pen << 3) | ((uint32_t)stop << 2) | ((uint32_t)dls << 0));
430 }
431
stdio_uart_dfmtcfg_unpack(uint8_t * divms,uint8_t * divae,uint8_t * brk,uint8_t * eps,uint8_t * pen,uint8_t * stop,uint8_t * dls)432 __STATIC_INLINE void stdio_uart_dfmtcfg_unpack(uint8_t* divms, uint8_t* divae, uint8_t* brk, uint8_t* eps, uint8_t* pen, uint8_t* stop, uint8_t* dls)
433 {
434 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_DFMTCFG_ADDR);
435
436 *divms = (localVal & ((uint32_t)0x00000100)) >> 8;
437 *divae = (localVal & ((uint32_t)0x00000080)) >> 7;
438 *brk = (localVal & ((uint32_t)0x00000040)) >> 6;
439 *eps = (localVal & ((uint32_t)0x00000010)) >> 4;
440 *pen = (localVal & ((uint32_t)0x00000008)) >> 3;
441 *stop = (localVal & ((uint32_t)0x00000004)) >> 2;
442 *dls = (localVal & ((uint32_t)0x00000003)) >> 0;
443 }
444
stdio_uart_divms_getf(void)445 __STATIC_INLINE uint8_t stdio_uart_divms_getf(void)
446 {
447 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_DFMTCFG_ADDR);
448 return ((localVal & ((uint32_t)0x00000100)) >> 8);
449 }
450
stdio_uart_divms_setf(uint8_t divmode)451 __STATIC_INLINE void stdio_uart_divms_setf(uint8_t divmode)
452 {
453 ASSERT_ERR((((uint32_t)divmode << 8) & ~((uint32_t)0x00000100)) == 0);
454 PLATFORM_REG_WRITE(STDIO_UART_DFMTCFG_ADDR, (PLATFORM_REG_READ(STDIO_UART_DFMTCFG_ADDR) & ~((uint32_t)0x00000100)) | ((uint32_t)divmode << 8));
455 }
456
stdio_uart_divae_getf(void)457 __STATIC_INLINE uint8_t stdio_uart_divae_getf(void)
458 {
459 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_DFMTCFG_ADDR);
460 return ((localVal & ((uint32_t)0x00000080)) >> 7);
461 }
462
stdio_uart_divae_setf(uint8_t DIVAE)463 __STATIC_INLINE void stdio_uart_divae_setf(uint8_t DIVAE)
464 {
465 ASSERT_ERR((((uint32_t)DIVAE << 7) & ~((uint32_t)0x00000080)) == 0);
466 PLATFORM_REG_WRITE(STDIO_UART_DFMTCFG_ADDR, (PLATFORM_REG_READ(STDIO_UART_DFMTCFG_ADDR) & ~((uint32_t)0x00000080)) | ((uint32_t)DIVAE << 7));
467 }
468
stdio_uart_brk_getf(void)469 __STATIC_INLINE uint8_t stdio_uart_brk_getf(void)
470 {
471 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_DFMTCFG_ADDR);
472 return ((localVal & ((uint32_t)0x00000040)) >> 6);
473 }
474
stdio_uart_brk_setf(uint8_t brk)475 __STATIC_INLINE void stdio_uart_brk_setf(uint8_t brk)
476 {
477 ASSERT_ERR((((uint32_t)brk << 6) & ~((uint32_t)0x00000040)) == 0);
478 PLATFORM_REG_WRITE(STDIO_UART_DFMTCFG_ADDR, (PLATFORM_REG_READ(STDIO_UART_DFMTCFG_ADDR) & ~((uint32_t)0x00000040)) | ((uint32_t)brk << 6));
479 }
480
stdio_uart_eps_getf(void)481 __STATIC_INLINE uint8_t stdio_uart_eps_getf(void)
482 {
483 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_DFMTCFG_ADDR);
484 return ((localVal & ((uint32_t)0x00000010)) >> 4);
485 }
486
stdio_uart_eps_setf(uint8_t eps)487 __STATIC_INLINE void stdio_uart_eps_setf(uint8_t eps)
488 {
489 ASSERT_ERR((((uint32_t)eps << 4) & ~((uint32_t)0x00000010)) == 0);
490 PLATFORM_REG_WRITE(STDIO_UART_DFMTCFG_ADDR, (PLATFORM_REG_READ(STDIO_UART_DFMTCFG_ADDR) & ~((uint32_t)0x00000010)) | ((uint32_t)eps << 4));
491 }
492
stdio_uart_pen_getf(void)493 __STATIC_INLINE uint8_t stdio_uart_pen_getf(void)
494 {
495 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_DFMTCFG_ADDR);
496 return ((localVal & ((uint32_t)0x00000008)) >> 3);
497 }
498
stdio_uart_pen_setf(uint8_t pen)499 __STATIC_INLINE void stdio_uart_pen_setf(uint8_t pen)
500 {
501 ASSERT_ERR((((uint32_t)pen << 3) & ~((uint32_t)0x00000008)) == 0);
502 PLATFORM_REG_WRITE(STDIO_UART_DFMTCFG_ADDR, (PLATFORM_REG_READ(STDIO_UART_DFMTCFG_ADDR) & ~((uint32_t)0x00000008)) | ((uint32_t)pen << 3));
503 }
504
stdio_uart_stop_getf(void)505 __STATIC_INLINE uint8_t stdio_uart_stop_getf(void)
506 {
507 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_DFMTCFG_ADDR);
508 return ((localVal & ((uint32_t)0x00000004)) >> 2);
509 }
510
stdio_uart_stop_setf(uint8_t stop)511 __STATIC_INLINE void stdio_uart_stop_setf(uint8_t stop)
512 {
513 ASSERT_ERR((((uint32_t)stop << 2) & ~((uint32_t)0x00000004)) == 0);
514 PLATFORM_REG_WRITE(STDIO_UART_DFMTCFG_ADDR, (PLATFORM_REG_READ(STDIO_UART_DFMTCFG_ADDR) & ~((uint32_t)0x00000004)) | ((uint32_t)stop << 2));
515 }
516
stdio_uart_dls_getf(void)517 __STATIC_INLINE uint8_t stdio_uart_dls_getf(void)
518 {
519 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_DFMTCFG_ADDR);
520 return ((localVal & ((uint32_t)0x00000003)) >> 0);
521 }
522
stdio_uart_dls_setf(uint8_t dls)523 __STATIC_INLINE void stdio_uart_dls_setf(uint8_t dls)
524 {
525 ASSERT_ERR((((uint32_t)dls << 0) & ~((uint32_t)0x00000003)) == 0);
526 PLATFORM_REG_WRITE(STDIO_UART_DFMTCFG_ADDR, (PLATFORM_REG_READ(STDIO_UART_DFMTCFG_ADDR) & ~((uint32_t)0x00000003)) | ((uint32_t)dls << 0));
527 }
528
529 /**
530 * @brief MDMCFG register definition
531 * <pre>
532 * Bits Field Name Reset Value
533 * ----- ------------------ -----------
534 * 08 CLK_P 0
535 * 07 AUTO_DET 0
536 * 06 SIRE 0
537 * 05 AFCE 0
538 * 04 LOOPBACK 0
539 * 03 OUT2 0
540 * 02 OUT1 0
541 * 01 RTS 0
542 * 00 DTR 0
543 * </pre>
544 */
545 #define STDIO_UART_MDMCFG_ADDR (REG_STDIO_UART_BASE_ADDR + 0x0010)
546 #define STDIO_UART_MDMCFG_OFFSET 0x00000010
547 #define STDIO_UART_MDMCFG_INDEX 0x00000004
548 #define STDIO_UART_MDMCFG_RESET 0x00000000
549
stdio_uart_mdmcfg_get(void)550 __STATIC_INLINE uint32_t stdio_uart_mdmcfg_get(void)
551 {
552 return PLATFORM_REG_READ(STDIO_UART_MDMCFG_ADDR);
553 }
554
stdio_uart_mdmcfg_set(uint32_t value)555 __STATIC_INLINE void stdio_uart_mdmcfg_set(uint32_t value)
556 {
557 PLATFORM_REG_WRITE(STDIO_UART_MDMCFG_ADDR, value);
558 }
559
560 // field definitions
561 #define STDIO_UART_CLK_P_BIT ((uint32_t)0x00000100)
562 #define STDIO_UART_CLK_P_POS 8
563 #define STDIO_UART_AUTO_DET_BIT ((uint32_t)0x00000080)
564 #define STDIO_UART_AUTO_DET_POS 7
565 #define STDIO_UART_SIRE_BIT ((uint32_t)0x00000040)
566 #define STDIO_UART_SIRE_POS 6
567 #define STDIO_UART_AFCE_BIT ((uint32_t)0x00000020)
568 #define STDIO_UART_AFCE_POS 5
569 #define STDIO_UART_LOOPBACK_BIT ((uint32_t)0x00000010)
570 #define STDIO_UART_LOOPBACK_POS 4
571 #define STDIO_UART_OUT2_BIT ((uint32_t)0x00000008)
572 #define STDIO_UART_OUT2_POS 3
573 #define STDIO_UART_OUT1_BIT ((uint32_t)0x00000004)
574 #define STDIO_UART_OUT1_POS 2
575 #define STDIO_UART_RTS_BIT ((uint32_t)0x00000002)
576 #define STDIO_UART_RTS_POS 1
577 #define STDIO_UART_DTR_BIT ((uint32_t)0x00000001)
578 #define STDIO_UART_DTR_POS 0
579
580 #define STDIO_UART_CLK_P_RST 0x0
581 #define STDIO_UART_AUTO_DET_RST 0x0
582 #define STDIO_UART_SIRE_RST 0x0
583 #define STDIO_UART_AFCE_RST 0x0
584 #define STDIO_UART_LOOPBACK_RST 0x0
585 #define STDIO_UART_OUT2_RST 0x0
586 #define STDIO_UART_OUT1_RST 0x0
587 #define STDIO_UART_RTS_RST 0x0
588 #define STDIO_UART_DTR_RST 0x0
589
stdio_uart_mdmcfg_pack(uint8_t clkp,uint8_t autodet,uint8_t sire,uint8_t afce,uint8_t loopback,uint8_t out2,uint8_t out1,uint8_t rts,uint8_t dtr)590 __STATIC_INLINE void stdio_uart_mdmcfg_pack(uint8_t clkp, uint8_t autodet, uint8_t sire, uint8_t afce, uint8_t loopback, uint8_t out2, uint8_t out1, uint8_t rts, uint8_t dtr)
591 {
592 PLATFORM_REG_WRITE(STDIO_UART_MDMCFG_ADDR, ((uint32_t)clkp << 8) | ((uint32_t)autodet << 7) | ((uint32_t)sire << 6) | ((uint32_t)afce << 5) | ((uint32_t)loopback << 4) | ((uint32_t)out2 << 3) | ((uint32_t)out1 << 2) | ((uint32_t)rts << 1) | ((uint32_t)dtr << 0));
593 }
594
stdio_uart_mdmcfg_unpack(uint8_t * clkp,uint8_t * autodet,uint8_t * sire,uint8_t * afce,uint8_t * loopback,uint8_t * out2,uint8_t * out1,uint8_t * rts,uint8_t * dtr)595 __STATIC_INLINE void stdio_uart_mdmcfg_unpack(uint8_t* clkp, uint8_t* autodet, uint8_t* sire, uint8_t* afce, uint8_t* loopback, uint8_t* out2, uint8_t* out1, uint8_t* rts, uint8_t* dtr)
596 {
597 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_MDMCFG_ADDR);
598
599 *clkp = (localVal & ((uint32_t)0x00000100)) >> 8;
600 *autodet = (localVal & ((uint32_t)0x00000080)) >> 7;
601 *sire = (localVal & ((uint32_t)0x00000040)) >> 6;
602 *afce = (localVal & ((uint32_t)0x00000020)) >> 5;
603 *loopback = (localVal & ((uint32_t)0x00000010)) >> 4;
604 *out2 = (localVal & ((uint32_t)0x00000008)) >> 3;
605 *out1 = (localVal & ((uint32_t)0x00000004)) >> 2;
606 *rts = (localVal & ((uint32_t)0x00000002)) >> 1;
607 *dtr = (localVal & ((uint32_t)0x00000001)) >> 0;
608 }
609
stdio_uart_clk_p_getf(void)610 __STATIC_INLINE uint8_t stdio_uart_clk_p_getf(void)
611 {
612 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_MDMCFG_ADDR);
613 return ((localVal & ((uint32_t)0x00000100)) >> 8);
614 }
615
stdio_uart_clk_p_setf(uint8_t clkp)616 __STATIC_INLINE void stdio_uart_clk_p_setf(uint8_t clkp)
617 {
618 PLATFORM_REG_WRITE(STDIO_UART_MDMCFG_ADDR, (PLATFORM_REG_READ(STDIO_UART_MDMCFG_ADDR) & ~((uint32_t)0x00000100)) | ((uint32_t)clkp << 8));
619 }
620
stdio_uart_auto_det_getf(void)621 __STATIC_INLINE uint8_t stdio_uart_auto_det_getf(void)
622 {
623 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_MDMCFG_ADDR);
624 return ((localVal & ((uint32_t)0x00000080)) >> 7);
625 }
626
stdio_uart_auto_det_setf(uint8_t autodet)627 __STATIC_INLINE void stdio_uart_auto_det_setf(uint8_t autodet)
628 {
629 PLATFORM_REG_WRITE(STDIO_UART_MDMCFG_ADDR, (PLATFORM_REG_READ(STDIO_UART_MDMCFG_ADDR) & ~((uint32_t)0x00000080)) | ((uint32_t)autodet << 7));
630 }
631
stdio_uart_sire_getf(void)632 __STATIC_INLINE uint8_t stdio_uart_sire_getf(void)
633 {
634 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_MDMCFG_ADDR);
635 return ((localVal & ((uint32_t)0x00000040)) >> 6);
636 }
637
stdio_uart_sire_setf(uint8_t sire)638 __STATIC_INLINE void stdio_uart_sire_setf(uint8_t sire)
639 {
640 PLATFORM_REG_WRITE(STDIO_UART_MDMCFG_ADDR, (PLATFORM_REG_READ(STDIO_UART_MDMCFG_ADDR) & ~((uint32_t)0x00000040)) | ((uint32_t)sire << 6));
641 }
642
stdio_uart_afce_getf(void)643 __STATIC_INLINE uint8_t stdio_uart_afce_getf(void)
644 {
645 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_MDMCFG_ADDR);
646 return ((localVal & ((uint32_t)0x00000020)) >> 5);
647 }
648
stdio_uart_afce_setf(uint8_t afce)649 __STATIC_INLINE void stdio_uart_afce_setf(uint8_t afce)
650 {
651 PLATFORM_REG_WRITE(STDIO_UART_MDMCFG_ADDR, (PLATFORM_REG_READ(STDIO_UART_MDMCFG_ADDR) & ~((uint32_t)0x00000020)) | ((uint32_t)afce << 5));
652 }
653
stdio_uart_loopback_getf(void)654 __STATIC_INLINE uint8_t stdio_uart_loopback_getf(void)
655 {
656 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_MDMCFG_ADDR);
657 return ((localVal & ((uint32_t)0x00000010)) >> 4);
658 }
659
stdio_uart_loopback_setf(uint8_t loopback)660 __STATIC_INLINE void stdio_uart_loopback_setf(uint8_t loopback)
661 {
662 PLATFORM_REG_WRITE(STDIO_UART_MDMCFG_ADDR, (PLATFORM_REG_READ(STDIO_UART_MDMCFG_ADDR) & ~((uint32_t)0x00000010)) | ((uint32_t)loopback << 4));
663 }
664
stdio_uart_out2_getf(void)665 __STATIC_INLINE uint8_t stdio_uart_out2_getf(void)
666 {
667 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_MDMCFG_ADDR);
668 return ((localVal & ((uint32_t)0x00000008)) >> 3);
669 }
670
stdio_uart_out2_setf(uint8_t out2)671 __STATIC_INLINE void stdio_uart_out2_setf(uint8_t out2)
672 {
673 PLATFORM_REG_WRITE(STDIO_UART_MDMCFG_ADDR, (PLATFORM_REG_READ(STDIO_UART_MDMCFG_ADDR) & ~((uint32_t)0x00000008)) | ((uint32_t)out2 << 3));
674 }
675
stdio_uart_out1_getf(void)676 __STATIC_INLINE uint8_t stdio_uart_out1_getf(void)
677 {
678 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_MDMCFG_ADDR);
679 return ((localVal & ((uint32_t)0x00000004)) >> 2);
680 }
681
stdio_uart_out1_setf(uint8_t out1)682 __STATIC_INLINE void stdio_uart_out1_setf(uint8_t out1)
683 {
684 PLATFORM_REG_WRITE(STDIO_UART_MDMCFG_ADDR, (PLATFORM_REG_READ(STDIO_UART_MDMCFG_ADDR) & ~((uint32_t)0x00000004)) | ((uint32_t)out1 << 2));
685 }
686
stdio_uart_rts_getf(void)687 __STATIC_INLINE uint8_t stdio_uart_rts_getf(void)
688 {
689 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_MDMCFG_ADDR);
690 return ((localVal & ((uint32_t)0x00000002)) >> 1);
691 }
692
stdio_uart_rts_setf(uint8_t rts)693 __STATIC_INLINE void stdio_uart_rts_setf(uint8_t rts)
694 {
695 PLATFORM_REG_WRITE(STDIO_UART_MDMCFG_ADDR, (PLATFORM_REG_READ(STDIO_UART_MDMCFG_ADDR) & ~((uint32_t)0x00000002)) | ((uint32_t)rts << 1));
696 }
697
stdio_uart_dtr_getf(void)698 __STATIC_INLINE uint8_t stdio_uart_dtr_getf(void)
699 {
700 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_MDMCFG_ADDR);
701 return ((localVal & ((uint32_t)0x00000001)) >> 0);
702 }
703
stdio_uart_dtr_setf(uint8_t dtr)704 __STATIC_INLINE void stdio_uart_dtr_setf(uint8_t dtr)
705 {
706 PLATFORM_REG_WRITE(STDIO_UART_MDMCFG_ADDR, (PLATFORM_REG_READ(STDIO_UART_MDMCFG_ADDR) & ~((uint32_t)0x00000001)) | ((uint32_t)dtr << 0));
707 }
708
709 /**
710 * @brief IRQSTS register definition
711 * <pre>
712 * Bits Field Name Reset Value
713 * ----- ------------------ -----------
714 * 08 RTDR 0
715 * 07 RFE 0
716 * 06 TEMT 1
717 * 05 THRE 1
718 * 01 OE 0
719 * 00 DR 0
720 * </pre>
721 */
722 #define STDIO_UART_IRQSTS_ADDR (REG_STDIO_UART_BASE_ADDR + 0x0014)
723 #define STDIO_UART_IRQSTS_OFFSET 0x00000014
724 #define STDIO_UART_IRQSTS_INDEX 0x00000005
725 #define STDIO_UART_IRQSTS_RESET 0x00000060
726
stdio_uart_irqsts_get(void)727 __STATIC_INLINE uint32_t stdio_uart_irqsts_get(void)
728 {
729 return PLATFORM_REG_READ(STDIO_UART_IRQSTS_ADDR);
730 }
731
732 // field definitions
733 #define STDIO_UART_RTDR_BIT ((uint32_t)0x00000100)
734 #define STDIO_UART_RTDR_POS 8
735 #define STDIO_UART_RFE_BIT ((uint32_t)0x00000080)
736 #define STDIO_UART_RFE_POS 7
737 #define STDIO_UART_TEMT_BIT ((uint32_t)0x00000040)
738 #define STDIO_UART_TEMT_POS 6
739 #define STDIO_UART_THRE_BIT ((uint32_t)0x00000020)
740 #define STDIO_UART_THRE_POS 5
741 #define STDIO_UART_OE_BIT ((uint32_t)0x00000002)
742 #define STDIO_UART_OE_POS 1
743 #define STDIO_UART_DR_BIT ((uint32_t)0x00000001)
744 #define STDIO_UART_DR_POS 0
745
746 #define STDIO_UART_RTDR_RST 0x0
747 #define STDIO_UART_RFE_RST 0x0
748 #define STDIO_UART_TEMT_RST 0x1
749 #define STDIO_UART_THRE_RST 0x1
750 #define STDIO_UART_OE_RST 0x0
751 #define STDIO_UART_DR_RST 0x0
752
stdio_uart_irqsts_unpack(uint8_t * rtdr,uint8_t * rfe,uint8_t * temt,uint8_t * thre,uint8_t * oe,uint8_t * dr)753 __STATIC_INLINE void stdio_uart_irqsts_unpack(uint8_t* rtdr, uint8_t* rfe, uint8_t* temt, uint8_t* thre, uint8_t* oe, uint8_t* dr)
754 {
755 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_IRQSTS_ADDR);
756
757 *rtdr = (localVal & ((uint32_t)0x00000100)) >> 8;
758 *rfe = (localVal & ((uint32_t)0x00000080)) >> 7;
759 *temt = (localVal & ((uint32_t)0x00000040)) >> 6;
760 *thre = (localVal & ((uint32_t)0x00000020)) >> 5;
761 *oe = (localVal & ((uint32_t)0x00000002)) >> 1;
762 *dr = (localVal & ((uint32_t)0x00000001)) >> 0;
763 }
764
stdio_uart_rtdr_getf(void)765 __STATIC_INLINE uint8_t stdio_uart_rtdr_getf(void)
766 {
767 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_IRQSTS_ADDR);
768 return ((localVal & ((uint32_t)0x00000100)) >> 8);
769 }
770
stdio_uart_rfe_getf(void)771 __STATIC_INLINE uint8_t stdio_uart_rfe_getf(void)
772 {
773 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_IRQSTS_ADDR);
774 return ((localVal & ((uint32_t)0x00000080)) >> 7);
775 }
776
stdio_uart_temt_getf(void)777 __STATIC_INLINE uint8_t stdio_uart_temt_getf(void)
778 {
779 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_IRQSTS_ADDR);
780 return ((localVal & ((uint32_t)0x00000040)) >> 6);
781 }
782
stdio_uart_thre_getf(void)783 __STATIC_INLINE uint8_t stdio_uart_thre_getf(void)
784 {
785 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_IRQSTS_ADDR);
786 return ((localVal & ((uint32_t)0x00000020)) >> 5);
787 }
788
stdio_uart_oe_getf(void)789 __STATIC_INLINE uint8_t stdio_uart_oe_getf(void)
790 {
791 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_IRQSTS_ADDR);
792 return ((localVal & ((uint32_t)0x00000002)) >> 1);
793 }
794
stdio_uart_dr_getf(void)795 __STATIC_INLINE uint8_t stdio_uart_dr_getf(void)
796 {
797 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_IRQSTS_ADDR);
798 return ((localVal & ((uint32_t)0x00000001)) >> 0);
799 }
800
801 /**
802 * @brief MDMSTS register definition
803 */
804 #define STDIO_UART_MDMSTS_ADDR (REG_STDIO_UART_BASE_ADDR + 0x0018)
805 #define STDIO_UART_MDMSTS_OFFSET 0x00000018
806 #define STDIO_UART_MDMSTS_INDEX 0x00000006
807 #define STDIO_UART_MDMSTS_RESET 0x00000060
808
stdio_uart_mdmsts_get(void)809 __STATIC_INLINE uint32_t stdio_uart_mdmsts_get(void)
810 {
811 return PLATFORM_REG_READ(STDIO_UART_MDMSTS_ADDR);
812 }
813
814 /**
815 * @brief DBUFSTS register definition
816 * <pre>
817 * Bits Field Name Reset Value
818 * ----- ------------------ -----------
819 * 21 RX_DBUF_FULL 0
820 * 20 RX_DBUF_EMPTY 1
821 * 19 TX_DBUF_FULL 0
822 * 18 TX_DBUF_EMPTY 1
823 * 16:09 RX_COUNT 0x0
824 * 07:00 TX_COUNT 0x0
825 * </pre>
826 */
827 #define STDIO_UART_DBUFSTS_ADDR (REG_STDIO_UART_BASE_ADDR + 0x0020)
828 #define STDIO_UART_DBUFSTS_OFFSET 0x00000020
829 #define STDIO_UART_DBUFSTS_INDEX 0x00000008
830 #define STDIO_UART_DBUFSTS_RESET 0x00140000
831
stdio_uart_dbufsts_get(void)832 __STATIC_INLINE uint32_t stdio_uart_dbufsts_get(void)
833 {
834 return PLATFORM_REG_READ(STDIO_UART_DBUFSTS_ADDR);
835 }
836
837 // field definitions
838 #define STDIO_UART_RX_DBUF_FULL_BIT ((uint32_t)0x00200000)
839 #define STDIO_UART_RX_DBUF_FULL_POS 21
840 #define STDIO_UART_RX_DBUF_EMPTY_BIT ((uint32_t)0x00100000)
841 #define STDIO_UART_RX_DBUF_EMPTY_POS 20
842 #define STDIO_UART_TX_DBUF_FULL_BIT ((uint32_t)0x00080000)
843 #define STDIO_UART_TX_DBUF_FULL_POS 19
844 #define STDIO_UART_TX_DBUF_EMPTY_BIT ((uint32_t)0x00040000)
845 #define STDIO_UART_TX_DBUF_EMPTY_POS 18
846 #define STDIO_UART_RX_COUNT_MASK ((uint32_t)0x0001FE00)
847 #define STDIO_UART_RX_COUNT_LSB 9
848 #define STDIO_UART_RX_COUNT_WIDTH ((uint32_t)0x00000008)
849 #define STDIO_UART_TX_COUNT_MASK ((uint32_t)0x000000FF)
850 #define STDIO_UART_TX_COUNT_LSB 0
851 #define STDIO_UART_TX_COUNT_WIDTH ((uint32_t)0x00000008)
852
853 #define STDIO_UART_RX_DBUF_FULL_RST 0x0
854 #define STDIO_UART_RX_DBUF_EMPTY_RST 0x1
855 #define STDIO_UART_TX_DBUF_FULL_RST 0x0
856 #define STDIO_UART_TX_DBUF_EMPTY_RST 0x1
857 #define STDIO_UART_RX_COUNT_RST 0x0
858 #define STDIO_UART_TX_COUNT_RST 0x0
859
stdio_uart_dbufsts_unpack(uint8_t * rxdbuffull,uint8_t * rxdbufempty,uint8_t * txdbuffull,uint8_t * txdbufempty,uint16_t * rxcount,uint16_t * txcount)860 __STATIC_INLINE void stdio_uart_dbufsts_unpack(uint8_t* rxdbuffull, uint8_t* rxdbufempty, uint8_t* txdbuffull, uint8_t* txdbufempty, uint16_t* rxcount, uint16_t* txcount)
861 {
862 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_DBUFSTS_ADDR);
863
864 *rxdbuffull = (localVal & ((uint32_t)0x00200000)) >> 21;
865 *rxdbufempty = (localVal & ((uint32_t)0x00100000)) >> 20;
866 *txdbuffull = (localVal & ((uint32_t)0x00080000)) >> 19;
867 *txdbufempty = (localVal & ((uint32_t)0x00040000)) >> 18;
868 *rxcount = (localVal & ((uint32_t)0x0001FE00)) >> 9;
869 *txcount = (localVal & ((uint32_t)0x000000FF)) >> 0;
870 }
871
stdio_uart_rx_dbuf_full_getf(void)872 __STATIC_INLINE uint8_t stdio_uart_rx_dbuf_full_getf(void)
873 {
874 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_DBUFSTS_ADDR);
875 return ((localVal & ((uint32_t)0x00200000)) >> 21);
876 }
877
stdio_uart_rx_dbuf_empty_getf(void)878 __STATIC_INLINE uint8_t stdio_uart_rx_dbuf_empty_getf(void)
879 {
880 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_DBUFSTS_ADDR);
881 return ((localVal & ((uint32_t)0x00100000)) >> 20);
882 }
883
stdio_uart_tx_dbuf_full_getf(void)884 __STATIC_INLINE uint8_t stdio_uart_tx_dbuf_full_getf(void)
885 {
886 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_DBUFSTS_ADDR);
887 return ((localVal & ((uint32_t)0x00080000)) >> 19);
888 }
889
stdio_uart_tx_dbuf_empty_getf(void)890 __STATIC_INLINE uint8_t stdio_uart_tx_dbuf_empty_getf(void)
891 {
892 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_DBUFSTS_ADDR);
893 return ((localVal & ((uint32_t)0x00040000)) >> 18);
894 }
895
stdio_uart_rx_count_getf(void)896 __STATIC_INLINE uint16_t stdio_uart_rx_count_getf(void)
897 {
898 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_DBUFSTS_ADDR);
899 return ((localVal & ((uint32_t)0x0001FE00)) >> 9);
900 }
901
stdio_uart_tx_count_getf(void)902 __STATIC_INLINE uint16_t stdio_uart_tx_count_getf(void)
903 {
904 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_DBUFSTS_ADDR);
905 return ((localVal & ((uint32_t)0x000000FF)) >> 0);
906 }
907
908 /**
909 * @brief DBUFTH register definition
910 * <pre>
911 * Bits Field Name Reset Value
912 * ----- ------------------ -----------
913 * 16:09 TXTRIGTH 0x10
914 * 07:00 RXTRIGTH 0x10
915 * </pre>
916 */
917 #define STDIO_UART_DBUFTH_ADDR (REG_STDIO_UART_BASE_ADDR + 0x0024)
918 #define STDIO_UART_DBUFTH_OFFSET 0x00000024
919 #define STDIO_UART_DBUFTH_INDEX 0x00000009
920 #define STDIO_UART_DBUFTH_RESET 0x00000810
921
stdio_uart_dbufth_get(void)922 __STATIC_INLINE uint32_t stdio_uart_dbufth_get(void)
923 {
924 return PLATFORM_REG_READ(STDIO_UART_DBUFTH_ADDR);
925 }
926
stdio_uart_dbufth_set(uint32_t value)927 __STATIC_INLINE void stdio_uart_dbufth_set(uint32_t value)
928 {
929 PLATFORM_REG_WRITE(STDIO_UART_DBUFTH_ADDR, value);
930 }
931
932 // field definitions
933 #define STDIO_UART_TXTRIGTH_MASK ((uint32_t)0x0001FE00)
934 #define STDIO_UART_TXTRIGTH_LSB 9
935 #define STDIO_UART_TXTRIGTH_WIDTH ((uint32_t)0x00000008)
936 #define STDIO_UART_RXTRIGTH_MASK ((uint32_t)0x000000FF)
937 #define STDIO_UART_RXTRIGTH_LSB 0
938 #define STDIO_UART_RXTRIGTH_WIDTH ((uint32_t)0x00000008)
939
940 #define STDIO_UART_TXTRIGTH_RST 0x10
941 #define STDIO_UART_RXTRIGTH_RST 0x10
942
stdio_uart_dbufth_pack(uint8_t txtrigth,uint8_t rxtrigth)943 __STATIC_INLINE void stdio_uart_dbufth_pack(uint8_t txtrigth, uint8_t rxtrigth)
944 {
945 PLATFORM_REG_WRITE(STDIO_UART_DBUFTH_ADDR, ((uint32_t)txtrigth << 9) | ((uint32_t)rxtrigth << 0));
946 }
947
stdio_uart_dbufth_unpack(uint8_t * txtrigth,uint8_t * rxtrigth)948 __STATIC_INLINE void stdio_uart_dbufth_unpack(uint8_t* txtrigth, uint8_t* rxtrigth)
949 {
950 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_DBUFTH_ADDR);
951
952 *txtrigth = (localVal & ((uint32_t)0x0001FE00)) >> 9;
953 *rxtrigth = (localVal & ((uint32_t)0x000000FF)) >> 0;
954 }
955
stdio_uart_txtrigth_getf(void)956 __STATIC_INLINE uint8_t stdio_uart_txtrigth_getf(void)
957 {
958 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_DBUFTH_ADDR);
959 return ((localVal & ((uint32_t)0x0001FE00)) >> 9);
960 }
961
stdio_uart_txtrigth_setf(uint8_t txtrigth)962 __STATIC_INLINE void stdio_uart_txtrigth_setf(uint8_t txtrigth)
963 {
964 PLATFORM_REG_WRITE(STDIO_UART_DBUFTH_ADDR, (PLATFORM_REG_READ(STDIO_UART_DBUFTH_ADDR) & ~((uint32_t)0x0001FE00)) | ((uint32_t)txtrigth << 9));
965 }
966
stdio_uart_rxtrigth_getf(void)967 __STATIC_INLINE uint8_t stdio_uart_rxtrigth_getf(void)
968 {
969 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_DBUFTH_ADDR);
970 return ((localVal & ((uint32_t)0x000000FF)) >> 0);
971 }
972
stdio_uart_rxtrigth_setf(uint8_t rxtrigth)973 __STATIC_INLINE void stdio_uart_rxtrigth_setf(uint8_t rxtrigth)
974 {
975 PLATFORM_REG_WRITE(STDIO_UART_DBUFTH_ADDR, (PLATFORM_REG_READ(STDIO_UART_DBUFTH_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)rxtrigth << 0));
976 }
977
978 /**
979 * @brief DIV2 register definition
980 * <pre>
981 * Bits Field Name Reset Value
982 * ----- ------------------ -----------
983 * 31:08 RSVD 0x0
984 * 07:00 DIV2 0x0
985 * </pre>
986 */
987 #define STDIO_UART_DIV2_ADDR (REG_STDIO_UART_BASE_ADDR + 0x0028)
988 #define STDIO_UART_DIV2_OFFSET 0x00000028
989 #define STDIO_UART_DIV2_INDEX 0x0000000A
990 #define STDIO_UART_DIV2_RESET 0x00000000
991
stdio_uart_div2_get(void)992 __STATIC_INLINE uint32_t stdio_uart_div2_get(void)
993 {
994 return PLATFORM_REG_READ(STDIO_UART_DIV2_ADDR);
995 }
996
stdio_uart_div2_set(uint32_t value)997 __STATIC_INLINE void stdio_uart_div2_set(uint32_t value)
998 {
999 PLATFORM_REG_WRITE(STDIO_UART_DIV2_ADDR, value);
1000 }
1001
1002 // field definitions
1003 #define STDIO_UART_DIV2_MASK ((uint32_t)0x000000FF)
1004 #define STDIO_UART_DIV2_LSB 0
1005 #define STDIO_UART_DIV2_WIDTH ((uint32_t)0x00000008)
1006
1007 #define STDIO_UART_DIV2_RST 0x0
1008
stdio_uart_div2_getf(void)1009 __STATIC_INLINE uint8_t stdio_uart_div2_getf(void)
1010 {
1011 uint32_t localVal = PLATFORM_REG_READ(STDIO_UART_DIV2_ADDR);
1012 return (localVal >> 0);
1013 }
1014
stdio_uart_div2_setf(uint8_t div2)1015 __STATIC_INLINE void stdio_uart_div2_setf(uint8_t div2)
1016 {
1017 PLATFORM_REG_WRITE(STDIO_UART_DIV2_ADDR, (uint32_t)div2 << 0);
1018 }
1019
1020 #endif // _REG_STDIO_UART_H_
1021