1 // Copyright (C) 2022 Beken Corporation
2 // Licensed under the Apache License, Version 2.0 (the "License");
3 // you may not use this file except in compliance with the License.
4 // You may obtain a copy of the License at
5 //
6 // http://www.apache.org/licenses/LICENSE-2.0
7 //
8 // Unless required by applicable law or agreed to in writing, software
9 // distributed under the License is distributed on an "AS IS" BASIS,
10 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
11 // See the License for the specific language governing permissions and
12 // limitations under the License.
13
14 #include <common/bk_include.h>
15 #include "sys_hal.h"
16 #include "sys_ll.h"
17 #include "aon_pmu_hal.h"
18 #include "gpio_hal.h"
19 #include "gpio_driver_base.h"
20 #include "sys_types.h"
21 #include <driver/aon_rtc.h>
22 #include "platform.h"
23 #include <arch_interrupt.h>
24 #include "modules/pm.h"
25 #include "bk_pm_control.h"
26
27 static sys_hal_t s_sys_hal;
28 uint32 sys_hal_get_int_group2_status(void);
29 /** Platform Start **/
30 //Platform
31
32
33 /** Platform Misc Start **/
sys_hal_init()34 bk_err_t sys_hal_init()
35 {
36 s_sys_hal.hw = (sys_hw_t *)SYS_LL_REG_BASE;
37 return BK_OK;
38 }
39 /** Platform Misc End **/
40
41
42 //sys_hal_主语(模块名)_谓语(动作:set/get/enable等)_宾语(status/value)
43 //该函数在每个芯片目录中都有一份
sys_hal_usb_enable_clk(bool en)44 void sys_hal_usb_enable_clk(bool en)
45 {
46 //ll层命名规范跟随ASIC的Address Mapping走，可以修改Address Mapping的注释
47 //这个注释ASIC的verilog也在使用
48 sys_ll_set_cpu_device_clk_enable_usb_cken(en);
49 }
50
sys_hal_usb_analog_phy_en(bool en)51 void sys_hal_usb_analog_phy_en(bool en)
52 {
53 sys_ll_set_ana_reg6_en_usb(en);
54 }
55
sys_hal_usb_analog_speed_en(bool en)56 void sys_hal_usb_analog_speed_en(bool en)
57 {
58 sys_ll_set_ana_reg9_usb_speed(en);
59 }
60
sys_hal_usb_analog_ckmcu_en(bool en)61 void sys_hal_usb_analog_ckmcu_en(bool en)
62 {
63 sys_ll_set_ana_reg11_ck2mcu(en);
64 }
65
sys_hal_usb_enable_charge(bool en)66 void sys_hal_usb_enable_charge(bool en)
67 {
68 sys_ll_set_ana_reg5_vctrl_dpllldo(en);
69 }
70
sys_hal_usb_charge_vlcf_cal()71 void sys_hal_usb_charge_vlcf_cal()
72 {
73
74 }
sys_hal_usb_charge_icp_cal()75 void sys_hal_usb_charge_icp_cal()
76 {}
sys_hal_usb_charge_vcv_cal()77 void sys_hal_usb_charge_vcv_cal()
78 {}
sys_hal_usb_charge_get_cal()79 void sys_hal_usb_charge_get_cal()
80 {}
81
82 /** Platform PWM Start **/
83
84 /** Platform PWM End **/
85
sys_hal_flash_set_dco(void)86 void sys_hal_flash_set_dco(void)
87 {
88 sys_ll_set_cpu_clk_div_mode2_cksel_flash(FLASH_CLK_DPLL);
89 }
90
sys_hal_flash_set_dpll(void)91 void sys_hal_flash_set_dpll(void)
92 {
93 sys_ll_set_cpu_clk_div_mode2_cksel_flash(FLASH_CLK_APLL);
94 }
95
sys_hal_flash_set_clk(uint32_t value)96 void sys_hal_flash_set_clk(uint32_t value)
97 {
98 sys_ll_set_cpu_clk_div_mode2_cksel_flash(value);
99 }
100
sys_hal_flash_set_clk_div(uint32_t value)101 void sys_hal_flash_set_clk_div(uint32_t value)
102 {
103 sys_ll_set_cpu_clk_div_mode2_ckdiv_flash(value);
104 }
105
106 /* REG_0x09:cpu_clk_div_mode2->cksel_flash:0:XTAL 1:APLL 1x :clk_120M,R/W,0x9[25:24]*/
sys_hal_flash_get_clk_sel(void)107 uint32_t sys_hal_flash_get_clk_sel(void)
108 {
109 return sys_ll_get_cpu_clk_div_mode2_cksel_flash();
110 }
111
112 /* REG_0x09:cpu_clk_div_mode2->ckdiv_flash:0:/1 1:/2 2:/4 3:/8,R/W,0x9[27:26]*/
sys_hal_flash_get_clk_div(void)113 uint32_t sys_hal_flash_get_clk_div(void)
114 {
115 return sys_ll_get_cpu_clk_div_mode2_ckdiv_flash();
116 }
117
118 /** Flash end **/
119
120 /*sleep feature start*/
sys_hal_enter_deep_sleep(void * param)121 __attribute__((section(".itcm_sec_code"))) void sys_hal_enter_deep_sleep(void * param)
122 {
123 uint32_t modules_power_state=0;
124 uint32_t clock_value = 0;
125 uint32_t pmu_val2 = 0;
126 int ret = 0;
127 /*mask all interner interrupt*/
128 sys_ll_set_cpu0_int_halt_clk_op_cpu0_int_mask(1);
129
130 /*1.switch cpu clock to xtal26m*/
131 sys_ll_set_cpu_clk_div_mode1_cksel_core(0);
132 sys_ll_set_cpu_clk_div_mode1_clkdiv_core(0);
133 sys_ll_set_cpu_clk_div_mode1_clkdiv_bus(0);
134
135 /*2.switch flash clock to xtal26m*/
136 clock_value = 0;
137 clock_value = sys_ll_get_cpu_clk_div_mode2_value();
138 clock_value &= ~(SYS_CPU_CLK_DIV_MODE2_CKSEL_FLASH_MASK << SYS_CPU_CLK_DIV_MODE2_CKSEL_FLASH_POS);
139 clock_value &= ~(SYS_CPU_CLK_DIV_MODE2_CKDIV_FLASH_MASK << SYS_CPU_CLK_DIV_MODE2_CKDIV_FLASH_POS);
140 sys_ll_set_cpu_clk_div_mode2_value(clock_value);
141
142 /*3.close high frequncy clock*/
143 clock_value = 0;
144 clock_value = sys_ll_get_ana_reg6_value();
145 clock_value |= (1 << SYS_ANA_REG6_EN_SLEEP_POS);
146 clock_value &= ~((1 << SYS_ANA_REG6_EN_DPLL_POS)|(1 << SYS_ANA_REG6_EN_AUDPLL_POS)|(1 << SYS_ANA_REG6_EN_PSRAM_LDO_POS)|(1 << SYS_ANA_REG6_EN_DCO_POS)|(1 << SYS_ANA_REG6_EN_USB_POS));
147
148 clock_value &= ~((1 << SYS_ANA_REG6_EN_SYSLDO_POS)|(1 << SYS_ANA_REG6_EN_TEMPDET_POS));
149
150 sys_ll_set_ana_reg6_value(clock_value);
151
152 clock_value = 0;
153 clock_value = sys_ll_get_ana_reg5_value();
154 clock_value &= ~(1 << SYS_ANA_REG5_ENCB_POS);//global central bias enable
155 sys_ll_set_ana_reg5_value(clock_value);
156
157 clock_value = 0;
158 clock_value = sys_ll_get_ana_reg9_value();
159 clock_value &= ~(1 << 5);
160 sys_ll_set_ana_reg9_value(clock_value);
161
162 clock_value = 0;
163 sys_ll_set_ana_reg19_value(clock_value);
164
165 /*4.set PMU parameters*/
166 ret = aon_pmu_hal_set_sleep_parameters(0x2);
167 if(ret== -1)
168 {
169 return;
170 }
171 /*5.set power flag*/
172 modules_power_state = sys_ll_get_cpu_power_sleep_wakeup_value();
173 modules_power_state |= 0xa0000;
174 sys_ll_set_cpu_power_sleep_wakeup_value(modules_power_state);
175
176 /*6.set sleep flag*/
177 pmu_val2 = aon_pmu_hal_reg_get(PMU_REG2);
178 pmu_val2 |= BIT(BIT_SLEEP_FLAG_DEEP_SLEEP);
179 aon_pmu_hal_reg_set(PMU_REG2,pmu_val2);
180
181 sys_ll_set_ana_reg8_en_lpmode(0x1);// touch enter low power mode
182 sys_ll_set_ana_reg6_vaon_sel(0);//0:vddaon drop enable
183
184 /*8.WFI*/
185 __asm volatile( "wfi" );
186
187 }
sys_hal_exit_low_voltage()188 void sys_hal_exit_low_voltage()
189 {
190 uint32_t modules_power_state=0;
191 uint32_t wakeup_souce = 0x1F0;
192 uint32_t reg_val = 0;
193 uint32_t clock_value = 0;
194
195 /*1.exit sleep*/
196 modules_power_state = sys_ll_get_cpu_power_sleep_wakeup_value();
197 modules_power_state &= ~0xf0000;
198 sys_ll_set_cpu_power_sleep_wakeup_value(modules_power_state);
199
200 /*2.disable wakeup source*/
201 reg_val = aon_pmu_hal_get_wakeup_source_reg();
202 reg_val &= ~wakeup_souce;
203 aon_pmu_hal_set_wakeup_source_reg(reg_val);
204
205 /*3.open high frequncy clock*/
206 clock_value = 0;
207 clock_value = sys_ll_get_ana_reg6_value();
208 clock_value |= (1 << 12);//en_dpll
209 clock_value |= (1 << 8);//en_dco
210 sys_ll_set_ana_reg6_value(clock_value);
211
212 }
213
214 #define BIT_AON_PMU_WAKEUP_ENA (0x1F0U)
215 #define PM_HARDEARE_DELAY_TIME_FROM_LOWVOL_WAKE (0x4)
216 #define PM_EXIT_WFI_FROM_LOWVOL_WAIT_COUNT (100)// about 4us(using 26m clock)
217 //specify:low voltage process can't be interrupt or the system can't response external interrupt after wakeup.
218 #if 1
219 #define MTIMER_LOW_VOLTAGE_MINIMUM_TICK (10400) //26M, 400 us
220 extern void mtimer_reset_next_tick(uint32_t minimum_offset);
221 #define CONFIG_LOW_VOLTAGE_DEBUG 0
222 #if CONFIG_LOW_VOLTAGE_DEBUG
223 uint64_t g_low_voltage_tick = 0;
224 extern u64 riscv_get_mtimer(void);
225 #endif
226 #endif
227 extern uint32_t s_pm_wakeup_from_lowvol_consume_time;
sys_hal_enter_low_voltage(void)228 __attribute__((section(".itcm_sec_code"))) void sys_hal_enter_low_voltage(void)
229 {
230 uint32_t modules_power_state = 0;
231 uint32_t clock_value = 0;
232 uint32_t clk_div_val0= 0, clk_div_val1 = 0, clk_div_val2 = 0;
233 uint32_t pmu_val2 = 0;
234 //uint32_t pmu_state = 0;
235 uint32_t previous_tick = 0;
236 uint32_t current_tick = 0;
237 uint32_t clk_div_temp = 0;
238 uint32_t int_state1 = 0;
239 uint32_t int_state2 = 0;
240 uint32_t h_vol = 0;
241 int ret = 0;
242 uint32_t analog_clk = 0;
243 uint32_t center_bias = 0;
244 uint32_t en_bias_5u = 0;
245 //uint32_t count = 0;
246
247 #if CONFIG_LOW_VOLTAGE_DEBUG
248 uint64_t start_tick = riscv_get_mtimer();
249 #endif
250
251 clear_csr(NDS_MIE, MIP_MTIP);
252
253 int_state1 = sys_ll_get_cpu0_int_0_31_en_value();
254 int_state2 = sys_ll_get_cpu0_int_32_63_en_value();
255 sys_ll_set_cpu0_int_0_31_en_value(0x0);
256 sys_ll_set_cpu0_int_32_63_en_value(0x0);
257 __asm volatile( "nop" );
258 __asm volatile( "nop" );
259 __asm volatile( "nop" );
260 __asm volatile( "nop" );
261 __asm volatile( "nop" );
262 __asm volatile( "nop" );
263 __asm volatile( "nop" );
264 __asm volatile( "nop" );
265 __asm volatile( "nop" );
266 __asm volatile( "nop" );
267
268 //confirm here hasn't mtimer/external interrupt
269 if(arch_get_plic_pending_status() ||
270 mtimer_is_timeout())
271 {
272 sys_ll_set_cpu0_int_0_31_en_value(int_state1);
273 sys_ll_set_cpu0_int_32_63_en_value(int_state2);
274
275 return;
276 }
277
278 //below interval time is about 5240(maybe CPU/Flash clock changes):
279 //after sys_ll_set_cpu0_int_halt_clk_op_cpu0_int_mask
280 //before WFI
281 mtimer_reset_next_tick(MTIMER_LOW_VOLTAGE_MINIMUM_TICK);
282
283 /*mask all external interrupt*/
284 sys_ll_set_cpu0_int_halt_clk_op_cpu0_int_mask(1);
285
286 //gpio_disable_output();
287 clk_div_val0 = sys_hal_all_modules_clk_div_get(CLK_DIV_REG0);
288 clk_div_val1 = sys_hal_all_modules_clk_div_get(CLK_DIV_REG1);
289 clk_div_val2 = sys_hal_all_modules_clk_div_get(CLK_DIV_REG2);
290
291 sys_ll_set_ana_reg2_spi_latchb(0x1);
292 h_vol = sys_ll_get_ana_reg3_vhsel_ldodig();
293 /*1.switch cpu clock to xtal26m*/
294 sys_ll_set_cpu_clk_div_mode1_cksel_core(0);
295 sys_ll_set_cpu_clk_div_mode1_clkdiv_core(0);
296 sys_ll_set_cpu_clk_div_mode1_clkdiv_bus(0);
297
298 //__asm volatile( "j ." );
299
300 /*2.switch flash clock to xtal26m*/
301 clock_value = 0;
302 clock_value = sys_ll_get_cpu_clk_div_mode2_value();
303 clock_value &= ~(SYS_CPU_CLK_DIV_MODE2_CKSEL_FLASH_MASK << SYS_CPU_CLK_DIV_MODE2_CKSEL_FLASH_POS);
304 clock_value &= ~(SYS_CPU_CLK_DIV_MODE2_CKDIV_FLASH_MASK << SYS_CPU_CLK_DIV_MODE2_CKDIV_FLASH_POS);
305 sys_ll_set_cpu_clk_div_mode2_value(clock_value);
306
307 /*3.close analog clk */
308 clock_value = 0;
309 clock_value = sys_ll_get_ana_reg6_value();
310 analog_clk = clock_value;
311
312 clock_value |= (1 << SYS_ANA_REG6_EN_SLEEP_POS);//enable xtal26m sleep
313
314 clock_value &= ~((1 << SYS_ANA_REG6_EN_DPLL_POS)|(1 << SYS_ANA_REG6_EN_USB_POS)|(1 << SYS_ANA_REG6_EN_AUDPLL_POS)|(1 << SYS_ANA_REG6_EN_PSRAM_LDO_POS)|(1 << SYS_ANA_REG6_EN_DCO_POS));
315
316 clock_value &= ~((1 << SYS_ANA_REG6_EN_SYSLDO_POS)|(1 << SYS_ANA_REG6_EN_TEMPDET_POS));
317
318 sys_ll_set_ana_reg6_value(clock_value);
319
320
321 clock_value = 0;
322 clock_value = sys_ll_get_ana_reg5_value();
323 center_bias = clock_value;
324 clock_value &= ~(1 << SYS_ANA_REG5_ENCB_POS);//global central bias enable
325 sys_ll_set_ana_reg5_value(clock_value);
326
327 clock_value = 0;
328 clock_value = sys_ll_get_ana_reg9_value();
329 en_bias_5u = clock_value;
330 clock_value &= ~(1 << 5);
331 sys_ll_set_ana_reg9_value(clock_value);
332
333
334 /*4.set sleep parameters*/
335 ret = aon_pmu_hal_set_sleep_parameters(0x1);
336 if(ret== -1)
337 {
338 return;
339 }
340
341 /*5.set power flag*/
342 modules_power_state = 0;
343 modules_power_state = sys_ll_get_cpu_power_sleep_wakeup_value();
344 modules_power_state |= 0xa0000;
345 sys_ll_set_cpu_power_sleep_wakeup_value(modules_power_state);
346
347 pmu_val2 = aon_pmu_hal_reg_get(PMU_REG2);
348 pmu_val2 |= BIT(BIT_SLEEP_FLAG_LOW_VOLTAGE);
349 aon_pmu_hal_reg_set(PMU_REG2,pmu_val2);
350
351
352 sys_ll_set_cpu0_int_32_63_en_cpu0_wifi_mac_int_gen_en(0x1);
353 sys_ll_set_cpu0_int_32_63_en_cpu0_gpio_int_en(0x1);
354 sys_ll_set_cpu0_int_32_63_en_cpu0_rtc_int_en(0x1);
355 sys_ll_set_cpu0_int_32_63_en_cpu0_touched_int_en(0x1);
356 sys_ll_set_cpu0_int_32_63_en_cpu0_dm_irq_en(0x1);
357
358 sys_ll_set_ana_reg8_en_lpmode(0x1);// touch enter low power mode
359 //just debug:maybe some guys changed the CPU clock or Flash clock caused the time of
360 //MTIMER_LOW_VOLTAGE_MINIMUM_TICK isn't enough.
361 //here can statistic the MAX time value.
362 #if CONFIG_LOW_VOLTAGE_DEBUG
363 if(g_low_voltage_tick < riscv_get_mtimer() - start_tick)
364 g_low_voltage_tick = riscv_get_mtimer() - start_tick;
365 #endif
366
367 /*6.WFI*/
368 while(1)
369 {
370 /*6.WFI*/
371 __asm volatile( "wfi" );
372 extern u32 arch_get_int_status(void);
373 if(arch_get_int_status() != 0)
374 {
375 break;
376 }
377 }
378 #if 0
379 __asm volatile( "wfi" );
380 __asm volatile( "nop" );
381 __asm volatile( "nop" );
382 __asm volatile( "nop" );
383 __asm volatile( "nop" );
384 __asm volatile( "nop" );
385 __asm volatile( "nop" );
386 __asm volatile( "nop" );
387 __asm volatile( "nop" );
388 __asm volatile( "nop" );
389 __asm volatile( "nop" );
390 __asm volatile( "nop" );
391 __asm volatile( "nop" );
392 for(count = PM_EXIT_WFI_FROM_LOWVOL_WAIT_COUNT; count > 0; count--);//for protect stability when exit wfi or halt cpu
393 #endif
394 s_pm_wakeup_from_lowvol_consume_time = 0;
395 s_pm_wakeup_from_lowvol_consume_time = bk_aon_rtc_get_current_tick(AON_RTC_ID_1);
396 sys_ll_set_ana_reg2_spi_latchb(0x1);
397 sys_ll_set_ana_reg3_vhsel_ldodig(h_vol);
398 extern uint32_t pm_wake_int_flag1, pm_wake_int_flag2;
399 extern uint32_t pm_wake_gpio_flag1, pm_wake_gpio_flag2;
400 extern gpio_driver_t s_gpio;
401 {
402 pm_wake_int_flag1 = sys_hal_get_int_status();
403 pm_wake_int_flag2 = sys_hal_get_int_group2_status();
404
405 gpio_hal_t *hal = &s_gpio.hal;
406 gpio_interrupt_status_t gpio_status;
407
408 gpio_hal_get_interrupt_status(hal, &gpio_status);
409 pm_wake_gpio_flag1 = gpio_status.gpio_0_31_int_status;
410 pm_wake_gpio_flag2 = gpio_status.gpio_32_64_int_status;
411 }
412 s_pm_wakeup_from_lowvol_consume_time -= ((aon_pmu_ll_get_reg40_wake1_delay()+1)+(aon_pmu_ll_get_reg40_wake2_delay()+1)+(aon_pmu_ll_get_reg40_wake3_delay()+1))+PM_HARDEARE_DELAY_TIME_FROM_LOWVOL_WAKE;
413 /*7.restore state before low voltage*/
414 modules_power_state = 0;
415 modules_power_state = sys_ll_get_cpu_power_sleep_wakeup_value();
416 modules_power_state &= ~0xf0000;
417 sys_ll_set_cpu_power_sleep_wakeup_value(modules_power_state);
418
419 /*8.restore the analog clk*/
420 clock_value = 0;
421 clock_value = sys_ll_get_ana_reg6_value();
422 //clock_value |= ((1 << SYS_ANA_REG6_EN_DPLL_POS)|(1 << SYS_ANA_REG6_EN_USB_POS)|(1 << SYS_ANA_REG6_EN_PSRAM_LDO_POS));//en_dpll, en_usb,en_PSRAM_LDO
423 clock_value |= analog_clk;
424 clock_value &= ~(1 << SYS_ANA_REG6_EN_SLEEP_POS);//disable xtal26m sleep
425 sys_ll_set_ana_reg6_value(clock_value);
426
427 clock_value = 0;
428 clock_value = sys_ll_get_ana_reg5_value();
429 clock_value |= center_bias;
430 sys_ll_set_ana_reg5_value(clock_value);
431
432 clock_value = 0;
433 clock_value = sys_ll_get_ana_reg9_value();
434 clock_value |= en_bias_5u;
435 sys_ll_set_ana_reg9_value(clock_value);
436
437
438 previous_tick = bk_aon_rtc_get_current_tick(AON_RTC_ID_1);
439
440 current_tick = previous_tick;
441 while(((uint32_t)(current_tick - previous_tick)) < (uint32_t)(LOW_POWER_DPLL_STABILITY_DELAY_TIME*RTC_TICKS_PER_1MS))/*32*1*/
442 {
443 current_tick = bk_aon_rtc_get_current_tick(AON_RTC_ID_1);
444 }
445
446 /*9.restore clk div*/
447 clk_div_temp = clk_div_val0;
448 clk_div_temp &= SYS_CPU_CLK_DIV_MODE1_CLKDIV_CORE_MASK << SYS_CPU_CLK_DIV_MODE1_CLKDIV_CORE_POS;
449 sys_ll_set_cpu_clk_div_mode1_clkdiv_core(clk_div_temp);
450 clk_div_temp = clk_div_val0;
451 clk_div_temp &= SYS_CPU_CLK_DIV_MODE1_CLKDIV_BUS_MASK << SYS_CPU_CLK_DIV_MODE1_CLKDIV_BUS_POS;
452 sys_ll_set_cpu_clk_div_mode1_clkdiv_bus(clk_div_temp);
453 clk_div_temp = clk_div_val0;
454 clk_div_temp &= SYS_CPU_CLK_DIV_MODE1_CKSEL_CORE_MASK << SYS_CPU_CLK_DIV_MODE1_CKSEL_CORE_POS;
455 sys_ll_set_cpu_clk_div_mode1_cksel_core(clk_div_temp);
456
457 sys_hal_all_modules_clk_div_set(CLK_DIV_REG0, clk_div_val0);
458 sys_hal_all_modules_clk_div_set(CLK_DIV_REG1, clk_div_val1);
459 sys_hal_all_modules_clk_div_set(CLK_DIV_REG2, clk_div_val2);
460
461 if(pm_wake_int_flag2&(WIFI_MAC_GEN_INT_BIT))
462 {
463 ps_switch(PS_UNALLOW, PS_EVENT_STA, PM_RF_BIT);
464 bk_pm_module_vote_power_ctrl(PM_POWER_SUB_MODULE_NAME_PHY_WIFI,PM_POWER_MODULE_STATE_ON);
465 }
466
467 sys_ll_set_cpu0_int_0_31_en_value(int_state1);
468 sys_ll_set_cpu0_int_32_63_en_value(int_state2);
469 sys_ll_set_ana_reg8_en_lpmode(0x0);// touch exit low power mode
470
471 set_csr(NDS_MIE, MIP_MTIP);
472
473 //gpio_restore();
474
475 }
476
sys_hal_touch_wakeup_enable(uint8_t index)477 void sys_hal_touch_wakeup_enable(uint8_t index)
478 {
479 uint32_t pmu_state = 0;
480 wakeup_source_t wakeup_source = WAKEUP_SOURCE_INT_TOUCHED;
481 pmu_state = aon_pmu_hal_reg_get(PMU_REG1);
482 pmu_state |= BIT(index) << 4;
483 pmu_state |= index << 0;
484 aon_pmu_hal_reg_set(PMU_REG1,pmu_state);
485 sys_hal_touch_power_down(0);
486
487 aon_pmu_hal_set_wakeup_source(wakeup_source);
488
489 sys_hal_touch_int_enable(1);
490 }
491
sys_hal_usb_wakeup_enable(uint8_t index)492 void sys_hal_usb_wakeup_enable(uint8_t index)
493 {
494 uint32_t wakeup_usb_int_en = 0x1;
495 uint32_t system_usb_int_en = 0x1 << 21;
496 wakeup_source_t wakeup_source = WAKEUP_SOURCE_INT_USBPLUG;
497 aon_pmu_hal_usbplug_int_en(wakeup_usb_int_en);
498 aon_pmu_hal_set_wakeup_source(wakeup_source);
499
500 sys_hal_int_group2_enable(system_usb_int_en);
501 }
502
sys_hal_rtc_wakeup_enable(uint32_t value)503 void sys_hal_rtc_wakeup_enable(uint32_t value)
504 {
505 uint32_t system_rtc_int_en = 0x1 << 21;
506 wakeup_source_t wakeup_source = WAKEUP_SOURCE_INT_RTC;
507 aon_pmu_hal_set_wakeup_source(wakeup_source);
508
509 sys_hal_int_group2_enable(system_rtc_int_en);
510 }
511
sys_hal_wifiorbt_wakeup_enable(uint32_t type)512 void sys_hal_wifiorbt_wakeup_enable(uint32_t type)
513 {
514 //wakeup_source_t wakeup_source = WAKEUP_SOURCE_INT_SYSTEM_WAKE;
515 //wifi: type=0, BT: type=1
516 if(type == 0){
517 sys_ll_set_cpu_power_sleep_wakeup_wifi_wakeup_platform_en(1);
518 }else{
519 sys_ll_set_cpu_power_sleep_wakeup_bts_wakeup_platform_en(1);
520 }
521
522 //aon_pmu_hal_set_wakeup_source(wakeup_source);
523 }
524
525 gpio_driver_t s_gpio_base = {0};
sys_hal_gpio_wakeup_enable(uint32_t index,gpio_int_type_t type)526 void sys_hal_gpio_wakeup_enable(uint32_t index, gpio_int_type_t type)
527 {
528 gpio_hal_init(&s_gpio_base.hal);
529 gpio_hal_t *hal = &s_gpio_base.hal;
530 wakeup_source_t wakeup_source = WAKEUP_SOURCE_INT_GPIO;
531 /*1.clear gpio int enable */
532 gpio_hal_disable_interrupt(hal, index);
533 /*2. gpio setting */
534 gpio_hal_input_enable(hal, index, 1);
535 gpio_hal_set_int_type(hal, index, type);
536 /*3. clear gpio int firstly */
537 gpio_hal_clear_chan_interrupt_status(hal, index);
538 /*4. open gpio int enable */
539 gpio_hal_enable_interrupt(hal, index);
540 /*5. set gpio wakeup source */
541 aon_pmu_hal_set_wakeup_source(wakeup_source);
542
543 }
sys_hal_enter_normal_sleep(uint32_t peri_clk)544 void sys_hal_enter_normal_sleep(uint32_t peri_clk)
545 {
546 sys_ll_set_cpu0_int_halt_clk_op_cpu0_halt(1);
547 __asm volatile( "wfi" );
548 }
549
sys_hal_enter_normal_wakeup()550 void sys_hal_enter_normal_wakeup()
551 {
552
553 }
554 /*for low power function start*/
sys_hal_module_power_ctrl(power_module_name_t module,power_module_state_t power_state)555 void sys_hal_module_power_ctrl(power_module_name_t module,power_module_state_t power_state)
556 {
557 uint32_t value = 0;
558 if((module >= POWER_MODULE_NAME_MEM1) && (module <= POWER_MODULE_NAME_WIFI_PHY))
559 {
560 value = 0;
561 value = sys_ll_get_cpu_power_sleep_wakeup_value();
562 if(power_state == POWER_MODULE_STATE_ON)//power on
563 {
564 value &= ~(1 << module);
565 }
566 else //power down
567 {
568 value |= (1 << module);
569 }
570 sys_ll_set_cpu_power_sleep_wakeup_value(value);
571 }
572 else if(module == POWER_MODULE_NAME_CPU1)
573 {
574 if(power_state == POWER_MODULE_STATE_ON)
575 {
576 //power on and then support clock
577 sys_ll_set_cpu1_int_halt_clk_op_cpu1_pwr_dw(POWER_MODULE_STATE_ON);
578 sys_ll_set_cpu1_int_halt_clk_op_cpu1_halt(0);
579
580 //wait halt really cleared,clock support finish
581 for(int i = 0; i < 1000; i++);
582 }
583 else
584 {
585 //un-support clock and then power down
586 sys_ll_set_cpu1_int_halt_clk_op_cpu1_halt(1);
587 //here should wait halt really finish and then power down
588 for(int i = 0; i < 1000; i++);
589
590 sys_ll_set_cpu1_int_halt_clk_op_cpu1_pwr_dw(POWER_MODULE_STATE_OFF);
591 }
592 }
593 else
594 {
595 ;//do something
596 }
597
598 }
sys_hal_module_power_state_get(power_module_name_t module)599 int32 sys_hal_module_power_state_get(power_module_name_t module)
600 {
601 uint32_t value = 0;
602 if((module >= POWER_MODULE_NAME_MEM1) && (module <= POWER_MODULE_NAME_WIFI_PHY))
603 {
604 value = 0;
605 value = sys_ll_get_cpu_power_sleep_wakeup_value();
606 value = ((value >> module) & 0x1);
607 return value;
608 }
609 else if(module == POWER_MODULE_NAME_CPU1)
610 {
611 //sys_ll_get_cpu1_int_halt_clk_op_cpu1_pwr_dw();
612 value = 0;
613 return sys_ll_get_cpu_current_run_status_cpu1_pwr_dw_state();
614 }
615 return -1;
616 }
sys_hal_module_RF_power_ctrl(module_name_t module,power_module_state_t power_state)617 void sys_hal_module_RF_power_ctrl (module_name_t module,power_module_state_t power_state)
618 {
619 uint32_t value = 0;
620 value = sys_ll_get_ana_reg6_value();
621 if(power_state == POWER_MODULE_STATE_ON)//power on
622 {
623 value |= ((1 << SYS_ANA_REG6_EN_SYSLDO_POS)|(1 << SYS_ANA_REG6_EN_DPLL_POS)|(1 << SYS_ANA_REG6_EN_DCO_POS));//en_sysldo,en_dpll
624 //value &= ~(1 << SYS_ANA_REG6_XTAL_LPMODE_CTRL_POS);//when using the xtal as the 32k,it need close the xtal low power mode
625 //value |= (1 << 11);//en_audpll //temp close,we will open when be neeeded
626 //value |= (1 << 8);//en_dco //now no module using,temp close,we will open when be neeeded
627 //value |= (1 << 7);//en_xtall //now no module using,temp close,we will open when be neeeded
628 }
629 else //power down
630 {
631 value &= ~(1 << 12);//en_dpll
632 value &= ~(1 << 11);//en_audpll
633 value &= ~(1 << 8);//en_dco
634 value &= ~(1 << 7);//en_xtall
635 }
636
637 sys_ll_set_ana_reg6_value(value);
638
639 }
sys_hal_core_bus_clock_ctrl(high_clock_module_name_t core,uint32_t clksel,uint32_t clkdiv,high_clock_module_name_t bus,uint32_t bus_clksel,uint32_t bus_clkdiv)640 void sys_hal_core_bus_clock_ctrl(high_clock_module_name_t core, uint32_t clksel,uint32_t clkdiv, high_clock_module_name_t bus,uint32_t bus_clksel,uint32_t bus_clkdiv)
641 {
642 uint32_t clock_value = 0;
643 clock_value = sys_ll_get_cpu_clk_div_mode1_value();
644 /*core:0: clk_DCO 1 : XTAL 2 : 320M 3 : 480M*/
645 clock_value &= ~(0x7F);
646 /*1.cpu0:120m ,maxtrix:120m*/
647 if((core == HIGH_FREQUECY_CLOCK_MODULE_CPU0) &&(clksel == 3))
648 {
649 clock_value |= 0x3 << 4; // select 480m
650 clock_value |= 0x3 << 0; //4// 480m/4 = 120m
651 //clock_value |= 0x1 << 6; //bus 120m
652 }/*2.cpu0:320m ,maxtrix:160m*/
653 else if((core == HIGH_FREQUECY_CLOCK_MODULE_CPU0) &&(clksel == 2))
654 {
655 clock_value |= 0x2 << 4;
656 clock_value |= 0x1 << 6;
657 }/*3.cpu0:240m ,maxtrix:120m*/
658 else if((core == HIGH_FREQUECY_CLOCK_MODULE_CPU0) &&(clksel == 0))
659 {
660 clock_value |= 0x3 << 4;
661 clock_value |= 0x1 << 0;
662 clock_value |= 0x1 << 6; //bus 120m
663 }/*3.cpu0:26m ,maxtrix:26m*/
664 else if((core == HIGH_FREQUECY_CLOCK_MODULE_CPU0) &&(clksel == 1))
665 {
666 clock_value |= 0x1 << 4;
667 clock_value |= 0x0 << 6;
668 }
669 else
670 {
671 clock_value |= 0x0 << 4;
672 clock_value |= 0x0 << 6;
673 }
674
675 sys_ll_set_cpu_clk_div_mode1_value(clock_value);
676
677 }
sys_hal_cpu0_main_int_ctrl(dev_clk_pwr_ctrl_t clock_state)678 void sys_hal_cpu0_main_int_ctrl(dev_clk_pwr_ctrl_t clock_state)
679 {
680 sys_ll_set_cpu0_int_halt_clk_op_cpu0_int_mask( clock_state);
681 }
sys_hal_cpu1_main_int_ctrl(dev_clk_pwr_ctrl_t clock_state)682 void sys_hal_cpu1_main_int_ctrl(dev_clk_pwr_ctrl_t clock_state)
683 {
684 sys_ll_set_cpu1_int_halt_clk_op_cpu1_int_mask( clock_state);
685 }
sys_hal_set_cpu1_boot_address_offset(uint32_t address_offset)686 void sys_hal_set_cpu1_boot_address_offset(uint32_t address_offset)
687 {
688 sys_ll_set_cpu1_int_halt_clk_op_cpu1_offset(address_offset);
689 }
sys_hal_set_cpu1_reset(uint32_t reset_value)690 void sys_hal_set_cpu1_reset(uint32_t reset_value)
691 {
692 /*1:reset ; 0:not reset*/
693 sys_ll_set_cpu1_int_halt_clk_op_cpu1_sw_rst(reset_value);
694 }
sys_hal_enable_mac_wakeup_source()695 void sys_hal_enable_mac_wakeup_source()
696 {
697 module_name_t module_name = MODULE_NAME_WIFI;
698 //wakeup_source_t wakeup_source = WAKEUP_SOURCE_INT_SYSTEM_WAKE;
699 sys_hal_wifiorbt_wakeup_enable(module_name);
700 //aon_pmu_hal_set_wakeup_source(wakeup_source);
701 }
sys_hal_enable_bt_wakeup_source()702 void sys_hal_enable_bt_wakeup_source()
703 {
704 module_name_t module_name = MODULE_NAME_BT;
705 //wakeup_source_t wakeup_source = WAKEUP_SOURCE_INT_SYSTEM_WAKE;
706 sys_hal_wifiorbt_wakeup_enable(module_name);
707 //aon_pmu_hal_set_wakeup_source(wakeup_source);
708 }
sys_hal_all_modules_clk_div_set(clk_div_reg_e reg,uint32_t value)709 void sys_hal_all_modules_clk_div_set(clk_div_reg_e reg, uint32_t value)
710 {
711 clk_div_address_map_t clk_div_address_map_table[] = CLK_DIV_ADDRESS_MAP;
712 clk_div_address_map_t *clk_div_addr = &clk_div_address_map_table[reg];
713
714 uint32_t clk_div_reg_address = clk_div_addr->reg_address;
715
716 REG_WRITE(clk_div_reg_address, value);
717 }
sys_hal_all_modules_clk_div_get(clk_div_reg_e reg)718 uint32_t sys_hal_all_modules_clk_div_get(clk_div_reg_e reg)
719 {
720 clk_div_address_map_t clk_div_address_map_table[] = CLK_DIV_ADDRESS_MAP;
721 clk_div_address_map_t *clk_div_addr = &clk_div_address_map_table[reg];
722
723 uint32_t clk_div_reg_address = clk_div_addr->reg_address;
724
725 return REG_READ(clk_div_reg_address);
726 }
sys_hal_wakeup_interrupt_clear(wakeup_source_t interrupt_source)727 void sys_hal_wakeup_interrupt_clear(wakeup_source_t interrupt_source)
728 {
729
730 }
sys_hal_cpu_clk_div_set(uint32_t core_index,uint32_t value)731 void sys_hal_cpu_clk_div_set(uint32_t core_index, uint32_t value)
732 {
733 if(core_index == 0)
734 {
735 sys_ll_set_cpu0_int_halt_clk_op_cpu0_clk_div(value);
736 }
737 else
738 {
739 sys_ll_set_cpu1_int_halt_clk_op_cpu1_clk_div(value);
740 }
741 }
sys_hal_cpu_clk_div_get(uint32_t core_index)742 uint32_t sys_hal_cpu_clk_div_get(uint32_t core_index)
743 {
744 if(core_index == 0)
745 {
746 return sys_ll_get_cpu0_int_halt_clk_op_cpu0_clk_div();
747 }
748 else
749 {
750 return sys_ll_get_cpu1_int_halt_clk_op_cpu1_clk_div();
751 }
752 }
sys_hal_low_power_hardware_init()753 void sys_hal_low_power_hardware_init()
754 {
755 uint32_t param = 0;
756 uint32_t pmu_state = 0;
757
758 param = 0x4;
759 sys_ll_set_ana_reg2_spi_latchb(0x1);
760 sys_ll_set_ana_reg3_vhsel_ldodig(param);
761
762 sys_ll_set_ana_reg0_band(0x13);//open the dpll 320m
763
764 param = 0;
765 param = sys_ll_get_ana_reg5_value();
766 param |= (1 << SYS_ANA_REG5_ENCB_POS);//global central bias enable
767 sys_ll_set_ana_reg5_value(param);
768
769 param = 0;
770 param = sys_ll_get_ana_reg6_value();
771 param &= ~((0x1 << SYS_ANA_REG6_EN_SLEEP_POS)|(1 << SYS_ANA_REG6_XTAL_LPMODE_CTRL_POS));
772 sys_ll_set_ana_reg6_value(param);
773
774 param = 0;
775 param = sys_ll_get_ana_reg6_value();
776 param |= ((0x7 << SYS_ANA_REG6_RXTAL_LP_POS)|(0x7 << SYS_ANA_REG6_RXTAL_HP_POS));
777 sys_ll_set_ana_reg6_value(param);
778
779 /*set wakeup source*/
780 pmu_state = aon_pmu_hal_reg_get(PMU_REG0x41);
781 pmu_state |= BIT_AON_PMU_WAKEUP_ENA;
782 aon_pmu_hal_reg_set(PMU_REG0x41,pmu_state);
783
784 }
sys_hal_lp_vol_set(uint32_t value)785 int32 sys_hal_lp_vol_set(uint32_t value)
786 {
787 sys_ll_set_ana_reg2_spi_latchb(0x1);
788 sys_ll_set_ana_reg3_vlsel_ldodig(value);
789 return 0;
790 }
sys_hal_lp_vol_get()791 uint32_t sys_hal_lp_vol_get()
792 {
793 sys_ll_set_ana_reg2_spi_latchb(0x1);
794 return sys_ll_get_ana_reg3_vlsel_ldodig();
795 }
796 /*for low power function end*/
797 /*sleep feature end*/
798
sys_hal_get_chip_id(void)799 uint32 sys_hal_get_chip_id(void)
800 {
801 return sys_ll_get_version_id_versionid();
802 }
803
sys_hal_get_device_id(void)804 uint32 sys_hal_get_device_id(void)
805 {
806 return sys_ll_get_device_id_deviceid();
807 }
808
809
sys_hal_int_disable(uint32 param)810 int32 sys_hal_int_disable(uint32 param) //CMD_ICU_INT_DISABLE
811 {
812 uint32 reg = 0;
813
814 reg = sys_ll_get_cpu0_int_0_31_en_value();
815 reg &= ~(param);
816 sys_ll_set_cpu0_int_0_31_en_value(reg);
817
818 return 0;
819 }
820
sys_hal_int_enable(uint32 param)821 int32 sys_hal_int_enable(uint32 param) //CMD_ICU_INT_ENABLE
822 {
823 uint32 reg = 0;
824
825 reg = sys_ll_get_cpu0_int_0_31_en_value();
826 reg |= (param);
827 sys_ll_set_cpu0_int_0_31_en_value(reg);
828
829 return 0;
830 }
831
832 //NOTICE:Temp add for BK7256 product which has more then 32 Interrupt sources
sys_hal_int_group2_disable(uint32 param)833 int32 sys_hal_int_group2_disable(uint32 param)
834 {
835 uint32 reg = 0;
836
837 reg = sys_ll_get_cpu0_int_32_63_en_value();
838 reg &= ~(param);
839 sys_ll_set_cpu0_int_32_63_en_value(reg);
840
841 return 0;
842 }
843
844 //NOTICE:Temp add for BK7256 product which has more then 32 Interrupt sources
sys_hal_int_group2_enable(uint32 param)845 int32 sys_hal_int_group2_enable(uint32 param)
846 {
847 uint32 reg = 0;
848
849 reg = sys_ll_get_cpu0_int_32_63_en_value();
850 reg |= (param);
851 sys_ll_set_cpu0_int_32_63_en_value(reg);
852
853 return 0;
854 }
855
sys_hal_fiq_disable(uint32 param)856 int32 sys_hal_fiq_disable(uint32 param)
857 {
858 uint32 reg = 0;
859
860 reg = sys_ll_get_cpu0_int_32_63_en_value();
861 reg &= ~(param);
862 sys_ll_set_cpu0_int_32_63_en_value(reg);
863
864 return 0;
865 }
866
sys_hal_fiq_enable(uint32 param)867 int32 sys_hal_fiq_enable(uint32 param)
868 {
869 uint32 reg = 0;
870
871 reg = sys_ll_get_cpu0_int_32_63_en_value();
872 reg |= (param);
873 sys_ll_set_cpu0_int_32_63_en_value(reg);
874
875 return 0;
876 }
877
878 // GLOBAL_INT_DECLARATION(); GLOBAL_INT_DISABLE();
sys_hal_global_int_disable(uint32 param)879 int32 sys_hal_global_int_disable(uint32 param)
880 {
881 int32 ret = 0;
882
883 return ret;
884 }
885
886 // GLOBAL_INT_RESTORE();
sys_hal_global_int_enable(uint32 param)887 int32 sys_hal_global_int_enable(uint32 param)
888 {
889 int32 ret = 0;
890
891 return ret;
892 }
893
sys_hal_get_int_status(void)894 uint32 sys_hal_get_int_status(void)
895 {
896 return sys_ll_get_cpu0_int_0_31_status_value();
897 }
898
sys_hal_get_int_group2_status(void)899 uint32 sys_hal_get_int_group2_status(void)
900 {
901 return sys_ll_get_cpu0_int_32_63_status_value();
902 }
903
904 //NOTICE:INT source status is read only and can't be set, other projects is error, we'll delete them.
sys_hal_set_int_status(uint32 param)905 int32 sys_hal_set_int_status(uint32 param)
906 {
907 return 0;
908 }
909
sys_hal_get_fiq_reg_status(void)910 uint32 sys_hal_get_fiq_reg_status(void)
911 {
912 uint32 reg = 0;
913
914 reg = sys_ll_get_cpu0_int_32_63_status_value();
915 return reg;
916 }
917
sys_hal_set_fiq_reg_status(uint32 param)918 uint32 sys_hal_set_fiq_reg_status(uint32 param)
919 {
920 uint32 reg = 0;
921
922 ///TODO:this reg is read only
923
924 return reg;
925 }
926
sys_hal_get_intr_raw_status(void)927 uint32 sys_hal_get_intr_raw_status(void)
928 {
929 uint32 reg = 0;
930
931 ///TODO:
932 reg = sys_ll_get_cpu0_int_0_31_status_value();
933
934 return reg;
935 }
936
sys_hal_set_intr_raw_status(uint32 param)937 uint32 sys_hal_set_intr_raw_status(uint32 param)
938 {
939 uint32 reg = 0;
940
941 ///TODO:this reg is read only
942
943 return reg;
944 }
945
sys_hal_set_jtag_mode(uint32 param)946 int32 sys_hal_set_jtag_mode(uint32 param)
947 {
948 int32 ret = 0;
949 sys_ll_set_cpu_storage_connect_op_select_jtag_core_sel(param);
950 return ret;
951 }
952
sys_hal_get_jtag_mode(void)953 uint32 sys_hal_get_jtag_mode(void)
954 {
955 uint32 reg = 0;
956 reg = sys_ll_get_cpu_storage_connect_op_select_jtag_core_sel();
957 return reg;
958 }
959
960 /* NOTICE: NOTICE: NOTICE: NOTICE: NOTICE: NOTICE: NOTICE
961 * BK7256 clock, power is different with previous products(2022-01-10).
962 * Previous products peripheral devices use only one signal of clock enable.
963 * BK7256 uses clock and power signal to control one device,
964 * This function only enable clock signal, we needs to enable power signal also
965 * if we want to enable one device.
966 */
sys_hal_clk_pwr_ctrl(dev_clk_pwr_id_t dev,dev_clk_pwr_ctrl_t power_up)967 void sys_hal_clk_pwr_ctrl(dev_clk_pwr_id_t dev, dev_clk_pwr_ctrl_t power_up)
968 {
969 uint32 v = sys_ll_get_cpu_device_clk_enable_value();
970
971 if(CLK_PWR_CTRL_PWR_UP == power_up)
972 v |= (1 << dev);
973 else
974 v &= ~(1 << dev);
975
976 sys_ll_set_cpu_device_clk_enable_value(v);
977 }
978
979 /* UART select clock **/
sys_hal_uart_select_clock(uart_id_t id,uart_src_clk_t mode)980 void sys_hal_uart_select_clock(uart_id_t id, uart_src_clk_t mode)
981 {
982 int sel_xtal = 0;
983 int sel_appl = 1;
984
985 switch(id)
986 {
987 case UART_ID_0:
988 {
989 if(mode == UART_SCLK_APLL)
990 sys_ll_set_cpu_clk_div_mode1_clksel_uart0(sel_appl);
991 else
992 sys_ll_set_cpu_clk_div_mode1_clksel_uart0(sel_xtal);
993 break;
994 }
995 case UART_ID_1:
996 {
997 if(mode == UART_SCLK_APLL)
998 sys_ll_set_cpu_clk_div_mode1_cksel_uart1(sel_appl);
999 else
1000 sys_ll_set_cpu_clk_div_mode1_cksel_uart1(sel_xtal);
1001 break;
1002 }
1003 case UART_ID_2:
1004 {
1005 if(mode == UART_SCLK_APLL)
1006 sys_ll_set_cpu_clk_div_mode1_cksel_uart2(sel_appl);
1007 else
1008 sys_ll_set_cpu_clk_div_mode1_cksel_uart2(sel_xtal);
1009 break;
1010 }
1011 default:
1012 break;
1013 }
1014
1015 }
1016
sys_hal_pwm_select_clock(sys_sel_pwm_t num,pwm_src_clk_t mode)1017 void sys_hal_pwm_select_clock(sys_sel_pwm_t num, pwm_src_clk_t mode)
1018 {
1019 int sel_clk32 = 0;
1020 int sel_xtal = 1;
1021
1022 switch(num)
1023 {
1024 case SYS_SEL_PWM0:
1025 if(mode == PWM_SCLK_XTAL)
1026 sys_ll_set_cpu_clk_div_mode1_cksel_pwm0(sel_xtal);
1027 else
1028 sys_ll_set_cpu_clk_div_mode1_cksel_pwm0(sel_clk32);
1029 break;
1030 case SYS_SEL_PWM1:
1031 if(mode == PWM_SCLK_XTAL)
1032 sys_ll_set_cpu_clk_div_mode1_cksel_pwm1(sel_xtal);
1033 else
1034 sys_ll_set_cpu_clk_div_mode1_cksel_pwm1(sel_clk32);
1035 break;
1036
1037 default:
1038 break;
1039 }
1040 }
1041
sys_hal_timer_select_clock(sys_sel_timer_t num,timer_src_clk_t mode)1042 void sys_hal_timer_select_clock(sys_sel_timer_t num, timer_src_clk_t mode)
1043 {
1044 int sel_clk32 = 0;
1045 int sel_xtal = 1;
1046
1047 switch(num)
1048 {
1049 case SYS_SEL_TIMER0:
1050 if(mode == TIMER_SCLK_XTAL)
1051 sys_ll_set_cpu_clk_div_mode1_cksel_timer0(sel_xtal);
1052 else
1053 sys_ll_set_cpu_clk_div_mode1_cksel_timer0(sel_clk32);
1054 break;
1055 case SYS_SEL_TIMER1:
1056 if(mode == TIMER_SCLK_XTAL)
1057 sys_ll_set_cpu_clk_div_mode1_cksel_timer1(sel_xtal);
1058 else
1059 sys_ll_set_cpu_clk_div_mode1_cksel_timer1(sel_clk32);
1060 break;
1061
1062 default:
1063 break;
1064 }
1065 }
1066
sys_hal_timer_select_clock_get(sys_sel_timer_t id)1067 uint32_t sys_hal_timer_select_clock_get(sys_sel_timer_t id)
1068 {
1069 uint32_t ret = 0;
1070
1071 switch(id)
1072 {
1073 case SYS_SEL_TIMER0:
1074 {
1075 ret = sys_ll_get_cpu_clk_div_mode1_cksel_timer0();
1076 break;
1077 }
1078 case SYS_SEL_TIMER1:
1079 {
1080 ret = sys_ll_get_cpu_clk_div_mode1_cksel_timer1();
1081 break;
1082 }
1083 default:
1084 break;
1085 }
1086
1087 ret = (ret)?TIMER_SCLK_XTAL:TIMER_SCLK_CLK32;
1088
1089 return ret;
1090 }
1091
sys_hal_spi_select_clock(spi_id_t num,spi_src_clk_t mode)1092 void sys_hal_spi_select_clock(spi_id_t num, spi_src_clk_t mode)
1093 {
1094 int sel_xtal = 0;
1095 int sel_apll = 1;
1096
1097 switch(num)
1098 {
1099 case SPI_ID_0:
1100 if(mode == SPI_CLK_XTAL)
1101 sys_ll_set_cpu_26m_wdt_clk_div_clksel_spi0(sel_xtal);
1102 else
1103 sys_ll_set_cpu_26m_wdt_clk_div_clksel_spi0(sel_apll);
1104 break;
1105 #if (SOC_SPI_UNIT_NUM > 1)
1106 case SPI_ID_1:
1107 if(mode == SPI_CLK_XTAL)
1108 sys_ll_set_cpu_26m_wdt_clk_div_clksel_spi1(sel_xtal);
1109 else
1110 sys_ll_set_cpu_26m_wdt_clk_div_clksel_spi1(sel_apll);
1111 break;
1112 #endif
1113 default:
1114 break;
1115 }
1116 }
1117
1118 #if 1 //tmp build
sys_hal_set_clk_select(dev_clk_select_id_t dev,dev_clk_select_t clk_sel)1119 void sys_hal_set_clk_select(dev_clk_select_id_t dev, dev_clk_select_t clk_sel)
1120 {
1121 //tmp build
1122 }
1123
sys_hal_get_clk_select(dev_clk_select_id_t dev)1124 dev_clk_select_t sys_hal_get_clk_select(dev_clk_select_id_t dev)
1125 {
1126 //tmp build
1127 return 0;
1128 }
1129
1130 //DCO divider is valid for all of the peri-devices.
sys_hal_set_dco_div(dev_clk_dco_div_t div)1131 void sys_hal_set_dco_div(dev_clk_dco_div_t div)
1132 {
1133 //tmp build
1134 }
1135
1136 //DCO divider is valid for all of the peri-devices.
sys_hal_get_dco_div(void)1137 dev_clk_dco_div_t sys_hal_get_dco_div(void)
1138 {
1139 //tmp build
1140 return 0;
1141 }
1142 #endif //temp build
1143
1144 /*clock power control end*/
1145
1146 /*wake up control start*/
sys_hal_arm_wakeup_enable(uint32_t param)1147 void sys_hal_arm_wakeup_enable(uint32_t param)
1148 {
1149 uint32_t reg = 0;
1150
1151 reg = aon_pmu_hal_get_wakeup_source_reg();
1152 reg |= param;
1153 aon_pmu_hal_set_wakeup_source_reg(reg);
1154 }
1155
sys_hal_arm_wakeup_disable(uint32_t param)1156 void sys_hal_arm_wakeup_disable(uint32_t param)
1157 {
1158 uint32_t reg = 0;
1159
1160 reg = aon_pmu_hal_get_wakeup_source_reg();
1161 reg &= ~(param);
1162 aon_pmu_hal_set_wakeup_source_reg(reg);
1163 }
1164
sys_hal_get_arm_wakeup(void)1165 uint32_t sys_hal_get_arm_wakeup(void)
1166 {
1167 return aon_pmu_hal_get_wakeup_source_reg();
1168 }
1169 /*wake up control end*/
1170
sys_hal_set_cksel_sadc(uint32_t value)1171 void sys_hal_set_cksel_sadc(uint32_t value)
1172 {
1173 sys_ll_set_cpu_clk_div_mode1_cksel_sadc(value);
1174 }
1175
sys_hal_set_cksel_pwm0(uint32_t value)1176 void sys_hal_set_cksel_pwm0(uint32_t value)
1177 {
1178 sys_ll_set_cpu_clk_div_mode1_cksel_pwm0(value);
1179 }
1180
sys_hal_set_cksel_pwm1(uint32_t value)1181 void sys_hal_set_cksel_pwm1(uint32_t value)
1182 {
1183 sys_ll_set_cpu_clk_div_mode1_cksel_pwm1(value);
1184 }
1185
sys_hal_set_cksel_pwm(uint32_t value)1186 void sys_hal_set_cksel_pwm(uint32_t value)
1187 {
1188 sys_hal_set_cksel_pwm0(value);
1189 sys_hal_set_cksel_pwm1(value);
1190 }
1191
sys_hal_uart_select_clock_get(uart_id_t id)1192 uint32_t sys_hal_uart_select_clock_get(uart_id_t id)
1193 {
1194 uint32_t ret = 0;
1195
1196 switch(id)
1197 {
1198 case UART_ID_0:
1199 {
1200 ret = sys_ll_get_cpu_clk_div_mode1_clksel_uart0();
1201 break;
1202 }
1203 case UART_ID_1:
1204 {
1205 ret = sys_ll_get_cpu_clk_div_mode1_cksel_uart1();
1206 break;
1207 }
1208 case UART_ID_2:
1209 {
1210 ret = sys_ll_get_cpu_clk_div_mode1_cksel_uart1();
1211 break;
1212 }
1213 default:
1214 break;
1215 }
1216
1217 ret = (!ret)?UART_SCLK_XTAL_26M:UART_SCLK_APLL;
1218
1219 return ret;
1220 }
1221
sys_hal_sadc_int_enable(void)1222 void sys_hal_sadc_int_enable(void)
1223 {
1224 sys_hal_int_enable(SADC_INTERRUPT_CTRL_BIT);
1225 }
1226
sys_hal_sadc_int_disable(void)1227 void sys_hal_sadc_int_disable(void)
1228 {
1229 sys_hal_int_disable(SADC_INTERRUPT_CTRL_BIT);
1230 }
1231
sys_hal_sadc_pwr_up(void)1232 void sys_hal_sadc_pwr_up(void)
1233 {
1234 }
1235
sys_hal_sadc_pwr_down(void)1236 void sys_hal_sadc_pwr_down(void)
1237 {
1238 }
1239
sys_hal_set_clksel_spi0(uint32_t value)1240 void sys_hal_set_clksel_spi0(uint32_t value)
1241 {
1242 sys_ll_set_cpu_26m_wdt_clk_div_clksel_spi0(value);
1243 }
1244
sys_hal_set_clksel_spi1(uint32_t value)1245 void sys_hal_set_clksel_spi1(uint32_t value)
1246 {
1247 sys_ll_set_cpu_26m_wdt_clk_div_clksel_spi1(value);
1248 }
1249
sys_hal_set_clksel_spi(uint32_t value)1250 void sys_hal_set_clksel_spi(uint32_t value)
1251 {
1252 if((SPI_CLK_SRC_XTAL == value) || (SPI_CLK_SRC_APLL == value))
1253 {
1254 sys_ll_set_cpu_26m_wdt_clk_div_clksel_spi0(value);
1255 sys_ll_set_cpu_26m_wdt_clk_div_clksel_spi1(value);
1256 }
1257 else
1258 {
1259 //os_printf("spi cksel is not support on BK7256 in function:%s, line:%d\n", __FUNCTION__, __LINE__);
1260 }
1261
1262 }
1263
sys_hal_en_tempdet(uint32_t value)1264 void sys_hal_en_tempdet(uint32_t value)
1265 {
1266 sys_ll_set_ana_reg6_en_tempdet(value);
1267 }
1268
sys_hal_mclk_mux_get(void)1269 uint32_t sys_hal_mclk_mux_get(void)
1270 {
1271 UINT32 ret = 0;
1272
1273 ret = sys_ll_get_cpu_clk_div_mode1_cksel_core();
1274
1275 return ret;
1276 }
1277
sys_hal_mclk_mux_set(uint32_t value)1278 void sys_hal_mclk_mux_set(uint32_t value)
1279 {
1280 sys_ll_set_cpu_clk_div_mode1_cksel_core(value);
1281 }
1282
sys_hal_mclk_div_get(void)1283 uint32_t sys_hal_mclk_div_get(void)
1284 {
1285 UINT32 ret = 0;
1286
1287 ret = sys_ll_get_cpu_clk_div_mode1_clkdiv_core();
1288
1289 return ret;
1290 }
1291
sys_hal_mclk_div_set(uint32_t value)1292 void sys_hal_mclk_div_set(uint32_t value)
1293 {
1294 sys_ll_set_cpu_clk_div_mode1_clkdiv_core(value);
1295 }
1296
sys_hal_nmi_wdt_get_clk_div(void)1297 uint32_t sys_hal_nmi_wdt_get_clk_div(void)
1298 {
1299 return sys_ll_get_cpu_26m_wdt_clk_div_ckdiv_wdt();
1300 }
1301
sys_hal_nmi_wdt_set_clk_div(uint32_t value)1302 void sys_hal_nmi_wdt_set_clk_div(uint32_t value)
1303 {
1304 sys_ll_set_cpu_26m_wdt_clk_div_ckdiv_wdt(value);
1305 }
1306
sys_hal_trng_disckg_set(uint32_t value)1307 void sys_hal_trng_disckg_set(uint32_t value)
1308 {
1309 sys_ll_set_cpu_mode_disckg1_trng_disckg(value);
1310 }
1311 /** Platform End **/
1312
1313 /** BT Start **/
1314 //BT
sys_hal_bt_power_ctrl(bool power_up)1315 void sys_hal_bt_power_ctrl(bool power_up)
1316 {
1317 if (power_up)
1318 {
1319 sys_ll_set_cpu_power_sleep_wakeup_pwd_btsp(0);
1320 }
1321 else
1322 {
1323 sys_ll_set_cpu_power_sleep_wakeup_pwd_btsp(1);
1324 }
1325 }
1326
sys_hal_bt_clock_ctrl(bool en)1327 void sys_hal_bt_clock_ctrl(bool en)
1328 {
1329 if (en)
1330 {
1331 sys_ll_set_cpu_device_clk_enable_btdm_cken(1);
1332 }
1333 else
1334 {
1335 sys_ll_set_cpu_device_clk_enable_btdm_cken(0);
1336 }
1337 }
1338
sys_hal_xvr_clock_ctrl(bool en)1339 void sys_hal_xvr_clock_ctrl(bool en)
1340 {
1341 if (en)
1342 {
1343 sys_ll_set_cpu_device_clk_enable_xvr_cken(1);
1344 }
1345 else
1346 {
1347 sys_ll_set_cpu_device_clk_enable_xvr_cken(0);
1348 }
1349 }
1350
sys_hal_btdm_interrupt_ctrl(bool en)1351 void sys_hal_btdm_interrupt_ctrl(bool en)
1352 {
1353 if (en)
1354 {
1355 sys_ll_set_cpu0_int_32_63_en_cpu0_dm_irq_en(1);
1356 //TODO enable PLIC Int Enable Registers
1357 }
1358 else
1359 {
1360 sys_ll_set_cpu0_int_32_63_en_cpu0_dm_irq_en(0);
1361 //TODO disable PLIC Int Enable Registers
1362 }
1363 }
1364
sys_hal_ble_interrupt_ctrl(bool en)1365 void sys_hal_ble_interrupt_ctrl(bool en)
1366 {
1367 if (en)
1368 {
1369 sys_ll_set_cpu0_int_32_63_en_cpu0_ble_irq_en(1);
1370 //TODO enable PLIC Int Enable Registers
1371 }
1372 else
1373 {
1374 sys_ll_set_cpu0_int_32_63_en_cpu0_ble_irq_en(0);
1375 //TODO disable PLIC Int Enable Registers
1376 }
1377 }
1378
sys_hal_bt_interrupt_ctrl(bool en)1379 void sys_hal_bt_interrupt_ctrl(bool en)
1380 {
1381 if (en)
1382 {
1383 sys_ll_set_cpu0_int_32_63_en_cpu0_bt_irq_en(1);
1384 //TODO enable PLIC Int Enable Registers
1385 }
1386 else
1387 {
1388 sys_ll_set_cpu0_int_32_63_en_cpu0_bt_irq_en(0);
1389 //TODO disable PLIC Int Enable Registers
1390 }
1391 }
1392
sys_hal_bt_rf_ctrl(bool en)1393 void sys_hal_bt_rf_ctrl(bool en)
1394 {
1395 if (en)
1396 {
1397 //todo
1398 }
1399 else
1400 {
1401 //todo
1402 }
1403 }
1404
sys_hal_bt_rf_status_get(void)1405 uint32_t sys_hal_bt_rf_status_get(void)
1406 {
1407 //todo
1408 return 0;
1409 }
1410
sys_hal_bt_sleep_exit_ctrl(bool en)1411 void sys_hal_bt_sleep_exit_ctrl(bool en)
1412 {
1413 if (en)
1414 {
1415 sys_ll_set_cpu_power_sleep_wakeup_bts_sleep_exit_req(1);
1416 }
1417 else
1418 {
1419 sys_ll_set_cpu_power_sleep_wakeup_bts_sleep_exit_req(0);
1420 }
1421 }
1422
1423 #if 1
sys_hal_set_bts_wakeup_platform_en(bool value)1424 void sys_hal_set_bts_wakeup_platform_en(bool value)
1425 {
1426 sys_ll_set_cpu_power_sleep_wakeup_bts_wakeup_platform_en(value);
1427 }
1428
sys_hal_get_bts_wakeup_platform_en()1429 uint32 sys_hal_get_bts_wakeup_platform_en()
1430 {
1431 return sys_ll_get_cpu_power_sleep_wakeup_bts_wakeup_platform_en();
1432 }
1433 #endif
1434
1435 /** BT End **/
1436
1437
1438
1439
1440 /** Audio Start **/
1441 //Audio
1442 /** Audio End **/
1443
1444
1445
1446
1447 /** Video Start **/
1448 /**
1449 * @brief lcd_disp system config
1450 * param1: clk source sel 0:clk_320M 1:clk_480M,
1451 * param2: clk_div F/(1+clkdiv_disp_l+clkdiv_disp_h*2)
1452 * param1: int_en eanble lcd cpu int
1453 * param2: clk_always_on, BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open, 0 by defult
1454 * return none
1455 */
sys_hal_lcd_disp_clk_en(uint8_t clk_src_sel,uint8_t clk_div_l,uint8_t clk_div_h,uint8_t int_en,uint8_t clk_always_on)1456 void sys_hal_lcd_disp_clk_en(uint8_t clk_src_sel, uint8_t clk_div_l, uint8_t clk_div_h, uint8_t int_en,uint8_t clk_always_on)
1457 {
1458 sys_ll_set_cpu_clk_div_mode1_clkdiv_disp_l(clk_div_l);
1459 sys_ll_set_cpu_clk_div_mode2_clkdiv_disp_h(clk_div_h);
1460 sys_ll_set_cpu_clk_div_mode2_cksel_disp( clk_src_sel);
1461 //sys_ll_set_cpu1_int_0_31_en_cpu1_lcd_int_en( 1);
1462 sys_ll_set_cpu0_int_0_31_en_cpu0_lcd_int_en( int_en);
1463 sys_ll_set_cpu_device_clk_enable_disp_cken(1);
1464 sys_ll_set_cpu_mode_disckg2_disp_disckg(clk_always_on);
1465 }
1466
1467 /**
1468 * @brief lcd clk close and int disable, reg value recover default.
1469 * return none
1470 */
sys_hal_lcd_disp_close(void)1471 void sys_hal_lcd_disp_close(void)
1472 {
1473 sys_ll_set_cpu_clk_div_mode1_clkdiv_disp_l(0);
1474 sys_ll_set_cpu_clk_div_mode2_clkdiv_disp_h(0);
1475 sys_ll_set_cpu_clk_div_mode2_cksel_disp(0);
1476 //sys_ll_set_cpu1_int_0_31_en_cpu1_lcd_int_en(&s_sys_hal, 1);
1477 sys_ll_set_cpu0_int_0_31_en_cpu0_lcd_int_en(0);
1478 sys_ll_set_cpu_device_clk_enable_disp_cken(0);
1479 sys_ll_set_cpu_mode_disckg2_disp_disckg(0);
1480 }
1481
1482 /**
1483 * @brief dma2d system config
1484 * param1: clk source sel 0:clk_320M 1:clk_480M,
1485 * param2: clk_always_on ENABLE,0: bus clock auto open when module is select,1:bus clock always open
1486 * param1: int_en eanble lcd cpu int
1487 * return none
1488 */
sys_hal_dma2d_clk_en(uint8_t clk_always_on,uint8_t sys_int_en)1489 void sys_hal_dma2d_clk_en(uint8_t clk_always_on, uint8_t sys_int_en)
1490 {
1491 sys_ll_set_cpu_mode_disckg2_dma2d_disckg(clk_always_on);
1492 ///sys_ll_set_cpu0_int_0_31_en_cpu0_dma2d_int_en(sys_int_en);
1493 sys_ll_set_cpu0_int_0_31_en_cpu0_dma2d_int_en(sys_int_en); //check
1494 }
1495
1496
1497
1498 /** Video End **/
1499
1500
1501
1502
1503 /** WIFI Start **/
1504 //WIFI
1505
1506 //Yantao Add Start
sys_hal_modem_core_reset(void)1507 void sys_hal_modem_core_reset(void)
1508 {
1509 //TODO, 7256 NO modem core reset
1510 }
1511
sys_hal_mpif_invert(void)1512 void sys_hal_mpif_invert(void)
1513 {
1514 //TODO, 7256 NO mpif_invert
1515 }
1516
sys_hal_modem_subsys_reset(void)1517 void sys_hal_modem_subsys_reset(void)
1518 {
1519 //TODO, 7256 NO subsys reset
1520 }
sys_hal_mac_subsys_reset(void)1521 void sys_hal_mac_subsys_reset(void)
1522 {
1523 //TODO, 7256 NO subsys reset
1524 }
sys_hal_usb_subsys_reset(void)1525 void sys_hal_usb_subsys_reset(void)
1526 {
1527 //TODO, 7256 NO subsys reset
1528 }
sys_hal_dsp_subsys_reset(void)1529 void sys_hal_dsp_subsys_reset(void)
1530 {
1531 //TODO, 7256 NO subsys reset
1532 }
sys_hal_mac_power_ctrl(bool power_up)1533 void sys_hal_mac_power_ctrl(bool power_up)
1534 {
1535 //WARNING:the low-level is power-down
1536 sys_ll_set_cpu_power_sleep_wakeup_pwd_wifp_mac(!(power_up));
1537 }
1538
sys_hal_modem_power_ctrl(bool power_up)1539 void sys_hal_modem_power_ctrl(bool power_up)
1540 {
1541 sys_ll_set_cpu_power_sleep_wakeup_pwd_wifp_phy(!(power_up));
1542 }
1543
sys_hal_pta_ctrl(bool pta_en)1544 void sys_hal_pta_ctrl(bool pta_en)
1545 {
1546 //TODO, 7256 NO pta enable
1547 }
1548
sys_hal_modem_bus_clk_ctrl(bool clk_en)1549 void sys_hal_modem_bus_clk_ctrl(bool clk_en)
1550 {
1551 //TODO, 7256 no bus clock enable
1552 }
1553
sys_hal_modem_clk_ctrl(bool clk_en)1554 void sys_hal_modem_clk_ctrl(bool clk_en)
1555 {
1556 sys_ll_set_cpu_device_clk_enable_phy_cken(clk_en);
1557 }
1558
1559
sys_hal_mac_bus_clk_ctrl(bool clk_en)1560 void sys_hal_mac_bus_clk_ctrl(bool clk_en)
1561 {
1562 //TODO, 7256 no bus clock enable
1563 }
1564
sys_hal_mac_clk_ctrl(bool clk_en)1565 void sys_hal_mac_clk_ctrl(bool clk_en)
1566 {
1567 sys_ll_set_cpu_device_clk_enable_mac_cken(clk_en);
1568 }
1569
1570
1571
sys_hal_set_vdd_value(uint32_t param)1572 void sys_hal_set_vdd_value(uint32_t param)
1573 {
1574 //TODO
1575 }
1576
sys_hal_get_vdd_value(void)1577 uint32_t sys_hal_get_vdd_value(void)
1578 {
1579 //TODO reg0x43 Write only
1580 return 4;
1581 }
1582
1583 //CMD_SCTRL_BLOCK_EN_MUX_SET
sys_hal_block_en_mux_set(uint32_t param)1584 void sys_hal_block_en_mux_set(uint32_t param)
1585 {
1586 //TODO 7256 no block en mux
1587 }
sys_hal_enable_mac_gen_int(void)1588 void sys_hal_enable_mac_gen_int(void)
1589 {
1590 sys_ll_set_cpu0_int_32_63_en_cpu0_wifi_mac_int_gen_en(1);
1591 }
sys_hal_enable_mac_prot_int(void)1592 void sys_hal_enable_mac_prot_int(void)
1593 {
1594 sys_ll_set_cpu0_int_32_63_en_cpu0_wifi_mac_int_prot_trigger_en(1);
1595 }
sys_hal_enable_mac_tx_trigger_int(void)1596 void sys_hal_enable_mac_tx_trigger_int(void)
1597 {
1598 sys_ll_set_cpu0_int_32_63_en_cpu0_wifi_mac_int_tx_trigger_en(1);
1599 }
sys_hal_enable_mac_rx_trigger_int(void)1600 void sys_hal_enable_mac_rx_trigger_int(void)
1601 {
1602 sys_ll_set_cpu0_int_32_63_en_cpu0_wifi_mac_int_rx_trigger_en(1);
1603 }
sys_hal_enable_mac_txrx_misc_int(void)1604 void sys_hal_enable_mac_txrx_misc_int(void)
1605 {
1606 sys_ll_set_cpu0_int_32_63_en_cpu0_wifi_mac_int_tx_rx_misc_en(1);
1607 }
sys_hal_enable_mac_txrx_timer_int(void)1608 void sys_hal_enable_mac_txrx_timer_int(void)
1609 {
1610 sys_ll_set_cpu0_int_0_31_en_cpu0_wifi_mac_int_tx_rx_timer_en(1);
1611 }
1612
sys_hal_enable_modem_int(void)1613 void sys_hal_enable_modem_int(void)
1614 {
1615 sys_ll_set_cpu0_int_0_31_en_cpu0_wifi_int_phy_mpb_en(1);
1616 }
sys_hal_enable_modem_rc_int(void)1617 void sys_hal_enable_modem_rc_int(void)
1618 {
1619 sys_ll_set_cpu0_int_0_31_en_cpu0_wifi_int_phy_riu_en(1);
1620 }
1621
1622
1623
1624 //Yantao Add End
1625
sys_hal_cali_dpll_spi_trig_disable(void)1626 void sys_hal_cali_dpll_spi_trig_disable(void)
1627 {
1628 sys_ll_set_ana_reg0_spitrig(0);
1629 }
1630
sys_hal_cali_dpll_spi_trig_enable(void)1631 void sys_hal_cali_dpll_spi_trig_enable(void)
1632 {
1633 sys_ll_set_ana_reg0_spitrig(1);
1634 }
1635
sys_hal_cali_dpll_spi_detect_disable(void)1636 void sys_hal_cali_dpll_spi_detect_disable(void)
1637 {
1638 sys_ll_set_ana_reg0_spideten(0);
1639 }
1640
sys_hal_cali_dpll_spi_detect_enable(void)1641 void sys_hal_cali_dpll_spi_detect_enable(void)
1642 {
1643 sys_ll_set_ana_reg0_spideten(1);
1644 }
1645
sys_hal_set_xtalh_ctune(uint32_t value)1646 void sys_hal_set_xtalh_ctune(uint32_t value)
1647 {
1648 sys_ll_set_ana_reg5_xtalh_ctune(value);
1649 }
1650
sys_hal_analog_set(analog_reg_t reg,uint32_t value)1651 void sys_hal_analog_set(analog_reg_t reg, uint32_t value)
1652 {
1653 analog_address_map_t analog_address_map_table[] = ANALOG_ADDRESS_MAP;
1654 analog_address_map_t *analog_addr_map = &analog_address_map_table[reg];
1655
1656 uint32_t analog_reg_address = analog_addr_map->analog_reg_address;
1657
1658 sys_ll_set_analog_reg_value(analog_reg_address, value);
1659 }
sys_hal_analog_get(analog_reg_t reg)1660 uint32_t sys_hal_analog_get(analog_reg_t reg)
1661 {
1662 analog_address_map_t analog_address_map_table[] = ANALOG_ADDRESS_MAP;
1663 analog_address_map_t *analog_addr_map = &analog_address_map_table[reg];
1664
1665 uint32_t analog_reg_address = analog_addr_map->analog_reg_address;
1666
1667 return sys_ll_get_analog_reg_value(analog_reg_address);
1668 }
1669
sys_hal_set_ana_reg1_value(uint32_t value)1670 void sys_hal_set_ana_reg1_value(uint32_t value)
1671 {
1672 sys_ll_set_ana_reg1_value(value);
1673 }
1674
sys_hal_set_ana_reg2_value(uint32_t value)1675 void sys_hal_set_ana_reg2_value(uint32_t value)
1676 {
1677 sys_ll_set_ana_reg2_value(value);
1678 }
1679
sys_hal_set_ana_reg3_value(uint32_t value)1680 void sys_hal_set_ana_reg3_value(uint32_t value)
1681 {
1682 sys_ll_set_ana_reg3_value(value);
1683 }
1684
sys_hal_set_ana_reg4_value(uint32_t value)1685 void sys_hal_set_ana_reg4_value(uint32_t value)
1686 {
1687 sys_ll_set_ana_reg4_value(value);
1688 }
1689
sys_hal_set_ana_reg12_value(uint32_t value)1690 void sys_hal_set_ana_reg12_value(uint32_t value)
1691 {
1692 sys_ll_set_ana_reg12_value(value);
1693 }
1694
sys_hal_set_ana_reg13_value(uint32_t value)1695 void sys_hal_set_ana_reg13_value(uint32_t value)
1696 {
1697 sys_ll_set_ana_reg13_value(value);
1698 }
1699
sys_hal_set_ana_reg14_value(uint32_t value)1700 void sys_hal_set_ana_reg14_value(uint32_t value)
1701 {
1702 sys_ll_set_ana_reg14_value(value);
1703 }
1704
sys_hal_set_ana_reg15_value(uint32_t value)1705 void sys_hal_set_ana_reg15_value(uint32_t value)
1706 {
1707 sys_ll_set_ana_reg15_value(value);
1708 }
1709
sys_hal_set_ana_reg16_value(uint32_t value)1710 void sys_hal_set_ana_reg16_value(uint32_t value)
1711 {
1712 sys_ll_set_ana_reg16_value(value);
1713 }
1714
sys_hal_set_ana_reg17_value(uint32_t value)1715 void sys_hal_set_ana_reg17_value(uint32_t value)
1716 {
1717 sys_ll_set_ana_reg17_value(value);
1718 }
1719
sys_hal_bias_reg_read(void)1720 uint32_t sys_hal_bias_reg_read(void)
1721 {
1722 ///TODO
1723 return 0;
1724 }
sys_hal_bias_reg_write(uint32_t param)1725 uint32_t sys_hal_bias_reg_write(uint32_t param)
1726 {
1727 ///TODO
1728
1729 return 0;
1730
1731 }
1732
sys_hal_analog_reg2_get(void)1733 uint32_t sys_hal_analog_reg2_get(void)
1734 {
1735 ///TODO
1736
1737 return 0;
1738 }
1739
sys_hal_bias_reg_set(uint32_t param)1740 uint32_t sys_hal_bias_reg_set(uint32_t param)
1741 {
1742 ///TODO
1743
1744 return 0;
1745 }
1746
sys_hal_bias_reg_clean(uint32_t param)1747 uint32_t sys_hal_bias_reg_clean(uint32_t param)
1748 {
1749 ///TODO
1750
1751 return 0;
1752 }
1753
1754
sys_hal_get_xtalh_ctune(void)1755 uint32_t sys_hal_get_xtalh_ctune(void)
1756 {
1757 return sys_ll_get_ana_reg5_xtalh_ctune();
1758 }
1759
sys_hal_get_bgcalm(void)1760 uint32_t sys_hal_get_bgcalm(void)
1761 {
1762 return sys_ll_get_ana_reg5_bgcalm();
1763 }
1764
sys_hal_set_bgcalm(uint32_t value)1765 void sys_hal_set_bgcalm(uint32_t value)
1766 {
1767 sys_ll_set_ana_reg5_bgcalm(value);
1768 }
1769
sys_hal_set_audioen(uint32_t value)1770 void sys_hal_set_audioen(uint32_t value)
1771 {
1772 sys_ll_set_ana_reg11_audioen(value);
1773 }
1774
sys_hal_set_dpll_div_cksel(uint32_t value)1775 void sys_hal_set_dpll_div_cksel(uint32_t value)
1776 {
1777 sys_ll_set_ana_reg11_cksel(value);
1778 }
1779
sys_hal_set_dpll_reset(uint32_t value)1780 void sys_hal_set_dpll_reset(uint32_t value)
1781 {
1782 sys_ll_set_ana_reg11_reset(value);
1783 }
1784
sys_hal_set_gadc_ten(uint32_t value)1785 void sys_hal_set_gadc_ten(uint32_t value)
1786 {
1787 // sys_ll_set_ana_reg7_gadc_ten(value);
1788 }
1789 /** WIFI End **/
1790
1791 /** Audio Start **/
1792
sys_hal_aud_select_clock(uint32_t value)1793 void sys_hal_aud_select_clock(uint32_t value)
1794 {
1795 sys_ll_set_cpu_clk_div_mode1_cksel_aud(value);
1796 }
1797
sys_hal_aud_clock_en(uint32_t value)1798 void sys_hal_aud_clock_en(uint32_t value)
1799 {
1800 sys_ll_set_cpu_device_clk_enable_aud_cken(value);
1801 }
1802
sys_hal_aud_vdd1v_en(uint32_t value)1803 void sys_hal_aud_vdd1v_en(uint32_t value)
1804 {
1805 sys_ll_set_ana_reg12_enaudvdd1v(value);
1806 }
1807
sys_hal_aud_vdd1v5_en(uint32_t value)1808 void sys_hal_aud_vdd1v5_en(uint32_t value)
1809 {
1810 sys_ll_set_ana_reg12_enaudvdd1v5(value);
1811 }
1812
sys_hal_aud_mic1_en(uint32_t value)1813 void sys_hal_aud_mic1_en(uint32_t value)
1814 {
1815 sys_ll_set_ana_reg14_micen(value);
1816 }
1817
sys_hal_aud_mic2_en(uint32_t value)1818 void sys_hal_aud_mic2_en(uint32_t value)
1819 {
1820 sys_ll_set_ana_reg15_micen(value);
1821 }
1822
sys_hal_aud_audpll_en(uint32_t value)1823 void sys_hal_aud_audpll_en(uint32_t value)
1824 {
1825 sys_ll_set_ana_reg6_en_audpll(value);
1826 }
1827
sys_hal_aud_dacdrv_en(uint32_t value)1828 void sys_hal_aud_dacdrv_en(uint32_t value)
1829 {
1830 sys_ll_set_ana_reg16_dacdrven(value);
1831 }
1832
sys_hal_aud_bias_en(uint32_t value)1833 void sys_hal_aud_bias_en(uint32_t value)
1834 {
1835 sys_ll_set_ana_reg17_enbias(value);
1836 }
1837
sys_hal_aud_dacr_en(uint32_t value)1838 void sys_hal_aud_dacr_en(uint32_t value)
1839 {
1840 sys_ll_set_ana_reg16_dacren(value);
1841 }
1842
sys_hal_aud_dacl_en(uint32_t value)1843 void sys_hal_aud_dacl_en(uint32_t value)
1844 {
1845 sys_ll_set_ana_reg16_daclen(value);
1846 }
1847
sys_hal_aud_rvcmd_en(uint32_t value)1848 void sys_hal_aud_rvcmd_en(uint32_t value)
1849 {
1850 sys_ll_set_ana_reg16_renvcmd(value);
1851 }
1852
sys_hal_aud_lvcmd_en(uint32_t value)1853 void sys_hal_aud_lvcmd_en(uint32_t value)
1854 {
1855 sys_ll_set_ana_reg16_lenvcmd(value);
1856 }
1857
sys_hal_aud_micbias1v_en(uint32_t value)1858 void sys_hal_aud_micbias1v_en(uint32_t value)
1859 {
1860 sys_ll_set_ana_reg12_enmicbias1v(value);
1861 }
1862
sys_hal_aud_micbias_trim_set(uint32_t value)1863 void sys_hal_aud_micbias_trim_set(uint32_t value)
1864 {
1865 sys_ll_set_ana_reg12_micbias_trim(value);
1866 }
1867
sys_hal_aud_mic_rst_set(uint32_t value)1868 void sys_hal_aud_mic_rst_set(uint32_t value)
1869 {
1870 sys_ll_set_ana_reg13_rst(value);
1871 }
1872
sys_hal_aud_mic1_gain_set(uint32_t value)1873 void sys_hal_aud_mic1_gain_set(uint32_t value)
1874 {
1875 sys_ll_set_ana_reg14_micgain(value);
1876 }
1877
sys_hal_aud_mic2_gain_set(uint32_t value)1878 void sys_hal_aud_mic2_gain_set(uint32_t value)
1879 {
1880 sys_ll_set_ana_reg15_micgain(value);
1881 }
1882
sys_hal_aud_int_en(uint32_t value)1883 void sys_hal_aud_int_en(uint32_t value)
1884 {
1885 sys_ll_set_cpu0_int_0_31_en_cpu0_aud_int_en(value);
1886 }
1887
sys_hal_aud_power_en(uint32_t value)1888 void sys_hal_aud_power_en(uint32_t value)
1889 {
1890 sys_ll_set_cpu_power_sleep_wakeup_pwd_audp(value);
1891 }
1892
1893
1894 /** Audio End **/
1895
1896 /** FFT Start **/
1897
sys_hal_fft_disckg_set(uint32_t value)1898 void sys_hal_fft_disckg_set(uint32_t value)
1899 {
1900 sys_ll_set_cpu_mode_disckg1_fft_disckg(value);
1901 }
1902
sys_hal_cpu0_fft_int_en(uint32_t value)1903 void sys_hal_cpu0_fft_int_en(uint32_t value)
1904 {
1905 sys_ll_set_cpu0_int_0_31_en_cpu0_fft_int_en(value);
1906 }
1907
1908 /** FFT End **/
1909
1910 /** I2S Start **/
sys_hal_i2s_select_clock(uint32_t value)1911 void sys_hal_i2s_select_clock(uint32_t value)
1912 {
1913 sys_ll_set_cpu_clk_div_mode1_cksel_i2s(value);
1914 }
1915
sys_hal_i2s_clock_en(uint32_t value)1916 void sys_hal_i2s_clock_en(uint32_t value)
1917 {
1918 sys_ll_set_cpu_device_clk_enable_i2s_cken(value);
1919 }
1920
sys_hal_i2s_disckg_set(uint32_t value)1921 void sys_hal_i2s_disckg_set(uint32_t value)
1922 {
1923 sys_ll_set_cpu_mode_disckg1_i2s_disckg(value);
1924 }
1925
sys_hal_i2s_int_en(uint32_t value)1926 void sys_hal_i2s_int_en(uint32_t value)
1927 {
1928 sys_ll_set_cpu0_int_0_31_en_cpu0_i2s_int_en(value);
1929 }
1930
sys_hal_apll_en(uint32_t value)1931 void sys_hal_apll_en(uint32_t value)
1932 {
1933 sys_ll_set_ana_reg6_en_audpll(value);
1934 }
1935
sys_hal_cb_manu_val_set(uint32_t value)1936 void sys_hal_cb_manu_val_set(uint32_t value)
1937 {
1938 sys_ll_set_ana_reg4_cb_manu_val(value);
1939 }
1940
sys_hal_ana_reg11_vsel_set(uint32_t value)1941 void sys_hal_ana_reg11_vsel_set(uint32_t value)
1942 {
1943 sys_ll_set_ana_reg11_vsel(value);
1944 }
1945
sys_hal_ana_reg10_sdm_val_set(uint32_t value)1946 void sys_hal_ana_reg10_sdm_val_set(uint32_t value)
1947 {
1948 sys_ll_set_ana_reg10_sdm_val(value);
1949 }
1950
sys_hal_ana_reg11_spi_trigger_set(uint32_t value)1951 void sys_hal_ana_reg11_spi_trigger_set(uint32_t value)
1952 {
1953 sys_ll_set_ana_reg11_spi_trigger(value);
1954 }
1955
1956 /** I2S End **/
1957
1958 /** Touch Start **/
sys_hal_touch_power_down(uint32_t value)1959 void sys_hal_touch_power_down(uint32_t value)
1960 {
1961 sys_ll_set_ana_reg8_pwd_td(value);
1962 }
1963
sys_hal_touch_sensitivity_level_set(uint32_t value)1964 void sys_hal_touch_sensitivity_level_set(uint32_t value)
1965 {
1966 sys_ll_set_ana_reg8_gain_s(value);
1967 }
1968
sys_hal_touch_scan_mode_enable(uint32_t value)1969 void sys_hal_touch_scan_mode_enable(uint32_t value)
1970 {
1971 sys_ll_set_ana_reg8_en_scm(value);
1972 }
1973
sys_hal_touch_detect_threshold_set(uint32_t value)1974 void sys_hal_touch_detect_threshold_set(uint32_t value)
1975 {
1976 sys_ll_set_ana_reg9_vrefs(value);
1977 }
1978
sys_hal_touch_detect_range_set(uint32_t value)1979 void sys_hal_touch_detect_range_set(uint32_t value)
1980 {
1981 sys_ll_set_ana_reg9_crg(value);
1982 }
1983
sys_hal_touch_calib_enable(uint32_t value)1984 void sys_hal_touch_calib_enable(uint32_t value)
1985 {
1986 sys_ll_set_ana_reg9_en_cal(value);
1987 }
1988
sys_hal_touch_manul_mode_calib_value_set(uint32_t value)1989 void sys_hal_touch_manul_mode_calib_value_set(uint32_t value)
1990 {
1991 sys_ll_set_ana_reg8_cap_calspi(value);
1992 }
1993
sys_hal_touch_manul_mode_enable(uint32_t value)1994 void sys_hal_touch_manul_mode_enable(uint32_t value)
1995 {
1996 sys_ll_set_ana_reg9_man_mode(value);
1997 }
1998
sys_hal_touch_scan_mode_chann_set(uint32_t value)1999 void sys_hal_touch_scan_mode_chann_set(uint32_t value)
2000 {
2001 sys_ll_set_ana_reg8_chs_scan(value);
2002 }
2003
sys_hal_touch_int_enable(uint32_t value)2004 void sys_hal_touch_int_enable(uint32_t value)
2005 {
2006 sys_ll_set_cpu0_int_32_63_en_cpu0_touched_int_en(value);
2007 }
2008
2009 /** Touch End **/
2010
2011
2012 /** jpeg start **/
sys_hal_set_jpeg_clk_sel(uint32_t value)2013 void sys_hal_set_jpeg_clk_sel(uint32_t value)
2014 {
2015 sys_ll_set_cpu_clk_div_mode1_cksel_jpeg(value);
2016 }
2017
sys_hal_set_clk_div_mode1_clkdiv_jpeg(uint32_t value)2018 void sys_hal_set_clk_div_mode1_clkdiv_jpeg(uint32_t value)
2019 {
2020 sys_ll_set_cpu_clk_div_mode1_clkdiv_jpeg(value);
2021 }
2022
sys_hal_set_jpeg_disckg(uint32_t value)2023 void sys_hal_set_jpeg_disckg(uint32_t value)
2024 {
2025 sys_ll_set_cpu_mode_disckg1_jpeg_disckg(value);
2026 }
2027
sys_hal_set_cpu_clk_div_mode1_clkdiv_bus(uint32_t value)2028 void sys_hal_set_cpu_clk_div_mode1_clkdiv_bus(uint32_t value)
2029 {
2030 sys_ll_set_cpu_clk_div_mode1_clkdiv_bus(value);
2031 }
2032
sys_hal_video_power_en(uint32_t value)2033 void sys_hal_video_power_en(uint32_t value)
2034 {
2035 sys_ll_set_cpu_power_sleep_wakeup_pwd_vidp(value);
2036 }
2037
sys_hal_set_auxs_clk_sel(uint32_t value)2038 void sys_hal_set_auxs_clk_sel(uint32_t value)
2039 {
2040 sys_ll_set_cpu_clk_div_mode2_cksel_auxs(value);
2041 }
2042
sys_hal_set_auxs_clk_div(uint32_t value)2043 void sys_hal_set_auxs_clk_div(uint32_t value)
2044 {
2045 sys_ll_set_cpu_clk_div_mode2_ckdiv_auxs(value);
2046 }
2047
2048 /** jpeg end **/
2049
2050 /** psram Start **/
sys_hal_psram_volstage_sel(uint32_t enable)2051 void sys_hal_psram_volstage_sel(uint32_t enable)
2052 {
2053 uint32_t value = sys_ll_get_ana_reg6_value();
2054
2055 if (enable)
2056 value |= (0x1 << 5);
2057 else
2058 value &= ~(0x1 << 5);
2059
2060 sys_ll_set_ana_reg6_value(value);
2061 }
2062
sys_hal_psram_xtall_osc_enable(uint32_t enable)2063 void sys_hal_psram_xtall_osc_enable(uint32_t enable)
2064 {
2065 uint32_t value = sys_ll_get_ana_reg6_value();
2066
2067 if (enable)
2068 value |= (0x1 << 7);
2069 else
2070 value &= ~(0x1 << 7);
2071
2072 sys_ll_set_ana_reg6_value(value);
2073 }
2074
sys_hal_psram_doc_enable(uint32_t enable)2075 void sys_hal_psram_doc_enable(uint32_t enable)
2076 {
2077 uint32_t value = sys_ll_get_ana_reg6_value();
2078
2079 if (enable)
2080 value |= (0x1 << 8);
2081 else
2082 value &= ~(0x1 << 8);
2083
2084 sys_ll_set_ana_reg6_value(value);
2085 }
2086
sys_hal_psram_ldo_enable(uint32_t enable)2087 void sys_hal_psram_ldo_enable(uint32_t enable)
2088 {
2089 uint32_t value = sys_ll_get_ana_reg6_value();
2090
2091 if (enable)
2092 value |= (0x1 << 9);
2093 else
2094 value &= ~(0x1 << 9);
2095
2096 sys_ll_set_ana_reg6_value(value);
2097 }
2098
sys_hal_psram_dpll_enable(uint32_t enable)2099 void sys_hal_psram_dpll_enable(uint32_t enable)
2100 {
2101 uint32_t value = sys_ll_get_ana_reg6_value();
2102
2103 if (enable)
2104 value |= (0x1 << 12);
2105 else
2106 value &= ~(0x1 << 12);
2107
2108 sys_ll_set_ana_reg6_value(value);
2109 }
2110
sys_hal_psram_clk_sel(uint32_t value)2111 void sys_hal_psram_clk_sel(uint32_t value)
2112 {
2113 sys_ll_set_cpu_clk_div_mode2_cksel_psram(value);
2114 }
2115
sys_hal_psram_set_clkdiv(uint32_t value)2116 void sys_hal_psram_set_clkdiv(uint32_t value)
2117 {
2118 sys_ll_set_cpu_clk_div_mode2_ckdiv_psram(value);
2119 }
2120
sys_hal_psram_power_enable(void)2121 void sys_hal_psram_power_enable(void)
2122 {
2123 uint32_t value = sys_ll_get_ana_reg6_value();
2124 value |= (0x1 << 9);
2125 //value &= ~(0x1 << 5);
2126 sys_ll_set_ana_reg6_value(value);
2127 }
2128
sys_hal_psram_psldo_vsel(uint32_t value)2129 void sys_hal_psram_psldo_vsel(uint32_t value)
2130 {
2131 sys_ll_set_ana_reg9_psldo_vsel(value);
2132 }
2133
2134 /** psram End **/
2135
2136 /* REG_0x03:cpu_storage_connect_op_select->flash_sel:0: normal flash operation 1:flash download by spi,R/W,0x3[9]*/
sys_hal_get_cpu_storage_connect_op_select_flash_sel(void)2137 uint32_t sys_hal_get_cpu_storage_connect_op_select_flash_sel(void)
2138 {
2139 return sys_ll_get_cpu_storage_connect_op_select_flash_sel();
2140 }
2141
sys_hal_set_cpu_storage_connect_op_select_flash_sel(uint32_t value)2142 void sys_hal_set_cpu_storage_connect_op_select_flash_sel(uint32_t value)
2143 {
2144 sys_ll_set_cpu_storage_connect_op_select_flash_sel(value);
2145 }
2146
2147 /** Misc Start **/
2148 //Misc
2149 /** Misc End **/
2150
2151
2152 /* generated codes by python tool with address mapping */
2153 #if 0 //just for reference
2154 // Copyright 2020-2021 Beken
2155 //
2156 // Licensed under the Apache License, Version 2.0 (the "License");
2157 // you may not use this file except in compliance with the License.
2158 // You may obtain a copy of the License at
2159 //
2160 // http://www.apache.org/licenses/LICENSE-2.0
2161 //
2162 // Unless required by applicable law or agreed to in writing, software
2163 // distributed under the License is distributed on an "AS IS" BASIS,
2164 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
2165 // See the License for the specific language governing permissions and
2166 // limitations under the License.
2167
2168 // Copyright 2020-2021 Beken
2169 //
2170 // Licensed under the Apache License, Version 2.0 (the "License");
2171 // you may not use this file except in compliance with the License.
2172 // You may obtain a copy of the License at
2173 //
2174 // http://www.apache.org/licenses/LICENSE-2.0
2175 //
2176 // Unless required by applicable law or agreed to in writing, software
2177 // distributed under the License is distributed on an "AS IS" BASIS,
2178 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
2179 // See the License for the specific language governing permissions and
2180 // limitations under the License.
2181
2182
2183 #include <common/bk_include.h>
2184 #include "sys_hal.h"
2185
2186 #include "sys_ll.h"
2187
2188 bk_err_t sys_hal_init(void)
2189 {
2190 s_sys_hal.hw = (sys_hw_t *)SYS_LL_REG_BASE;
2191 return BK_OK;
2192 }
2193
2194 /* REG_0x00 */
2195
2196 uint32_t sys_hal_get_device_id_value(sys_hw_t *hw)
2197 {
2198 return sys_ll_get_device_id_value(hw);
2199 }
2200
2201 /* REG_0x00:device_id->DeviceID: ,RO,0x0[31:0]*/
2202 uint32_t sys_hal_get_device_id_deviceid(sys_hw_t *hw)
2203 {
2204 return sys_ll_get_device_id_deviceid(hw);
2205 }
2206
2207 /* REG_0x01 */
2208
2209 uint32_t sys_hal_get_version_id_value(sys_hw_t *hw)
2210 {
2211 return sys_ll_get_version_id_value(hw);
2212 }
2213
2214 /* REG_0x01:version_id->VersionID: ,RO,0x1[31:0]*/
2215 uint32_t sys_hal_get_version_id_versionid(sys_hw_t *hw)
2216 {
2217 return sys_ll_get_version_id_versionid(hw);
2218 }
2219
2220 /* REG_0x02 */
2221
2222 uint32_t sys_hal_get_cpu_current_run_status_value(sys_hw_t *hw)
2223 {
2224 return sys_ll_get_cpu_current_run_status_value(hw);
2225 }
2226
2227 /* REG_0x02:cpu_current_run_status->core0_halted:core0 halt indicate,RO,0x2[0]*/
2228 uint32_t sys_hal_get_cpu_current_run_status_core0_halted(sys_hw_t *hw)
2229 {
2230 return sys_ll_get_cpu_current_run_status_core0_halted(hw);
2231 }
2232
2233 /* REG_0x02:cpu_current_run_status->core1_halted:core1 halt indicate,RO,0x2[1]*/
2234 uint32_t sys_hal_get_cpu_current_run_status_core1_halted(sys_hw_t *hw)
2235 {
2236 return sys_ll_get_cpu_current_run_status_core1_halted(hw);
2237 }
2238
2239 /* REG_0x02:cpu_current_run_status->cpu0_sw_reset:cpu0_sw_reset indicate,RO,0x2[4]*/
2240 uint32_t sys_hal_get_cpu_current_run_status_cpu0_sw_reset(sys_hw_t *hw)
2241 {
2242 return sys_ll_get_cpu_current_run_status_cpu0_sw_reset(hw);
2243 }
2244
2245 /* REG_0x02:cpu_current_run_status->cpu1_sw_reset:cpu1_sw_reset indicate,RO,0x2[5]*/
2246 uint32_t sys_hal_get_cpu_current_run_status_cpu1_sw_reset(sys_hw_t *hw)
2247 {
2248 return sys_ll_get_cpu_current_run_status_cpu1_sw_reset(hw);
2249 }
2250
2251 /* REG_0x02:cpu_current_run_status->cpu0_pwr_dw_state:cpu0_pwr_dw_state,RO,0x2[8]*/
2252 uint32_t sys_hal_get_cpu_current_run_status_cpu0_pwr_dw_state(sys_hw_t *hw)
2253 {
2254 return sys_ll_get_cpu_current_run_status_cpu0_pwr_dw_state(hw);
2255 }
2256
2257 /* REG_0x02:cpu_current_run_status->cpu1_pwr_dw_state:cpu1_pwr_dw_state,RO,0x2[9]*/
2258 uint32_t sys_hal_get_cpu_current_run_status_cpu1_pwr_dw_state(sys_hw_t *hw)
2259 {
2260 return sys_ll_get_cpu_current_run_status_cpu1_pwr_dw_state(hw);
2261 }
2262
2263 /* REG_0x03 */
2264
2265 uint32_t sys_hal_get_cpu_storage_connect_op_select_value(sys_hw_t *hw)
2266 {
2267 return sys_ll_get_cpu_storage_connect_op_select_value(hw);
2268 }
2269
2270 void sys_hal_set_cpu_storage_connect_op_select_value(sys_hw_t *hw, uint32_t value)
2271 {
2272 sys_ll_set_cpu_storage_connect_op_select_value(hw, value);
2273 }
2274
2275 /* REG_0x03:cpu_storage_connect_op_select->boot_mode:0:ROM boot 1:FLASH boot,R/W,0x3[0]*/
2276 uint32_t sys_hal_get_cpu_storage_connect_op_select_boot_mode(sys_hw_t *hw)
2277 {
2278 return sys_ll_get_cpu_storage_connect_op_select_boot_mode(hw);
2279 }
2280
2281 void sys_hal_set_cpu_storage_connect_op_select_boot_mode(sys_hw_t *hw, uint32_t value)
2282 {
2283 sys_ll_set_cpu_storage_connect_op_select_boot_mode(hw, value);
2284 }
2285
2286 /* REG_0x03:cpu_storage_connect_op_select->jtag_core_sel:0:jtag connect core0, 1:jtag connect core1,R/W,0x3[8]*/
2287 uint32_t sys_hal_get_cpu_storage_connect_op_select_jtag_core_sel(sys_hw_t *hw)
2288 {
2289 return sys_ll_get_cpu_storage_connect_op_select_jtag_core_sel(hw);
2290 }
2291
2292 void sys_hal_set_cpu_storage_connect_op_select_jtag_core_sel(sys_hw_t *hw, uint32_t value)
2293 {
2294 sys_ll_set_cpu_storage_connect_op_select_jtag_core_sel(hw, value);
2295 }
2296
2297 /* REG_0x04 */
2298
2299 uint32_t sys_hal_get_cpu0_int_halt_clk_op_value(sys_hw_t *hw)
2300 {
2301 return sys_ll_get_cpu0_int_halt_clk_op_value(hw);
2302 }
2303
2304 void sys_hal_set_cpu0_int_halt_clk_op_value(sys_hw_t *hw, uint32_t value)
2305 {
2306 sys_ll_set_cpu0_int_halt_clk_op_value(hw, value);
2307 }
2308
2309 /* REG_0x04:cpu0_int_halt_clk_op->cpu0_sw_rst:reserved,R/W,0x4[0]*/
2310 uint32_t sys_hal_get_cpu0_int_halt_clk_op_cpu0_sw_rst(sys_hw_t *hw)
2311 {
2312 return sys_ll_get_cpu0_int_halt_clk_op_cpu0_sw_rst(hw);
2313 }
2314
2315 void sys_hal_set_cpu0_int_halt_clk_op_cpu0_sw_rst(sys_hw_t *hw, uint32_t value)
2316 {
2317 sys_ll_set_cpu0_int_halt_clk_op_cpu0_sw_rst(hw, value);
2318 }
2319
2320 /* REG_0x04:cpu0_int_halt_clk_op->cpu0_pwr_dw:reserved,R/W,0x4[1]*/
2321 uint32_t sys_hal_get_cpu0_int_halt_clk_op_cpu0_pwr_dw(sys_hw_t *hw)
2322 {
2323 return sys_ll_get_cpu0_int_halt_clk_op_cpu0_pwr_dw(hw);
2324 }
2325
2326 void sys_hal_set_cpu0_int_halt_clk_op_cpu0_pwr_dw(sys_hw_t *hw, uint32_t value)
2327 {
2328 sys_ll_set_cpu0_int_halt_clk_op_cpu0_pwr_dw(hw, value);
2329 }
2330
2331 /* REG_0x04:cpu0_int_halt_clk_op->cpu0_int_mask:cpu0 int mask,R/W,0x4[2]*/
2332 uint32_t sys_hal_get_cpu0_int_halt_clk_op_cpu0_int_mask(sys_hw_t *hw)
2333 {
2334 return sys_ll_get_cpu0_int_halt_clk_op_cpu0_int_mask(hw);
2335 }
2336
2337 void sys_hal_set_cpu0_int_halt_clk_op_cpu0_int_mask(sys_hw_t *hw, uint32_t value)
2338 {
2339 sys_ll_set_cpu0_int_halt_clk_op_cpu0_int_mask(hw, value);
2340 }
2341
2342 /* REG_0x04:cpu0_int_halt_clk_op->cpu0_halt:core0 halt indicate,R/W,0x4[3]*/
2343 uint32_t sys_hal_get_cpu0_int_halt_clk_op_cpu0_halt(sys_hw_t *hw)
2344 {
2345 return sys_ll_get_cpu0_int_halt_clk_op_cpu0_halt(hw);
2346 }
2347
2348 void sys_hal_set_cpu0_int_halt_clk_op_cpu0_halt(sys_hw_t *hw, uint32_t value)
2349 {
2350 sys_ll_set_cpu0_int_halt_clk_op_cpu0_halt(hw, value);
2351 }
2352
2353 /* REG_0x04:cpu0_int_halt_clk_op->cpu0_clk_div:Frequency division : F/(1+N), N is the data of the reg value,R/W,0x4[7:4]*/
2354 uint32_t sys_hal_get_cpu0_int_halt_clk_op_cpu0_clk_div(sys_hw_t *hw)
2355 {
2356 return sys_ll_get_cpu0_int_halt_clk_op_cpu0_clk_div(hw);
2357 }
2358
2359 void sys_hal_set_cpu0_int_halt_clk_op_cpu0_clk_div(sys_hw_t *hw, uint32_t value)
2360 {
2361 sys_ll_set_cpu0_int_halt_clk_op_cpu0_clk_div(hw, value);
2362 }
2363
2364 /* REG_0x04:cpu0_int_halt_clk_op->cpu0_offset:reserved,RO,0x4[31:8]*/
2365 uint32_t sys_hal_get_cpu0_int_halt_clk_op_cpu0_offset(sys_hw_t *hw)
2366 {
2367 return sys_ll_get_cpu0_int_halt_clk_op_cpu0_offset(hw);
2368 }
2369
2370 /* REG_0x05 */
2371
2372 uint32_t sys_hal_get_cpu1_int_halt_clk_op_value(sys_hw_t *hw)
2373 {
2374 return sys_ll_get_cpu1_int_halt_clk_op_value(hw);
2375 }
2376
2377 void sys_hal_set_cpu1_int_halt_clk_op_value(sys_hw_t *hw, uint32_t value)
2378 {
2379 sys_ll_set_cpu1_int_halt_clk_op_value(hw, value);
2380 }
2381
2382 /* REG_0x05:cpu1_int_halt_clk_op->cpu1_sw_rst:reserved,R/W,0x5[0]*/
2383 uint32_t sys_hal_get_cpu1_int_halt_clk_op_cpu1_sw_rst(sys_hw_t *hw)
2384 {
2385 return sys_ll_get_cpu1_int_halt_clk_op_cpu1_sw_rst(hw);
2386 }
2387
2388 void sys_hal_set_cpu1_int_halt_clk_op_cpu1_sw_rst(sys_hw_t *hw, uint32_t value)
2389 {
2390 sys_ll_set_cpu1_int_halt_clk_op_cpu1_sw_rst(hw, value);
2391 }
2392
2393 /* REG_0x05:cpu1_int_halt_clk_op->cpu1_pwr_dw:reserved,R/W,0x5[1]*/
2394 uint32_t sys_hal_get_cpu1_int_halt_clk_op_cpu1_pwr_dw(sys_hw_t *hw)
2395 {
2396 return sys_ll_get_cpu1_int_halt_clk_op_cpu1_pwr_dw(hw);
2397 }
2398
2399 void sys_hal_set_cpu1_int_halt_clk_op_cpu1_pwr_dw(sys_hw_t *hw, uint32_t value)
2400 {
2401 sys_ll_set_cpu1_int_halt_clk_op_cpu1_pwr_dw(hw, value);
2402 }
2403
2404 /* REG_0x05:cpu1_int_halt_clk_op->cpu1_int_mask:cpu1 int mask,R/W,0x5[2]*/
2405 uint32_t sys_hal_get_cpu1_int_halt_clk_op_cpu1_int_mask(sys_hw_t *hw)
2406 {
2407 return sys_ll_get_cpu1_int_halt_clk_op_cpu1_int_mask(hw);
2408 }
2409
2410 void sys_hal_set_cpu1_int_halt_clk_op_cpu1_int_mask(sys_hw_t *hw, uint32_t value)
2411 {
2412 sys_ll_set_cpu1_int_halt_clk_op_cpu1_int_mask(hw, value);
2413 }
2414
2415 /* REG_0x05:cpu1_int_halt_clk_op->cpu1_halt:core1 halt indicate,R/W,0x5[3]*/
2416 uint32_t sys_hal_get_cpu1_int_halt_clk_op_cpu1_halt(sys_hw_t *hw)
2417 {
2418 return sys_ll_get_cpu1_int_halt_clk_op_cpu1_halt(hw);
2419 }
2420
2421 void sys_hal_set_cpu1_int_halt_clk_op_cpu1_halt(sys_hw_t *hw, uint32_t value)
2422 {
2423 sys_ll_set_cpu1_int_halt_clk_op_cpu1_halt(hw, value);
2424 }
2425
2426 /* REG_0x05:cpu1_int_halt_clk_op->cpu1_clk_div:Frequency division : F/(1+N), N is the data of the reg value,R/W,0x5[7:4]*/
2427 uint32_t sys_hal_get_cpu1_int_halt_clk_op_cpu1_clk_div(sys_hw_t *hw)
2428 {
2429 return sys_ll_get_cpu1_int_halt_clk_op_cpu1_clk_div(hw);
2430 }
2431
2432 void sys_hal_set_cpu1_int_halt_clk_op_cpu1_clk_div(sys_hw_t *hw, uint32_t value)
2433 {
2434 sys_ll_set_cpu1_int_halt_clk_op_cpu1_clk_div(hw, value);
2435 }
2436
2437 /* REG_0x05:cpu1_int_halt_clk_op->cpu1_offset:reserved,R/W,0x5[31:8]*/
2438 uint32_t sys_hal_get_cpu1_int_halt_clk_op_cpu1_offset(sys_hw_t *hw)
2439 {
2440 return sys_ll_get_cpu1_int_halt_clk_op_cpu1_offset(hw);
2441 }
2442
2443 void sys_hal_set_cpu1_int_halt_clk_op_cpu1_offset(sys_hw_t *hw, uint32_t value)
2444 {
2445 sys_ll_set_cpu1_int_halt_clk_op_cpu1_offset(hw, value);
2446 }
2447
2448 /* REG_0x06 */
2449
2450 /* REG_0x08 */
2451
2452 uint32_t sys_hal_get_cpu_clk_div_mode1_value(sys_hw_t *hw)
2453 {
2454 return sys_ll_get_cpu_clk_div_mode1_value(hw);
2455 }
2456
2457 void sys_hal_set_cpu_clk_div_mode1_value(sys_hw_t *hw, uint32_t value)
2458 {
2459 sys_ll_set_cpu_clk_div_mode1_value(hw, value);
2460 }
2461
2462 /* REG_0x08:cpu_clk_div_mode1->clkdiv_core:Frequency division : F/(1+N), N is the data of the reg value,R/W,0x8[3:0]*/
2463 uint32_t sys_hal_get_cpu_clk_div_mode1_clkdiv_core(sys_hw_t *hw)
2464 {
2465 return sys_ll_get_cpu_clk_div_mode1_clkdiv_core(hw);
2466 }
2467
2468 void sys_hal_set_cpu_clk_div_mode1_clkdiv_core(sys_hw_t *hw, uint32_t value)
2469 {
2470 sys_ll_set_cpu_clk_div_mode1_clkdiv_core(hw, value);
2471 }
2472
2473 /* REG_0x08:cpu_clk_div_mode1->cksel_core:0: clk_DCO 1 : XTAL 2 : 320M 3 : 480M,R/W,0x8[5:4]*/
2474 uint32_t sys_hal_get_cpu_clk_div_mode1_cksel_core(sys_hw_t *hw)
2475 {
2476 return sys_ll_get_cpu_clk_div_mode1_cksel_core(hw);
2477 }
2478
2479 void sys_hal_set_cpu_clk_div_mode1_cksel_core(sys_hw_t *hw, uint32_t value)
2480 {
2481 sys_ll_set_cpu_clk_div_mode1_cksel_core(hw, value);
2482 }
2483
2484 /* REG_0x08:cpu_clk_div_mode1->clkdiv_bus:Frequency division : F/(1+N), N is the data of the reg value,R/W,0x8[6]*/
2485 uint32_t sys_hal_get_cpu_clk_div_mode1_clkdiv_bus(sys_hw_t *hw)
2486 {
2487 return sys_ll_get_cpu_clk_div_mode1_clkdiv_bus(hw);
2488 }
2489
2490 void sys_hal_set_cpu_clk_div_mode1_clkdiv_bus(sys_hw_t *hw, uint32_t value)
2491 {
2492 sys_ll_set_cpu_clk_div_mode1_clkdiv_bus(hw, value);
2493 }
2494
2495 /* REG_0x08:cpu_clk_div_mode1->clkdiv_uart0:Frequency division : 0:/1 1:/2 2:/4 3:/8,R/W,0x8[9:8]*/
2496 uint32_t sys_hal_get_cpu_clk_div_mode1_clkdiv_uart0(sys_hw_t *hw)
2497 {
2498 return sys_ll_get_cpu_clk_div_mode1_clkdiv_uart0(hw);
2499 }
2500
2501 void sys_hal_set_cpu_clk_div_mode1_clkdiv_uart0(sys_hw_t *hw, uint32_t value)
2502 {
2503 sys_ll_set_cpu_clk_div_mode1_clkdiv_uart0(hw, value);
2504 }
2505
2506 /* REG_0x08:cpu_clk_div_mode1->clksel_uart0:0:XTAL 1:APLL,R/W,0x8[10]*/
2507 uint32_t sys_hal_get_cpu_clk_div_mode1_clksel_uart0(sys_hw_t *hw)
2508 {
2509 return sys_ll_get_cpu_clk_div_mode1_clksel_uart0(hw);
2510 }
2511
2512 void sys_hal_set_cpu_clk_div_mode1_clksel_uart0(sys_hw_t *hw, uint32_t value)
2513 {
2514 sys_ll_set_cpu_clk_div_mode1_clksel_uart0(hw, value);
2515 }
2516
2517 /* REG_0x08:cpu_clk_div_mode1->clkdiv_uart1:Frequency division : 0:/1 1:/2 2:/4 3:/8,R/W,0x8[12:11]*/
2518 uint32_t sys_hal_get_cpu_clk_div_mode1_clkdiv_uart1(sys_hw_t *hw)
2519 {
2520 return sys_ll_get_cpu_clk_div_mode1_clkdiv_uart1(hw);
2521 }
2522
2523 void sys_hal_set_cpu_clk_div_mode1_clkdiv_uart1(sys_hw_t *hw, uint32_t value)
2524 {
2525 sys_ll_set_cpu_clk_div_mode1_clkdiv_uart1(hw, value);
2526 }
2527
2528 /* REG_0x08:cpu_clk_div_mode1->cksel_uart1:0:XTAL 1:APLL,R/W,0x8[13]*/
2529 uint32_t sys_hal_get_cpu_clk_div_mode1_cksel_uart1(sys_hw_t *hw)
2530 {
2531 return sys_ll_get_cpu_clk_div_mode1_cksel_uart1(hw);
2532 }
2533
2534 void sys_hal_set_cpu_clk_div_mode1_cksel_uart1(sys_hw_t *hw, uint32_t value)
2535 {
2536 sys_ll_set_cpu_clk_div_mode1_cksel_uart1(hw, value);
2537 }
2538
2539 /* REG_0x08:cpu_clk_div_mode1->clkdiv_uart2:Frequency division : 0:/1 1:/2 2:/4 3:/8,R/W,0x8[15:14]*/
2540 uint32_t sys_hal_get_cpu_clk_div_mode1_clkdiv_uart2(sys_hw_t *hw)
2541 {
2542 return sys_ll_get_cpu_clk_div_mode1_clkdiv_uart2(hw);
2543 }
2544
2545 void sys_hal_set_cpu_clk_div_mode1_clkdiv_uart2(sys_hw_t *hw, uint32_t value)
2546 {
2547 sys_ll_set_cpu_clk_div_mode1_clkdiv_uart2(hw, value);
2548 }
2549
2550 /* REG_0x08:cpu_clk_div_mode1->cksel_uart2:0:XTAL 1:APLL,R/W,0x8[16]*/
2551 uint32_t sys_hal_get_cpu_clk_div_mode1_cksel_uart2(sys_hw_t *hw)
2552 {
2553 return sys_ll_get_cpu_clk_div_mode1_cksel_uart2(hw);
2554 }
2555
2556 void sys_hal_set_cpu_clk_div_mode1_cksel_uart2(sys_hw_t *hw, uint32_t value)
2557 {
2558 sys_ll_set_cpu_clk_div_mode1_cksel_uart2(hw, value);
2559 }
2560
2561 /* REG_0x08:cpu_clk_div_mode1->cksel_sadc:0:XTAL 1:APLL,R/W,0x8[17]*/
2562 uint32_t sys_hal_get_cpu_clk_div_mode1_cksel_sadc(sys_hw_t *hw)
2563 {
2564 return sys_ll_get_cpu_clk_div_mode1_cksel_sadc(hw);
2565 }
2566
2567 void sys_hal_set_cpu_clk_div_mode1_cksel_sadc(sys_hw_t *hw, uint32_t value)
2568 {
2569 sys_ll_set_cpu_clk_div_mode1_cksel_sadc(hw, value);
2570 }
2571
2572 /* REG_0x08:cpu_clk_div_mode1->cksel_pwm0:0:clk32 1:XTAL,R/W,0x8[18]*/
2573 uint32_t sys_hal_get_cpu_clk_div_mode1_cksel_pwm0(sys_hw_t *hw)
2574 {
2575 return sys_ll_get_cpu_clk_div_mode1_cksel_pwm0(hw);
2576 }
2577
2578 void sys_hal_set_cpu_clk_div_mode1_cksel_pwm0(sys_hw_t *hw, uint32_t value)
2579 {
2580 sys_ll_set_cpu_clk_div_mode1_cksel_pwm0(hw, value);
2581 }
2582
2583 /* REG_0x08:cpu_clk_div_mode1->cksel_pwm1:0:clk32 1:XTAL,R/W,0x8[19]*/
2584 uint32_t sys_hal_get_cpu_clk_div_mode1_cksel_pwm1(sys_hw_t *hw)
2585 {
2586 return sys_ll_get_cpu_clk_div_mode1_cksel_pwm1(hw);
2587 }
2588
2589 void sys_hal_set_cpu_clk_div_mode1_cksel_pwm1(sys_hw_t *hw, uint32_t value)
2590 {
2591 sys_ll_set_cpu_clk_div_mode1_cksel_pwm1(hw, value);
2592 }
2593
2594 /* REG_0x08:cpu_clk_div_mode1->cksel_timer0:0:clk32 1:XTAL,R/W,0x8[20]*/
2595 uint32_t sys_hal_get_cpu_clk_div_mode1_cksel_timer0(sys_hw_t *hw)
2596 {
2597 return sys_ll_get_cpu_clk_div_mode1_cksel_timer0(hw);
2598 }
2599
2600 void sys_hal_set_cpu_clk_div_mode1_cksel_timer0(sys_hw_t *hw, uint32_t value)
2601 {
2602 sys_ll_set_cpu_clk_div_mode1_cksel_timer0(hw, value);
2603 }
2604
2605 /* REG_0x08:cpu_clk_div_mode1->cksel_timer1:0:clk32 1:XTAL,R/W,0x8[21]*/
2606 uint32_t sys_hal_get_cpu_clk_div_mode1_cksel_timer1(sys_hw_t *hw)
2607 {
2608 return sys_ll_get_cpu_clk_div_mode1_cksel_timer1(hw);
2609 }
2610
2611 void sys_hal_set_cpu_clk_div_mode1_cksel_timer1(sys_hw_t *hw, uint32_t value)
2612 {
2613 sys_ll_set_cpu_clk_div_mode1_cksel_timer1(hw, value);
2614 }
2615
2616 /* REG_0x08:cpu_clk_div_mode1->cksel_timer2:0:clk32 1:XTAL,R/W,0x8[22]*/
2617 uint32_t sys_hal_get_cpu_clk_div_mode1_cksel_timer2(sys_hw_t *hw)
2618 {
2619 return sys_ll_get_cpu_clk_div_mode1_cksel_timer2(hw);
2620 }
2621
2622 void sys_hal_set_cpu_clk_div_mode1_cksel_timer2(sys_hw_t *hw, uint32_t value)
2623 {
2624 sys_ll_set_cpu_clk_div_mode1_cksel_timer2(hw, value);
2625 }
2626
2627 /* REG_0x08:cpu_clk_div_mode1->cksel_i2s:0:XTAL 1:APLL,R/W,0x8[24]*/
2628 uint32_t sys_hal_get_cpu_clk_div_mode1_cksel_i2s(sys_hw_t *hw)
2629 {
2630 return sys_ll_get_cpu_clk_div_mode1_cksel_i2s(hw);
2631 }
2632
2633 void sys_hal_set_cpu_clk_div_mode1_cksel_i2s(sys_hw_t *hw, uint32_t value)
2634 {
2635 sys_ll_set_cpu_clk_div_mode1_cksel_i2s(hw, value);
2636 }
2637
2638 /* REG_0x08:cpu_clk_div_mode1->cksel_aud:0:XTAL 1:APLL,R/W,0x8[25]*/
2639 uint32_t sys_hal_get_cpu_clk_div_mode1_cksel_aud(sys_hw_t *hw)
2640 {
2641 return sys_ll_get_cpu_clk_div_mode1_cksel_aud(hw);
2642 }
2643
2644 void sys_hal_set_cpu_clk_div_mode1_cksel_aud(sys_hw_t *hw, uint32_t value)
2645 {
2646 sys_ll_set_cpu_clk_div_mode1_cksel_aud(hw, value);
2647 }
2648
2649 /* REG_0x08:cpu_clk_div_mode1->clkdiv_jpeg:Frequency division : F/(1+N), N is the data of the reg value,R/W,0x8[29:26]*/
2650 uint32_t sys_hal_get_cpu_clk_div_mode1_clkdiv_jpeg(sys_hw_t *hw)
2651 {
2652 return sys_ll_get_cpu_clk_div_mode1_clkdiv_jpeg(hw);
2653 }
2654
2655 void sys_hal_set_cpu_clk_div_mode1_clkdiv_jpeg(sys_hw_t *hw, uint32_t value)
2656 {
2657 sys_ll_set_cpu_clk_div_mode1_clkdiv_jpeg(hw, value);
2658 }
2659
2660 /* REG_0x08:cpu_clk_div_mode1->cksel_jpeg:0:clk_320M 1:clk_480M,R/W,0x8[30]*/
2661 uint32_t sys_hal_get_cpu_clk_div_mode1_cksel_jpeg(sys_hw_t *hw)
2662 {
2663 return sys_ll_get_cpu_clk_div_mode1_cksel_jpeg(hw);
2664 }
2665
2666 void sys_hal_set_cpu_clk_div_mode1_cksel_jpeg(sys_hw_t *hw, uint32_t value)
2667 {
2668 sys_ll_set_cpu_clk_div_mode1_cksel_jpeg(hw, value);
2669 }
2670
2671 /* REG_0x08:cpu_clk_div_mode1->clkdiv_disp_l:Frequency division : F/(1+clkdiv_disp_l+clkdiv_disp_h*2),R/W,0x8[31]*/
2672 uint32_t sys_hal_get_cpu_clk_div_mode1_clkdiv_disp_l(sys_hw_t *hw)
2673 {
2674 return sys_ll_get_cpu_clk_div_mode1_clkdiv_disp_l(hw);
2675 }
2676
2677 void sys_hal_set_cpu_clk_div_mode1_clkdiv_disp_l(sys_hw_t *hw, uint32_t value)
2678 {
2679 sys_ll_set_cpu_clk_div_mode1_clkdiv_disp_l(hw, value);
2680 }
2681
2682 /* REG_0x09 */
2683
2684 uint32_t sys_hal_get_cpu_clk_div_mode2_value(sys_hw_t *hw)
2685 {
2686 return sys_ll_get_cpu_clk_div_mode2_value(hw);
2687 }
2688
2689 void sys_hal_set_cpu_clk_div_mode2_value(sys_hw_t *hw, uint32_t value)
2690 {
2691 sys_ll_set_cpu_clk_div_mode2_value(hw, value);
2692 }
2693
2694 /* REG_0x09:cpu_clk_div_mode2->clkdiv_disp_h:Frequency division : F/(1+clkdiv_disp_l+clkdiv_disp_h*2),R/W,0x9[2:0]*/
2695 uint32_t sys_hal_get_cpu_clk_div_mode2_clkdiv_disp_h(sys_hw_t *hw)
2696 {
2697 return sys_ll_get_cpu_clk_div_mode2_clkdiv_disp_h(hw);
2698 }
2699
2700 void sys_hal_set_cpu_clk_div_mode2_clkdiv_disp_h(sys_hw_t *hw, uint32_t value)
2701 {
2702 sys_ll_set_cpu_clk_div_mode2_clkdiv_disp_h(hw, value);
2703 }
2704
2705 /* REG_0x09:cpu_clk_div_mode2->cksel_disp:0:clk_320M 1:clk_480M,R/W,0x9[3]*/
2706 uint32_t sys_hal_get_cpu_clk_div_mode2_cksel_disp(sys_hw_t *hw)
2707 {
2708 return sys_ll_get_cpu_clk_div_mode2_cksel_disp(hw);
2709 }
2710
2711 void sys_hal_set_cpu_clk_div_mode2_cksel_disp(sys_hw_t *hw, uint32_t value)
2712 {
2713 sys_ll_set_cpu_clk_div_mode2_cksel_disp(hw, value);
2714 }
2715
2716 /* REG_0x09:cpu_clk_div_mode2->ckdiv_psram:Frequency division : F/(1+N), N is the data of the reg value,R/W,0x9[4]*/
2717 uint32_t sys_hal_get_cpu_clk_div_mode2_ckdiv_psram(sys_hw_t *hw)
2718 {
2719 return sys_ll_get_cpu_clk_div_mode2_ckdiv_psram(hw);
2720 }
2721
2722 void sys_hal_set_cpu_clk_div_mode2_ckdiv_psram(sys_hw_t *hw, uint32_t value)
2723 {
2724 sys_ll_set_cpu_clk_div_mode2_ckdiv_psram(hw, value);
2725 }
2726
2727 /* REG_0x09:cpu_clk_div_mode2->cksel_psram:0:clk_320M 1:clk_480M,R/W,0x9[5]*/
2728 uint32_t sys_hal_get_cpu_clk_div_mode2_cksel_psram(sys_hw_t *hw)
2729 {
2730 return sys_ll_get_cpu_clk_div_mode2_cksel_psram(hw);
2731 }
2732
2733 void sys_hal_set_cpu_clk_div_mode2_cksel_psram(sys_hw_t *hw, uint32_t value)
2734 {
2735 sys_ll_set_cpu_clk_div_mode2_cksel_psram(hw, value);
2736 }
2737
2738 /* REG_0x09:cpu_clk_div_mode2->ckdiv_qspi0:Frequency division : F/(1+N), N is the data of the reg value,R/W,0x9[9:6]*/
2739 uint32_t sys_hal_get_cpu_clk_div_mode2_ckdiv_qspi0(sys_hw_t *hw)
2740 {
2741 return sys_ll_get_cpu_clk_div_mode2_ckdiv_qspi0(hw);
2742 }
2743
2744 void sys_hal_set_cpu_clk_div_mode2_ckdiv_qspi0(sys_hw_t *hw, uint32_t value)
2745 {
2746 sys_ll_set_cpu_clk_div_mode2_ckdiv_qspi0(hw, value);
2747 }
2748
2749 /* REG_0x09:cpu_clk_div_mode2->ckdiv_sdio:0:/1 1:/2 2:/4 3:/8 4:/16 5:/32 6:/64 7:/256,R/W,0x9[16:14]*/
2750 uint32_t sys_hal_get_cpu_clk_div_mode2_ckdiv_sdio(sys_hw_t *hw)
2751 {
2752 return sys_ll_get_cpu_clk_div_mode2_ckdiv_sdio(hw);
2753 }
2754
2755 void sys_hal_set_cpu_clk_div_mode2_ckdiv_sdio(sys_hw_t *hw, uint32_t value)
2756 {
2757 sys_ll_set_cpu_clk_div_mode2_ckdiv_sdio(hw, value);
2758 }
2759
2760 /* REG_0x09:cpu_clk_div_mode2->cksel_sdio:0：XTAL 1：320M,R/W,0x9[17]*/
2761 uint32_t sys_hal_get_cpu_clk_div_mode2_cksel_sdio(sys_hw_t *hw)
2762 {
2763 return sys_ll_get_cpu_clk_div_mode2_cksel_sdio(hw);
2764 }
2765
2766 void sys_hal_set_cpu_clk_div_mode2_cksel_sdio(sys_hw_t *hw, uint32_t value)
2767 {
2768 sys_ll_set_cpu_clk_div_mode2_cksel_sdio(hw, value);
2769 }
2770
2771 /* REG_0x09:cpu_clk_div_mode2->ckdiv_auxs:Frequency division : F/(1+N), N is the data of the reg value,R/W,0x9[21:18]*/
2772 uint32_t sys_hal_get_cpu_clk_div_mode2_ckdiv_auxs(sys_hw_t *hw)
2773 {
2774 return sys_ll_get_cpu_clk_div_mode2_ckdiv_auxs(hw);
2775 }
2776
2777 void sys_hal_set_cpu_clk_div_mode2_ckdiv_auxs(sys_hw_t *hw, uint32_t value)
2778 {
2779 sys_ll_set_cpu_clk_div_mode2_ckdiv_auxs(hw, value);
2780 }
2781
2782 /* REG_0x09:cpu_clk_div_mode2->cksel_auxs:0:DCO 1:APLL 2:320M 4:480M,R/W,0x9[23:22]*/
2783 uint32_t sys_hal_get_cpu_clk_div_mode2_cksel_auxs(sys_hw_t *hw)
2784 {
2785 return sys_ll_get_cpu_clk_div_mode2_cksel_auxs(hw);
2786 }
2787
2788 void sys_hal_set_cpu_clk_div_mode2_cksel_auxs(sys_hw_t *hw, uint32_t value)
2789 {
2790 sys_ll_set_cpu_clk_div_mode2_cksel_auxs(hw, value);
2791 }
2792
2793 /* REG_0x09:cpu_clk_div_mode2->cksel_flash:0:XTAL 1:APLL 1x :clk_120M,R/W,0x9[25:24]*/
2794 uint32_t sys_hal_get_cpu_clk_div_mode2_cksel_flash(sys_hw_t *hw)
2795 {
2796 return sys_ll_get_cpu_clk_div_mode2_cksel_flash(hw);
2797 }
2798
2799 void sys_hal_set_cpu_clk_div_mode2_cksel_flash(sys_hw_t *hw, uint32_t value)
2800 {
2801 sys_ll_set_cpu_clk_div_mode2_cksel_flash(hw, value);
2802 }
2803
2804 /* REG_0x09:cpu_clk_div_mode2->ckdiv_flash:0:/1 1:/2 2:/4 3:/8,R/W,0x9[27:26]*/
2805 uint32_t sys_hal_get_cpu_clk_div_mode2_ckdiv_flash(sys_hw_t *hw)
2806 {
2807 return sys_ll_get_cpu_clk_div_mode2_ckdiv_flash(hw);
2808 }
2809
2810 void sys_hal_set_cpu_clk_div_mode2_ckdiv_flash(sys_hw_t *hw, uint32_t value)
2811 {
2812 sys_ll_set_cpu_clk_div_mode2_ckdiv_flash(hw, value);
2813 }
2814
2815 /* REG_0x09:cpu_clk_div_mode2->ckdiv_i2s0:0:/1 1:/2 2:/4 3:/8 4:/16 5:/32 6:/64 7:/256,R/W,0x9[30:28]*/
2816 uint32_t sys_hal_get_cpu_clk_div_mode2_ckdiv_i2s0(sys_hw_t *hw)
2817 {
2818 return sys_ll_get_cpu_clk_div_mode2_ckdiv_i2s0(hw);
2819 }
2820
2821 void sys_hal_set_cpu_clk_div_mode2_ckdiv_i2s0(sys_hw_t *hw, uint32_t value)
2822 {
2823 sys_ll_set_cpu_clk_div_mode2_ckdiv_i2s0(hw, value);
2824 }
2825
2826 /* REG_0x0a */
2827
2828 uint32_t sys_hal_get_cpu_26m_wdt_clk_div_value(sys_hw_t *hw)
2829 {
2830 return sys_ll_get_cpu_26m_wdt_clk_div_value(hw);
2831 }
2832
2833 void sys_hal_set_cpu_26m_wdt_clk_div_value(sys_hw_t *hw, uint32_t value)
2834 {
2835 sys_ll_set_cpu_26m_wdt_clk_div_value(hw, value);
2836 }
2837
2838 /* REG_0x0a:cpu_26m_wdt_clk_div->ckdiv_26m:0:/1 1:/2 2:/4 3:/8,R/W,0xa[1:0]*/
2839 uint32_t sys_hal_get_cpu_26m_wdt_clk_div_ckdiv_26m(sys_hw_t *hw)
2840 {
2841 return sys_ll_get_cpu_26m_wdt_clk_div_ckdiv_26m(hw);
2842 }
2843
2844 void sys_hal_set_cpu_26m_wdt_clk_div_ckdiv_26m(sys_hw_t *hw, uint32_t value)
2845 {
2846 sys_ll_set_cpu_26m_wdt_clk_div_ckdiv_26m(hw, value);
2847 }
2848
2849 /* REG_0x0a:cpu_26m_wdt_clk_div->ckdiv_wdt:0:/2 1:/4 2:/8 3:/16,R/W,0xa[3:2]*/
2850 uint32_t sys_hal_get_cpu_26m_wdt_clk_div_ckdiv_wdt(sys_hw_t *hw)
2851 {
2852 return sys_ll_get_cpu_26m_wdt_clk_div_ckdiv_wdt(hw);
2853 }
2854
2855 void sys_hal_set_cpu_26m_wdt_clk_div_ckdiv_wdt(sys_hw_t *hw, uint32_t value)
2856 {
2857 sys_ll_set_cpu_26m_wdt_clk_div_ckdiv_wdt(hw, value);
2858 }
2859
2860 /* REG_0x0b */
2861
2862 uint32_t sys_hal_get_cpu_anaspi_freq_value(sys_hw_t *hw)
2863 {
2864 return sys_ll_get_cpu_anaspi_freq_value(hw);
2865 }
2866
2867 void sys_hal_set_cpu_anaspi_freq_value(sys_hw_t *hw, uint32_t value)
2868 {
2869 sys_ll_set_cpu_anaspi_freq_value(hw, value);
2870 }
2871
2872 /* REG_0x0b:cpu_anaspi_freq->anaspi_freq: ,R/W,0xb[5:0]*/
2873 uint32_t sys_hal_get_cpu_anaspi_freq_anaspi_freq(sys_hw_t *hw)
2874 {
2875 return sys_ll_get_cpu_anaspi_freq_anaspi_freq(hw);
2876 }
2877
2878 void sys_hal_set_cpu_anaspi_freq_anaspi_freq(sys_hw_t *hw, uint32_t value)
2879 {
2880 sys_ll_set_cpu_anaspi_freq_anaspi_freq(hw, value);
2881 }
2882
2883 /* REG_0x0c */
2884
2885 uint32_t sys_hal_get_cpu_device_clk_enable_value(sys_hw_t *hw)
2886 {
2887 return sys_ll_get_cpu_device_clk_enable_value(hw);
2888 }
2889
2890 void sys_hal_set_cpu_device_clk_enable_value(sys_hw_t *hw, uint32_t value)
2891 {
2892 sys_ll_set_cpu_device_clk_enable_value(hw, value);
2893 }
2894
2895 /* REG_0x0c:cpu_device_clk_enable->i2c0_cken:1:i2c0_clk enable,R/W,0xc[0]*/
2896 uint32_t sys_hal_get_cpu_device_clk_enable_i2c0_cken(sys_hw_t *hw)
2897 {
2898 return sys_ll_get_cpu_device_clk_enable_i2c0_cken(hw);
2899 }
2900
2901 void sys_hal_set_cpu_device_clk_enable_i2c0_cken(sys_hw_t *hw, uint32_t value)
2902 {
2903 sys_ll_set_cpu_device_clk_enable_i2c0_cken(hw, value);
2904 }
2905
2906 /* REG_0x0c:cpu_device_clk_enable->spi0_cken:1:spi0_clk enable ,R/W,0xc[1]*/
2907 uint32_t sys_hal_get_cpu_device_clk_enable_spi0_cken(sys_hw_t *hw)
2908 {
2909 return sys_ll_get_cpu_device_clk_enable_spi0_cken(hw);
2910 }
2911
2912 void sys_hal_set_cpu_device_clk_enable_spi0_cken(sys_hw_t *hw, uint32_t value)
2913 {
2914 sys_ll_set_cpu_device_clk_enable_spi0_cken(hw, value);
2915 }
2916
2917 /* REG_0x0c:cpu_device_clk_enable->uart0_cken:1:uart0_clk enable,R/W,0xc[2]*/
2918 uint32_t sys_hal_get_cpu_device_clk_enable_uart0_cken(sys_hw_t *hw)
2919 {
2920 return sys_ll_get_cpu_device_clk_enable_uart0_cken(hw);
2921 }
2922
2923 void sys_hal_set_cpu_device_clk_enable_uart0_cken(sys_hw_t *hw, uint32_t value)
2924 {
2925 sys_ll_set_cpu_device_clk_enable_uart0_cken(hw, value);
2926 }
2927
2928 /* REG_0x0c:cpu_device_clk_enable->pwm0_cken:1:pwm0_clk enable ,R/W,0xc[3]*/
2929 uint32_t sys_hal_get_cpu_device_clk_enable_pwm0_cken(sys_hw_t *hw)
2930 {
2931 return sys_ll_get_cpu_device_clk_enable_pwm0_cken(hw);
2932 }
2933
2934 void sys_hal_set_cpu_device_clk_enable_pwm0_cken(sys_hw_t *hw, uint32_t value)
2935 {
2936 sys_ll_set_cpu_device_clk_enable_pwm0_cken(hw, value);
2937 }
2938
2939 /* REG_0x0c:cpu_device_clk_enable->tim0_cken:1:tim0_clk enable ,R/W,0xc[4]*/
2940 uint32_t sys_hal_get_cpu_device_clk_enable_tim0_cken(sys_hw_t *hw)
2941 {
2942 return sys_ll_get_cpu_device_clk_enable_tim0_cken(hw);
2943 }
2944
2945 void sys_hal_set_cpu_device_clk_enable_tim0_cken(sys_hw_t *hw, uint32_t value)
2946 {
2947 sys_ll_set_cpu_device_clk_enable_tim0_cken(hw, value);
2948 }
2949
2950 /* REG_0x0c:cpu_device_clk_enable->sadc_cken:1:sadc_clk enable ,R/W,0xc[5]*/
2951 uint32_t sys_hal_get_cpu_device_clk_enable_sadc_cken(sys_hw_t *hw)
2952 {
2953 return sys_ll_get_cpu_device_clk_enable_sadc_cken(hw);
2954 }
2955
2956 void sys_hal_set_cpu_device_clk_enable_sadc_cken(sys_hw_t *hw, uint32_t value)
2957 {
2958 sys_ll_set_cpu_device_clk_enable_sadc_cken(hw, value);
2959 }
2960
2961 /* REG_0x0c:cpu_device_clk_enable->irda_cken:1:irda_clk enable ,R/W,0xc[6]*/
2962 uint32_t sys_hal_get_cpu_device_clk_enable_irda_cken(sys_hw_t *hw)
2963 {
2964 return sys_ll_get_cpu_device_clk_enable_irda_cken(hw);
2965 }
2966
2967 void sys_hal_set_cpu_device_clk_enable_irda_cken(sys_hw_t *hw, uint32_t value)
2968 {
2969 sys_ll_set_cpu_device_clk_enable_irda_cken(hw, value);
2970 }
2971
2972 /* REG_0x0c:cpu_device_clk_enable->efuse_cken:1:efuse_clk enable,R/W,0xc[7]*/
2973 uint32_t sys_hal_get_cpu_device_clk_enable_efuse_cken(sys_hw_t *hw)
2974 {
2975 return sys_ll_get_cpu_device_clk_enable_efuse_cken(hw);
2976 }
2977
2978 void sys_hal_set_cpu_device_clk_enable_efuse_cken(sys_hw_t *hw, uint32_t value)
2979 {
2980 sys_ll_set_cpu_device_clk_enable_efuse_cken(hw, value);
2981 }
2982
2983 /* REG_0x0c:cpu_device_clk_enable->i2c1_cken:1:i2c1_clk enable ,R/W,0xc[8]*/
2984 uint32_t sys_hal_get_cpu_device_clk_enable_i2c1_cken(sys_hw_t *hw)
2985 {
2986 return sys_ll_get_cpu_device_clk_enable_i2c1_cken(hw);
2987 }
2988
2989 void sys_hal_set_cpu_device_clk_enable_i2c1_cken(sys_hw_t *hw, uint32_t value)
2990 {
2991 sys_ll_set_cpu_device_clk_enable_i2c1_cken(hw, value);
2992 }
2993
2994 /* REG_0x0c:cpu_device_clk_enable->spi1_cken:1:spi1_clk enable ,R/W,0xc[9]*/
2995 uint32_t sys_hal_get_cpu_device_clk_enable_spi1_cken(sys_hw_t *hw)
2996 {
2997 return sys_ll_get_cpu_device_clk_enable_spi1_cken(hw);
2998 }
2999
3000 void sys_hal_set_cpu_device_clk_enable_spi1_cken(sys_hw_t *hw, uint32_t value)
3001 {
3002 sys_ll_set_cpu_device_clk_enable_spi1_cken(hw, value);
3003 }
3004
3005 /* REG_0x0c:cpu_device_clk_enable->uart1_cken:1:uart1_clk enable,R/W,0xc[10]*/
3006 uint32_t sys_hal_get_cpu_device_clk_enable_uart1_cken(sys_hw_t *hw)
3007 {
3008 return sys_ll_get_cpu_device_clk_enable_uart1_cken(hw);
3009 }
3010
3011 void sys_hal_set_cpu_device_clk_enable_uart1_cken(sys_hw_t *hw, uint32_t value)
3012 {
3013 sys_ll_set_cpu_device_clk_enable_uart1_cken(hw, value);
3014 }
3015
3016 /* REG_0x0c:cpu_device_clk_enable->uart2_cken:1:uart2_clk enable,R/W,0xc[11]*/
3017 uint32_t sys_hal_get_cpu_device_clk_enable_uart2_cken(sys_hw_t *hw)
3018 {
3019 return sys_ll_get_cpu_device_clk_enable_uart2_cken(hw);
3020 }
3021
3022 void sys_hal_set_cpu_device_clk_enable_uart2_cken(sys_hw_t *hw, uint32_t value)
3023 {
3024 sys_ll_set_cpu_device_clk_enable_uart2_cken(hw, value);
3025 }
3026
3027 /* REG_0x0c:cpu_device_clk_enable->pwm1_cken:1:pwm1_clk enable ,R/W,0xc[12]*/
3028 uint32_t sys_hal_get_cpu_device_clk_enable_pwm1_cken(sys_hw_t *hw)
3029 {
3030 return sys_ll_get_cpu_device_clk_enable_pwm1_cken(hw);
3031 }
3032
3033 void sys_hal_set_cpu_device_clk_enable_pwm1_cken(sys_hw_t *hw, uint32_t value)
3034 {
3035 sys_ll_set_cpu_device_clk_enable_pwm1_cken(hw, value);
3036 }
3037
3038 /* REG_0x0c:cpu_device_clk_enable->tim1_cken:1:tim1_clk enable ,R/W,0xc[13]*/
3039 uint32_t sys_hal_get_cpu_device_clk_enable_tim1_cken(sys_hw_t *hw)
3040 {
3041 return sys_ll_get_cpu_device_clk_enable_tim1_cken(hw);
3042 }
3043
3044 void sys_hal_set_cpu_device_clk_enable_tim1_cken(sys_hw_t *hw, uint32_t value)
3045 {
3046 sys_ll_set_cpu_device_clk_enable_tim1_cken(hw, value);
3047 }
3048
3049 /* REG_0x0c:cpu_device_clk_enable->tim2_cken:1:tim2_clk enable ,R/W,0xc[14]*/
3050 uint32_t sys_hal_get_cpu_device_clk_enable_tim2_cken(sys_hw_t *hw)
3051 {
3052 return sys_ll_get_cpu_device_clk_enable_tim2_cken(hw);
3053 }
3054
3055 void sys_hal_set_cpu_device_clk_enable_tim2_cken(sys_hw_t *hw, uint32_t value)
3056 {
3057 sys_ll_set_cpu_device_clk_enable_tim2_cken(hw, value);
3058 }
3059
3060 /* REG_0x0c:cpu_device_clk_enable->otp_cken:1:otp_clk enable ,R/W,0xc[15]*/
3061 uint32_t sys_hal_get_cpu_device_clk_enable_otp_cken(sys_hw_t *hw)
3062 {
3063 return sys_ll_get_cpu_device_clk_enable_otp_cken(hw);
3064 }
3065
3066 void sys_hal_set_cpu_device_clk_enable_otp_cken(sys_hw_t *hw, uint32_t value)
3067 {
3068 sys_ll_set_cpu_device_clk_enable_otp_cken(hw, value);
3069 }
3070
3071 /* REG_0x0c:cpu_device_clk_enable->i2s_cken:1:i2s_clk enable ,R/W,0xc[16]*/
3072 uint32_t sys_hal_get_cpu_device_clk_enable_i2s_cken(sys_hw_t *hw)
3073 {
3074 return sys_ll_get_cpu_device_clk_enable_i2s_cken(hw);
3075 }
3076
3077 void sys_hal_set_cpu_device_clk_enable_i2s_cken(sys_hw_t *hw, uint32_t value)
3078 {
3079 sys_ll_set_cpu_device_clk_enable_i2s_cken(hw, value);
3080 }
3081
3082 /* REG_0x0c:cpu_device_clk_enable->usb_cken:1:usb_clk enable ,R/W,0xc[17]*/
3083 uint32_t sys_hal_get_cpu_device_clk_enable_usb_cken(sys_hw_t *hw)
3084 {
3085 return sys_ll_get_cpu_device_clk_enable_usb_cken(hw);
3086 }
3087
3088 void sys_hal_set_cpu_device_clk_enable_usb_cken(sys_hw_t *hw, uint32_t value)
3089 {
3090 sys_ll_set_cpu_device_clk_enable_usb_cken(hw, value);
3091 }
3092
3093 /* REG_0x0c:cpu_device_clk_enable->can_cken:1:can_clk enable ,R/W,0xc[18]*/
3094 uint32_t sys_hal_get_cpu_device_clk_enable_can_cken(sys_hw_t *hw)
3095 {
3096 return sys_ll_get_cpu_device_clk_enable_can_cken(hw);
3097 }
3098
3099 void sys_hal_set_cpu_device_clk_enable_can_cken(sys_hw_t *hw, uint32_t value)
3100 {
3101 sys_ll_set_cpu_device_clk_enable_can_cken(hw, value);
3102 }
3103
3104 /* REG_0x0c:cpu_device_clk_enable->psram_cken:1:psram_clk enable,R/W,0xc[19]*/
3105 uint32_t sys_hal_get_cpu_device_clk_enable_psram_cken(sys_hw_t *hw)
3106 {
3107 return sys_ll_get_cpu_device_clk_enable_psram_cken(hw);
3108 }
3109
3110 void sys_hal_set_cpu_device_clk_enable_psram_cken(sys_hw_t *hw, uint32_t value)
3111 {
3112 sys_ll_set_cpu_device_clk_enable_psram_cken(hw, value);
3113 }
3114
3115 /* REG_0x0c:cpu_device_clk_enable->qspi0_cken:1:qspi0_clk enable,R/W,0xc[20]*/
3116 uint32_t sys_hal_get_cpu_device_clk_enable_qspi0_cken(sys_hw_t *hw)
3117 {
3118 return sys_ll_get_cpu_device_clk_enable_qspi0_cken(hw);
3119 }
3120
3121 void sys_hal_set_cpu_device_clk_enable_qspi0_cken(sys_hw_t *hw, uint32_t value)
3122 {
3123 sys_ll_set_cpu_device_clk_enable_qspi0_cken(hw, value);
3124 }
3125
3126 /* REG_0x0c:cpu_device_clk_enable->qspi1_cken:1:qspi1_clk enable,R/W,0xc[21]*/
3127 uint32_t sys_hal_get_cpu_device_clk_enable_qspi1_cken(sys_hw_t *hw)
3128 {
3129 return sys_ll_get_cpu_device_clk_enable_qspi1_cken(hw);
3130 }
3131
3132 void sys_hal_set_cpu_device_clk_enable_qspi1_cken(sys_hw_t *hw, uint32_t value)
3133 {
3134 sys_ll_set_cpu_device_clk_enable_qspi1_cken(hw, value);
3135 }
3136
3137 /* REG_0x0c:cpu_device_clk_enable->sdio_cken:1:sdio_clk enable ,R/W,0xc[22]*/
3138 uint32_t sys_hal_get_cpu_device_clk_enable_sdio_cken(sys_hw_t *hw)
3139 {
3140 return sys_ll_get_cpu_device_clk_enable_sdio_cken(hw);
3141 }
3142
3143 void sys_hal_set_cpu_device_clk_enable_sdio_cken(sys_hw_t *hw, uint32_t value)
3144 {
3145 sys_ll_set_cpu_device_clk_enable_sdio_cken(hw, value);
3146 }
3147
3148 /* REG_0x0c:cpu_device_clk_enable->auxs_cken:1:auxs_clk enable ,R/W,0xc[23]*/
3149 uint32_t sys_hal_get_cpu_device_clk_enable_auxs_cken(sys_hw_t *hw)
3150 {
3151 return sys_ll_get_cpu_device_clk_enable_auxs_cken(hw);
3152 }
3153
3154 void sys_hal_set_cpu_device_clk_enable_auxs_cken(sys_hw_t *hw, uint32_t value)
3155 {
3156 sys_ll_set_cpu_device_clk_enable_auxs_cken(hw, value);
3157 }
3158
3159 /* REG_0x0c:cpu_device_clk_enable->btdm_cken:1:btdm_clk enable ,R/W,0xc[24]*/
3160 uint32_t sys_hal_get_cpu_device_clk_enable_btdm_cken(sys_hw_t *hw)
3161 {
3162 return sys_ll_get_cpu_device_clk_enable_btdm_cken(hw);
3163 }
3164
3165 void sys_hal_set_cpu_device_clk_enable_btdm_cken(sys_hw_t *hw, uint32_t value)
3166 {
3167 sys_ll_set_cpu_device_clk_enable_btdm_cken(hw, value);
3168 }
3169
3170 /* REG_0x0c:cpu_device_clk_enable->xvr_cken:1:xvr_clk enable ,R/W,0xc[25]*/
3171 uint32_t sys_hal_get_cpu_device_clk_enable_xvr_cken(sys_hw_t *hw)
3172 {
3173 return sys_ll_get_cpu_device_clk_enable_xvr_cken(hw);
3174 }
3175
3176 void sys_hal_set_cpu_device_clk_enable_xvr_cken(sys_hw_t *hw, uint32_t value)
3177 {
3178 sys_ll_set_cpu_device_clk_enable_xvr_cken(hw, value);
3179 }
3180
3181 /* REG_0x0c:cpu_device_clk_enable->mac_cken:1:mac_clk enable ,R/W,0xc[26]*/
3182 uint32_t sys_hal_get_cpu_device_clk_enable_mac_cken(sys_hw_t *hw)
3183 {
3184 return sys_ll_get_cpu_device_clk_enable_mac_cken(hw);
3185 }
3186
3187 void sys_hal_set_cpu_device_clk_enable_mac_cken(sys_hw_t *hw, uint32_t value)
3188 {
3189 sys_ll_set_cpu_device_clk_enable_mac_cken(hw, value);
3190 }
3191
3192 /* REG_0x0c:cpu_device_clk_enable->phy_cken:1:phy_clk enable ,R/W,0xc[27]*/
3193 uint32_t sys_hal_get_cpu_device_clk_enable_phy_cken(sys_hw_t *hw)
3194 {
3195 return sys_ll_get_cpu_device_clk_enable_phy_cken(hw);
3196 }
3197
3198 void sys_hal_set_cpu_device_clk_enable_phy_cken(sys_hw_t *hw, uint32_t value)
3199 {
3200 sys_ll_set_cpu_device_clk_enable_phy_cken(hw, value);
3201 }
3202
3203 /* REG_0x0c:cpu_device_clk_enable->jpeg_cken:1:jpeg_clk enable ,R/W,0xc[28]*/
3204 uint32_t sys_hal_get_cpu_device_clk_enable_jpeg_cken(sys_hw_t *hw)
3205 {
3206 return sys_ll_get_cpu_device_clk_enable_jpeg_cken(hw);
3207 }
3208
3209 void sys_hal_set_cpu_device_clk_enable_jpeg_cken(sys_hw_t *hw, uint32_t value)
3210 {
3211 sys_ll_set_cpu_device_clk_enable_jpeg_cken(hw, value);
3212 }
3213
3214 /* REG_0x0c:cpu_device_clk_enable->disp_cken:1:disp_clk enable ,R/W,0xc[29]*/
3215 uint32_t sys_hal_get_cpu_device_clk_enable_disp_cken(sys_hw_t *hw)
3216 {
3217 return sys_ll_get_cpu_device_clk_enable_disp_cken(hw);
3218 }
3219
3220 void sys_hal_set_cpu_device_clk_enable_disp_cken(sys_hw_t *hw, uint32_t value)
3221 {
3222 sys_ll_set_cpu_device_clk_enable_disp_cken(hw, value);
3223 }
3224
3225 /* REG_0x0c:cpu_device_clk_enable->aud_cken:1:aud_clk enable ,R/W,0xc[30]*/
3226 uint32_t sys_hal_get_cpu_device_clk_enable_aud_cken(sys_hw_t *hw)
3227 {
3228 return sys_ll_get_cpu_device_clk_enable_aud_cken(hw);
3229 }
3230
3231 void sys_hal_set_cpu_device_clk_enable_aud_cken(sys_hw_t *hw, uint32_t value)
3232 {
3233 sys_ll_set_cpu_device_clk_enable_aud_cken(hw, value);
3234 }
3235
3236 /* REG_0x0c:cpu_device_clk_enable->wdt_cken:1:wdt_clk enable ,R/W,0xc[31]*/
3237 uint32_t sys_hal_get_cpu_device_clk_enable_wdt_cken(sys_hw_t *hw)
3238 {
3239 return sys_ll_get_cpu_device_clk_enable_wdt_cken(hw);
3240 }
3241
3242 void sys_hal_set_cpu_device_clk_enable_wdt_cken(sys_hw_t *hw, uint32_t value)
3243 {
3244 sys_ll_set_cpu_device_clk_enable_wdt_cken(hw, value);
3245 }
3246
3247 /* REG_0x0d */
3248
3249 /* REG_0x0e */
3250
3251 uint32_t sys_hal_get_cpu_mode_disckg1_value(sys_hw_t *hw)
3252 {
3253 return sys_ll_get_cpu_mode_disckg1_value(hw);
3254 }
3255
3256 void sys_hal_set_cpu_mode_disckg1_value(sys_hw_t *hw, uint32_t value)
3257 {
3258 sys_ll_set_cpu_mode_disckg1_value(hw, value);
3259 }
3260
3261 /* REG_0x0e:cpu_mode_disckg1->aon_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[0]*/
3262 uint32_t sys_hal_get_cpu_mode_disckg1_aon_disckg(sys_hw_t *hw)
3263 {
3264 return sys_ll_get_cpu_mode_disckg1_aon_disckg(hw);
3265 }
3266
3267 void sys_hal_set_cpu_mode_disckg1_aon_disckg(sys_hw_t *hw, uint32_t value)
3268 {
3269 sys_ll_set_cpu_mode_disckg1_aon_disckg(hw, value);
3270 }
3271
3272 /* REG_0x0e:cpu_mode_disckg1->sys_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[1]*/
3273 uint32_t sys_hal_get_cpu_mode_disckg1_sys_disckg(sys_hw_t *hw)
3274 {
3275 return sys_ll_get_cpu_mode_disckg1_sys_disckg(hw);
3276 }
3277
3278 void sys_hal_set_cpu_mode_disckg1_sys_disckg(sys_hw_t *hw, uint32_t value)
3279 {
3280 sys_ll_set_cpu_mode_disckg1_sys_disckg(hw, value);
3281 }
3282
3283 /* REG_0x0e:cpu_mode_disckg1->dma_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[2]*/
3284 uint32_t sys_hal_get_cpu_mode_disckg1_dma_disckg(sys_hw_t *hw)
3285 {
3286 return sys_ll_get_cpu_mode_disckg1_dma_disckg(hw);
3287 }
3288
3289 void sys_hal_set_cpu_mode_disckg1_dma_disckg(sys_hw_t *hw, uint32_t value)
3290 {
3291 sys_ll_set_cpu_mode_disckg1_dma_disckg(hw, value);
3292 }
3293
3294 /* REG_0x0e:cpu_mode_disckg1->flash_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[3]*/
3295 uint32_t sys_hal_get_cpu_mode_disckg1_flash_disckg(sys_hw_t *hw)
3296 {
3297 return sys_ll_get_cpu_mode_disckg1_flash_disckg(hw);
3298 }
3299
3300 void sys_hal_set_cpu_mode_disckg1_flash_disckg(sys_hw_t *hw, uint32_t value)
3301 {
3302 sys_ll_set_cpu_mode_disckg1_flash_disckg(hw, value);
3303 }
3304
3305 /* REG_0x0e:cpu_mode_disckg1->wdt_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[4]*/
3306 uint32_t sys_hal_get_cpu_mode_disckg1_wdt_disckg(sys_hw_t *hw)
3307 {
3308 return sys_ll_get_cpu_mode_disckg1_wdt_disckg(hw);
3309 }
3310
3311 void sys_hal_set_cpu_mode_disckg1_wdt_disckg(sys_hw_t *hw, uint32_t value)
3312 {
3313 sys_ll_set_cpu_mode_disckg1_wdt_disckg(hw, value);
3314 }
3315
3316 /* REG_0x0e:cpu_mode_disckg1->tim_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[5]*/
3317 uint32_t sys_hal_get_cpu_mode_disckg1_tim_disckg(sys_hw_t *hw)
3318 {
3319 return sys_ll_get_cpu_mode_disckg1_tim_disckg(hw);
3320 }
3321
3322 void sys_hal_set_cpu_mode_disckg1_tim_disckg(sys_hw_t *hw, uint32_t value)
3323 {
3324 sys_ll_set_cpu_mode_disckg1_tim_disckg(hw, value);
3325 }
3326
3327 /* REG_0x0e:cpu_mode_disckg1->urt_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[6]*/
3328 uint32_t sys_hal_get_cpu_mode_disckg1_urt_disckg(sys_hw_t *hw)
3329 {
3330 return sys_ll_get_cpu_mode_disckg1_urt_disckg(hw);
3331 }
3332
3333 void sys_hal_set_cpu_mode_disckg1_urt_disckg(sys_hw_t *hw, uint32_t value)
3334 {
3335 sys_ll_set_cpu_mode_disckg1_urt_disckg(hw, value);
3336 }
3337
3338 /* REG_0x0e:cpu_mode_disckg1->pwm_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[7]*/
3339 uint32_t sys_hal_get_cpu_mode_disckg1_pwm_disckg(sys_hw_t *hw)
3340 {
3341 return sys_ll_get_cpu_mode_disckg1_pwm_disckg(hw);
3342 }
3343
3344 void sys_hal_set_cpu_mode_disckg1_pwm_disckg(sys_hw_t *hw, uint32_t value)
3345 {
3346 sys_ll_set_cpu_mode_disckg1_pwm_disckg(hw, value);
3347 }
3348
3349 /* REG_0x0e:cpu_mode_disckg1->i2c_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[8]*/
3350 uint32_t sys_hal_get_cpu_mode_disckg1_i2c_disckg(sys_hw_t *hw)
3351 {
3352 return sys_ll_get_cpu_mode_disckg1_i2c_disckg(hw);
3353 }
3354
3355 void sys_hal_set_cpu_mode_disckg1_i2c_disckg(sys_hw_t *hw, uint32_t value)
3356 {
3357 sys_ll_set_cpu_mode_disckg1_i2c_disckg(hw, value);
3358 }
3359
3360 /* REG_0x0e:cpu_mode_disckg1->spi_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[9]*/
3361 uint32_t sys_hal_get_cpu_mode_disckg1_spi_disckg(sys_hw_t *hw)
3362 {
3363 return sys_ll_get_cpu_mode_disckg1_spi_disckg(hw);
3364 }
3365
3366 void sys_hal_set_cpu_mode_disckg1_spi_disckg(sys_hw_t *hw, uint32_t value)
3367 {
3368 sys_ll_set_cpu_mode_disckg1_spi_disckg(hw, value);
3369 }
3370
3371 /* REG_0x0e:cpu_mode_disckg1->sadc_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[10]*/
3372 uint32_t sys_hal_get_cpu_mode_disckg1_sadc_disckg(sys_hw_t *hw)
3373 {
3374 return sys_ll_get_cpu_mode_disckg1_sadc_disckg(hw);
3375 }
3376
3377 void sys_hal_set_cpu_mode_disckg1_sadc_disckg(sys_hw_t *hw, uint32_t value)
3378 {
3379 sys_ll_set_cpu_mode_disckg1_sadc_disckg(hw, value);
3380 }
3381
3382 /* REG_0x0e:cpu_mode_disckg1->efs_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[11]*/
3383 uint32_t sys_hal_get_cpu_mode_disckg1_efs_disckg(sys_hw_t *hw)
3384 {
3385 return sys_ll_get_cpu_mode_disckg1_efs_disckg(hw);
3386 }
3387
3388 void sys_hal_set_cpu_mode_disckg1_efs_disckg(sys_hw_t *hw, uint32_t value)
3389 {
3390 sys_ll_set_cpu_mode_disckg1_efs_disckg(hw, value);
3391 }
3392
3393 /* REG_0x0e:cpu_mode_disckg1->irda_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[12]*/
3394 uint32_t sys_hal_get_cpu_mode_disckg1_irda_disckg(sys_hw_t *hw)
3395 {
3396 return sys_ll_get_cpu_mode_disckg1_irda_disckg(hw);
3397 }
3398
3399 void sys_hal_set_cpu_mode_disckg1_irda_disckg(sys_hw_t *hw, uint32_t value)
3400 {
3401 sys_ll_set_cpu_mode_disckg1_irda_disckg(hw, value);
3402 }
3403
3404 /* REG_0x0e:cpu_mode_disckg1->trng_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[13]*/
3405 uint32_t sys_hal_get_cpu_mode_disckg1_trng_disckg(sys_hw_t *hw)
3406 {
3407 return sys_ll_get_cpu_mode_disckg1_trng_disckg(hw);
3408 }
3409
3410 void sys_hal_set_cpu_mode_disckg1_trng_disckg(sys_hw_t *hw, uint32_t value)
3411 {
3412 sys_ll_set_cpu_mode_disckg1_trng_disckg(hw, value);
3413 }
3414
3415 /* REG_0x0e:cpu_mode_disckg1->sdio_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[14]*/
3416 uint32_t sys_hal_get_cpu_mode_disckg1_sdio_disckg(sys_hw_t *hw)
3417 {
3418 return sys_ll_get_cpu_mode_disckg1_sdio_disckg(hw);
3419 }
3420
3421 void sys_hal_set_cpu_mode_disckg1_sdio_disckg(sys_hw_t *hw, uint32_t value)
3422 {
3423 sys_ll_set_cpu_mode_disckg1_sdio_disckg(hw, value);
3424 }
3425
3426 /* REG_0x0e:cpu_mode_disckg1->LA_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[15]*/
3427 uint32_t sys_hal_get_cpu_mode_disckg1_la_disckg(sys_hw_t *hw)
3428 {
3429 return sys_ll_get_cpu_mode_disckg1_la_disckg(hw);
3430 }
3431
3432 void sys_hal_set_cpu_mode_disckg1_la_disckg(sys_hw_t *hw, uint32_t value)
3433 {
3434 sys_ll_set_cpu_mode_disckg1_la_disckg(hw, value);
3435 }
3436
3437 /* REG_0x0e:cpu_mode_disckg1->tim1_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[16]*/
3438 uint32_t sys_hal_get_cpu_mode_disckg1_tim1_disckg(sys_hw_t *hw)
3439 {
3440 return sys_ll_get_cpu_mode_disckg1_tim1_disckg(hw);
3441 }
3442
3443 void sys_hal_set_cpu_mode_disckg1_tim1_disckg(sys_hw_t *hw, uint32_t value)
3444 {
3445 sys_ll_set_cpu_mode_disckg1_tim1_disckg(hw, value);
3446 }
3447
3448 /* REG_0x0e:cpu_mode_disckg1->urt1_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[17]*/
3449 uint32_t sys_hal_get_cpu_mode_disckg1_urt1_disckg(sys_hw_t *hw)
3450 {
3451 return sys_ll_get_cpu_mode_disckg1_urt1_disckg(hw);
3452 }
3453
3454 void sys_hal_set_cpu_mode_disckg1_urt1_disckg(sys_hw_t *hw, uint32_t value)
3455 {
3456 sys_ll_set_cpu_mode_disckg1_urt1_disckg(hw, value);
3457 }
3458
3459 /* REG_0x0e:cpu_mode_disckg1->urt2_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[18]*/
3460 uint32_t sys_hal_get_cpu_mode_disckg1_urt2_disckg(sys_hw_t *hw)
3461 {
3462 return sys_ll_get_cpu_mode_disckg1_urt2_disckg(hw);
3463 }
3464
3465 void sys_hal_set_cpu_mode_disckg1_urt2_disckg(sys_hw_t *hw, uint32_t value)
3466 {
3467 sys_ll_set_cpu_mode_disckg1_urt2_disckg(hw, value);
3468 }
3469
3470 /* REG_0x0e:cpu_mode_disckg1->pwm1_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[19]*/
3471 uint32_t sys_hal_get_cpu_mode_disckg1_pwm1_disckg(sys_hw_t *hw)
3472 {
3473 return sys_ll_get_cpu_mode_disckg1_pwm1_disckg(hw);
3474 }
3475
3476 void sys_hal_set_cpu_mode_disckg1_pwm1_disckg(sys_hw_t *hw, uint32_t value)
3477 {
3478 sys_ll_set_cpu_mode_disckg1_pwm1_disckg(hw, value);
3479 }
3480
3481 /* REG_0x0e:cpu_mode_disckg1->i2c1_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[20]*/
3482 uint32_t sys_hal_get_cpu_mode_disckg1_i2c1_disckg(sys_hw_t *hw)
3483 {
3484 return sys_ll_get_cpu_mode_disckg1_i2c1_disckg(hw);
3485 }
3486
3487 void sys_hal_set_cpu_mode_disckg1_i2c1_disckg(sys_hw_t *hw, uint32_t value)
3488 {
3489 sys_ll_set_cpu_mode_disckg1_i2c1_disckg(hw, value);
3490 }
3491
3492 /* REG_0x0e:cpu_mode_disckg1->spi1_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[21]*/
3493 uint32_t sys_hal_get_cpu_mode_disckg1_spi1_disckg(sys_hw_t *hw)
3494 {
3495 return sys_ll_get_cpu_mode_disckg1_spi1_disckg(hw);
3496 }
3497
3498 void sys_hal_set_cpu_mode_disckg1_spi1_disckg(sys_hw_t *hw, uint32_t value)
3499 {
3500 sys_ll_set_cpu_mode_disckg1_spi1_disckg(hw, value);
3501 }
3502
3503 /* REG_0x0e:cpu_mode_disckg1->usb_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[22]*/
3504 uint32_t sys_hal_get_cpu_mode_disckg1_usb_disckg(sys_hw_t *hw)
3505 {
3506 return sys_ll_get_cpu_mode_disckg1_usb_disckg(hw);
3507 }
3508
3509 void sys_hal_set_cpu_mode_disckg1_usb_disckg(sys_hw_t *hw, uint32_t value)
3510 {
3511 sys_ll_set_cpu_mode_disckg1_usb_disckg(hw, value);
3512 }
3513
3514 /* REG_0x0e:cpu_mode_disckg1->can_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[23]*/
3515 uint32_t sys_hal_get_cpu_mode_disckg1_can_disckg(sys_hw_t *hw)
3516 {
3517 return sys_ll_get_cpu_mode_disckg1_can_disckg(hw);
3518 }
3519
3520 void sys_hal_set_cpu_mode_disckg1_can_disckg(sys_hw_t *hw, uint32_t value)
3521 {
3522 sys_ll_set_cpu_mode_disckg1_can_disckg(hw, value);
3523 }
3524
3525 /* REG_0x0e:cpu_mode_disckg1->qspi0_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[24]*/
3526 uint32_t sys_hal_get_cpu_mode_disckg1_qspi0_disckg(sys_hw_t *hw)
3527 {
3528 return sys_ll_get_cpu_mode_disckg1_qspi0_disckg(hw);
3529 }
3530
3531 void sys_hal_set_cpu_mode_disckg1_qspi0_disckg(sys_hw_t *hw, uint32_t value)
3532 {
3533 sys_ll_set_cpu_mode_disckg1_qspi0_disckg(hw, value);
3534 }
3535
3536 /* REG_0x0e:cpu_mode_disckg1->psram_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[25]*/
3537 uint32_t sys_hal_get_cpu_mode_disckg1_psram_disckg(sys_hw_t *hw)
3538 {
3539 return sys_ll_get_cpu_mode_disckg1_psram_disckg(hw);
3540 }
3541
3542 void sys_hal_set_cpu_mode_disckg1_psram_disckg(sys_hw_t *hw, uint32_t value)
3543 {
3544 sys_ll_set_cpu_mode_disckg1_psram_disckg(hw, value);
3545 }
3546
3547 /* REG_0x0e:cpu_mode_disckg1->fft_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[26]*/
3548 uint32_t sys_hal_get_cpu_mode_disckg1_fft_disckg(sys_hw_t *hw)
3549 {
3550 return sys_ll_get_cpu_mode_disckg1_fft_disckg(hw);
3551 }
3552
3553 void sys_hal_set_cpu_mode_disckg1_fft_disckg(sys_hw_t *hw, uint32_t value)
3554 {
3555 sys_ll_set_cpu_mode_disckg1_fft_disckg(hw, value);
3556 }
3557
3558 /* REG_0x0e:cpu_mode_disckg1->sbc_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[27]*/
3559 uint32_t sys_hal_get_cpu_mode_disckg1_sbc_disckg(sys_hw_t *hw)
3560 {
3561 return sys_ll_get_cpu_mode_disckg1_sbc_disckg(hw);
3562 }
3563
3564 void sys_hal_set_cpu_mode_disckg1_sbc_disckg(sys_hw_t *hw, uint32_t value)
3565 {
3566 sys_ll_set_cpu_mode_disckg1_sbc_disckg(hw, value);
3567 }
3568
3569 /* REG_0x0e:cpu_mode_disckg1->aud_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[28]*/
3570 uint32_t sys_hal_get_cpu_mode_disckg1_aud_disckg(sys_hw_t *hw)
3571 {
3572 return sys_ll_get_cpu_mode_disckg1_aud_disckg(hw);
3573 }
3574
3575 void sys_hal_set_cpu_mode_disckg1_aud_disckg(sys_hw_t *hw, uint32_t value)
3576 {
3577 sys_ll_set_cpu_mode_disckg1_aud_disckg(hw, value);
3578 }
3579
3580 /* REG_0x0e:cpu_mode_disckg1->i2s_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[29]*/
3581 uint32_t sys_hal_get_cpu_mode_disckg1_i2s_disckg(sys_hw_t *hw)
3582 {
3583 return sys_ll_get_cpu_mode_disckg1_i2s_disckg(hw);
3584 }
3585
3586 void sys_hal_set_cpu_mode_disckg1_i2s_disckg(sys_hw_t *hw, uint32_t value)
3587 {
3588 sys_ll_set_cpu_mode_disckg1_i2s_disckg(hw, value);
3589 }
3590
3591 /* REG_0x0e:cpu_mode_disckg1->jpeg_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[30]*/
3592 uint32_t sys_hal_get_cpu_mode_disckg1_jpeg_disckg(sys_hw_t *hw)
3593 {
3594 return sys_ll_get_cpu_mode_disckg1_jpeg_disckg(hw);
3595 }
3596
3597 void sys_hal_set_cpu_mode_disckg1_jpeg_disckg(sys_hw_t *hw, uint32_t value)
3598 {
3599 sys_ll_set_cpu_mode_disckg1_jpeg_disckg(hw, value);
3600 }
3601
3602 /* REG_0x0e:cpu_mode_disckg1->jpeg_dec_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[31]*/
3603 uint32_t sys_hal_get_cpu_mode_disckg1_jpeg_dec_disckg(sys_hw_t *hw)
3604 {
3605 return sys_ll_get_cpu_mode_disckg1_jpeg_dec_disckg(hw);
3606 }
3607
3608 void sys_hal_set_cpu_mode_disckg1_jpeg_dec_disckg(sys_hw_t *hw, uint32_t value)
3609 {
3610 sys_ll_set_cpu_mode_disckg1_jpeg_dec_disckg(hw, value);
3611 }
3612
3613 /* REG_0x0f */
3614
3615 uint32_t sys_hal_get_cpu_mode_disckg2_value(sys_hw_t *hw)
3616 {
3617 return sys_ll_get_cpu_mode_disckg2_value(hw);
3618 }
3619
3620 void sys_hal_set_cpu_mode_disckg2_value(sys_hw_t *hw, uint32_t value)
3621 {
3622 sys_ll_set_cpu_mode_disckg2_value(hw, value);
3623 }
3624
3625 /* REG_0x0f:cpu_mode_disckg2->disp_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xf[0]*/
3626 uint32_t sys_hal_get_cpu_mode_disckg2_disp_disckg(sys_hw_t *hw)
3627 {
3628 return sys_ll_get_cpu_mode_disckg2_disp_disckg(hw);
3629 }
3630
3631 void sys_hal_set_cpu_mode_disckg2_disp_disckg(sys_hw_t *hw, uint32_t value)
3632 {
3633 sys_ll_set_cpu_mode_disckg2_disp_disckg(hw, value);
3634 }
3635
3636 /* REG_0x0f:cpu_mode_disckg2->dma2d_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xf[1]*/
3637 uint32_t sys_hal_get_cpu_mode_disckg2_dma2d_disckg(sys_hw_t *hw)
3638 {
3639 return sys_ll_get_cpu_mode_disckg2_dma2d_disckg(hw);
3640 }
3641
3642 void sys_hal_set_cpu_mode_disckg2_dma2d_disckg(sys_hw_t *hw, uint32_t value)
3643 {
3644 sys_ll_set_cpu_mode_disckg2_dma2d_disckg(hw, value);
3645 }
3646
3647 /* REG_0x0f:cpu_mode_disckg2->btdm_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xf[3]*/
3648 uint32_t sys_hal_get_cpu_mode_disckg2_btdm_disckg(sys_hw_t *hw)
3649 {
3650 return sys_ll_get_cpu_mode_disckg2_btdm_disckg(hw);
3651 }
3652
3653 void sys_hal_set_cpu_mode_disckg2_btdm_disckg(sys_hw_t *hw, uint32_t value)
3654 {
3655 sys_ll_set_cpu_mode_disckg2_btdm_disckg(hw, value);
3656 }
3657
3658 /* REG_0x0f:cpu_mode_disckg2->xver_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xf[4]*/
3659 uint32_t sys_hal_get_cpu_mode_disckg2_xver_disckg(sys_hw_t *hw)
3660 {
3661 return sys_ll_get_cpu_mode_disckg2_xver_disckg(hw);
3662 }
3663
3664 void sys_hal_set_cpu_mode_disckg2_xver_disckg(sys_hw_t *hw, uint32_t value)
3665 {
3666 sys_ll_set_cpu_mode_disckg2_xver_disckg(hw, value);
3667 }
3668
3669 /* REG_0x0f:cpu_mode_disckg2->btdm_bps_ckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xf[8:5]*/
3670 uint32_t sys_hal_get_cpu_mode_disckg2_btdm_bps_ckg(sys_hw_t *hw)
3671 {
3672 return sys_ll_get_cpu_mode_disckg2_btdm_bps_ckg(hw);
3673 }
3674
3675 void sys_hal_set_cpu_mode_disckg2_btdm_bps_ckg(sys_hw_t *hw, uint32_t value)
3676 {
3677 sys_ll_set_cpu_mode_disckg2_btdm_bps_ckg(hw, value);
3678 }
3679
3680 /* REG_0x10 */
3681
3682 uint32_t sys_hal_get_cpu_power_sleep_wakeup_value(sys_hw_t *hw)
3683 {
3684 return sys_ll_get_cpu_power_sleep_wakeup_value(hw);
3685 }
3686
3687 void sys_hal_set_cpu_power_sleep_wakeup_value(sys_hw_t *hw, uint32_t value)
3688 {
3689 sys_ll_set_cpu_power_sleep_wakeup_value(hw, value);
3690 }
3691
3692 /* REG_0x10:cpu_power_sleep_wakeup->pwd_mem1:0:power on of mem1 ,RW,0x10[0]*/
3693 uint32_t sys_hal_get_cpu_power_sleep_wakeup_pwd_mem1(sys_hw_t *hw)
3694 {
3695 return sys_ll_get_cpu_power_sleep_wakeup_pwd_mem1(hw);
3696 }
3697
3698 void sys_hal_set_cpu_power_sleep_wakeup_pwd_mem1(sys_hw_t *hw, uint32_t value)
3699 {
3700 sys_ll_set_cpu_power_sleep_wakeup_pwd_mem1(hw, value);
3701 }
3702
3703 /* REG_0x10:cpu_power_sleep_wakeup->pwd_mem2:0:power on of mem2 ,RW,0x10[1]*/
3704 uint32_t sys_hal_get_cpu_power_sleep_wakeup_pwd_mem2(sys_hw_t *hw)
3705 {
3706 return sys_ll_get_cpu_power_sleep_wakeup_pwd_mem2(hw);
3707 }
3708
3709 void sys_hal_set_cpu_power_sleep_wakeup_pwd_mem2(sys_hw_t *hw, uint32_t value)
3710 {
3711 sys_ll_set_cpu_power_sleep_wakeup_pwd_mem2(hw, value);
3712 }
3713
3714 /* REG_0x10:cpu_power_sleep_wakeup->pwd_mem3:0:power on of mem3 ,RW,0x10[2]*/
3715 uint32_t sys_hal_get_cpu_power_sleep_wakeup_pwd_mem3(sys_hw_t *hw)
3716 {
3717 return sys_ll_get_cpu_power_sleep_wakeup_pwd_mem3(hw);
3718 }
3719
3720 void sys_hal_set_cpu_power_sleep_wakeup_pwd_mem3(sys_hw_t *hw, uint32_t value)
3721 {
3722 sys_ll_set_cpu_power_sleep_wakeup_pwd_mem3(hw, value);
3723 }
3724
3725 /* REG_0x10:cpu_power_sleep_wakeup->pwd_encp:0:power on of encp ,RW,0x10[3]*/
3726 uint32_t sys_hal_get_cpu_power_sleep_wakeup_pwd_encp(sys_hw_t *hw)
3727 {
3728 return sys_ll_get_cpu_power_sleep_wakeup_pwd_encp(hw);
3729 }
3730
3731 void sys_hal_set_cpu_power_sleep_wakeup_pwd_encp(sys_hw_t *hw, uint32_t value)
3732 {
3733 sys_ll_set_cpu_power_sleep_wakeup_pwd_encp(hw, value);
3734 }
3735
3736 /* REG_0x10:cpu_power_sleep_wakeup->pwd_bakp:0:power on of bakp ,RW,0x10[4]*/
3737 uint32_t sys_hal_get_cpu_power_sleep_wakeup_pwd_bakp(sys_hw_t *hw)
3738 {
3739 return sys_ll_get_cpu_power_sleep_wakeup_pwd_bakp(hw);
3740 }
3741
3742 void sys_hal_set_cpu_power_sleep_wakeup_pwd_bakp(sys_hw_t *hw, uint32_t value)
3743 {
3744 sys_ll_set_cpu_power_sleep_wakeup_pwd_bakp(hw, value);
3745 }
3746
3747 /* REG_0x10:cpu_power_sleep_wakeup->pwd_ahbp:0:power on of ahbp ,RW,0x10[5]*/
3748 uint32_t sys_hal_get_cpu_power_sleep_wakeup_pwd_ahbp(sys_hw_t *hw)
3749 {
3750 return sys_ll_get_cpu_power_sleep_wakeup_pwd_ahbp(hw);
3751 }
3752
3753 void sys_hal_set_cpu_power_sleep_wakeup_pwd_ahbp(sys_hw_t *hw, uint32_t value)
3754 {
3755 sys_ll_set_cpu_power_sleep_wakeup_pwd_ahbp(hw, value);
3756 }
3757
3758 /* REG_0x10:cpu_power_sleep_wakeup->pwd_audp:0:power on of audp ,RW,0x10[6]*/
3759 uint32_t sys_hal_get_cpu_power_sleep_wakeup_pwd_audp(sys_hw_t *hw)
3760 {
3761 return sys_ll_get_cpu_power_sleep_wakeup_pwd_audp(hw);
3762 }
3763
3764 void sys_hal_set_cpu_power_sleep_wakeup_pwd_audp(sys_hw_t *hw, uint32_t value)
3765 {
3766 sys_ll_set_cpu_power_sleep_wakeup_pwd_audp(hw, value);
3767 }
3768
3769 /* REG_0x10:cpu_power_sleep_wakeup->pwd_vidp:0:power on of vidp ,RW,0x10[7]*/
3770 uint32_t sys_hal_get_cpu_power_sleep_wakeup_pwd_vidp(sys_hw_t *hw)
3771 {
3772 return sys_ll_get_cpu_power_sleep_wakeup_pwd_vidp(hw);
3773 }
3774
3775 void sys_hal_set_cpu_power_sleep_wakeup_pwd_vidp(sys_hw_t *hw, uint32_t value)
3776 {
3777 sys_ll_set_cpu_power_sleep_wakeup_pwd_vidp(hw, value);
3778 }
3779
3780 /* REG_0x10:cpu_power_sleep_wakeup->pwd_btsp:0:power on of btsp ,RW,0x10[8]*/
3781 uint32_t sys_hal_get_cpu_power_sleep_wakeup_pwd_btsp(sys_hw_t *hw)
3782 {
3783 return sys_ll_get_cpu_power_sleep_wakeup_pwd_btsp(hw);
3784 }
3785
3786 void sys_hal_set_cpu_power_sleep_wakeup_pwd_btsp(sys_hw_t *hw, uint32_t value)
3787 {
3788 sys_ll_set_cpu_power_sleep_wakeup_pwd_btsp(hw, value);
3789 }
3790
3791 /* REG_0x10:cpu_power_sleep_wakeup->pwd_wifp_mac:0:power on of wifp_mac ,RW,0x10[9]*/
3792 uint32_t sys_hal_get_cpu_power_sleep_wakeup_pwd_wifp_mac(sys_hw_t *hw)
3793 {
3794 return sys_ll_get_cpu_power_sleep_wakeup_pwd_wifp_mac(hw);
3795 }
3796
3797 void sys_hal_set_cpu_power_sleep_wakeup_pwd_wifp_mac(sys_hw_t *hw, uint32_t value)
3798 {
3799 sys_ll_set_cpu_power_sleep_wakeup_pwd_wifp_mac(hw, value);
3800 }
3801
3802 /* REG_0x10:cpu_power_sleep_wakeup->pwd_wifp_phy:0:power on of wifp_phy ,RW,0x10[10]*/
3803 uint32_t sys_hal_get_cpu_power_sleep_wakeup_pwd_wifp_phy(sys_hw_t *hw)
3804 {
3805 return sys_ll_get_cpu_power_sleep_wakeup_pwd_wifp_phy(hw);
3806 }
3807
3808 void sys_hal_set_cpu_power_sleep_wakeup_pwd_wifp_phy(sys_hw_t *hw, uint32_t value)
3809 {
3810 sys_ll_set_cpu_power_sleep_wakeup_pwd_wifp_phy(hw, value);
3811 }
3812
3813 /* REG_0x10:cpu_power_sleep_wakeup->sleep_en_need_flash_idle:0:sleep_en of flash_idle,RW,0x10[16]*/
3814 uint32_t sys_hal_get_cpu_power_sleep_wakeup_sleep_en_need_flash_idle(sys_hw_t *hw)
3815 {
3816 return sys_ll_get_cpu_power_sleep_wakeup_sleep_en_need_flash_idle(hw);
3817 }
3818
3819 void sys_hal_set_cpu_power_sleep_wakeup_sleep_en_need_flash_idle(sys_hw_t *hw, uint32_t value)
3820 {
3821 sys_ll_set_cpu_power_sleep_wakeup_sleep_en_need_flash_idle(hw, value);
3822 }
3823
3824 /* REG_0x10:cpu_power_sleep_wakeup->sleep_en_need_cpu1_wfi:0:sleep_en of cpu1_wfi ,RW,0x10[17]*/
3825 uint32_t sys_hal_get_cpu_power_sleep_wakeup_sleep_en_need_cpu1_wfi(sys_hw_t *hw)
3826 {
3827 return sys_ll_get_cpu_power_sleep_wakeup_sleep_en_need_cpu1_wfi(hw);
3828 }
3829
3830 void sys_hal_set_cpu_power_sleep_wakeup_sleep_en_need_cpu1_wfi(sys_hw_t *hw, uint32_t value)
3831 {
3832 sys_ll_set_cpu_power_sleep_wakeup_sleep_en_need_cpu1_wfi(hw, value);
3833 }
3834
3835 /* REG_0x10:cpu_power_sleep_wakeup->sleep_en_need_cpu0_wfi:0:sleep_en of cpu0_wfi ,RW,0x10[18]*/
3836 uint32_t sys_hal_get_cpu_power_sleep_wakeup_sleep_en_need_cpu0_wfi(sys_hw_t *hw)
3837 {
3838 return sys_ll_get_cpu_power_sleep_wakeup_sleep_en_need_cpu0_wfi(hw);
3839 }
3840
3841 void sys_hal_set_cpu_power_sleep_wakeup_sleep_en_need_cpu0_wfi(sys_hw_t *hw, uint32_t value)
3842 {
3843 sys_ll_set_cpu_power_sleep_wakeup_sleep_en_need_cpu0_wfi(hw, value);
3844 }
3845
3846 /* REG_0x10:cpu_power_sleep_wakeup->sleep_en_global:0:sleep_en of global ,RW,0x10[19]*/
3847 uint32_t sys_hal_get_cpu_power_sleep_wakeup_sleep_en_global(sys_hw_t *hw)
3848 {
3849 return sys_ll_get_cpu_power_sleep_wakeup_sleep_en_global(hw);
3850 }
3851
3852 void sys_hal_set_cpu_power_sleep_wakeup_sleep_en_global(sys_hw_t *hw, uint32_t value)
3853 {
3854 sys_ll_set_cpu_power_sleep_wakeup_sleep_en_global(hw, value);
3855 }
3856
3857 /* REG_0x10:cpu_power_sleep_wakeup->wifi_wakeup_platform_en:0:wifi_wakeup_en ,RW,0x10[20]*/
3858 uint32_t sys_hal_get_cpu_power_sleep_wakeup_wifi_wakeup_platform_en(sys_hw_t *hw)
3859 {
3860 return sys_ll_get_cpu_power_sleep_wakeup_wifi_wakeup_platform_en(hw);
3861 }
3862
3863 void sys_hal_set_cpu_power_sleep_wakeup_wifi_wakeup_platform_en(sys_hw_t *hw, uint32_t value)
3864 {
3865 sys_ll_set_cpu_power_sleep_wakeup_wifi_wakeup_platform_en(hw, value);
3866 }
3867
3868 /* REG_0x10:cpu_power_sleep_wakeup->bts_wakeup_platform_en:0:bts_wakeup_en ,RW,0x10[21]*/
3869 uint32_t sys_hal_get_cpu_power_sleep_wakeup_bts_wakeup_platform_en(sys_hw_t *hw)
3870 {
3871 return sys_ll_get_cpu_power_sleep_wakeup_bts_wakeup_platform_en(hw);
3872 }
3873
3874 void sys_hal_set_cpu_power_sleep_wakeup_bts_wakeup_platform_en(sys_hw_t *hw, uint32_t value)
3875 {
3876 sys_ll_set_cpu_power_sleep_wakeup_bts_wakeup_platform_en(hw, value);
3877 }
3878
3879 /* REG_0x10:cpu_power_sleep_wakeup->bts_sleep_exit_req:0:bt sleep exit request ,RW,0x10[22]*/
3880 uint32_t sys_hal_get_cpu_power_sleep_wakeup_bts_sleep_exit_req(sys_hw_t *hw)
3881 {
3882 return sys_ll_get_cpu_power_sleep_wakeup_bts_sleep_exit_req(hw);
3883 }
3884
3885 void sys_hal_set_cpu_power_sleep_wakeup_bts_sleep_exit_req(sys_hw_t *hw, uint32_t value)
3886 {
3887 sys_ll_set_cpu_power_sleep_wakeup_bts_sleep_exit_req(hw, value);
3888 }
3889
3890 /* REG_0x11 */
3891
3892 /* REG_0x20 */
3893
3894 uint32_t sys_hal_get_cpu0_int_0_31_en_value(sys_hw_t *hw)
3895 {
3896 return sys_ll_get_cpu0_int_0_31_en_value(hw);
3897 }
3898
3899 void sys_hal_set_cpu0_int_0_31_en_value(sys_hw_t *hw, uint32_t value)
3900 {
3901 sys_ll_set_cpu0_int_0_31_en_value(hw, value);
3902 }
3903
3904 /* REG_0x20:cpu0_int_0_31_en->cpu0_bmc32_int_en: ,R/W,0x20[0]*/
3905 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_bmc32_int_en(sys_hw_t *hw)
3906 {
3907 return sys_ll_get_cpu0_int_0_31_en_cpu0_bmc32_int_en(hw);
3908 }
3909
3910 void sys_hal_set_cpu0_int_0_31_en_cpu0_bmc32_int_en(sys_hw_t *hw, uint32_t value)
3911 {
3912 sys_ll_set_cpu0_int_0_31_en_cpu0_bmc32_int_en(hw, value);
3913 }
3914
3915 /* REG_0x20:cpu0_int_0_31_en->cpu0_host_0_irq_en: ,R/W,0x20[1]*/
3916 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_host_0_irq_en(sys_hw_t *hw)
3917 {
3918 return sys_ll_get_cpu0_int_0_31_en_cpu0_host_0_irq_en(hw);
3919 }
3920
3921 void sys_hal_set_cpu0_int_0_31_en_cpu0_host_0_irq_en(sys_hw_t *hw, uint32_t value)
3922 {
3923 sys_ll_set_cpu0_int_0_31_en_cpu0_host_0_irq_en(hw, value);
3924 }
3925
3926 /* REG_0x20:cpu0_int_0_31_en->cpu0_host_0_sec_irq_en: ,R/W,0x20[2]*/
3927 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_host_0_sec_irq_en(sys_hw_t *hw)
3928 {
3929 return sys_ll_get_cpu0_int_0_31_en_cpu0_host_0_sec_irq_en(hw);
3930 }
3931
3932 void sys_hal_set_cpu0_int_0_31_en_cpu0_host_0_sec_irq_en(sys_hw_t *hw, uint32_t value)
3933 {
3934 sys_ll_set_cpu0_int_0_31_en_cpu0_host_0_sec_irq_en(hw, value);
3935 }
3936
3937 /* REG_0x20:cpu0_int_0_31_en->cpu0_timer_int_en: ,R/W,0x20[3]*/
3938 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_timer_int_en(sys_hw_t *hw)
3939 {
3940 return sys_ll_get_cpu0_int_0_31_en_cpu0_timer_int_en(hw);
3941 }
3942
3943 void sys_hal_set_cpu0_int_0_31_en_cpu0_timer_int_en(sys_hw_t *hw, uint32_t value)
3944 {
3945 sys_ll_set_cpu0_int_0_31_en_cpu0_timer_int_en(hw, value);
3946 }
3947
3948 /* REG_0x20:cpu0_int_0_31_en->cpu0_uart_int_en: ,R/W,0x20[4]*/
3949 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_uart_int_en(sys_hw_t *hw)
3950 {
3951 return sys_ll_get_cpu0_int_0_31_en_cpu0_uart_int_en(hw);
3952 }
3953
3954 void sys_hal_set_cpu0_int_0_31_en_cpu0_uart_int_en(sys_hw_t *hw, uint32_t value)
3955 {
3956 sys_ll_set_cpu0_int_0_31_en_cpu0_uart_int_en(hw, value);
3957 }
3958
3959 /* REG_0x20:cpu0_int_0_31_en->cpu0_pwm_int_en: ,R/W,0x20[5]*/
3960 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_pwm_int_en(sys_hw_t *hw)
3961 {
3962 return sys_ll_get_cpu0_int_0_31_en_cpu0_pwm_int_en(hw);
3963 }
3964
3965 void sys_hal_set_cpu0_int_0_31_en_cpu0_pwm_int_en(sys_hw_t *hw, uint32_t value)
3966 {
3967 sys_ll_set_cpu0_int_0_31_en_cpu0_pwm_int_en(hw, value);
3968 }
3969
3970 /* REG_0x20:cpu0_int_0_31_en->cpu0_i2c_int_en: ,R/W,0x20[6]*/
3971 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_i2c_int_en(sys_hw_t *hw)
3972 {
3973 return sys_ll_get_cpu0_int_0_31_en_cpu0_i2c_int_en(hw);
3974 }
3975
3976 void sys_hal_set_cpu0_int_0_31_en_cpu0_i2c_int_en(sys_hw_t *hw, uint32_t value)
3977 {
3978 sys_ll_set_cpu0_int_0_31_en_cpu0_i2c_int_en(hw, value);
3979 }
3980
3981 /* REG_0x20:cpu0_int_0_31_en->cpu0_spi_int_en: ,R/W,0x20[7]*/
3982 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_spi_int_en(sys_hw_t *hw)
3983 {
3984 return sys_ll_get_cpu0_int_0_31_en_cpu0_spi_int_en(hw);
3985 }
3986
3987 void sys_hal_set_cpu0_int_0_31_en_cpu0_spi_int_en(sys_hw_t *hw, uint32_t value)
3988 {
3989 sys_ll_set_cpu0_int_0_31_en_cpu0_spi_int_en(hw, value);
3990 }
3991
3992 /* REG_0x20:cpu0_int_0_31_en->cpu0_sadc_int_en: ,R/W,0x20[8]*/
3993 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_sadc_int_en(sys_hw_t *hw)
3994 {
3995 return sys_ll_get_cpu0_int_0_31_en_cpu0_sadc_int_en(hw);
3996 }
3997
3998 void sys_hal_set_cpu0_int_0_31_en_cpu0_sadc_int_en(sys_hw_t *hw, uint32_t value)
3999 {
4000 sys_ll_set_cpu0_int_0_31_en_cpu0_sadc_int_en(hw, value);
4001 }
4002
4003 /* REG_0x20:cpu0_int_0_31_en->cpu0_irda_int_en: ,R/W,0x20[9]*/
4004 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_irda_int_en(sys_hw_t *hw)
4005 {
4006 return sys_ll_get_cpu0_int_0_31_en_cpu0_irda_int_en(hw);
4007 }
4008
4009 void sys_hal_set_cpu0_int_0_31_en_cpu0_irda_int_en(sys_hw_t *hw, uint32_t value)
4010 {
4011 sys_ll_set_cpu0_int_0_31_en_cpu0_irda_int_en(hw, value);
4012 }
4013
4014 /* REG_0x20:cpu0_int_0_31_en->cpu0_sdio_int_en: ,R/W,0x20[10]*/
4015 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_sdio_int_en(sys_hw_t *hw)
4016 {
4017 return sys_ll_get_cpu0_int_0_31_en_cpu0_sdio_int_en(hw);
4018 }
4019
4020 void sys_hal_set_cpu0_int_0_31_en_cpu0_sdio_int_en(sys_hw_t *hw, uint32_t value)
4021 {
4022 sys_ll_set_cpu0_int_0_31_en_cpu0_sdio_int_en(hw, value);
4023 }
4024
4025 /* REG_0x20:cpu0_int_0_31_en->cpu0_gdma_int_en: ,R/W,0x20[11]*/
4026 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_gdma_int_en(sys_hw_t *hw)
4027 {
4028 return sys_ll_get_cpu0_int_0_31_en_cpu0_gdma_int_en(hw);
4029 }
4030
4031 void sys_hal_set_cpu0_int_0_31_en_cpu0_gdma_int_en(sys_hw_t *hw, uint32_t value)
4032 {
4033 sys_ll_set_cpu0_int_0_31_en_cpu0_gdma_int_en(hw, value);
4034 }
4035
4036 /* REG_0x20:cpu0_int_0_31_en->cpu0_la_int_en: ,R/W,0x20[12]*/
4037 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_la_int_en(sys_hw_t *hw)
4038 {
4039 return sys_ll_get_cpu0_int_0_31_en_cpu0_la_int_en(hw);
4040 }
4041
4042 void sys_hal_set_cpu0_int_0_31_en_cpu0_la_int_en(sys_hw_t *hw, uint32_t value)
4043 {
4044 sys_ll_set_cpu0_int_0_31_en_cpu0_la_int_en(hw, value);
4045 }
4046
4047 /* REG_0x20:cpu0_int_0_31_en->cpu0_timer1_int_en: ,R/W,0x20[13]*/
4048 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_timer1_int_en(sys_hw_t *hw)
4049 {
4050 return sys_ll_get_cpu0_int_0_31_en_cpu0_timer1_int_en(hw);
4051 }
4052
4053 void sys_hal_set_cpu0_int_0_31_en_cpu0_timer1_int_en(sys_hw_t *hw, uint32_t value)
4054 {
4055 sys_ll_set_cpu0_int_0_31_en_cpu0_timer1_int_en(hw, value);
4056 }
4057
4058 /* REG_0x20:cpu0_int_0_31_en->cpu0_i2c1_int_en: ,R/W,0x20[14]*/
4059 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_i2c1_int_en(sys_hw_t *hw)
4060 {
4061 return sys_ll_get_cpu0_int_0_31_en_cpu0_i2c1_int_en(hw);
4062 }
4063
4064 void sys_hal_set_cpu0_int_0_31_en_cpu0_i2c1_int_en(sys_hw_t *hw, uint32_t value)
4065 {
4066 sys_ll_set_cpu0_int_0_31_en_cpu0_i2c1_int_en(hw, value);
4067 }
4068
4069 /* REG_0x20:cpu0_int_0_31_en->cpu0_uart1_int_en: ,R/W,0x20[15]*/
4070 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_uart1_int_en(sys_hw_t *hw)
4071 {
4072 return sys_ll_get_cpu0_int_0_31_en_cpu0_uart1_int_en(hw);
4073 }
4074
4075 void sys_hal_set_cpu0_int_0_31_en_cpu0_uart1_int_en(sys_hw_t *hw, uint32_t value)
4076 {
4077 sys_ll_set_cpu0_int_0_31_en_cpu0_uart1_int_en(hw, value);
4078 }
4079
4080 /* REG_0x20:cpu0_int_0_31_en->cpu0_uart2_int_en: ,R/W,0x20[16]*/
4081 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_uart2_int_en(sys_hw_t *hw)
4082 {
4083 return sys_ll_get_cpu0_int_0_31_en_cpu0_uart2_int_en(hw);
4084 }
4085
4086 void sys_hal_set_cpu0_int_0_31_en_cpu0_uart2_int_en(sys_hw_t *hw, uint32_t value)
4087 {
4088 sys_ll_set_cpu0_int_0_31_en_cpu0_uart2_int_en(hw, value);
4089 }
4090
4091 /* REG_0x20:cpu0_int_0_31_en->cpu0_spi1_int_en: ,R/W,0x20[17]*/
4092 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_spi1_int_en(sys_hw_t *hw)
4093 {
4094 return sys_ll_get_cpu0_int_0_31_en_cpu0_spi1_int_en(hw);
4095 }
4096
4097 void sys_hal_set_cpu0_int_0_31_en_cpu0_spi1_int_en(sys_hw_t *hw, uint32_t value)
4098 {
4099 sys_ll_set_cpu0_int_0_31_en_cpu0_spi1_int_en(hw, value);
4100 }
4101
4102 /* REG_0x20:cpu0_int_0_31_en->cpu0_can_int_en: ,R/W,0x20[18]*/
4103 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_can_int_en(sys_hw_t *hw)
4104 {
4105 return sys_ll_get_cpu0_int_0_31_en_cpu0_can_int_en(hw);
4106 }
4107
4108 void sys_hal_set_cpu0_int_0_31_en_cpu0_can_int_en(sys_hw_t *hw, uint32_t value)
4109 {
4110 sys_ll_set_cpu0_int_0_31_en_cpu0_can_int_en(hw, value);
4111 }
4112
4113 /* REG_0x20:cpu0_int_0_31_en->cpu0_usb_int_en: ,R/W,0x20[19]*/
4114 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_usb_int_en(sys_hw_t *hw)
4115 {
4116 return sys_ll_get_cpu0_int_0_31_en_cpu0_usb_int_en(hw);
4117 }
4118
4119 void sys_hal_set_cpu0_int_0_31_en_cpu0_usb_int_en(sys_hw_t *hw, uint32_t value)
4120 {
4121 sys_ll_set_cpu0_int_0_31_en_cpu0_usb_int_en(hw, value);
4122 }
4123
4124 /* REG_0x20:cpu0_int_0_31_en->cpu0_qspi_int_en: ,R/W,0x20[20]*/
4125 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_qspi_int_en(sys_hw_t *hw)
4126 {
4127 return sys_ll_get_cpu0_int_0_31_en_cpu0_qspi_int_en(hw);
4128 }
4129
4130 void sys_hal_set_cpu0_int_0_31_en_cpu0_qspi_int_en(sys_hw_t *hw, uint32_t value)
4131 {
4132 sys_ll_set_cpu0_int_0_31_en_cpu0_qspi_int_en(hw, value);
4133 }
4134
4135 /* REG_0x20:cpu0_int_0_31_en->cpu0_fft_int_en: ,R/W,0x20[21]*/
4136 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_fft_int_en(sys_hw_t *hw)
4137 {
4138 return sys_ll_get_cpu0_int_0_31_en_cpu0_fft_int_en(hw);
4139 }
4140
4141 void sys_hal_set_cpu0_int_0_31_en_cpu0_fft_int_en(sys_hw_t *hw, uint32_t value)
4142 {
4143 sys_ll_set_cpu0_int_0_31_en_cpu0_fft_int_en(hw, value);
4144 }
4145
4146 /* REG_0x20:cpu0_int_0_31_en->cpu0_sbc_int_en: ,R/W,0x20[22]*/
4147 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_sbc_int_en(sys_hw_t *hw)
4148 {
4149 return sys_ll_get_cpu0_int_0_31_en_cpu0_sbc_int_en(hw);
4150 }
4151
4152 void sys_hal_set_cpu0_int_0_31_en_cpu0_sbc_int_en(sys_hw_t *hw, uint32_t value)
4153 {
4154 sys_ll_set_cpu0_int_0_31_en_cpu0_sbc_int_en(hw, value);
4155 }
4156
4157 /* REG_0x20:cpu0_int_0_31_en->cpu0_aud_int_en: ,R/W,0x20[23]*/
4158 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_aud_int_en(sys_hw_t *hw)
4159 {
4160 return sys_ll_get_cpu0_int_0_31_en_cpu0_aud_int_en(hw);
4161 }
4162
4163 void sys_hal_set_cpu0_int_0_31_en_cpu0_aud_int_en(sys_hw_t *hw, uint32_t value)
4164 {
4165 sys_ll_set_cpu0_int_0_31_en_cpu0_aud_int_en(hw, value);
4166 }
4167
4168 /* REG_0x20:cpu0_int_0_31_en->cpu0_i2s_int_en: ,R/W,0x20[24]*/
4169 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_i2s_int_en(sys_hw_t *hw)
4170 {
4171 return sys_ll_get_cpu0_int_0_31_en_cpu0_i2s_int_en(hw);
4172 }
4173
4174 void sys_hal_set_cpu0_int_0_31_en_cpu0_i2s_int_en(sys_hw_t *hw, uint32_t value)
4175 {
4176 sys_ll_set_cpu0_int_0_31_en_cpu0_i2s_int_en(hw, value);
4177 }
4178
4179 /* REG_0x20:cpu0_int_0_31_en->cpu0_jpegenc_int_en: ,R/W,0x20[25]*/
4180 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_jpegenc_int_en(sys_hw_t *hw)
4181 {
4182 return sys_ll_get_cpu0_int_0_31_en_cpu0_jpegenc_int_en(hw);
4183 }
4184
4185 void sys_hal_set_cpu0_int_0_31_en_cpu0_jpegenc_int_en(sys_hw_t *hw, uint32_t value)
4186 {
4187 sys_ll_set_cpu0_int_0_31_en_cpu0_jpegenc_int_en(hw, value);
4188 }
4189
4190 /* REG_0x20:cpu0_int_0_31_en->cpu0_jpegdec_int_en: ,R/W,0x20[26]*/
4191 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_jpegdec_int_en(sys_hw_t *hw)
4192 {
4193 return sys_ll_get_cpu0_int_0_31_en_cpu0_jpegdec_int_en(hw);
4194 }
4195
4196 void sys_hal_set_cpu0_int_0_31_en_cpu0_jpegdec_int_en(sys_hw_t *hw, uint32_t value)
4197 {
4198 sys_ll_set_cpu0_int_0_31_en_cpu0_jpegdec_int_en(hw, value);
4199 }
4200
4201 /* REG_0x20:cpu0_int_0_31_en->cpu0_lcd_int_en: ,R/W,0x20[27]*/
4202 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_lcd_int_en(sys_hw_t *hw)
4203 {
4204 return sys_ll_get_cpu0_int_0_31_en_cpu0_lcd_int_en(hw);
4205 }
4206
4207 void sys_hal_set_cpu0_int_0_31_en_cpu0_lcd_int_en(sys_hw_t *hw, uint32_t value)
4208 {
4209 sys_ll_set_cpu0_int_0_31_en_cpu0_lcd_int_en(hw, value);
4210 }
4211
4212 /* REG_0x20:cpu0_int_0_31_en->cpu0_wifi_int_phy_en: ,R/W,0x20[29]*/
4213 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_wifi_int_phy_en(sys_hw_t *hw)
4214 {
4215 return sys_ll_get_cpu0_int_0_31_en_cpu0_wifi_int_phy_en(hw);
4216 }
4217
4218 void sys_hal_set_cpu0_int_0_31_en_cpu0_wifi_int_phy_en(sys_hw_t *hw, uint32_t value)
4219 {
4220 sys_ll_set_cpu0_int_0_31_en_cpu0_wifi_int_phy_en(hw, value);
4221 }
4222
4223 /* REG_0x20:cpu0_int_0_31_en->cpu0_wifi_mac_int_tx_rx_timer_en: ,R/W,0x20[30]*/
4224 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_wifi_mac_int_tx_rx_timer_en(sys_hw_t *hw)
4225 {
4226 return sys_ll_get_cpu0_int_0_31_en_cpu0_wifi_mac_int_tx_rx_timer_en(hw);
4227 }
4228
4229 void sys_hal_set_cpu0_int_0_31_en_cpu0_wifi_mac_int_tx_rx_timer_en(sys_hw_t *hw, uint32_t value)
4230 {
4231 sys_ll_set_cpu0_int_0_31_en_cpu0_wifi_mac_int_tx_rx_timer_en(hw, value);
4232 }
4233
4234 /* REG_0x20:cpu0_int_0_31_en->cpu0_wifi_mac_int_tx_rx_misc_en: ,R/W,0x20[31]*/
4235 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_wifi_mac_int_tx_rx_misc_en(sys_hw_t *hw)
4236 {
4237 return sys_ll_get_cpu0_int_0_31_en_cpu0_wifi_mac_int_tx_rx_misc_en(hw);
4238 }
4239
4240 void sys_hal_set_cpu0_int_0_31_en_cpu0_wifi_mac_int_tx_rx_misc_en(sys_hw_t *hw, uint32_t value)
4241 {
4242 sys_ll_set_cpu0_int_0_31_en_cpu0_wifi_mac_int_tx_rx_misc_en(hw, value);
4243 }
4244
4245 /* REG_0x21 */
4246
4247 uint32_t sys_hal_get_cpu0_int_32_63_en_value(sys_hw_t *hw)
4248 {
4249 return sys_ll_get_cpu0_int_32_63_en_value(hw);
4250 }
4251
4252 void sys_hal_set_cpu0_int_32_63_en_value(sys_hw_t *hw, uint32_t value)
4253 {
4254 sys_ll_set_cpu0_int_32_63_en_value(hw, value);
4255 }
4256
4257 /* REG_0x21:cpu0_int_32_63_en->cpu0_wifi_mac_int_rx_trigger_en: ,R/W,0x21[0]*/
4258 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_wifi_mac_int_rx_trigger_en(sys_hw_t *hw)
4259 {
4260 return sys_ll_get_cpu0_int_32_63_en_cpu0_wifi_mac_int_rx_trigger_en(hw);
4261 }
4262
4263 void sys_hal_set_cpu0_int_32_63_en_cpu0_wifi_mac_int_rx_trigger_en(sys_hw_t *hw, uint32_t value)
4264 {
4265 sys_ll_set_cpu0_int_32_63_en_cpu0_wifi_mac_int_rx_trigger_en(hw, value);
4266 }
4267
4268 /* REG_0x21:cpu0_int_32_63_en->cpu0_wifi_mac_int_tx_trigger_en: ,R/W,0x21[1]*/
4269 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_wifi_mac_int_tx_trigger_en(sys_hw_t *hw)
4270 {
4271 return sys_ll_get_cpu0_int_32_63_en_cpu0_wifi_mac_int_tx_trigger_en(hw);
4272 }
4273
4274 void sys_hal_set_cpu0_int_32_63_en_cpu0_wifi_mac_int_tx_trigger_en(sys_hw_t *hw, uint32_t value)
4275 {
4276 sys_ll_set_cpu0_int_32_63_en_cpu0_wifi_mac_int_tx_trigger_en(hw, value);
4277 }
4278
4279 /* REG_0x21:cpu0_int_32_63_en->cpu0_wifi_mac_port_trigger_en: ,R/W,0x21[2]*/
4280 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_wifi_mac_port_trigger_en(sys_hw_t *hw)
4281 {
4282 return sys_ll_get_cpu0_int_32_63_en_cpu0_wifi_mac_port_trigger_en(hw);
4283 }
4284
4285 void sys_hal_set_cpu0_int_32_63_en_cpu0_wifi_mac_port_trigger_en(sys_hw_t *hw, uint32_t value)
4286 {
4287 sys_ll_set_cpu0_int_32_63_en_cpu0_wifi_mac_port_trigger_en(hw, value);
4288 }
4289
4290 /* REG_0x21:cpu0_int_32_63_en->cpu0_wifi_mac_int_gen_en: ,R/W,0x21[3]*/
4291 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_wifi_mac_int_gen_en(sys_hw_t *hw)
4292 {
4293 return sys_ll_get_cpu0_int_32_63_en_cpu0_wifi_mac_int_gen_en(hw);
4294 }
4295
4296 void sys_hal_set_cpu0_int_32_63_en_cpu0_wifi_mac_int_gen_en(sys_hw_t *hw, uint32_t value)
4297 {
4298 sys_ll_set_cpu0_int_32_63_en_cpu0_wifi_mac_int_gen_en(hw, value);
4299 }
4300
4301 /* REG_0x21:cpu0_int_32_63_en->cpu0_wifi_hsu_irq_en: ,R/W,0x21[4]*/
4302 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_wifi_hsu_irq_en(sys_hw_t *hw)
4303 {
4304 return sys_ll_get_cpu0_int_32_63_en_cpu0_wifi_hsu_irq_en(hw);
4305 }
4306
4307 void sys_hal_set_cpu0_int_32_63_en_cpu0_wifi_hsu_irq_en(sys_hw_t *hw, uint32_t value)
4308 {
4309 sys_ll_set_cpu0_int_32_63_en_cpu0_wifi_hsu_irq_en(hw, value);
4310 }
4311
4312 /* REG_0x21:cpu0_int_32_63_en->cpu0_wifi_int_mac_wakeup_en: ,R/W,0x21[5]*/
4313 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_wifi_int_mac_wakeup_en(sys_hw_t *hw)
4314 {
4315 return sys_ll_get_cpu0_int_32_63_en_cpu0_wifi_int_mac_wakeup_en(hw);
4316 }
4317
4318 void sys_hal_set_cpu0_int_32_63_en_cpu0_wifi_int_mac_wakeup_en(sys_hw_t *hw, uint32_t value)
4319 {
4320 sys_ll_set_cpu0_int_32_63_en_cpu0_wifi_int_mac_wakeup_en(hw, value);
4321 }
4322
4323 /* REG_0x21:cpu0_int_32_63_en->cpu0_dm_irq_en: ,R/W,0x21[7]*/
4324 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_dm_irq_en(sys_hw_t *hw)
4325 {
4326 return sys_ll_get_cpu0_int_32_63_en_cpu0_dm_irq_en(hw);
4327 }
4328
4329 void sys_hal_set_cpu0_int_32_63_en_cpu0_dm_irq_en(sys_hw_t *hw, uint32_t value)
4330 {
4331 sys_ll_set_cpu0_int_32_63_en_cpu0_dm_irq_en(hw, value);
4332 }
4333
4334 /* REG_0x21:cpu0_int_32_63_en->cpu0_ble_irq_en: ,R/W,0x21[8]*/
4335 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_ble_irq_en(sys_hw_t *hw)
4336 {
4337 return sys_ll_get_cpu0_int_32_63_en_cpu0_ble_irq_en(hw);
4338 }
4339
4340 void sys_hal_set_cpu0_int_32_63_en_cpu0_ble_irq_en(sys_hw_t *hw, uint32_t value)
4341 {
4342 sys_ll_set_cpu0_int_32_63_en_cpu0_ble_irq_en(hw, value);
4343 }
4344
4345 /* REG_0x21:cpu0_int_32_63_en->cpu0_bt_irq_en: ,R/W,0x21[9]*/
4346 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_bt_irq_en(sys_hw_t *hw)
4347 {
4348 return sys_ll_get_cpu0_int_32_63_en_cpu0_bt_irq_en(hw);
4349 }
4350
4351 void sys_hal_set_cpu0_int_32_63_en_cpu0_bt_irq_en(sys_hw_t *hw, uint32_t value)
4352 {
4353 sys_ll_set_cpu0_int_32_63_en_cpu0_bt_irq_en(hw, value);
4354 }
4355
4356 /* REG_0x21:cpu0_int_32_63_en->cpu0_mbox0_int_en: ,R/W,0x21[15]*/
4357 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_mbox0_int_en(sys_hw_t *hw)
4358 {
4359 return sys_ll_get_cpu0_int_32_63_en_cpu0_mbox0_int_en(hw);
4360 }
4361
4362 void sys_hal_set_cpu0_int_32_63_en_cpu0_mbox0_int_en(sys_hw_t *hw, uint32_t value)
4363 {
4364 sys_ll_set_cpu0_int_32_63_en_cpu0_mbox0_int_en(hw, value);
4365 }
4366
4367 /* REG_0x21:cpu0_int_32_63_en->cpu0_mbox1_int_en: ,R/W,0x21[16]*/
4368 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_mbox1_int_en(sys_hw_t *hw)
4369 {
4370 return sys_ll_get_cpu0_int_32_63_en_cpu0_mbox1_int_en(hw);
4371 }
4372
4373 void sys_hal_set_cpu0_int_32_63_en_cpu0_mbox1_int_en(sys_hw_t *hw, uint32_t value)
4374 {
4375 sys_ll_set_cpu0_int_32_63_en_cpu0_mbox1_int_en(hw, value);
4376 }
4377
4378 /* REG_0x21:cpu0_int_32_63_en->cpu0_bmc64_int_en: ,R/W,0x21[17]*/
4379 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_bmc64_int_en(sys_hw_t *hw)
4380 {
4381 return sys_ll_get_cpu0_int_32_63_en_cpu0_bmc64_int_en(hw);
4382 }
4383
4384 void sys_hal_set_cpu0_int_32_63_en_cpu0_bmc64_int_en(sys_hw_t *hw, uint32_t value)
4385 {
4386 sys_ll_set_cpu0_int_32_63_en_cpu0_bmc64_int_en(hw, value);
4387 }
4388
4389 /* REG_0x21:cpu0_int_32_63_en->cpu0_touched_int_en: ,R/W,0x21[19]*/
4390 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_touched_int_en(sys_hw_t *hw)
4391 {
4392 return sys_ll_get_cpu0_int_32_63_en_cpu0_touched_int_en(hw);
4393 }
4394
4395 void sys_hal_set_cpu0_int_32_63_en_cpu0_touched_int_en(sys_hw_t *hw, uint32_t value)
4396 {
4397 sys_ll_set_cpu0_int_32_63_en_cpu0_touched_int_en(hw, value);
4398 }
4399
4400 /* REG_0x21:cpu0_int_32_63_en->cpu0_usbplug_int_en: ,R/W,0x21[20]*/
4401 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_usbplug_int_en(sys_hw_t *hw)
4402 {
4403 return sys_ll_get_cpu0_int_32_63_en_cpu0_usbplug_int_en(hw);
4404 }
4405
4406 void sys_hal_set_cpu0_int_32_63_en_cpu0_usbplug_int_en(sys_hw_t *hw, uint32_t value)
4407 {
4408 sys_ll_set_cpu0_int_32_63_en_cpu0_usbplug_int_en(hw, value);
4409 }
4410
4411 /* REG_0x21:cpu0_int_32_63_en->cpu0_rtc_int_en: ,R/W,0x21[21]*/
4412 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_rtc_int_en(sys_hw_t *hw)
4413 {
4414 return sys_ll_get_cpu0_int_32_63_en_cpu0_rtc_int_en(hw);
4415 }
4416
4417 void sys_hal_set_cpu0_int_32_63_en_cpu0_rtc_int_en(sys_hw_t *hw, uint32_t value)
4418 {
4419 sys_ll_set_cpu0_int_32_63_en_cpu0_rtc_int_en(hw, value);
4420 }
4421
4422 /* REG_0x21:cpu0_int_32_63_en->cpu0_gpio_int_en: ,R/W,0x21[22]*/
4423 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_gpio_int_en(sys_hw_t *hw)
4424 {
4425 return sys_ll_get_cpu0_int_32_63_en_cpu0_gpio_int_en(hw);
4426 }
4427
4428 void sys_hal_set_cpu0_int_32_63_en_cpu0_gpio_int_en(sys_hw_t *hw, uint32_t value)
4429 {
4430 sys_ll_set_cpu0_int_32_63_en_cpu0_gpio_int_en(hw, value);
4431 }
4432
4433 /* REG_0x22 */
4434
4435 uint32_t sys_hal_get_cpu1_int_0_31_en_value(sys_hw_t *hw)
4436 {
4437 return sys_ll_get_cpu1_int_0_31_en_value(hw);
4438 }
4439
4440 void sys_hal_set_cpu1_int_0_31_en_value(sys_hw_t *hw, uint32_t value)
4441 {
4442 sys_ll_set_cpu1_int_0_31_en_value(hw, value);
4443 }
4444
4445 /* REG_0x22:cpu1_int_0_31_en->cpu1_bmc32_int_en: ,R/W,0x22[0]*/
4446 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_bmc32_int_en(sys_hw_t *hw)
4447 {
4448 return sys_ll_get_cpu1_int_0_31_en_cpu1_bmc32_int_en(hw);
4449 }
4450
4451 void sys_hal_set_cpu1_int_0_31_en_cpu1_bmc32_int_en(sys_hw_t *hw, uint32_t value)
4452 {
4453 sys_ll_set_cpu1_int_0_31_en_cpu1_bmc32_int_en(hw, value);
4454 }
4455
4456 /* REG_0x22:cpu1_int_0_31_en->cpu1_host_0_irq_en: ,R/W,0x22[1]*/
4457 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_host_0_irq_en(sys_hw_t *hw)
4458 {
4459 return sys_ll_get_cpu1_int_0_31_en_cpu1_host_0_irq_en(hw);
4460 }
4461
4462 void sys_hal_set_cpu1_int_0_31_en_cpu1_host_0_irq_en(sys_hw_t *hw, uint32_t value)
4463 {
4464 sys_ll_set_cpu1_int_0_31_en_cpu1_host_0_irq_en(hw, value);
4465 }
4466
4467 /* REG_0x22:cpu1_int_0_31_en->cpu1_host_0_sec_irq_en: ,R/W,0x22[2]*/
4468 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_host_0_sec_irq_en(sys_hw_t *hw)
4469 {
4470 return sys_ll_get_cpu1_int_0_31_en_cpu1_host_0_sec_irq_en(hw);
4471 }
4472
4473 void sys_hal_set_cpu1_int_0_31_en_cpu1_host_0_sec_irq_en(sys_hw_t *hw, uint32_t value)
4474 {
4475 sys_ll_set_cpu1_int_0_31_en_cpu1_host_0_sec_irq_en(hw, value);
4476 }
4477
4478 /* REG_0x22:cpu1_int_0_31_en->cpu1_timer_int_en: ,R/W,0x22[3]*/
4479 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_timer_int_en(sys_hw_t *hw)
4480 {
4481 return sys_ll_get_cpu1_int_0_31_en_cpu1_timer_int_en(hw);
4482 }
4483
4484 void sys_hal_set_cpu1_int_0_31_en_cpu1_timer_int_en(sys_hw_t *hw, uint32_t value)
4485 {
4486 sys_ll_set_cpu1_int_0_31_en_cpu1_timer_int_en(hw, value);
4487 }
4488
4489 /* REG_0x22:cpu1_int_0_31_en->cpu1_uart_int_en: ,R/W,0x22[4]*/
4490 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_uart_int_en(sys_hw_t *hw)
4491 {
4492 return sys_ll_get_cpu1_int_0_31_en_cpu1_uart_int_en(hw);
4493 }
4494
4495 void sys_hal_set_cpu1_int_0_31_en_cpu1_uart_int_en(sys_hw_t *hw, uint32_t value)
4496 {
4497 sys_ll_set_cpu1_int_0_31_en_cpu1_uart_int_en(hw, value);
4498 }
4499
4500 /* REG_0x22:cpu1_int_0_31_en->cpu1_pwm_int_en: ,R/W,0x22[5]*/
4501 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_pwm_int_en(sys_hw_t *hw)
4502 {
4503 return sys_ll_get_cpu1_int_0_31_en_cpu1_pwm_int_en(hw);
4504 }
4505
4506 void sys_hal_set_cpu1_int_0_31_en_cpu1_pwm_int_en(sys_hw_t *hw, uint32_t value)
4507 {
4508 sys_ll_set_cpu1_int_0_31_en_cpu1_pwm_int_en(hw, value);
4509 }
4510
4511 /* REG_0x22:cpu1_int_0_31_en->cpu1_i2c_int_en: ,R/W,0x22[6]*/
4512 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_i2c_int_en(sys_hw_t *hw)
4513 {
4514 return sys_ll_get_cpu1_int_0_31_en_cpu1_i2c_int_en(hw);
4515 }
4516
4517 void sys_hal_set_cpu1_int_0_31_en_cpu1_i2c_int_en(sys_hw_t *hw, uint32_t value)
4518 {
4519 sys_ll_set_cpu1_int_0_31_en_cpu1_i2c_int_en(hw, value);
4520 }
4521
4522 /* REG_0x22:cpu1_int_0_31_en->cpu1_spi_int_en: ,R/W,0x22[7]*/
4523 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_spi_int_en(sys_hw_t *hw)
4524 {
4525 return sys_ll_get_cpu1_int_0_31_en_cpu1_spi_int_en(hw);
4526 }
4527
4528 void sys_hal_set_cpu1_int_0_31_en_cpu1_spi_int_en(sys_hw_t *hw, uint32_t value)
4529 {
4530 sys_ll_set_cpu1_int_0_31_en_cpu1_spi_int_en(hw, value);
4531 }
4532
4533 /* REG_0x22:cpu1_int_0_31_en->cpu1_sadc_int_en: ,R/W,0x22[8]*/
4534 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_sadc_int_en(sys_hw_t *hw)
4535 {
4536 return sys_ll_get_cpu1_int_0_31_en_cpu1_sadc_int_en(hw);
4537 }
4538
4539 void sys_hal_set_cpu1_int_0_31_en_cpu1_sadc_int_en(sys_hw_t *hw, uint32_t value)
4540 {
4541 sys_ll_set_cpu1_int_0_31_en_cpu1_sadc_int_en(hw, value);
4542 }
4543
4544 /* REG_0x22:cpu1_int_0_31_en->cpu1_irda_int_en: ,R/W,0x22[9]*/
4545 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_irda_int_en(sys_hw_t *hw)
4546 {
4547 return sys_ll_get_cpu1_int_0_31_en_cpu1_irda_int_en(hw);
4548 }
4549
4550 void sys_hal_set_cpu1_int_0_31_en_cpu1_irda_int_en(sys_hw_t *hw, uint32_t value)
4551 {
4552 sys_ll_set_cpu1_int_0_31_en_cpu1_irda_int_en(hw, value);
4553 }
4554
4555 /* REG_0x22:cpu1_int_0_31_en->cpu1_sdio_int_en: ,R/W,0x22[10]*/
4556 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_sdio_int_en(sys_hw_t *hw)
4557 {
4558 return sys_ll_get_cpu1_int_0_31_en_cpu1_sdio_int_en(hw);
4559 }
4560
4561 void sys_hal_set_cpu1_int_0_31_en_cpu1_sdio_int_en(sys_hw_t *hw, uint32_t value)
4562 {
4563 sys_ll_set_cpu1_int_0_31_en_cpu1_sdio_int_en(hw, value);
4564 }
4565
4566 /* REG_0x22:cpu1_int_0_31_en->cpu1_gdma_int_en: ,R/W,0x22[11]*/
4567 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_gdma_int_en(sys_hw_t *hw)
4568 {
4569 return sys_ll_get_cpu1_int_0_31_en_cpu1_gdma_int_en(hw);
4570 }
4571
4572 void sys_hal_set_cpu1_int_0_31_en_cpu1_gdma_int_en(sys_hw_t *hw, uint32_t value)
4573 {
4574 sys_ll_set_cpu1_int_0_31_en_cpu1_gdma_int_en(hw, value);
4575 }
4576
4577 /* REG_0x22:cpu1_int_0_31_en->cpu1_la_int_en: ,R/W,0x22[12]*/
4578 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_la_int_en(sys_hw_t *hw)
4579 {
4580 return sys_ll_get_cpu1_int_0_31_en_cpu1_la_int_en(hw);
4581 }
4582
4583 void sys_hal_set_cpu1_int_0_31_en_cpu1_la_int_en(sys_hw_t *hw, uint32_t value)
4584 {
4585 sys_ll_set_cpu1_int_0_31_en_cpu1_la_int_en(hw, value);
4586 }
4587
4588 /* REG_0x22:cpu1_int_0_31_en->cpu1_timer1_int_en: ,R/W,0x22[13]*/
4589 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_timer1_int_en(sys_hw_t *hw)
4590 {
4591 return sys_ll_get_cpu1_int_0_31_en_cpu1_timer1_int_en(hw);
4592 }
4593
4594 void sys_hal_set_cpu1_int_0_31_en_cpu1_timer1_int_en(sys_hw_t *hw, uint32_t value)
4595 {
4596 sys_ll_set_cpu1_int_0_31_en_cpu1_timer1_int_en(hw, value);
4597 }
4598
4599 /* REG_0x22:cpu1_int_0_31_en->cpu1_i2c1_int_en: ,R/W,0x22[14]*/
4600 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_i2c1_int_en(sys_hw_t *hw)
4601 {
4602 return sys_ll_get_cpu1_int_0_31_en_cpu1_i2c1_int_en(hw);
4603 }
4604
4605 void sys_hal_set_cpu1_int_0_31_en_cpu1_i2c1_int_en(sys_hw_t *hw, uint32_t value)
4606 {
4607 sys_ll_set_cpu1_int_0_31_en_cpu1_i2c1_int_en(hw, value);
4608 }
4609
4610 /* REG_0x22:cpu1_int_0_31_en->cpu1_uart1_int_en: ,R/W,0x22[15]*/
4611 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_uart1_int_en(sys_hw_t *hw)
4612 {
4613 return sys_ll_get_cpu1_int_0_31_en_cpu1_uart1_int_en(hw);
4614 }
4615
4616 void sys_hal_set_cpu1_int_0_31_en_cpu1_uart1_int_en(sys_hw_t *hw, uint32_t value)
4617 {
4618 sys_ll_set_cpu1_int_0_31_en_cpu1_uart1_int_en(hw, value);
4619 }
4620
4621 /* REG_0x22:cpu1_int_0_31_en->cpu1_uart2_int_en: ,R/W,0x22[16]*/
4622 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_uart2_int_en(sys_hw_t *hw)
4623 {
4624 return sys_ll_get_cpu1_int_0_31_en_cpu1_uart2_int_en(hw);
4625 }
4626
4627 void sys_hal_set_cpu1_int_0_31_en_cpu1_uart2_int_en(sys_hw_t *hw, uint32_t value)
4628 {
4629 sys_ll_set_cpu1_int_0_31_en_cpu1_uart2_int_en(hw, value);
4630 }
4631
4632 /* REG_0x22:cpu1_int_0_31_en->cpu1_spi1_int_en: ,R/W,0x22[17]*/
4633 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_spi1_int_en(sys_hw_t *hw)
4634 {
4635 return sys_ll_get_cpu1_int_0_31_en_cpu1_spi1_int_en(hw);
4636 }
4637
4638 void sys_hal_set_cpu1_int_0_31_en_cpu1_spi1_int_en(sys_hw_t *hw, uint32_t value)
4639 {
4640 sys_ll_set_cpu1_int_0_31_en_cpu1_spi1_int_en(hw, value);
4641 }
4642
4643 /* REG_0x22:cpu1_int_0_31_en->cpu1_can_int_en: ,R/W,0x22[18]*/
4644 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_can_int_en(sys_hw_t *hw)
4645 {
4646 return sys_ll_get_cpu1_int_0_31_en_cpu1_can_int_en(hw);
4647 }
4648
4649 void sys_hal_set_cpu1_int_0_31_en_cpu1_can_int_en(sys_hw_t *hw, uint32_t value)
4650 {
4651 sys_ll_set_cpu1_int_0_31_en_cpu1_can_int_en(hw, value);
4652 }
4653
4654 /* REG_0x22:cpu1_int_0_31_en->cpu1_usb_int_en: ,R/W,0x22[19]*/
4655 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_usb_int_en(sys_hw_t *hw)
4656 {
4657 return sys_ll_get_cpu1_int_0_31_en_cpu1_usb_int_en(hw);
4658 }
4659
4660 void sys_hal_set_cpu1_int_0_31_en_cpu1_usb_int_en(sys_hw_t *hw, uint32_t value)
4661 {
4662 sys_ll_set_cpu1_int_0_31_en_cpu1_usb_int_en(hw, value);
4663 }
4664
4665 /* REG_0x22:cpu1_int_0_31_en->cpu1_qspi_int_en: ,R/W,0x22[20]*/
4666 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_qspi_int_en(sys_hw_t *hw)
4667 {
4668 return sys_ll_get_cpu1_int_0_31_en_cpu1_qspi_int_en(hw);
4669 }
4670
4671 void sys_hal_set_cpu1_int_0_31_en_cpu1_qspi_int_en(sys_hw_t *hw, uint32_t value)
4672 {
4673 sys_ll_set_cpu1_int_0_31_en_cpu1_qspi_int_en(hw, value);
4674 }
4675
4676 /* REG_0x22:cpu1_int_0_31_en->cpu1_fft_int_en: ,R/W,0x22[21]*/
4677 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_fft_int_en(sys_hw_t *hw)
4678 {
4679 return sys_ll_get_cpu1_int_0_31_en_cpu1_fft_int_en(hw);
4680 }
4681
4682 void sys_hal_set_cpu1_int_0_31_en_cpu1_fft_int_en(sys_hw_t *hw, uint32_t value)
4683 {
4684 sys_ll_set_cpu1_int_0_31_en_cpu1_fft_int_en(hw, value);
4685 }
4686
4687 /* REG_0x22:cpu1_int_0_31_en->cpu1_sbc_int_en: ,R/W,0x22[22]*/
4688 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_sbc_int_en(sys_hw_t *hw)
4689 {
4690 return sys_ll_get_cpu1_int_0_31_en_cpu1_sbc_int_en(hw);
4691 }
4692
4693 void sys_hal_set_cpu1_int_0_31_en_cpu1_sbc_int_en(sys_hw_t *hw, uint32_t value)
4694 {
4695 sys_ll_set_cpu1_int_0_31_en_cpu1_sbc_int_en(hw, value);
4696 }
4697
4698 /* REG_0x22:cpu1_int_0_31_en->cpu1_aud_int_en: ,R/W,0x22[23]*/
4699 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_aud_int_en(sys_hw_t *hw)
4700 {
4701 return sys_ll_get_cpu1_int_0_31_en_cpu1_aud_int_en(hw);
4702 }
4703
4704 void sys_hal_set_cpu1_int_0_31_en_cpu1_aud_int_en(sys_hw_t *hw, uint32_t value)
4705 {
4706 sys_ll_set_cpu1_int_0_31_en_cpu1_aud_int_en(hw, value);
4707 }
4708
4709 /* REG_0x22:cpu1_int_0_31_en->cpu1_i2s_int_en: ,R/W,0x22[24]*/
4710 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_i2s_int_en(sys_hw_t *hw)
4711 {
4712 return sys_ll_get_cpu1_int_0_31_en_cpu1_i2s_int_en(hw);
4713 }
4714
4715 void sys_hal_set_cpu1_int_0_31_en_cpu1_i2s_int_en(sys_hw_t *hw, uint32_t value)
4716 {
4717 sys_ll_set_cpu1_int_0_31_en_cpu1_i2s_int_en(hw, value);
4718 }
4719
4720 /* REG_0x22:cpu1_int_0_31_en->cpu1_jpegenc_int_en: ,R/W,0x22[25]*/
4721 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_jpegenc_int_en(sys_hw_t *hw)
4722 {
4723 return sys_ll_get_cpu1_int_0_31_en_cpu1_jpegenc_int_en(hw);
4724 }
4725
4726 void sys_hal_set_cpu1_int_0_31_en_cpu1_jpegenc_int_en(sys_hw_t *hw, uint32_t value)
4727 {
4728 sys_ll_set_cpu1_int_0_31_en_cpu1_jpegenc_int_en(hw, value);
4729 }
4730
4731 /* REG_0x22:cpu1_int_0_31_en->cpu1_jpegdec_int_en: ,R/W,0x22[26]*/
4732 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_jpegdec_int_en(sys_hw_t *hw)
4733 {
4734 return sys_ll_get_cpu1_int_0_31_en_cpu1_jpegdec_int_en(hw);
4735 }
4736
4737 void sys_hal_set_cpu1_int_0_31_en_cpu1_jpegdec_int_en(sys_hw_t *hw, uint32_t value)
4738 {
4739 sys_ll_set_cpu1_int_0_31_en_cpu1_jpegdec_int_en(hw, value);
4740 }
4741
4742 /* REG_0x22:cpu1_int_0_31_en->cpu1_lcd_int_en: ,R/W,0x22[27]*/
4743 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_lcd_int_en(sys_hw_t *hw)
4744 {
4745 return sys_ll_get_cpu1_int_0_31_en_cpu1_lcd_int_en(hw);
4746 }
4747
4748 void sys_hal_set_cpu1_int_0_31_en_cpu1_lcd_int_en(sys_hw_t *hw, uint32_t value)
4749 {
4750 sys_ll_set_cpu1_int_0_31_en_cpu1_lcd_int_en(hw, value);
4751 }
4752
4753 /* REG_0x22:cpu1_int_0_31_en->cpu1_wifi_int_phy_en: ,R/W,0x22[29]*/
4754 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_wifi_int_phy_en(sys_hw_t *hw)
4755 {
4756 return sys_ll_get_cpu1_int_0_31_en_cpu1_wifi_int_phy_en(hw);
4757 }
4758
4759 void sys_hal_set_cpu1_int_0_31_en_cpu1_wifi_int_phy_en(sys_hw_t *hw, uint32_t value)
4760 {
4761 sys_ll_set_cpu1_int_0_31_en_cpu1_wifi_int_phy_en(hw, value);
4762 }
4763
4764 /* REG_0x22:cpu1_int_0_31_en->cpu1_wifi_mac_int_tx_rx_timer_en: ,R/W,0x22[30]*/
4765 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_wifi_mac_int_tx_rx_timer_en(sys_hw_t *hw)
4766 {
4767 return sys_ll_get_cpu1_int_0_31_en_cpu1_wifi_mac_int_tx_rx_timer_en(hw);
4768 }
4769
4770 void sys_hal_set_cpu1_int_0_31_en_cpu1_wifi_mac_int_tx_rx_timer_en(sys_hw_t *hw, uint32_t value)
4771 {
4772 sys_ll_set_cpu1_int_0_31_en_cpu1_wifi_mac_int_tx_rx_timer_en(hw, value);
4773 }
4774
4775 /* REG_0x22:cpu1_int_0_31_en->cpu1_wifi_mac_int_tx_rx_misc_en: ,R/W,0x22[31]*/
4776 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_wifi_mac_int_tx_rx_misc_en(sys_hw_t *hw)
4777 {
4778 return sys_ll_get_cpu1_int_0_31_en_cpu1_wifi_mac_int_tx_rx_misc_en(hw);
4779 }
4780
4781 void sys_hal_set_cpu1_int_0_31_en_cpu1_wifi_mac_int_tx_rx_misc_en(sys_hw_t *hw, uint32_t value)
4782 {
4783 sys_ll_set_cpu1_int_0_31_en_cpu1_wifi_mac_int_tx_rx_misc_en(hw, value);
4784 }
4785
4786 /* REG_0x23 */
4787
4788 uint32_t sys_hal_get_cpu1_int_32_63_en_value(sys_hw_t *hw)
4789 {
4790 return sys_ll_get_cpu1_int_32_63_en_value(hw);
4791 }
4792
4793 void sys_hal_set_cpu1_int_32_63_en_value(sys_hw_t *hw, uint32_t value)
4794 {
4795 sys_ll_set_cpu1_int_32_63_en_value(hw, value);
4796 }
4797
4798 /* REG_0x23:cpu1_int_32_63_en->cpu1_wifi_mac_int_rx_trigger_en: ,R/W,0x23[0]*/
4799 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_wifi_mac_int_rx_trigger_en(sys_hw_t *hw)
4800 {
4801 return sys_ll_get_cpu1_int_32_63_en_cpu1_wifi_mac_int_rx_trigger_en(hw);
4802 }
4803
4804 void sys_hal_set_cpu1_int_32_63_en_cpu1_wifi_mac_int_rx_trigger_en(sys_hw_t *hw, uint32_t value)
4805 {
4806 sys_ll_set_cpu1_int_32_63_en_cpu1_wifi_mac_int_rx_trigger_en(hw, value);
4807 }
4808
4809 /* REG_0x23:cpu1_int_32_63_en->cpu1_wifi_mac_int_tx_trigger_en: ,R/W,0x23[1]*/
4810 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_wifi_mac_int_tx_trigger_en(sys_hw_t *hw)
4811 {
4812 return sys_ll_get_cpu1_int_32_63_en_cpu1_wifi_mac_int_tx_trigger_en(hw);
4813 }
4814
4815 void sys_hal_set_cpu1_int_32_63_en_cpu1_wifi_mac_int_tx_trigger_en(sys_hw_t *hw, uint32_t value)
4816 {
4817 sys_ll_set_cpu1_int_32_63_en_cpu1_wifi_mac_int_tx_trigger_en(hw, value);
4818 }
4819
4820 /* REG_0x23:cpu1_int_32_63_en->cpu1_wifi_mac_port_trigger_en: ,R/W,0x23[2]*/
4821 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_wifi_mac_port_trigger_en(sys_hw_t *hw)
4822 {
4823 return sys_ll_get_cpu1_int_32_63_en_cpu1_wifi_mac_port_trigger_en(hw);
4824 }
4825
4826 void sys_hal_set_cpu1_int_32_63_en_cpu1_wifi_mac_port_trigger_en(sys_hw_t *hw, uint32_t value)
4827 {
4828 sys_ll_set_cpu1_int_32_63_en_cpu1_wifi_mac_port_trigger_en(hw, value);
4829 }
4830
4831 /* REG_0x23:cpu1_int_32_63_en->cpu1_wifi_mac_int_gen_en: ,R/W,0x23[3]*/
4832 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_wifi_mac_int_gen_en(sys_hw_t *hw)
4833 {
4834 return sys_ll_get_cpu1_int_32_63_en_cpu1_wifi_mac_int_gen_en(hw);
4835 }
4836
4837 void sys_hal_set_cpu1_int_32_63_en_cpu1_wifi_mac_int_gen_en(sys_hw_t *hw, uint32_t value)
4838 {
4839 sys_ll_set_cpu1_int_32_63_en_cpu1_wifi_mac_int_gen_en(hw, value);
4840 }
4841
4842 /* REG_0x23:cpu1_int_32_63_en->cpu1_wifi_hsu_irq_en: ,R/W,0x23[4]*/
4843 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_wifi_hsu_irq_en(sys_hw_t *hw)
4844 {
4845 return sys_ll_get_cpu1_int_32_63_en_cpu1_wifi_hsu_irq_en(hw);
4846 }
4847
4848 void sys_hal_set_cpu1_int_32_63_en_cpu1_wifi_hsu_irq_en(sys_hw_t *hw, uint32_t value)
4849 {
4850 sys_ll_set_cpu1_int_32_63_en_cpu1_wifi_hsu_irq_en(hw, value);
4851 }
4852
4853 /* REG_0x23:cpu1_int_32_63_en->cpu1_wifi_int_mac_wakeup_en: ,R/W,0x23[5]*/
4854 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_wifi_int_mac_wakeup_en(sys_hw_t *hw)
4855 {
4856 return sys_ll_get_cpu1_int_32_63_en_cpu1_wifi_int_mac_wakeup_en(hw);
4857 }
4858
4859 void sys_hal_set_cpu1_int_32_63_en_cpu1_wifi_int_mac_wakeup_en(sys_hw_t *hw, uint32_t value)
4860 {
4861 sys_ll_set_cpu1_int_32_63_en_cpu1_wifi_int_mac_wakeup_en(hw, value);
4862 }
4863
4864 /* REG_0x23:cpu1_int_32_63_en->cpu1_dm_irq_en: ,R/W,0x23[7]*/
4865 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_dm_irq_en(sys_hw_t *hw)
4866 {
4867 return sys_ll_get_cpu1_int_32_63_en_cpu1_dm_irq_en(hw);
4868 }
4869
4870 void sys_hal_set_cpu1_int_32_63_en_cpu1_dm_irq_en(sys_hw_t *hw, uint32_t value)
4871 {
4872 sys_ll_set_cpu1_int_32_63_en_cpu1_dm_irq_en(hw, value);
4873 }
4874
4875 /* REG_0x23:cpu1_int_32_63_en->cpu1_ble_irq_en: ,R/W,0x23[8]*/
4876 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_ble_irq_en(sys_hw_t *hw)
4877 {
4878 return sys_ll_get_cpu1_int_32_63_en_cpu1_ble_irq_en(hw);
4879 }
4880
4881 void sys_hal_set_cpu1_int_32_63_en_cpu1_ble_irq_en(sys_hw_t *hw, uint32_t value)
4882 {
4883 sys_ll_set_cpu1_int_32_63_en_cpu1_ble_irq_en(hw, value);
4884 }
4885
4886 /* REG_0x23:cpu1_int_32_63_en->cpu1_bt_irq_en: ,R/W,0x23[9]*/
4887 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_bt_irq_en(sys_hw_t *hw)
4888 {
4889 return sys_ll_get_cpu1_int_32_63_en_cpu1_bt_irq_en(hw);
4890 }
4891
4892 void sys_hal_set_cpu1_int_32_63_en_cpu1_bt_irq_en(sys_hw_t *hw, uint32_t value)
4893 {
4894 sys_ll_set_cpu1_int_32_63_en_cpu1_bt_irq_en(hw, value);
4895 }
4896
4897 /* REG_0x23:cpu1_int_32_63_en->cpu1_mbox0_int_en: ,R/W,0x23[15]*/
4898 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_mbox0_int_en(sys_hw_t *hw)
4899 {
4900 return sys_ll_get_cpu1_int_32_63_en_cpu1_mbox0_int_en(hw);
4901 }
4902
4903 void sys_hal_set_cpu1_int_32_63_en_cpu1_mbox0_int_en(sys_hw_t *hw, uint32_t value)
4904 {
4905 sys_ll_set_cpu1_int_32_63_en_cpu1_mbox0_int_en(hw, value);
4906 }
4907
4908 /* REG_0x23:cpu1_int_32_63_en->cpu1_mbox1_int_en: ,R/W,0x23[16]*/
4909 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_mbox1_int_en(sys_hw_t *hw)
4910 {
4911 return sys_ll_get_cpu1_int_32_63_en_cpu1_mbox1_int_en(hw);
4912 }
4913
4914 void sys_hal_set_cpu1_int_32_63_en_cpu1_mbox1_int_en(sys_hw_t *hw, uint32_t value)
4915 {
4916 sys_ll_set_cpu1_int_32_63_en_cpu1_mbox1_int_en(hw, value);
4917 }
4918
4919 /* REG_0x23:cpu1_int_32_63_en->cpu1_bmc64_int_en: ,R/W,0x23[17]*/
4920 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_bmc64_int_en(sys_hw_t *hw)
4921 {
4922 return sys_ll_get_cpu1_int_32_63_en_cpu1_bmc64_int_en(hw);
4923 }
4924
4925 void sys_hal_set_cpu1_int_32_63_en_cpu1_bmc64_int_en(sys_hw_t *hw, uint32_t value)
4926 {
4927 sys_ll_set_cpu1_int_32_63_en_cpu1_bmc64_int_en(hw, value);
4928 }
4929
4930 /* REG_0x23:cpu1_int_32_63_en->cpu1_touched_int_en: ,R/W,0x23[19]*/
4931 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_touched_int_en(sys_hw_t *hw)
4932 {
4933 return sys_ll_get_cpu1_int_32_63_en_cpu1_touched_int_en(hw);
4934 }
4935
4936 void sys_hal_set_cpu1_int_32_63_en_cpu1_touched_int_en(sys_hw_t *hw, uint32_t value)
4937 {
4938 sys_ll_set_cpu1_int_32_63_en_cpu1_touched_int_en(hw, value);
4939 }
4940
4941 /* REG_0x23:cpu1_int_32_63_en->cpu1_usbplug_int_en: ,R/W,0x23[20]*/
4942 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_usbplug_int_en(sys_hw_t *hw)
4943 {
4944 return sys_ll_get_cpu1_int_32_63_en_cpu1_usbplug_int_en(hw);
4945 }
4946
4947 void sys_hal_set_cpu1_int_32_63_en_cpu1_usbplug_int_en(sys_hw_t *hw, uint32_t value)
4948 {
4949 sys_ll_set_cpu1_int_32_63_en_cpu1_usbplug_int_en(hw, value);
4950 }
4951
4952 /* REG_0x23:cpu1_int_32_63_en->cpu1_rtc_int_en: ,R/W,0x23[21]*/
4953 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_rtc_int_en(sys_hw_t *hw)
4954 {
4955 return sys_ll_get_cpu1_int_32_63_en_cpu1_rtc_int_en(hw);
4956 }
4957
4958 void sys_hal_set_cpu1_int_32_63_en_cpu1_rtc_int_en(sys_hw_t *hw, uint32_t value)
4959 {
4960 sys_ll_set_cpu1_int_32_63_en_cpu1_rtc_int_en(hw, value);
4961 }
4962
4963 /* REG_0x23:cpu1_int_32_63_en->cpu1_gpio_int_en: ,R/W,0x23[22]*/
4964 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_gpio_int_en(sys_hw_t *hw)
4965 {
4966 return sys_ll_get_cpu1_int_32_63_en_cpu1_gpio_int_en(hw);
4967 }
4968
4969 void sys_hal_set_cpu1_int_32_63_en_cpu1_gpio_int_en(sys_hw_t *hw, uint32_t value)
4970 {
4971 sys_ll_set_cpu1_int_32_63_en_cpu1_gpio_int_en(hw, value);
4972 }
4973
4974 /* REG_0x28 */
4975
4976 uint32_t sys_hal_get_cpu0_int_0_31_status_value(sys_hw_t *hw)
4977 {
4978 return sys_ll_get_cpu0_int_0_31_status_value(hw);
4979 }
4980
4981 /* REG_0x28:cpu0_int_0_31_status->cpu0_bmc32_int_st: ,R,0x28[0]*/
4982 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_bmc32_int_st(sys_hw_t *hw)
4983 {
4984 return sys_ll_get_cpu0_int_0_31_status_cpu0_bmc32_int_st(hw);
4985 }
4986
4987 /* REG_0x28:cpu0_int_0_31_status->cpu0_host_0_irq_st: ,R,0x28[1]*/
4988 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_host_0_irq_st(sys_hw_t *hw)
4989 {
4990 return sys_ll_get_cpu0_int_0_31_status_cpu0_host_0_irq_st(hw);
4991 }
4992
4993 /* REG_0x28:cpu0_int_0_31_status->cpu0_host_0_sec_irq_st: ,R,0x28[2]*/
4994 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_host_0_sec_irq_st(sys_hw_t *hw)
4995 {
4996 return sys_ll_get_cpu0_int_0_31_status_cpu0_host_0_sec_irq_st(hw);
4997 }
4998
4999 /* REG_0x28:cpu0_int_0_31_status->cpu0_timer_int_st: ,R,0x28[3]*/
5000 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_timer_int_st(sys_hw_t *hw)
5001 {
5002 return sys_ll_get_cpu0_int_0_31_status_cpu0_timer_int_st(hw);
5003 }
5004
5005 /* REG_0x28:cpu0_int_0_31_status->cpu0_uart_int_st: ,R,0x28[4]*/
5006 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_uart_int_st(sys_hw_t *hw)
5007 {
5008 return sys_ll_get_cpu0_int_0_31_status_cpu0_uart_int_st(hw);
5009 }
5010
5011 /* REG_0x28:cpu0_int_0_31_status->cpu0_pwm_int_st: ,R,0x28[5]*/
5012 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_pwm_int_st(sys_hw_t *hw)
5013 {
5014 return sys_ll_get_cpu0_int_0_31_status_cpu0_pwm_int_st(hw);
5015 }
5016
5017 /* REG_0x28:cpu0_int_0_31_status->cpu0_i2c_int_st: ,R,0x28[6]*/
5018 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_i2c_int_st(sys_hw_t *hw)
5019 {
5020 return sys_ll_get_cpu0_int_0_31_status_cpu0_i2c_int_st(hw);
5021 }
5022
5023 /* REG_0x28:cpu0_int_0_31_status->cpu0_spi_int_st: ,R,0x28[7]*/
5024 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_spi_int_st(sys_hw_t *hw)
5025 {
5026 return sys_ll_get_cpu0_int_0_31_status_cpu0_spi_int_st(hw);
5027 }
5028
5029 /* REG_0x28:cpu0_int_0_31_status->cpu0_sadc_int_st: ,R,0x28[8]*/
5030 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_sadc_int_st(sys_hw_t *hw)
5031 {
5032 return sys_ll_get_cpu0_int_0_31_status_cpu0_sadc_int_st(hw);
5033 }
5034
5035 /* REG_0x28:cpu0_int_0_31_status->cpu0_irda_int_st: ,R,0x28[9]*/
5036 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_irda_int_st(sys_hw_t *hw)
5037 {
5038 return sys_ll_get_cpu0_int_0_31_status_cpu0_irda_int_st(hw);
5039 }
5040
5041 /* REG_0x28:cpu0_int_0_31_status->cpu0_sdio_int_st: ,R,0x28[10]*/
5042 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_sdio_int_st(sys_hw_t *hw)
5043 {
5044 return sys_ll_get_cpu0_int_0_31_status_cpu0_sdio_int_st(hw);
5045 }
5046
5047 /* REG_0x28:cpu0_int_0_31_status->cpu0_gdma_int_st: ,R,0x28[11]*/
5048 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_gdma_int_st(sys_hw_t *hw)
5049 {
5050 return sys_ll_get_cpu0_int_0_31_status_cpu0_gdma_int_st(hw);
5051 }
5052
5053 /* REG_0x28:cpu0_int_0_31_status->cpu0_la_int_st: ,R,0x28[12]*/
5054 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_la_int_st(sys_hw_t *hw)
5055 {
5056 return sys_ll_get_cpu0_int_0_31_status_cpu0_la_int_st(hw);
5057 }
5058
5059 /* REG_0x28:cpu0_int_0_31_status->cpu0_timer1_int_st: ,R,0x28[13]*/
5060 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_timer1_int_st(sys_hw_t *hw)
5061 {
5062 return sys_ll_get_cpu0_int_0_31_status_cpu0_timer1_int_st(hw);
5063 }
5064
5065 /* REG_0x28:cpu0_int_0_31_status->cpu0_i2c1_int_st: ,R,0x28[14]*/
5066 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_i2c1_int_st(sys_hw_t *hw)
5067 {
5068 return sys_ll_get_cpu0_int_0_31_status_cpu0_i2c1_int_st(hw);
5069 }
5070
5071 /* REG_0x28:cpu0_int_0_31_status->cpu0_uart1_int_st: ,R,0x28[15]*/
5072 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_uart1_int_st(sys_hw_t *hw)
5073 {
5074 return sys_ll_get_cpu0_int_0_31_status_cpu0_uart1_int_st(hw);
5075 }
5076
5077 /* REG_0x28:cpu0_int_0_31_status->cpu0_uart2_int_st: ,R,0x28[16]*/
5078 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_uart2_int_st(sys_hw_t *hw)
5079 {
5080 return sys_ll_get_cpu0_int_0_31_status_cpu0_uart2_int_st(hw);
5081 }
5082
5083 /* REG_0x28:cpu0_int_0_31_status->cpu0_spi1_int_st: ,R,0x28[17]*/
5084 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_spi1_int_st(sys_hw_t *hw)
5085 {
5086 return sys_ll_get_cpu0_int_0_31_status_cpu0_spi1_int_st(hw);
5087 }
5088
5089 /* REG_0x28:cpu0_int_0_31_status->cpu0_can_int_st: ,R,0x28[18]*/
5090 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_can_int_st(sys_hw_t *hw)
5091 {
5092 return sys_ll_get_cpu0_int_0_31_status_cpu0_can_int_st(hw);
5093 }
5094
5095 /* REG_0x28:cpu0_int_0_31_status->cpu0_usb_int_st: ,R,0x28[19]*/
5096 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_usb_int_st(sys_hw_t *hw)
5097 {
5098 return sys_ll_get_cpu0_int_0_31_status_cpu0_usb_int_st(hw);
5099 }
5100
5101 /* REG_0x28:cpu0_int_0_31_status->cpu0_qspi_int_st: ,R,0x28[20]*/
5102 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_qspi_int_st(sys_hw_t *hw)
5103 {
5104 return sys_ll_get_cpu0_int_0_31_status_cpu0_qspi_int_st(hw);
5105 }
5106
5107 /* REG_0x28:cpu0_int_0_31_status->cpu0_fft_int_st: ,R,0x28[21]*/
5108 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_fft_int_st(sys_hw_t *hw)
5109 {
5110 return sys_ll_get_cpu0_int_0_31_status_cpu0_fft_int_st(hw);
5111 }
5112
5113 /* REG_0x28:cpu0_int_0_31_status->cpu0_sbc_int_st: ,R,0x28[22]*/
5114 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_sbc_int_st(sys_hw_t *hw)
5115 {
5116 return sys_ll_get_cpu0_int_0_31_status_cpu0_sbc_int_st(hw);
5117 }
5118
5119 /* REG_0x28:cpu0_int_0_31_status->cpu0_aud_int_st: ,R,0x28[23]*/
5120 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_aud_int_st(sys_hw_t *hw)
5121 {
5122 return sys_ll_get_cpu0_int_0_31_status_cpu0_aud_int_st(hw);
5123 }
5124
5125 /* REG_0x28:cpu0_int_0_31_status->cpu0_i2s_int_st: ,R,0x28[24]*/
5126 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_i2s_int_st(sys_hw_t *hw)
5127 {
5128 return sys_ll_get_cpu0_int_0_31_status_cpu0_i2s_int_st(hw);
5129 }
5130
5131 /* REG_0x28:cpu0_int_0_31_status->cpu0_jpegenc_int_st: ,R,0x28[25]*/
5132 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_jpegenc_int_st(sys_hw_t *hw)
5133 {
5134 return sys_ll_get_cpu0_int_0_31_status_cpu0_jpegenc_int_st(hw);
5135 }
5136
5137 /* REG_0x28:cpu0_int_0_31_status->cpu0_jpegdec_int_st: ,R,0x28[26]*/
5138 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_jpegdec_int_st(sys_hw_t *hw)
5139 {
5140 return sys_ll_get_cpu0_int_0_31_status_cpu0_jpegdec_int_st(hw);
5141 }
5142
5143 /* REG_0x28:cpu0_int_0_31_status->cpu0_lcd_int_st: ,R,0x28[27]*/
5144 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_lcd_int_st(sys_hw_t *hw)
5145 {
5146 return sys_ll_get_cpu0_int_0_31_status_cpu0_lcd_int_st(hw);
5147 }
5148
5149 /* REG_0x28:cpu0_int_0_31_status->cpu0_wifi_int_phy_st: ,R,0x28[29]*/
5150 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_wifi_int_phy_st(sys_hw_t *hw)
5151 {
5152 return sys_ll_get_cpu0_int_0_31_status_cpu0_wifi_int_phy_st(hw);
5153 }
5154
5155 /* REG_0x28:cpu0_int_0_31_status->cpu0_wifi_mac_int_tx_rx_timer_st: ,R,0x28[30]*/
5156 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_wifi_mac_int_tx_rx_timer_st(sys_hw_t *hw)
5157 {
5158 return sys_ll_get_cpu0_int_0_31_status_cpu0_wifi_mac_int_tx_rx_timer_st(hw);
5159 }
5160
5161 /* REG_0x28:cpu0_int_0_31_status->cpu0_wifi_mac_int_tx_rx_misc_st: ,R,0x28[31]*/
5162 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_wifi_mac_int_tx_rx_misc_st(sys_hw_t *hw)
5163 {
5164 return sys_ll_get_cpu0_int_0_31_status_cpu0_wifi_mac_int_tx_rx_misc_st(hw);
5165 }
5166
5167 /* REG_0x29 */
5168
5169 uint32_t sys_hal_get_cpu0_int_32_63_status_value(sys_hw_t *hw)
5170 {
5171 return sys_ll_get_cpu0_int_32_63_status_value(hw);
5172 }
5173
5174 /* REG_0x29:cpu0_int_32_63_status->cpu0_wifi_mac_int_rx_trigger_st: ,R,0x29[0]*/
5175 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_wifi_mac_int_rx_trigger_st(sys_hw_t *hw)
5176 {
5177 return sys_ll_get_cpu0_int_32_63_status_cpu0_wifi_mac_int_rx_trigger_st(hw);
5178 }
5179
5180 /* REG_0x29:cpu0_int_32_63_status->cpu0_wifi_mac_int_tx_trigger_st: ,R,0x29[1]*/
5181 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_wifi_mac_int_tx_trigger_st(sys_hw_t *hw)
5182 {
5183 return sys_ll_get_cpu0_int_32_63_status_cpu0_wifi_mac_int_tx_trigger_st(hw);
5184 }
5185
5186 /* REG_0x29:cpu0_int_32_63_status->cpu0_wifi_mac_port_trigger_st: ,R,0x29[2]*/
5187 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_wifi_mac_port_trigger_st(sys_hw_t *hw)
5188 {
5189 return sys_ll_get_cpu0_int_32_63_status_cpu0_wifi_mac_port_trigger_st(hw);
5190 }
5191
5192 /* REG_0x29:cpu0_int_32_63_status->cpu0_wifi_mac_int_gen_st: ,R,0x29[3]*/
5193 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_wifi_mac_int_gen_st(sys_hw_t *hw)
5194 {
5195 return sys_ll_get_cpu0_int_32_63_status_cpu0_wifi_mac_int_gen_st(hw);
5196 }
5197
5198 /* REG_0x29:cpu0_int_32_63_status->cpu0_wifi_hsu_irq_st: ,R,0x29[4]*/
5199 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_wifi_hsu_irq_st(sys_hw_t *hw)
5200 {
5201 return sys_ll_get_cpu0_int_32_63_status_cpu0_wifi_hsu_irq_st(hw);
5202 }
5203
5204 /* REG_0x29:cpu0_int_32_63_status->cpu0_wifi_int_mac_wakeup_st: ,R,0x29[5]*/
5205 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_wifi_int_mac_wakeup_st(sys_hw_t *hw)
5206 {
5207 return sys_ll_get_cpu0_int_32_63_status_cpu0_wifi_int_mac_wakeup_st(hw);
5208 }
5209
5210 /* REG_0x29:cpu0_int_32_63_status->cpu0_dm_irq_st: ,R,0x29[7]*/
5211 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_dm_irq_st(sys_hw_t *hw)
5212 {
5213 return sys_ll_get_cpu0_int_32_63_status_cpu0_dm_irq_st(hw);
5214 }
5215
5216 /* REG_0x29:cpu0_int_32_63_status->cpu0_ble_irq_st: ,R,0x29[8]*/
5217 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_ble_irq_st(sys_hw_t *hw)
5218 {
5219 return sys_ll_get_cpu0_int_32_63_status_cpu0_ble_irq_st(hw);
5220 }
5221
5222 /* REG_0x29:cpu0_int_32_63_status->cpu0_bt_irq_st: ,R,0x29[9]*/
5223 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_bt_irq_st(sys_hw_t *hw)
5224 {
5225 return sys_ll_get_cpu0_int_32_63_status_cpu0_bt_irq_st(hw);
5226 }
5227
5228 /* REG_0x29:cpu0_int_32_63_status->cpu0_mbox0_int_st: ,R,0x29[15]*/
5229 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_mbox0_int_st(sys_hw_t *hw)
5230 {
5231 return sys_ll_get_cpu0_int_32_63_status_cpu0_mbox0_int_st(hw);
5232 }
5233
5234 /* REG_0x29:cpu0_int_32_63_status->cpu0_mbox1_int_st: ,R,0x29[16]*/
5235 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_mbox1_int_st(sys_hw_t *hw)
5236 {
5237 return sys_ll_get_cpu0_int_32_63_status_cpu0_mbox1_int_st(hw);
5238 }
5239
5240 /* REG_0x29:cpu0_int_32_63_status->cpu0_bmc64_int_st: ,R,0x29[17]*/
5241 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_bmc64_int_st(sys_hw_t *hw)
5242 {
5243 return sys_ll_get_cpu0_int_32_63_status_cpu0_bmc64_int_st(hw);
5244 }
5245
5246 /* REG_0x29:cpu0_int_32_63_status->cpu0_touched_int_st: ,R,0x29[19]*/
5247 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_touched_int_st(sys_hw_t *hw)
5248 {
5249 return sys_ll_get_cpu0_int_32_63_status_cpu0_touched_int_st(hw);
5250 }
5251
5252 /* REG_0x29:cpu0_int_32_63_status->cpu0_usbplug_int_st: ,R,0x29[20]*/
5253 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_usbplug_int_st(sys_hw_t *hw)
5254 {
5255 return sys_ll_get_cpu0_int_32_63_status_cpu0_usbplug_int_st(hw);
5256 }
5257
5258 /* REG_0x29:cpu0_int_32_63_status->cpu0_rtc_int_st: ,R,0x29[21]*/
5259 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_rtc_int_st(sys_hw_t *hw)
5260 {
5261 return sys_ll_get_cpu0_int_32_63_status_cpu0_rtc_int_st(hw);
5262 }
5263
5264 /* REG_0x29:cpu0_int_32_63_status->cpu0_gpio_int_st: ,R,0x29[22]*/
5265 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_gpio_int_st(sys_hw_t *hw)
5266 {
5267 return sys_ll_get_cpu0_int_32_63_status_cpu0_gpio_int_st(hw);
5268 }
5269
5270 /* REG_0x2a */
5271
5272 uint32_t sys_hal_get_cpu1_int_0_31_status_value(sys_hw_t *hw)
5273 {
5274 return sys_ll_get_cpu1_int_0_31_status_value(hw);
5275 }
5276
5277 /* REG_0x2a:cpu1_int_0_31_status->cpu1_bmc32_int_st: ,R,0x2a[0]*/
5278 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_bmc32_int_st(sys_hw_t *hw)
5279 {
5280 return sys_ll_get_cpu1_int_0_31_status_cpu1_bmc32_int_st(hw);
5281 }
5282
5283 /* REG_0x2a:cpu1_int_0_31_status->cpu1_host_0_irq_st: ,R,0x2a[1]*/
5284 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_host_0_irq_st(sys_hw_t *hw)
5285 {
5286 return sys_ll_get_cpu1_int_0_31_status_cpu1_host_0_irq_st(hw);
5287 }
5288
5289 /* REG_0x2a:cpu1_int_0_31_status->cpu1_host_0_sec_irq_st: ,R,0x2a[2]*/
5290 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_host_0_sec_irq_st(sys_hw_t *hw)
5291 {
5292 return sys_ll_get_cpu1_int_0_31_status_cpu1_host_0_sec_irq_st(hw);
5293 }
5294
5295 /* REG_0x2a:cpu1_int_0_31_status->cpu1_timer_int_st: ,R,0x2a[3]*/
5296 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_timer_int_st(sys_hw_t *hw)
5297 {
5298 return sys_ll_get_cpu1_int_0_31_status_cpu1_timer_int_st(hw);
5299 }
5300
5301 /* REG_0x2a:cpu1_int_0_31_status->cpu1_uart_int_st: ,R,0x2a[4]*/
5302 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_uart_int_st(sys_hw_t *hw)
5303 {
5304 return sys_ll_get_cpu1_int_0_31_status_cpu1_uart_int_st(hw);
5305 }
5306
5307 /* REG_0x2a:cpu1_int_0_31_status->cpu1_pwm_int_st: ,R,0x2a[5]*/
5308 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_pwm_int_st(sys_hw_t *hw)
5309 {
5310 return sys_ll_get_cpu1_int_0_31_status_cpu1_pwm_int_st(hw);
5311 }
5312
5313 /* REG_0x2a:cpu1_int_0_31_status->cpu1_i2c_int_st: ,R,0x2a[6]*/
5314 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_i2c_int_st(sys_hw_t *hw)
5315 {
5316 return sys_ll_get_cpu1_int_0_31_status_cpu1_i2c_int_st(hw);
5317 }
5318
5319 /* REG_0x2a:cpu1_int_0_31_status->cpu1_spi_int_st: ,R,0x2a[7]*/
5320 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_spi_int_st(sys_hw_t *hw)
5321 {
5322 return sys_ll_get_cpu1_int_0_31_status_cpu1_spi_int_st(hw);
5323 }
5324
5325 /* REG_0x2a:cpu1_int_0_31_status->cpu1_sadc_int_st: ,R,0x2a[8]*/
5326 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_sadc_int_st(sys_hw_t *hw)
5327 {
5328 return sys_ll_get_cpu1_int_0_31_status_cpu1_sadc_int_st(hw);
5329 }
5330
5331 /* REG_0x2a:cpu1_int_0_31_status->cpu1_irda_int_st: ,R,0x2a[9]*/
5332 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_irda_int_st(sys_hw_t *hw)
5333 {
5334 return sys_ll_get_cpu1_int_0_31_status_cpu1_irda_int_st(hw);
5335 }
5336
5337 /* REG_0x2a:cpu1_int_0_31_status->cpu1_sdio_int_st: ,R,0x2a[10]*/
5338 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_sdio_int_st(sys_hw_t *hw)
5339 {
5340 return sys_ll_get_cpu1_int_0_31_status_cpu1_sdio_int_st(hw);
5341 }
5342
5343 /* REG_0x2a:cpu1_int_0_31_status->cpu1_gdma_int_st: ,R,0x2a[11]*/
5344 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_gdma_int_st(sys_hw_t *hw)
5345 {
5346 return sys_ll_get_cpu1_int_0_31_status_cpu1_gdma_int_st(hw);
5347 }
5348
5349 /* REG_0x2a:cpu1_int_0_31_status->cpu1_la_int_st: ,R,0x2a[12]*/
5350 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_la_int_st(sys_hw_t *hw)
5351 {
5352 return sys_ll_get_cpu1_int_0_31_status_cpu1_la_int_st(hw);
5353 }
5354
5355 /* REG_0x2a:cpu1_int_0_31_status->cpu1_timer1_int_st: ,R,0x2a[13]*/
5356 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_timer1_int_st(sys_hw_t *hw)
5357 {
5358 return sys_ll_get_cpu1_int_0_31_status_cpu1_timer1_int_st(hw);
5359 }
5360
5361 /* REG_0x2a:cpu1_int_0_31_status->cpu1_i2c1_int_st: ,R,0x2a[14]*/
5362 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_i2c1_int_st(sys_hw_t *hw)
5363 {
5364 return sys_ll_get_cpu1_int_0_31_status_cpu1_i2c1_int_st(hw);
5365 }
5366
5367 /* REG_0x2a:cpu1_int_0_31_status->cpu1_uart1_int_st: ,R,0x2a[15]*/
5368 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_uart1_int_st(sys_hw_t *hw)
5369 {
5370 return sys_ll_get_cpu1_int_0_31_status_cpu1_uart1_int_st(hw);
5371 }
5372
5373 /* REG_0x2a:cpu1_int_0_31_status->cpu1_uart2_int_st: ,R,0x2a[16]*/
5374 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_uart2_int_st(sys_hw_t *hw)
5375 {
5376 return sys_ll_get_cpu1_int_0_31_status_cpu1_uart2_int_st(hw);
5377 }
5378
5379 /* REG_0x2a:cpu1_int_0_31_status->cpu1_spi1_int_st: ,R,0x2a[17]*/
5380 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_spi1_int_st(sys_hw_t *hw)
5381 {
5382 return sys_ll_get_cpu1_int_0_31_status_cpu1_spi1_int_st(hw);
5383 }
5384
5385 /* REG_0x2a:cpu1_int_0_31_status->cpu1_can_int_st: ,R,0x2a[18]*/
5386 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_can_int_st(sys_hw_t *hw)
5387 {
5388 return sys_ll_get_cpu1_int_0_31_status_cpu1_can_int_st(hw);
5389 }
5390
5391 /* REG_0x2a:cpu1_int_0_31_status->cpu1_usb_int_st: ,R,0x2a[19]*/
5392 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_usb_int_st(sys_hw_t *hw)
5393 {
5394 return sys_ll_get_cpu1_int_0_31_status_cpu1_usb_int_st(hw);
5395 }
5396
5397 /* REG_0x2a:cpu1_int_0_31_status->cpu1_qspi_int_st: ,R,0x2a[20]*/
5398 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_qspi_int_st(sys_hw_t *hw)
5399 {
5400 return sys_ll_get_cpu1_int_0_31_status_cpu1_qspi_int_st(hw);
5401 }
5402
5403 /* REG_0x2a:cpu1_int_0_31_status->cpu1_fft_int_st: ,R,0x2a[21]*/
5404 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_fft_int_st(sys_hw_t *hw)
5405 {
5406 return sys_ll_get_cpu1_int_0_31_status_cpu1_fft_int_st(hw);
5407 }
5408
5409 /* REG_0x2a:cpu1_int_0_31_status->cpu1_sbc_int_st: ,R,0x2a[22]*/
5410 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_sbc_int_st(sys_hw_t *hw)
5411 {
5412 return sys_ll_get_cpu1_int_0_31_status_cpu1_sbc_int_st(hw);
5413 }
5414
5415 /* REG_0x2a:cpu1_int_0_31_status->cpu1_aud_int_st: ,R,0x2a[23]*/
5416 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_aud_int_st(sys_hw_t *hw)
5417 {
5418 return sys_ll_get_cpu1_int_0_31_status_cpu1_aud_int_st(hw);
5419 }
5420
5421 /* REG_0x2a:cpu1_int_0_31_status->cpu1_i2s_int_st: ,R,0x2a[24]*/
5422 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_i2s_int_st(sys_hw_t *hw)
5423 {
5424 return sys_ll_get_cpu1_int_0_31_status_cpu1_i2s_int_st(hw);
5425 }
5426
5427 /* REG_0x2a:cpu1_int_0_31_status->cpu1_jpegenc_int_st: ,R,0x2a[25]*/
5428 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_jpegenc_int_st(sys_hw_t *hw)
5429 {
5430 return sys_ll_get_cpu1_int_0_31_status_cpu1_jpegenc_int_st(hw);
5431 }
5432
5433 /* REG_0x2a:cpu1_int_0_31_status->cpu1_jpegdec_int_st: ,R,0x2a[26]*/
5434 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_jpegdec_int_st(sys_hw_t *hw)
5435 {
5436 return sys_ll_get_cpu1_int_0_31_status_cpu1_jpegdec_int_st(hw);
5437 }
5438
5439 /* REG_0x2a:cpu1_int_0_31_status->cpu1_lcd_int_st: ,R,0x2a[27]*/
5440 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_lcd_int_st(sys_hw_t *hw)
5441 {
5442 return sys_ll_get_cpu1_int_0_31_status_cpu1_lcd_int_st(hw);
5443 }
5444
5445 /* REG_0x2a:cpu1_int_0_31_status->cpu1_wifi_int_phy_st: ,R,0x2a[29]*/
5446 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_wifi_int_phy_st(sys_hw_t *hw)
5447 {
5448 return sys_ll_get_cpu1_int_0_31_status_cpu1_wifi_int_phy_st(hw);
5449 }
5450
5451 /* REG_0x2a:cpu1_int_0_31_status->cpu1_wifi_mac_int_tx_rx_timer_st: ,R,0x2a[30]*/
5452 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_wifi_mac_int_tx_rx_timer_st(sys_hw_t *hw)
5453 {
5454 return sys_ll_get_cpu1_int_0_31_status_cpu1_wifi_mac_int_tx_rx_timer_st(hw);
5455 }
5456
5457 /* REG_0x2a:cpu1_int_0_31_status->cpu1_wifi_mac_int_tx_rx_misc_st: ,R,0x2a[31]*/
5458 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_wifi_mac_int_tx_rx_misc_st(sys_hw_t *hw)
5459 {
5460 return sys_ll_get_cpu1_int_0_31_status_cpu1_wifi_mac_int_tx_rx_misc_st(hw);
5461 }
5462
5463 /* REG_0x2b */
5464
5465 uint32_t sys_hal_get_cpu1_int_32_63_status_value(sys_hw_t *hw)
5466 {
5467 return sys_ll_get_cpu1_int_32_63_status_value(hw);
5468 }
5469
5470 /* REG_0x2b:cpu1_int_32_63_status->cpu1_wifi_mac_int_rx_trigger_st: ,R,0x2b[0]*/
5471 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_wifi_mac_int_rx_trigger_st(sys_hw_t *hw)
5472 {
5473 return sys_ll_get_cpu1_int_32_63_status_cpu1_wifi_mac_int_rx_trigger_st(hw);
5474 }
5475
5476 /* REG_0x2b:cpu1_int_32_63_status->cpu1_wifi_mac_int_tx_trigger_st: ,R,0x2b[1]*/
5477 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_wifi_mac_int_tx_trigger_st(sys_hw_t *hw)
5478 {
5479 return sys_ll_get_cpu1_int_32_63_status_cpu1_wifi_mac_int_tx_trigger_st(hw);
5480 }
5481
5482 /* REG_0x2b:cpu1_int_32_63_status->cpu1_wifi_mac_port_trigger_st: ,R,0x2b[2]*/
5483 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_wifi_mac_port_trigger_st(sys_hw_t *hw)
5484 {
5485 return sys_ll_get_cpu1_int_32_63_status_cpu1_wifi_mac_port_trigger_st(hw);
5486 }
5487
5488 /* REG_0x2b:cpu1_int_32_63_status->cpu1_wifi_mac_int_gen_st: ,R,0x2b[3]*/
5489 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_wifi_mac_int_gen_st(sys_hw_t *hw)
5490 {
5491 return sys_ll_get_cpu1_int_32_63_status_cpu1_wifi_mac_int_gen_st(hw);
5492 }
5493
5494 /* REG_0x2b:cpu1_int_32_63_status->cpu1_wifi_hsu_irq_st: ,R,0x2b[4]*/
5495 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_wifi_hsu_irq_st(sys_hw_t *hw)
5496 {
5497 return sys_ll_get_cpu1_int_32_63_status_cpu1_wifi_hsu_irq_st(hw);
5498 }
5499
5500 /* REG_0x2b:cpu1_int_32_63_status->cpu1_wifi_int_mac_wakeup_st: ,R,0x2b[5]*/
5501 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_wifi_int_mac_wakeup_st(sys_hw_t *hw)
5502 {
5503 return sys_ll_get_cpu1_int_32_63_status_cpu1_wifi_int_mac_wakeup_st(hw);
5504 }
5505
5506 /* REG_0x2b:cpu1_int_32_63_status->cpu1_dm_irq_st: ,R,0x2b[7]*/
5507 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_dm_irq_st(sys_hw_t *hw)
5508 {
5509 return sys_ll_get_cpu1_int_32_63_status_cpu1_dm_irq_st(hw);
5510 }
5511
5512 /* REG_0x2b:cpu1_int_32_63_status->cpu1_ble_irq_st: ,R,0x2b[8]*/
5513 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_ble_irq_st(sys_hw_t *hw)
5514 {
5515 return sys_ll_get_cpu1_int_32_63_status_cpu1_ble_irq_st(hw);
5516 }
5517
5518 /* REG_0x2b:cpu1_int_32_63_status->cpu1_bt_irq_st: ,R,0x2b[9]*/
5519 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_bt_irq_st(sys_hw_t *hw)
5520 {
5521 return sys_ll_get_cpu1_int_32_63_status_cpu1_bt_irq_st(hw);
5522 }
5523
5524 /* REG_0x2b:cpu1_int_32_63_status->cpu1_mbox0_int_st: ,R,0x2b[15]*/
5525 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_mbox0_int_st(sys_hw_t *hw)
5526 {
5527 return sys_ll_get_cpu1_int_32_63_status_cpu1_mbox0_int_st(hw);
5528 }
5529
5530 /* REG_0x2b:cpu1_int_32_63_status->cpu1_mbox1_int_st: ,R,0x2b[16]*/
5531 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_mbox1_int_st(sys_hw_t *hw)
5532 {
5533 return sys_ll_get_cpu1_int_32_63_status_cpu1_mbox1_int_st(hw);
5534 }
5535
5536 /* REG_0x2b:cpu1_int_32_63_status->cpu1_bmc64_int_st: ,R,0x2b[17]*/
5537 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_bmc64_int_st(sys_hw_t *hw)
5538 {
5539 return sys_ll_get_cpu1_int_32_63_status_cpu1_bmc64_int_st(hw);
5540 }
5541
5542 /* REG_0x2b:cpu1_int_32_63_status->cpu1_touched_int_st: ,R,0x2b[19]*/
5543 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_touched_int_st(sys_hw_t *hw)
5544 {
5545 return sys_ll_get_cpu1_int_32_63_status_cpu1_touched_int_st(hw);
5546 }
5547
5548 /* REG_0x2b:cpu1_int_32_63_status->cpu1_usbplug_int_st: ,R,0x2b[20]*/
5549 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_usbplug_int_st(sys_hw_t *hw)
5550 {
5551 return sys_ll_get_cpu1_int_32_63_status_cpu1_usbplug_int_st(hw);
5552 }
5553
5554 /* REG_0x2b:cpu1_int_32_63_status->cpu1_rtc_int_st: ,R,0x2b[21]*/
5555 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_rtc_int_st(sys_hw_t *hw)
5556 {
5557 return sys_ll_get_cpu1_int_32_63_status_cpu1_rtc_int_st(hw);
5558 }
5559
5560 /* REG_0x2b:cpu1_int_32_63_status->cpu1_gpio_int_st: ,R,0x2b[22]*/
5561 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_gpio_int_st(sys_hw_t *hw)
5562 {
5563 return sys_ll_get_cpu1_int_32_63_status_cpu1_gpio_int_st(hw);
5564 }
5565
5566 /* REG_0x30 */
5567
5568 uint32_t sys_hal_get_gpio_config0_value(sys_hw_t *hw)
5569 {
5570 return sys_ll_get_gpio_config0_value(hw);
5571 }
5572
5573 void sys_hal_set_gpio_config0_value(sys_hw_t *hw, uint32_t value)
5574 {
5575 sys_ll_set_gpio_config0_value(hw, value);
5576 }
5577
5578 /* REG_0x30:gpio_config0->sys_gpio0:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x30[3:0]*/
5579 uint32_t sys_hal_get_gpio_config0_sys_gpio0(sys_hw_t *hw)
5580 {
5581 return sys_ll_get_gpio_config0_sys_gpio0(hw);
5582 }
5583
5584 void sys_hal_set_gpio_config0_sys_gpio0(sys_hw_t *hw, uint32_t value)
5585 {
5586 sys_ll_set_gpio_config0_sys_gpio0(hw, value);
5587 }
5588
5589 /* REG_0x30:gpio_config0->sys_gpio1:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x30[7:4]*/
5590 uint32_t sys_hal_get_gpio_config0_sys_gpio1(sys_hw_t *hw)
5591 {
5592 return sys_ll_get_gpio_config0_sys_gpio1(hw);
5593 }
5594
5595 void sys_hal_set_gpio_config0_sys_gpio1(sys_hw_t *hw, uint32_t value)
5596 {
5597 sys_ll_set_gpio_config0_sys_gpio1(hw, value);
5598 }
5599
5600 /* REG_0x30:gpio_config0->sys_gpio2:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x30[11:8]*/
5601 uint32_t sys_hal_get_gpio_config0_sys_gpio2(sys_hw_t *hw)
5602 {
5603 return sys_ll_get_gpio_config0_sys_gpio2(hw);
5604 }
5605
5606 void sys_hal_set_gpio_config0_sys_gpio2(sys_hw_t *hw, uint32_t value)
5607 {
5608 sys_ll_set_gpio_config0_sys_gpio2(hw, value);
5609 }
5610
5611 /* REG_0x30:gpio_config0->sys_gpio3:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x30[15:12]*/
5612 uint32_t sys_hal_get_gpio_config0_sys_gpio3(sys_hw_t *hw)
5613 {
5614 return sys_ll_get_gpio_config0_sys_gpio3(hw);
5615 }
5616
5617 void sys_hal_set_gpio_config0_sys_gpio3(sys_hw_t *hw, uint32_t value)
5618 {
5619 sys_ll_set_gpio_config0_sys_gpio3(hw, value);
5620 }
5621
5622 /* REG_0x30:gpio_config0->sys_gpio4:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x30[19:16]*/
5623 uint32_t sys_hal_get_gpio_config0_sys_gpio4(sys_hw_t *hw)
5624 {
5625 return sys_ll_get_gpio_config0_sys_gpio4(hw);
5626 }
5627
5628 void sys_hal_set_gpio_config0_sys_gpio4(sys_hw_t *hw, uint32_t value)
5629 {
5630 sys_ll_set_gpio_config0_sys_gpio4(hw, value);
5631 }
5632
5633 /* REG_0x30:gpio_config0->sys_gpio5:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x30[23:20]*/
5634 uint32_t sys_hal_get_gpio_config0_sys_gpio5(sys_hw_t *hw)
5635 {
5636 return sys_ll_get_gpio_config0_sys_gpio5(hw);
5637 }
5638
5639 void sys_hal_set_gpio_config0_sys_gpio5(sys_hw_t *hw, uint32_t value)
5640 {
5641 sys_ll_set_gpio_config0_sys_gpio5(hw, value);
5642 }
5643
5644 /* REG_0x30:gpio_config0->sys_gpio6:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x30[27:24]*/
5645 uint32_t sys_hal_get_gpio_config0_sys_gpio6(sys_hw_t *hw)
5646 {
5647 return sys_ll_get_gpio_config0_sys_gpio6(hw);
5648 }
5649
5650 void sys_hal_set_gpio_config0_sys_gpio6(sys_hw_t *hw, uint32_t value)
5651 {
5652 sys_ll_set_gpio_config0_sys_gpio6(hw, value);
5653 }
5654
5655 /* REG_0x30:gpio_config0->sys_gpio7:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x30[31:28]*/
5656 uint32_t sys_hal_get_gpio_config0_sys_gpio7(sys_hw_t *hw)
5657 {
5658 return sys_ll_get_gpio_config0_sys_gpio7(hw);
5659 }
5660
5661 void sys_hal_set_gpio_config0_sys_gpio7(sys_hw_t *hw, uint32_t value)
5662 {
5663 sys_ll_set_gpio_config0_sys_gpio7(hw, value);
5664 }
5665
5666 /* REG_0x31 */
5667
5668 uint32_t sys_hal_get_gpio_config1_value(sys_hw_t *hw)
5669 {
5670 return sys_ll_get_gpio_config1_value(hw);
5671 }
5672
5673 void sys_hal_set_gpio_config1_value(sys_hw_t *hw, uint32_t value)
5674 {
5675 sys_ll_set_gpio_config1_value(hw, value);
5676 }
5677
5678 /* REG_0x31:gpio_config1->sys_gpio8:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x31[3:0]*/
5679 uint32_t sys_hal_get_gpio_config1_sys_gpio8(sys_hw_t *hw)
5680 {
5681 return sys_ll_get_gpio_config1_sys_gpio8(hw);
5682 }
5683
5684 void sys_hal_set_gpio_config1_sys_gpio8(sys_hw_t *hw, uint32_t value)
5685 {
5686 sys_ll_set_gpio_config1_sys_gpio8(hw, value);
5687 }
5688
5689 /* REG_0x31:gpio_config1->sys_gpio9:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x31[7:4]*/
5690 uint32_t sys_hal_get_gpio_config1_sys_gpio9(sys_hw_t *hw)
5691 {
5692 return sys_ll_get_gpio_config1_sys_gpio9(hw);
5693 }
5694
5695 void sys_hal_set_gpio_config1_sys_gpio9(sys_hw_t *hw, uint32_t value)
5696 {
5697 sys_ll_set_gpio_config1_sys_gpio9(hw, value);
5698 }
5699
5700 /* REG_0x31:gpio_config1->sys_gpio10:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x31[11:8]*/
5701 uint32_t sys_hal_get_gpio_config1_sys_gpio10(sys_hw_t *hw)
5702 {
5703 return sys_ll_get_gpio_config1_sys_gpio10(hw);
5704 }
5705
5706 void sys_hal_set_gpio_config1_sys_gpio10(sys_hw_t *hw, uint32_t value)
5707 {
5708 sys_ll_set_gpio_config1_sys_gpio10(hw, value);
5709 }
5710
5711 /* REG_0x31:gpio_config1->sys_gpio11:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x31[15:12]*/
5712 uint32_t sys_hal_get_gpio_config1_sys_gpio11(sys_hw_t *hw)
5713 {
5714 return sys_ll_get_gpio_config1_sys_gpio11(hw);
5715 }
5716
5717 void sys_hal_set_gpio_config1_sys_gpio11(sys_hw_t *hw, uint32_t value)
5718 {
5719 sys_ll_set_gpio_config1_sys_gpio11(hw, value);
5720 }
5721
5722 /* REG_0x31:gpio_config1->sys_gpio12:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x31[19:16]*/
5723 uint32_t sys_hal_get_gpio_config1_sys_gpio12(sys_hw_t *hw)
5724 {
5725 return sys_ll_get_gpio_config1_sys_gpio12(hw);
5726 }
5727
5728 void sys_hal_set_gpio_config1_sys_gpio12(sys_hw_t *hw, uint32_t value)
5729 {
5730 sys_ll_set_gpio_config1_sys_gpio12(hw, value);
5731 }
5732
5733 /* REG_0x31:gpio_config1->sys_gpio13:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x31[23:20]*/
5734 uint32_t sys_hal_get_gpio_config1_sys_gpio13(sys_hw_t *hw)
5735 {
5736 return sys_ll_get_gpio_config1_sys_gpio13(hw);
5737 }
5738
5739 void sys_hal_set_gpio_config1_sys_gpio13(sys_hw_t *hw, uint32_t value)
5740 {
5741 sys_ll_set_gpio_config1_sys_gpio13(hw, value);
5742 }
5743
5744 /* REG_0x31:gpio_config1->sys_gpio14:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x31[27:24]*/
5745 uint32_t sys_hal_get_gpio_config1_sys_gpio14(sys_hw_t *hw)
5746 {
5747 return sys_ll_get_gpio_config1_sys_gpio14(hw);
5748 }
5749
5750 void sys_hal_set_gpio_config1_sys_gpio14(sys_hw_t *hw, uint32_t value)
5751 {
5752 sys_ll_set_gpio_config1_sys_gpio14(hw, value);
5753 }
5754
5755 /* REG_0x31:gpio_config1->sys_gpio15:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x31[31:28]*/
5756 uint32_t sys_hal_get_gpio_config1_sys_gpio15(sys_hw_t *hw)
5757 {
5758 return sys_ll_get_gpio_config1_sys_gpio15(hw);
5759 }
5760
5761 void sys_hal_set_gpio_config1_sys_gpio15(sys_hw_t *hw, uint32_t value)
5762 {
5763 sys_ll_set_gpio_config1_sys_gpio15(hw, value);
5764 }
5765
5766 /* REG_0x32 */
5767
5768 uint32_t sys_hal_get_gpio_config2_value(sys_hw_t *hw)
5769 {
5770 return sys_ll_get_gpio_config2_value(hw);
5771 }
5772
5773 void sys_hal_set_gpio_config2_value(sys_hw_t *hw, uint32_t value)
5774 {
5775 sys_ll_set_gpio_config2_value(hw, value);
5776 }
5777
5778 /* REG_0x32:gpio_config2->sys_gpio16:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x32[3:0]*/
5779 uint32_t sys_hal_get_gpio_config2_sys_gpio16(sys_hw_t *hw)
5780 {
5781 return sys_ll_get_gpio_config2_sys_gpio16(hw);
5782 }
5783
5784 void sys_hal_set_gpio_config2_sys_gpio16(sys_hw_t *hw, uint32_t value)
5785 {
5786 sys_ll_set_gpio_config2_sys_gpio16(hw, value);
5787 }
5788
5789 /* REG_0x32:gpio_config2->sys_gpio17:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x32[7:4]*/
5790 uint32_t sys_hal_get_gpio_config2_sys_gpio17(sys_hw_t *hw)
5791 {
5792 return sys_ll_get_gpio_config2_sys_gpio17(hw);
5793 }
5794
5795 void sys_hal_set_gpio_config2_sys_gpio17(sys_hw_t *hw, uint32_t value)
5796 {
5797 sys_ll_set_gpio_config2_sys_gpio17(hw, value);
5798 }
5799
5800 /* REG_0x32:gpio_config2->sys_gpio18:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x32[11:8]*/
5801 uint32_t sys_hal_get_gpio_config2_sys_gpio18(sys_hw_t *hw)
5802 {
5803 return sys_ll_get_gpio_config2_sys_gpio18(hw);
5804 }
5805
5806 void sys_hal_set_gpio_config2_sys_gpio18(sys_hw_t *hw, uint32_t value)
5807 {
5808 sys_ll_set_gpio_config2_sys_gpio18(hw, value);
5809 }
5810
5811 /* REG_0x32:gpio_config2->sys_gpio19:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x32[15:12]*/
5812 uint32_t sys_hal_get_gpio_config2_sys_gpio19(sys_hw_t *hw)
5813 {
5814 return sys_ll_get_gpio_config2_sys_gpio19(hw);
5815 }
5816
5817 void sys_hal_set_gpio_config2_sys_gpio19(sys_hw_t *hw, uint32_t value)
5818 {
5819 sys_ll_set_gpio_config2_sys_gpio19(hw, value);
5820 }
5821
5822 /* REG_0x32:gpio_config2->sys_gpio20:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x32[19:16]*/
5823 uint32_t sys_hal_get_gpio_config2_sys_gpio20(sys_hw_t *hw)
5824 {
5825 return sys_ll_get_gpio_config2_sys_gpio20(hw);
5826 }
5827
5828 void sys_hal_set_gpio_config2_sys_gpio20(sys_hw_t *hw, uint32_t value)
5829 {
5830 sys_ll_set_gpio_config2_sys_gpio20(hw, value);
5831 }
5832
5833 /* REG_0x32:gpio_config2->sys_gpio21:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x32[23:20]*/
5834 uint32_t sys_hal_get_gpio_config2_sys_gpio21(sys_hw_t *hw)
5835 {
5836 return sys_ll_get_gpio_config2_sys_gpio21(hw);
5837 }
5838
5839 void sys_hal_set_gpio_config2_sys_gpio21(sys_hw_t *hw, uint32_t value)
5840 {
5841 sys_ll_set_gpio_config2_sys_gpio21(hw, value);
5842 }
5843
5844 /* REG_0x32:gpio_config2->sys_gpio22:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x32[27:24]*/
5845 uint32_t sys_hal_get_gpio_config2_sys_gpio22(sys_hw_t *hw)
5846 {
5847 return sys_ll_get_gpio_config2_sys_gpio22(hw);
5848 }
5849
5850 void sys_hal_set_gpio_config2_sys_gpio22(sys_hw_t *hw, uint32_t value)
5851 {
5852 sys_ll_set_gpio_config2_sys_gpio22(hw, value);
5853 }
5854
5855 /* REG_0x32:gpio_config2->sys_gpio23:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x32[31:28]*/
5856 uint32_t sys_hal_get_gpio_config2_sys_gpio23(sys_hw_t *hw)
5857 {
5858 return sys_ll_get_gpio_config2_sys_gpio23(hw);
5859 }
5860
5861 void sys_hal_set_gpio_config2_sys_gpio23(sys_hw_t *hw, uint32_t value)
5862 {
5863 sys_ll_set_gpio_config2_sys_gpio23(hw, value);
5864 }
5865
5866 /* REG_0x33 */
5867
5868 uint32_t sys_hal_get_gpio_config3_value(sys_hw_t *hw)
5869 {
5870 return sys_ll_get_gpio_config3_value(hw);
5871 }
5872
5873 void sys_hal_set_gpio_config3_value(sys_hw_t *hw, uint32_t value)
5874 {
5875 sys_ll_set_gpio_config3_value(hw, value);
5876 }
5877
5878 /* REG_0x33:gpio_config3->sys_gpio24:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x33[3:0]*/
5879 uint32_t sys_hal_get_gpio_config3_sys_gpio24(sys_hw_t *hw)
5880 {
5881 return sys_ll_get_gpio_config3_sys_gpio24(hw);
5882 }
5883
5884 void sys_hal_set_gpio_config3_sys_gpio24(sys_hw_t *hw, uint32_t value)
5885 {
5886 sys_ll_set_gpio_config3_sys_gpio24(hw, value);
5887 }
5888
5889 /* REG_0x33:gpio_config3->sys_gpio25:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x33[7:4]*/
5890 uint32_t sys_hal_get_gpio_config3_sys_gpio25(sys_hw_t *hw)
5891 {
5892 return sys_ll_get_gpio_config3_sys_gpio25(hw);
5893 }
5894
5895 void sys_hal_set_gpio_config3_sys_gpio25(sys_hw_t *hw, uint32_t value)
5896 {
5897 sys_ll_set_gpio_config3_sys_gpio25(hw, value);
5898 }
5899
5900 /* REG_0x33:gpio_config3->sys_gpio26:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x33[11:8]*/
5901 uint32_t sys_hal_get_gpio_config3_sys_gpio26(sys_hw_t *hw)
5902 {
5903 return sys_ll_get_gpio_config3_sys_gpio26(hw);
5904 }
5905
5906 void sys_hal_set_gpio_config3_sys_gpio26(sys_hw_t *hw, uint32_t value)
5907 {
5908 sys_ll_set_gpio_config3_sys_gpio26(hw, value);
5909 }
5910
5911 /* REG_0x33:gpio_config3->sys_gpio27:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x33[15:12]*/
5912 uint32_t sys_hal_get_gpio_config3_sys_gpio27(sys_hw_t *hw)
5913 {
5914 return sys_ll_get_gpio_config3_sys_gpio27(hw);
5915 }
5916
5917 void sys_hal_set_gpio_config3_sys_gpio27(sys_hw_t *hw, uint32_t value)
5918 {
5919 sys_ll_set_gpio_config3_sys_gpio27(hw, value);
5920 }
5921
5922 /* REG_0x33:gpio_config3->sys_gpio28:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x33[19:16]*/
5923 uint32_t sys_hal_get_gpio_config3_sys_gpio28(sys_hw_t *hw)
5924 {
5925 return sys_ll_get_gpio_config3_sys_gpio28(hw);
5926 }
5927
5928 void sys_hal_set_gpio_config3_sys_gpio28(sys_hw_t *hw, uint32_t value)
5929 {
5930 sys_ll_set_gpio_config3_sys_gpio28(hw, value);
5931 }
5932
5933 /* REG_0x33:gpio_config3->sys_gpio29:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x33[23:20]*/
5934 uint32_t sys_hal_get_gpio_config3_sys_gpio29(sys_hw_t *hw)
5935 {
5936 return sys_ll_get_gpio_config3_sys_gpio29(hw);
5937 }
5938
5939 void sys_hal_set_gpio_config3_sys_gpio29(sys_hw_t *hw, uint32_t value)
5940 {
5941 sys_ll_set_gpio_config3_sys_gpio29(hw, value);
5942 }
5943
5944 /* REG_0x33:gpio_config3->sys_gpio30:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x33[27:24]*/
5945 uint32_t sys_hal_get_gpio_config3_sys_gpio30(sys_hw_t *hw)
5946 {
5947 return sys_ll_get_gpio_config3_sys_gpio30(hw);
5948 }
5949
5950 void sys_hal_set_gpio_config3_sys_gpio30(sys_hw_t *hw, uint32_t value)
5951 {
5952 sys_ll_set_gpio_config3_sys_gpio30(hw, value);
5953 }
5954
5955 /* REG_0x33:gpio_config3->sys_gpio31:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x33[31:28]*/
5956 uint32_t sys_hal_get_gpio_config3_sys_gpio31(sys_hw_t *hw)
5957 {
5958 return sys_ll_get_gpio_config3_sys_gpio31(hw);
5959 }
5960
5961 void sys_hal_set_gpio_config3_sys_gpio31(sys_hw_t *hw, uint32_t value)
5962 {
5963 sys_ll_set_gpio_config3_sys_gpio31(hw, value);
5964 }
5965
5966 /* REG_0x34 */
5967
5968 uint32_t sys_hal_get_gpio_config4_value(sys_hw_t *hw)
5969 {
5970 return sys_ll_get_gpio_config4_value(hw);
5971 }
5972
5973 void sys_hal_set_gpio_config4_value(sys_hw_t *hw, uint32_t value)
5974 {
5975 sys_ll_set_gpio_config4_value(hw, value);
5976 }
5977
5978 /* REG_0x34:gpio_config4->sys_gpio32:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x34[3:0]*/
5979 uint32_t sys_hal_get_gpio_config4_sys_gpio32(sys_hw_t *hw)
5980 {
5981 return sys_ll_get_gpio_config4_sys_gpio32(hw);
5982 }
5983
5984 void sys_hal_set_gpio_config4_sys_gpio32(sys_hw_t *hw, uint32_t value)
5985 {
5986 sys_ll_set_gpio_config4_sys_gpio32(hw, value);
5987 }
5988
5989 /* REG_0x34:gpio_config4->sys_gpio33:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x34[7:4]*/
5990 uint32_t sys_hal_get_gpio_config4_sys_gpio33(sys_hw_t *hw)
5991 {
5992 return sys_ll_get_gpio_config4_sys_gpio33(hw);
5993 }
5994
5995 void sys_hal_set_gpio_config4_sys_gpio33(sys_hw_t *hw, uint32_t value)
5996 {
5997 sys_ll_set_gpio_config4_sys_gpio33(hw, value);
5998 }
5999
6000 /* REG_0x34:gpio_config4->sys_gpio34:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x34[11:8]*/
6001 uint32_t sys_hal_get_gpio_config4_sys_gpio34(sys_hw_t *hw)
6002 {
6003 return sys_ll_get_gpio_config4_sys_gpio34(hw);
6004 }
6005
6006 void sys_hal_set_gpio_config4_sys_gpio34(sys_hw_t *hw, uint32_t value)
6007 {
6008 sys_ll_set_gpio_config4_sys_gpio34(hw, value);
6009 }
6010
6011 /* REG_0x34:gpio_config4->sys_gpio35:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x34[15:12]*/
6012 uint32_t sys_hal_get_gpio_config4_sys_gpio35(sys_hw_t *hw)
6013 {
6014 return sys_ll_get_gpio_config4_sys_gpio35(hw);
6015 }
6016
6017 void sys_hal_set_gpio_config4_sys_gpio35(sys_hw_t *hw, uint32_t value)
6018 {
6019 sys_ll_set_gpio_config4_sys_gpio35(hw, value);
6020 }
6021
6022 /* REG_0x34:gpio_config4->sys_gpio36:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x34[19:16]*/
6023 uint32_t sys_hal_get_gpio_config4_sys_gpio36(sys_hw_t *hw)
6024 {
6025 return sys_ll_get_gpio_config4_sys_gpio36(hw);
6026 }
6027
6028 void sys_hal_set_gpio_config4_sys_gpio36(sys_hw_t *hw, uint32_t value)
6029 {
6030 sys_ll_set_gpio_config4_sys_gpio36(hw, value);
6031 }
6032
6033 /* REG_0x34:gpio_config4->sys_gpio37:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x34[23:20]*/
6034 uint32_t sys_hal_get_gpio_config4_sys_gpio37(sys_hw_t *hw)
6035 {
6036 return sys_ll_get_gpio_config4_sys_gpio37(hw);
6037 }
6038
6039 void sys_hal_set_gpio_config4_sys_gpio37(sys_hw_t *hw, uint32_t value)
6040 {
6041 sys_ll_set_gpio_config4_sys_gpio37(hw, value);
6042 }
6043
6044 /* REG_0x34:gpio_config4->sys_gpio38:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x34[27:24]*/
6045 uint32_t sys_hal_get_gpio_config4_sys_gpio38(sys_hw_t *hw)
6046 {
6047 return sys_ll_get_gpio_config4_sys_gpio38(hw);
6048 }
6049
6050 void sys_hal_set_gpio_config4_sys_gpio38(sys_hw_t *hw, uint32_t value)
6051 {
6052 sys_ll_set_gpio_config4_sys_gpio38(hw, value);
6053 }
6054
6055 /* REG_0x34:gpio_config4->sys_gpio39:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x34[31:28]*/
6056 uint32_t sys_hal_get_gpio_config4_sys_gpio39(sys_hw_t *hw)
6057 {
6058 return sys_ll_get_gpio_config4_sys_gpio39(hw);
6059 }
6060
6061 void sys_hal_set_gpio_config4_sys_gpio39(sys_hw_t *hw, uint32_t value)
6062 {
6063 sys_ll_set_gpio_config4_sys_gpio39(hw, value);
6064 }
6065
6066 /* REG_0x35 */
6067
6068 uint32_t sys_hal_get_gpio_config5_value(sys_hw_t *hw)
6069 {
6070 return sys_ll_get_gpio_config5_value(hw);
6071 }
6072
6073 void sys_hal_set_gpio_config5_value(sys_hw_t *hw, uint32_t value)
6074 {
6075 sys_ll_set_gpio_config5_value(hw, value);
6076 }
6077
6078 /* REG_0x35:gpio_config5->sys_gpio40:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x35[3:0]*/
6079 uint32_t sys_hal_get_gpio_config5_sys_gpio40(sys_hw_t *hw)
6080 {
6081 return sys_ll_get_gpio_config5_sys_gpio40(hw);
6082 }
6083
6084 void sys_hal_set_gpio_config5_sys_gpio40(sys_hw_t *hw, uint32_t value)
6085 {
6086 sys_ll_set_gpio_config5_sys_gpio40(hw, value);
6087 }
6088
6089 /* REG_0x35:gpio_config5->sys_gpio41:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x35[7:4]*/
6090 uint32_t sys_hal_get_gpio_config5_sys_gpio41(sys_hw_t *hw)
6091 {
6092 return sys_ll_get_gpio_config5_sys_gpio41(hw);
6093 }
6094
6095 void sys_hal_set_gpio_config5_sys_gpio41(sys_hw_t *hw, uint32_t value)
6096 {
6097 sys_ll_set_gpio_config5_sys_gpio41(hw, value);
6098 }
6099
6100 /* REG_0x35:gpio_config5->sys_gpio42:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x35[11:8]*/
6101 uint32_t sys_hal_get_gpio_config5_sys_gpio42(sys_hw_t *hw)
6102 {
6103 return sys_ll_get_gpio_config5_sys_gpio42(hw);
6104 }
6105
6106 void sys_hal_set_gpio_config5_sys_gpio42(sys_hw_t *hw, uint32_t value)
6107 {
6108 sys_ll_set_gpio_config5_sys_gpio42(hw, value);
6109 }
6110
6111 /* REG_0x35:gpio_config5->sys_gpio43:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x35[15:12]*/
6112 uint32_t sys_hal_get_gpio_config5_sys_gpio43(sys_hw_t *hw)
6113 {
6114 return sys_ll_get_gpio_config5_sys_gpio43(hw);
6115 }
6116
6117 void sys_hal_set_gpio_config5_sys_gpio43(sys_hw_t *hw, uint32_t value)
6118 {
6119 sys_ll_set_gpio_config5_sys_gpio43(hw, value);
6120 }
6121
6122 /* REG_0x35:gpio_config5->sys_gpio44:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x35[19:16]*/
6123 uint32_t sys_hal_get_gpio_config5_sys_gpio44(sys_hw_t *hw)
6124 {
6125 return sys_ll_get_gpio_config5_sys_gpio44(hw);
6126 }
6127
6128 void sys_hal_set_gpio_config5_sys_gpio44(sys_hw_t *hw, uint32_t value)
6129 {
6130 sys_ll_set_gpio_config5_sys_gpio44(hw, value);
6131 }
6132
6133 /* REG_0x35:gpio_config5->sys_gpio45:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x35[23:20]*/
6134 uint32_t sys_hal_get_gpio_config5_sys_gpio45(sys_hw_t *hw)
6135 {
6136 return sys_ll_get_gpio_config5_sys_gpio45(hw);
6137 }
6138
6139 void sys_hal_set_gpio_config5_sys_gpio45(sys_hw_t *hw, uint32_t value)
6140 {
6141 sys_ll_set_gpio_config5_sys_gpio45(hw, value);
6142 }
6143
6144 /* REG_0x35:gpio_config5->sys_gpio46:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x35[27:24]*/
6145 uint32_t sys_hal_get_gpio_config5_sys_gpio46(sys_hw_t *hw)
6146 {
6147 return sys_ll_get_gpio_config5_sys_gpio46(hw);
6148 }
6149
6150 void sys_hal_set_gpio_config5_sys_gpio46(sys_hw_t *hw, uint32_t value)
6151 {
6152 sys_ll_set_gpio_config5_sys_gpio46(hw, value);
6153 }
6154
6155 /* REG_0x35:gpio_config5->sys_gpio47:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x35[31:28]*/
6156 uint32_t sys_hal_get_gpio_config5_sys_gpio47(sys_hw_t *hw)
6157 {
6158 return sys_ll_get_gpio_config5_sys_gpio47(hw);
6159 }
6160
6161 void sys_hal_set_gpio_config5_sys_gpio47(sys_hw_t *hw, uint32_t value)
6162 {
6163 sys_ll_set_gpio_config5_sys_gpio47(hw, value);
6164 }
6165
6166 /* REG_0x38 */
6167
6168 uint32_t sys_hal_get_sys_debug_config0_value(sys_hw_t *hw)
6169 {
6170 return sys_ll_get_sys_debug_config0_value(hw);
6171 }
6172
6173 void sys_hal_set_sys_debug_config0_value(sys_hw_t *hw, uint32_t value)
6174 {
6175 sys_ll_set_sys_debug_config0_value(hw, value);
6176 }
6177
6178 /* REG_0x38:sys_debug_config0->dbug_config0: ,R/W,0x38[31:0]*/
6179 uint32_t sys_hal_get_sys_debug_config0_dbug_config0(sys_hw_t *hw)
6180 {
6181 return sys_ll_get_sys_debug_config0_dbug_config0(hw);
6182 }
6183
6184 void sys_hal_set_sys_debug_config0_dbug_config0(sys_hw_t *hw, uint32_t value)
6185 {
6186 sys_ll_set_sys_debug_config0_dbug_config0(hw, value);
6187 }
6188
6189 /* REG_0x39 */
6190
6191 uint32_t sys_hal_get_sys_debug_config1_value(sys_hw_t *hw)
6192 {
6193 return sys_ll_get_sys_debug_config1_value(hw);
6194 }
6195
6196 void sys_hal_set_sys_debug_config1_value(sys_hw_t *hw, uint32_t value)
6197 {
6198 sys_ll_set_sys_debug_config1_value(hw, value);
6199 }
6200
6201 /* REG_0x39:sys_debug_config1->dbug_config1:0: btsp_debug[0:32] 1: btsp_debug[32+:32] 2: btsp_debug[64+:32] 4:btsp_debug[96+:6] 5:wifip_mac_dbg[31:0] 6: wifip_phy_dbg[31:0] default: dbug_config0 ,R/W,0x39[31:0]*/
6202 uint32_t sys_hal_get_sys_debug_config1_dbug_config1(sys_hw_t *hw)
6203 {
6204 return sys_ll_get_sys_debug_config1_dbug_config1(hw);
6205 }
6206
6207 void sys_hal_set_sys_debug_config1_dbug_config1(sys_hw_t *hw, uint32_t value)
6208 {
6209 sys_ll_set_sys_debug_config1_dbug_config1(hw, value);
6210 }
6211
6212 /* REG_0x40 */
6213
6214 void sys_hal_set_ana_reg0_value(sys_hw_t *hw, uint32_t value)
6215 {
6216 sys_ll_set_ana_reg0_value(hw, value);
6217 }
6218
6219 /* REG_0x40:ana_reg0->ck2652sel:1:26MHz/0:52MHz,W,0x40[0]*/
6220 void sys_hal_set_ana_reg0_ck2652sel(sys_hw_t *hw, uint32_t value)
6221 {
6222 sys_ll_set_ana_reg0_ck2652sel(hw, value);
6223 }
6224
6225 /* REG_0x40:ana_reg0->cp:cp curent control 0to 350uA 50uA step,W,0x40[3:1]*/
6226 void sys_hal_set_ana_reg0_cp(sys_hw_t *hw, uint32_t value)
6227 {
6228 sys_ll_set_ana_reg0_cp(hw, value);
6229 }
6230
6231 /* REG_0x40:ana_reg0->spideten:unlock detect enable fron spi 1:enable,W,0x40[4]*/
6232 void sys_hal_set_ana_reg0_spideten(sys_hw_t *hw, uint32_t value)
6233 {
6234 sys_ll_set_ana_reg0_spideten(hw, value);
6235 }
6236
6237 /* REG_0x40:ana_reg0->hvref:high vth control for unlock detect 00:0.85V;01:0.9V;10:0.95V;11:1.05V,W,0x40[6:5]*/
6238 void sys_hal_set_ana_reg0_hvref(sys_hw_t *hw, uint32_t value)
6239 {
6240 sys_ll_set_ana_reg0_hvref(hw, value);
6241 }
6242
6243 /* REG_0x40:ana_reg0->lvref:low vth control for unlock detect 00:0.2V;01:0.3V;10:0.35V;11:0.4V,W,0x40[8:7]*/
6244 void sys_hal_set_ana_reg0_lvref(sys_hw_t *hw, uint32_t value)
6245 {
6246 sys_ll_set_ana_reg0_lvref(hw, value);
6247 }
6248
6249 /* REG_0x40:ana_reg0->Rzctrl26M:Rz ctrl in 26M mode:1:normal;0:add 14K,W,0x40[9]*/
6250 void sys_hal_set_ana_reg0_rzctrl26m(sys_hw_t *hw, uint32_t value)
6251 {
6252 sys_ll_set_ana_reg0_rzctrl26m(hw, value);
6253 }
6254
6255 /* REG_0x40:ana_reg0->LoopRzctrl:Rz ctrl:2K to 17K,1K step,W,0x40[13:10]*/
6256 void sys_hal_set_ana_reg0_looprzctrl(sys_hw_t *hw, uint32_t value)
6257 {
6258 sys_ll_set_ana_reg0_looprzctrl(hw, value);
6259 }
6260
6261 /* REG_0x40:ana_reg0->rpc:second pole Rp ctrl:00:30K;01:10K;10:22K;11:2K,W,0x40[15:14]*/
6262 void sys_hal_set_ana_reg0_rpc(sys_hw_t *hw, uint32_t value)
6263 {
6264 sys_ll_set_ana_reg0_rpc(hw, value);
6265 }
6266
6267 /* REG_0x40:ana_reg0->nsyn:N divider rst,W,0x40[16]*/
6268 void sys_hal_set_ana_reg0_nsyn(sys_hw_t *hw, uint32_t value)
6269 {
6270 sys_ll_set_ana_reg0_nsyn(hw, value);
6271 }
6272
6273 /* REG_0x40:ana_reg0->cksel:0:26M;1:40M;2:24M;3:19.2M,W,0x40[18:17]*/
6274 void sys_hal_set_ana_reg0_cksel(sys_hw_t *hw, uint32_t value)
6275 {
6276 sys_ll_set_ana_reg0_cksel(hw, value);
6277 }
6278
6279 /* REG_0x40:ana_reg0->spitrig:SPI band selection trigger signal,W,0x40[19]*/
6280 void sys_hal_set_ana_reg0_spitrig(sys_hw_t *hw, uint32_t value)
6281 {
6282 sys_ll_set_ana_reg0_spitrig(hw, value);
6283 }
6284
6285 /* REG_0x40:ana_reg0->band:band manual value/band[0] ,W,0x40[24:20]*/
6286 void sys_hal_set_ana_reg0_band(sys_hw_t *hw, uint32_t value)
6287 {
6288 sys_ll_set_ana_reg0_band(hw, value);
6289 }
6290
6291 /* REG_0x40:ana_reg0->bandmanual:1:band manual;0:band auto,W,0x40[25]*/
6292 void sys_hal_set_ana_reg0_bandmanual(sys_hw_t *hw, uint32_t value)
6293 {
6294 sys_ll_set_ana_reg0_bandmanual(hw, value);
6295 }
6296
6297 /* REG_0x40:ana_reg0->dsptrig:band selection trigger signal,W,0x40[26]*/
6298 void sys_hal_set_ana_reg0_dsptrig(sys_hw_t *hw, uint32_t value)
6299 {
6300 sys_ll_set_ana_reg0_dsptrig(hw, value);
6301 }
6302
6303 /* REG_0x40:ana_reg0->lpen_dpll:dpll low power mode enable,W,0x40[27]*/
6304 void sys_hal_set_ana_reg0_lpen_dpll(sys_hw_t *hw, uint32_t value)
6305 {
6306 sys_ll_set_ana_reg0_lpen_dpll(hw, value);
6307 }
6308
6309 /* REG_0x40:ana_reg0->xamp:xtal OSC amp control/xamp<0> shared with pll_cktst_en,W,0x40[31:28]*/
6310 void sys_hal_set_ana_reg0_xamp(sys_hw_t *hw, uint32_t value)
6311 {
6312 sys_ll_set_ana_reg0_xamp(hw, value);
6313 }
6314
6315 /* REG_0x41 */
6316
6317 void sys_hal_set_ana_reg1_value(sys_hw_t *hw, uint32_t value)
6318 {
6319 sys_ll_set_ana_reg1_value(hw, value);
6320 }
6321
6322 /* REG_0x41:ana_reg1->dpll_vrefsel:dpll ldo reference voltage selection 0:vbg_aon/1:vbg_cal,W,0x41[1]*/
6323 void sys_hal_set_ana_reg1_dpll_vrefsel(sys_hw_t *hw, uint32_t value)
6324 {
6325 sys_ll_set_ana_reg1_dpll_vrefsel(hw, value);
6326 }
6327
6328 /* REG_0x41:ana_reg1->msw:set the frequency of DCO manual,W,0x41[10:2]*/
6329 void sys_hal_set_ana_reg1_msw(sys_hw_t *hw, uint32_t value)
6330 {
6331 sys_ll_set_ana_reg1_msw(hw, value);
6332 }
6333
6334 /* REG_0x41:ana_reg1->ictrl:controlling the bias cuttent of DCO core,W,0x41[13:11]*/
6335 void sys_hal_set_ana_reg1_ictrl(sys_hw_t *hw, uint32_t value)
6336 {
6337 sys_ll_set_ana_reg1_ictrl(hw, value);
6338 }
6339
6340 /* REG_0x41:ana_reg1->osc_trig:reset the DCO core by spi to make it oscillate again,W,0x41[14]*/
6341 void sys_hal_set_ana_reg1_osc_trig(sys_hw_t *hw, uint32_t value)
6342 {
6343 sys_ll_set_ana_reg1_osc_trig(hw, value);
6344 }
6345
6346 /* REG_0x41:ana_reg1->osccal_trig:trigger the action of callibration in the DCO,W,0x41[15]*/
6347 void sys_hal_set_ana_reg1_osccal_trig(sys_hw_t *hw, uint32_t value)
6348 {
6349 sys_ll_set_ana_reg1_osccal_trig(hw, value);
6350 }
6351
6352 /* REG_0x41:ana_reg1->cnti:set the controlling work of calibration in the DCO block to get the different frequency,W,0x41[24:16]*/
6353 void sys_hal_set_ana_reg1_cnti(sys_hw_t *hw, uint32_t value)
6354 {
6355 sys_ll_set_ana_reg1_cnti(hw, value);
6356 }
6357
6358 /* REG_0x41:ana_reg1->spi_rst:reset the calibration block of DCO by spi,W,0x41[25]*/
6359 void sys_hal_set_ana_reg1_spi_rst(sys_hw_t *hw, uint32_t value)
6360 {
6361 sys_ll_set_ana_reg1_spi_rst(hw, value);
6362 }
6363
6364 /* REG_0x41:ana_reg1->amsel:disable the calibration function of the DCO,set the frequency of DCO manual,W,0x41[26]*/
6365 void sys_hal_set_ana_reg1_amsel(sys_hw_t *hw, uint32_t value)
6366 {
6367 sys_ll_set_ana_reg1_amsel(hw, value);
6368 }
6369
6370 /* REG_0x41:ana_reg1->divctrl:controlling the value of divider in the DCO to get the different frequency,W,0x41[29:27]*/
6371 void sys_hal_set_ana_reg1_divctrl(sys_hw_t *hw, uint32_t value)
6372 {
6373 sys_ll_set_ana_reg1_divctrl(hw, value);
6374 }
6375
6376 /* REG_0x41:ana_reg1->dco_tsten:dco test enable,W,0x41[30]*/
6377 void sys_hal_set_ana_reg1_dco_tsten(sys_hw_t *hw, uint32_t value)
6378 {
6379 sys_ll_set_ana_reg1_dco_tsten(hw, value);
6380 }
6381
6382 /* REG_0x41:ana_reg1->rosc_tsten:rosc test enable,W,0x41[31]*/
6383 void sys_hal_set_ana_reg1_rosc_tsten(sys_hw_t *hw, uint32_t value)
6384 {
6385 sys_ll_set_ana_reg1_rosc_tsten(hw, value);
6386 }
6387
6388 /* REG_0x42 */
6389
6390 void sys_hal_set_ana_reg2_value(sys_hw_t *hw, uint32_t value)
6391 {
6392 sys_ll_set_ana_reg2_value(hw, value);
6393 }
6394
6395 /* REG_0x42:ana_reg2->pwmscmen:buck nmos disable,W,0x42[0]*/
6396 void sys_hal_set_ana_reg2_pwmscmen(sys_hw_t *hw, uint32_t value)
6397 {
6398 sys_ll_set_ana_reg2_pwmscmen(hw, value);
6399 }
6400
6401 /* REG_0x42:ana_reg2->buck_fasten:buck EA fast transient enable(=1),W,0x42[1]*/
6402 void sys_hal_set_ana_reg2_buck_fasten(sys_hw_t *hw, uint32_t value)
6403 {
6404 sys_ll_set_ana_reg2_buck_fasten(hw, value);
6405 }
6406
6407 /* REG_0x42:ana_reg2->cls:buck current limit setting,W,0x42[4:2]*/
6408 void sys_hal_set_ana_reg2_cls(sys_hw_t *hw, uint32_t value)
6409 {
6410 sys_ll_set_ana_reg2_cls(hw, value);
6411 }
6412
6413 /* REG_0x42:ana_reg2->pfms:buck freewheeling damping enable(=1) ,W,0x42[9:5]*/
6414 void sys_hal_set_ana_reg2_pfms(sys_hw_t *hw, uint32_t value)
6415 {
6416 sys_ll_set_ana_reg2_pfms(hw, value);
6417 }
6418
6419 /* REG_0x42:ana_reg2->ripc:buck pfm mode voltage ripple control setting,W,0x42[12:10]*/
6420 void sys_hal_set_ana_reg2_ripc(sys_hw_t *hw, uint32_t value)
6421 {
6422 sys_ll_set_ana_reg2_ripc(hw, value);
6423 }
6424
6425 /* REG_0x42:ana_reg2->rampc:buck ramping compensation setting,W,0x42[16:13]*/
6426 void sys_hal_set_ana_reg2_rampc(sys_hw_t *hw, uint32_t value)
6427 {
6428 sys_ll_set_ana_reg2_rampc(hw, value);
6429 }
6430
6431 /* REG_0x42:ana_reg2->rampcen:buck ramping compensation enable(=1),W,0x42[17]*/
6432 void sys_hal_set_ana_reg2_rampcen(sys_hw_t *hw, uint32_t value)
6433 {
6434 sys_ll_set_ana_reg2_rampcen(hw, value);
6435 }
6436
6437 /* REG_0x42:ana_reg2->dpfmen:buck pfm mode current reduce enable(=1),W,0x42[18]*/
6438 void sys_hal_set_ana_reg2_dpfmen(sys_hw_t *hw, uint32_t value)
6439 {
6440 sys_ll_set_ana_reg2_dpfmen(hw, value);
6441 }
6442
6443 /* REG_0x42:ana_reg2->pfmen:buck pfm mode enable(=1),W,0x42[19]*/
6444 void sys_hal_set_ana_reg2_pfmen(sys_hw_t *hw, uint32_t value)
6445 {
6446 sys_ll_set_ana_reg2_pfmen(hw, value);
6447 }
6448
6449 /* REG_0x42:ana_reg2->forcepfm:buck force pfm mode(=1),W,0x42[20]*/
6450 void sys_hal_set_ana_reg2_forcepfm(sys_hw_t *hw, uint32_t value)
6451 {
6452 sys_ll_set_ana_reg2_forcepfm(hw, value);
6453 }
6454
6455 /* REG_0x42:ana_reg2->swrsten:buck freewheeling damping enable(=1) ,W,0x42[21]*/
6456 void sys_hal_set_ana_reg2_swrsten(sys_hw_t *hw, uint32_t value)
6457 {
6458 sys_ll_set_ana_reg2_swrsten(hw, value);
6459 }
6460
6461 /* REG_0x42:ana_reg2->tmposel:buck mpo pulse width control 0--shortest 3---longest,W,0x42[23:22]*/
6462 void sys_hal_set_ana_reg2_tmposel(sys_hw_t *hw, uint32_t value)
6463 {
6464 sys_ll_set_ana_reg2_tmposel(hw, value);
6465 }
6466
6467 /* REG_0x42:ana_reg2->mpoen:buck mpo mode enable( =1),W,0x42[24]*/
6468 void sys_hal_set_ana_reg2_mpoen(sys_hw_t *hw, uint32_t value)
6469 {
6470 sys_ll_set_ana_reg2_mpoen(hw, value);
6471 }
6472
6473 /* REG_0x42:ana_reg2->spi_latchb:spi latch disable 0:latch;1:no latch,W,0x42[25]*/
6474 void sys_hal_set_ana_reg2_spi_latchb(sys_hw_t *hw, uint32_t value)
6475 {
6476 sys_ll_set_ana_reg2_spi_latchb(hw, value);
6477 }
6478
6479 /* REG_0x42:ana_reg2->ldosel:ldo/buck select, 0:buck;1:LDO,W,0x42[26]*/
6480 void sys_hal_set_ana_reg2_ldosel(sys_hw_t *hw, uint32_t value)
6481 {
6482 sys_ll_set_ana_reg2_ldosel(hw, value);
6483 }
6484
6485 /* REG_0x42:ana_reg2->iovoc:ioldo output voltage select 0:2.9V,….7:3.6V,W,0x42[29:27]*/
6486 void sys_hal_set_ana_reg2_iovoc(sys_hw_t *hw, uint32_t value)
6487 {
6488 sys_ll_set_ana_reg2_iovoc(hw, value);
6489 }
6490
6491 /* REG_0x42:ana_reg2->vbpbuf_hp:vbspbuffer high power enable,W,0x42[30]*/
6492 void sys_hal_set_ana_reg2_vbpbuf_hp(sys_hw_t *hw, uint32_t value)
6493 {
6494 sys_ll_set_ana_reg2_vbpbuf_hp(hw, value);
6495 }
6496
6497 /* REG_0x42:ana_reg2->bypassen:ioldo bypass enable,W,0x42[31]*/
6498 void sys_hal_set_ana_reg2_bypassen(sys_hw_t *hw, uint32_t value)
6499 {
6500 sys_ll_set_ana_reg2_bypassen(hw, value);
6501 }
6502
6503 /* REG_0x43 */
6504
6505 void sys_hal_set_ana_reg3_value(sys_hw_t *hw, uint32_t value)
6506 {
6507 sys_ll_set_ana_reg3_value(hw, value);
6508 }
6509
6510 /* REG_0x43:ana_reg3->zcdta:buck zcd delay tune setting,W,0x43[4:0]*/
6511 void sys_hal_set_ana_reg3_zcdta(sys_hw_t *hw, uint32_t value)
6512 {
6513 sys_ll_set_ana_reg3_zcdta(hw, value);
6514 }
6515
6516 /* REG_0x43:ana_reg3->zcdcala:buck zcd offset cali setting,W,0x43[10:5]*/
6517 void sys_hal_set_ana_reg3_zcdcala(sys_hw_t *hw, uint32_t value)
6518 {
6519 sys_ll_set_ana_reg3_zcdcala(hw, value);
6520 }
6521
6522 /* REG_0x43:ana_reg3->zcdmen:buck zcd manual cali enable(=1),W,0x43[11]*/
6523 void sys_hal_set_ana_reg3_zcdmen(sys_hw_t *hw, uint32_t value)
6524 {
6525 sys_ll_set_ana_reg3_zcdmen(hw, value);
6526 }
6527
6528 /* REG_0x43:ana_reg3->zcdcalen:buck zcd calibration enable(=1),W,0x43[12]*/
6529 void sys_hal_set_ana_reg3_zcdcalen(sys_hw_t *hw, uint32_t value)
6530 {
6531 sys_ll_set_ana_reg3_zcdcalen(hw, value);
6532 }
6533
6534 /* REG_0x43:ana_reg3->zcdcal_tri:buck zcd auto cali triggle(0-->1),W,0x43[13]*/
6535 void sys_hal_set_ana_reg3_zcdcal_tri(sys_hw_t *hw, uint32_t value)
6536 {
6537 sys_ll_set_ana_reg3_zcdcal_tri(hw, value);
6538 }
6539
6540 /* REG_0x43:ana_reg3->mroscsel:buck oscillator manual cali. enable(=1),W,0x43[14]*/
6541 void sys_hal_set_ana_reg3_mroscsel(sys_hw_t *hw, uint32_t value)
6542 {
6543 sys_ll_set_ana_reg3_mroscsel(hw, value);
6544 }
6545
6546 /* REG_0x43:ana_reg3->mfsel:buck oscillator manual fsel ,W,0x43[17:15]*/
6547 void sys_hal_set_ana_reg3_mfsel(sys_hw_t *hw, uint32_t value)
6548 {
6549 sys_ll_set_ana_reg3_mfsel(hw, value);
6550 }
6551
6552 /* REG_0x43:ana_reg3->mroscbcal:buck oscillator manual cap_cal 0xA---500k 0xB--1M 0x9---2M,W,0x43[21:18]*/
6553 void sys_hal_set_ana_reg3_mroscbcal(sys_hw_t *hw, uint32_t value)
6554 {
6555 sys_ll_set_ana_reg3_mroscbcal(hw, value);
6556 }
6557
6558 /* REG_0x43:ana_reg3->osccaltrig:buck oscillator manual cali. enable(=1),W,0x43[22]*/
6559 void sys_hal_set_ana_reg3_osccaltrig(sys_hw_t *hw, uint32_t value)
6560 {
6561 sys_ll_set_ana_reg3_osccaltrig(hw, value);
6562 }
6563
6564 /* REG_0x43:ana_reg3->ckintsel:buck clock source select 1-- ring oscillator 0--divider,W,0x43[23]*/
6565 void sys_hal_set_ana_reg3_ckintsel(sys_hw_t *hw, uint32_t value)
6566 {
6567 sys_ll_set_ana_reg3_ckintsel(hw, value);
6568 }
6569
6570 /* REG_0x43:ana_reg3->ckfs:buck output clock freq. select 0--500k 1---1M 2--2M 3--4M,W,0x43[25:24]*/
6571 void sys_hal_set_ana_reg3_ckfs(sys_hw_t *hw, uint32_t value)
6572 {
6573 sys_ll_set_ana_reg3_ckfs(hw, value);
6574 }
6575
6576 /* REG_0x43:ana_reg3->vlsel_ldodig:digldo output voltage select(low power) 0:0.6V,…..7:1.4V,W,0x43[28:26]*/
6577 void sys_hal_set_ana_reg3_vlsel_ldodig(sys_hw_t *hw, uint32_t value)
6578 {
6579 sys_ll_set_ana_reg3_vlsel_ldodig(hw, value);
6580 }
6581
6582 /* REG_0x43:ana_reg3->vhsel_ldodig:digldo output voltage select(high power) 0:0.6V,…..7:1.4V,W,0x43[31:29]*/
6583 void sys_hal_set_ana_reg3_vhsel_ldodig(sys_hw_t *hw, uint32_t value)
6584 {
6585 sys_ll_set_ana_reg3_vhsel_ldodig(hw, value);
6586 }
6587
6588 /* REG_0x44 */
6589
6590 void sys_hal_set_ana_reg4_value(sys_hw_t *hw, uint32_t value)
6591 {
6592 sys_ll_set_ana_reg4_value(hw, value);
6593 }
6594
6595 /* REG_0x44:ana_reg4->cb_manu_val:CB Calibration Manual Value,W,0x44[9:5]*/
6596 void sys_hal_set_ana_reg4_cb_manu_val(sys_hw_t *hw, uint32_t value)
6597 {
6598 sys_ll_set_ana_reg4_cb_manu_val(hw, value);
6599 }
6600
6601 /* REG_0x44:ana_reg4->cb_cal_trig:CB Calibration Trigger,W,0x44[10]*/
6602 void sys_hal_set_ana_reg4_cb_cal_trig(sys_hw_t *hw, uint32_t value)
6603 {
6604 sys_ll_set_ana_reg4_cb_cal_trig(hw, value);
6605 }
6606
6607 /* REG_0x44:ana_reg4->cb_cal_manu:CB Calibration Manual Mode ,W,0x44[11]*/
6608 void sys_hal_set_ana_reg4_cb_cal_manu(sys_hw_t *hw, uint32_t value)
6609 {
6610 sys_ll_set_ana_reg4_cb_cal_manu(hw, value);
6611 }
6612
6613 /* REG_0x44:ana_reg4->rosc_cal_intval:Rosc Calibration Interlval 0.25s~2s,W,0x44[14:12]*/
6614 void sys_hal_set_ana_reg4_rosc_cal_intval(sys_hw_t *hw, uint32_t value)
6615 {
6616 sys_ll_set_ana_reg4_rosc_cal_intval(hw, value);
6617 }
6618
6619 /* REG_0x44:ana_reg4->manu_cin:Rosc Calibration Manual Cin,W,0x44[21:15]*/
6620 void sys_hal_set_ana_reg4_manu_cin(sys_hw_t *hw, uint32_t value)
6621 {
6622 sys_ll_set_ana_reg4_manu_cin(hw, value);
6623 }
6624
6625 /* REG_0x44:ana_reg4->manu_fin:Rosc Calibration Manual Fin,W,0x44[26:22]*/
6626 void sys_hal_set_ana_reg4_manu_fin(sys_hw_t *hw, uint32_t value)
6627 {
6628 sys_ll_set_ana_reg4_manu_fin(hw, value);
6629 }
6630
6631 /* REG_0x44:ana_reg4->rosc_cal_mode:Rosc Calibration Mode:; 0x1: 32K; 0x0: 31.25K,W,0x44[27]*/
6632 void sys_hal_set_ana_reg4_rosc_cal_mode(sys_hw_t *hw, uint32_t value)
6633 {
6634 sys_ll_set_ana_reg4_rosc_cal_mode(hw, value);
6635 }
6636
6637 /* REG_0x44:ana_reg4->rosc_cal_trig:Rosc Calibration Trigger,W,0x44[28]*/
6638 void sys_hal_set_ana_reg4_rosc_cal_trig(sys_hw_t *hw, uint32_t value)
6639 {
6640 sys_ll_set_ana_reg4_rosc_cal_trig(hw, value);
6641 }
6642
6643 /* REG_0x44:ana_reg4->rosc_cal_en:Rosc Calibration Enable,W,0x44[29]*/
6644 void sys_hal_set_ana_reg4_rosc_cal_en(sys_hw_t *hw, uint32_t value)
6645 {
6646 sys_ll_set_ana_reg4_rosc_cal_en(hw, value);
6647 }
6648
6649 /* REG_0x44:ana_reg4->rosc_manu_en:Rosc Calibration Manual Mode ,W,0x44[30]*/
6650 void sys_hal_set_ana_reg4_rosc_manu_en(sys_hw_t *hw, uint32_t value)
6651 {
6652 sys_ll_set_ana_reg4_rosc_manu_en(hw, value);
6653 }
6654
6655 /* REG_0x44:ana_reg4->rosc_tsten:Rosc test enable,W,0x44[31]*/
6656 void sys_hal_set_ana_reg4_rosc_tsten(sys_hw_t *hw, uint32_t value)
6657 {
6658 sys_ll_set_ana_reg4_rosc_tsten(hw, value);
6659 }
6660
6661 /* REG_0x45 */
6662
6663 void sys_hal_set_ana_reg5_value(sys_hw_t *hw, uint32_t value)
6664 {
6665 sys_ll_set_ana_reg5_value(hw, value);
6666 }
6667
6668 /* REG_0x45:ana_reg5->vref_scale:gadc reference voltage scale enable,W,0x45[0]*/
6669 void sys_hal_set_ana_reg5_vref_scale(sys_hw_t *hw, uint32_t value)
6670 {
6671 sys_ll_set_ana_reg5_vref_scale(hw, value);
6672 }
6673
6674 /* REG_0x45:ana_reg5->dccal_en:gadc DC calibration enable,W,0x45[1]*/
6675 void sys_hal_set_ana_reg5_dccal_en(sys_hw_t *hw, uint32_t value)
6676 {
6677 sys_ll_set_ana_reg5_dccal_en(hw, value);
6678 }
6679
6680 /* REG_0x45:ana_reg5->xtalh_ctune:xtalh load cap tuning,W,0x45[8:2]*/
6681 void sys_hal_set_ana_reg5_xtalh_ctune(sys_hw_t *hw, uint32_t value)
6682 {
6683 sys_ll_set_ana_reg5_xtalh_ctune(hw, value);
6684 }
6685
6686 /* REG_0x45:ana_reg5->cktst_sel:clock test signal selection rosc/xtall/dco/dpll,W,0x45[10:9]*/
6687 void sys_hal_set_ana_reg5_cktst_sel(sys_hw_t *hw, uint32_t value)
6688 {
6689 sys_ll_set_ana_reg5_cktst_sel(hw, value);
6690 }
6691
6692 /* REG_0x45:ana_reg5->ck_tst_enbale:system clock test enable,W,0x45[11]*/
6693 void sys_hal_set_ana_reg5_ck_tst_enbale(sys_hw_t *hw, uint32_t value)
6694 {
6695 sys_ll_set_ana_reg5_ck_tst_enbale(hw, value);
6696 }
6697
6698 /* REG_0x45:ana_reg5->trxt_tst_enable:wifi trx test enable,W,0x45[12]*/
6699 void sys_hal_set_ana_reg5_trxt_tst_enable(sys_hw_t *hw, uint32_t value)
6700 {
6701 sys_ll_set_ana_reg5_trxt_tst_enable(hw, value);
6702 }
6703
6704 /* REG_0x45:ana_reg5->encb:global central bias enable,W,0x45[13]*/
6705 void sys_hal_set_ana_reg5_encb(sys_hw_t *hw, uint32_t value)
6706 {
6707 sys_ll_set_ana_reg5_encb(hw, value);
6708 }
6709
6710 /* REG_0x45:ana_reg5->vctrl_dpllldo:dpll ldo output selection,W,0x45[15:14]*/
6711 void sys_hal_set_ana_reg5_vctrl_dpllldo(sys_hw_t *hw, uint32_t value)
6712 {
6713 sys_ll_set_ana_reg5_vctrl_dpllldo(hw, value);
6714 }
6715
6716 /* REG_0x45:ana_reg5->vctrl_sysldo:sys ldo output selection,W,0x45[17:16]*/
6717 void sys_hal_set_ana_reg5_vctrl_sysldo(sys_hw_t *hw, uint32_t value)
6718 {
6719 sys_ll_set_ana_reg5_vctrl_sysldo(hw, value);
6720 }
6721
6722 /* REG_0x45:ana_reg5->temptst_en:tempdet test enable,W,0x45[18]*/
6723 void sys_hal_set_ana_reg5_temptst_en(sys_hw_t *hw, uint32_t value)
6724 {
6725 sys_ll_set_ana_reg5_temptst_en(hw, value);
6726 }
6727
6728 /* REG_0x45:ana_reg5->gadc_tsel:gadc test signal selection,W,0x45[21:19]*/
6729 void sys_hal_set_ana_reg5_gadc_tsel(sys_hw_t *hw, uint32_t value)
6730 {
6731 sys_ll_set_ana_reg5_gadc_tsel(hw, value);
6732 }
6733
6734 /* REG_0x45:ana_reg5->xtalh_ictrl:xtalh current control,W,0x45[22]*/
6735 void sys_hal_set_ana_reg5_xtalh_ictrl(sys_hw_t *hw, uint32_t value)
6736 {
6737 sys_ll_set_ana_reg5_xtalh_ictrl(hw, value);
6738 }
6739
6740 /* REG_0x45:ana_reg5->bgcalm:bandgap calibration manual setting,W,0x45[28:23]*/
6741 void sys_hal_set_ana_reg5_bgcalm(sys_hw_t *hw, uint32_t value)
6742 {
6743 sys_ll_set_ana_reg5_bgcalm(hw, value);
6744 }
6745
6746 /* REG_0x45:ana_reg5->bgcal_trig:bandgap calibrarion trig,W,0x45[29]*/
6747 void sys_hal_set_ana_reg5_bgcal_trig(sys_hw_t *hw, uint32_t value)
6748 {
6749 sys_ll_set_ana_reg5_bgcal_trig(hw, value);
6750 }
6751
6752 /* REG_0x45:ana_reg5->bgcal_manu:bandgap calibration manual mode enable,W,0x45[30]*/
6753 void sys_hal_set_ana_reg5_bgcal_manu(sys_hw_t *hw, uint32_t value)
6754 {
6755 sys_ll_set_ana_reg5_bgcal_manu(hw, value);
6756 }
6757
6758 /* REG_0x45:ana_reg5->bgcal_en:bandgap calibration enable,W,0x45[31]*/
6759 void sys_hal_set_ana_reg5_bgcal_en(sys_hw_t *hw, uint32_t value)
6760 {
6761 sys_ll_set_ana_reg5_bgcal_en(hw, value);
6762 }
6763
6764 /* REG_0x46 */
6765
6766 void sys_hal_set_ana_reg6_value(sys_hw_t *hw, uint32_t value)
6767 {
6768 sys_ll_set_ana_reg6_value(hw, value);
6769 }
6770
6771 /* REG_0x46:ana_reg6->itune_xtall:xtall core current control,W,0x46[3:0]*/
6772 void sys_hal_set_ana_reg6_itune_xtall(sys_hw_t *hw, uint32_t value)
6773 {
6774 sys_ll_set_ana_reg6_itune_xtall(hw, value);
6775 }
6776
6777 /* REG_0x46:ana_reg6->xtall_ten:xtall test enable,W,0x46[4]*/
6778 void sys_hal_set_ana_reg6_xtall_ten(sys_hw_t *hw, uint32_t value)
6779 {
6780 sys_ll_set_ana_reg6_xtall_ten(hw, value);
6781 }
6782
6783 /* REG_0x46:ana_reg6->psldo_vsel:ps ldo output voltage selection,0:VIO /1:1.8V,W,0x46[5]*/
6784 void sys_hal_set_ana_reg6_psldo_vsel(sys_hw_t *hw, uint32_t value)
6785 {
6786 sys_ll_set_ana_reg6_psldo_vsel(hw, value);
6787 }
6788
6789 /* REG_0x46:ana_reg6->en_usb:usb phy enable,W,0x46[6]*/
6790 void sys_hal_set_ana_reg6_en_usb(sys_hw_t *hw, uint32_t value)
6791 {
6792 sys_ll_set_ana_reg6_en_usb(hw, value);
6793 }
6794
6795 /* REG_0x46:ana_reg6->en_xtall:xtall oscillator enable,W,0x46[7]*/
6796 void sys_hal_set_ana_reg6_en_xtall(sys_hw_t *hw, uint32_t value)
6797 {
6798 sys_ll_set_ana_reg6_en_xtall(hw, value);
6799 }
6800
6801 /* REG_0x46:ana_reg6->en_dco:dco enable,W,0x46[8]*/
6802 void sys_hal_set_ana_reg6_en_dco(sys_hw_t *hw, uint32_t value)
6803 {
6804 sys_ll_set_ana_reg6_en_dco(hw, value);
6805 }
6806
6807 /* REG_0x46:ana_reg6->en_psram_ldo:psram ldo enable,W,0x46[9]*/
6808 void sys_hal_set_ana_reg6_en_psram_ldo(sys_hw_t *hw, uint32_t value)
6809 {
6810 sys_ll_set_ana_reg6_en_psram_ldo(hw, value);
6811 }
6812
6813 /* REG_0x46:ana_reg6->en_tempdet:tempreture det enable,W,0x46[10]*/
6814 void sys_hal_set_ana_reg6_en_tempdet(sys_hw_t *hw, uint32_t value)
6815 {
6816 sys_ll_set_ana_reg6_en_tempdet(hw, value);
6817 }
6818
6819 /* REG_0x46:ana_reg6->en_audpll:audio pll enable,W,0x46[11]*/
6820 void sys_hal_set_ana_reg6_en_audpll(sys_hw_t *hw, uint32_t value)
6821 {
6822 sys_ll_set_ana_reg6_en_audpll(hw, value);
6823 }
6824
6825 /* REG_0x46:ana_reg6->en_dpll:dpll enable,W,0x46[12]*/
6826 void sys_hal_set_ana_reg6_en_dpll(sys_hw_t *hw, uint32_t value)
6827 {
6828 sys_ll_set_ana_reg6_en_dpll(hw, value);
6829 }
6830
6831 /* REG_0x46:ana_reg6->en_sysldo:sysldo enable,W,0x46[13]*/
6832 void sys_hal_set_ana_reg6_en_sysldo(sys_hw_t *hw, uint32_t value)
6833 {
6834 sys_ll_set_ana_reg6_en_sysldo(hw, value);
6835 }
6836
6837 /* REG_0x46:ana_reg6->pwd_gadc_buf:gadc input buffer pwd,W,0x46[17]*/
6838 void sys_hal_set_ana_reg6_pwd_gadc_buf(sys_hw_t *hw, uint32_t value)
6839 {
6840 sys_ll_set_ana_reg6_pwd_gadc_buf(hw, value);
6841 }
6842
6843 /* REG_0x46:ana_reg6->xtal_hpsrr_en:xtal high psrr buffer enable,W,0x46[18]*/
6844 void sys_hal_set_ana_reg6_xtal_hpsrr_en(sys_hw_t *hw, uint32_t value)
6845 {
6846 sys_ll_set_ana_reg6_xtal_hpsrr_en(hw, value);
6847 }
6848
6849 /* REG_0x46:ana_reg6->en_xtal2rf:xtal clock to rfpll gate enable ,W,0x46[19]*/
6850 void sys_hal_set_ana_reg6_en_xtal2rf(sys_hw_t *hw, uint32_t value)
6851 {
6852 sys_ll_set_ana_reg6_en_xtal2rf(hw, value);
6853 }
6854
6855 /* REG_0x46:ana_reg6->en_sleep:xtal sleep enable,W,0x46[20]*/
6856 void sys_hal_set_ana_reg6_en_sleep(sys_hw_t *hw, uint32_t value)
6857 {
6858 sys_ll_set_ana_reg6_en_sleep(hw, value);
6859 }
6860
6861 /* REG_0x46:ana_reg6->clkbuf_hd:xtal lpsrr clock buffer high power mode ,W,0x46[21]*/
6862 void sys_hal_set_ana_reg6_clkbuf_hd(sys_hw_t *hw, uint32_t value)
6863 {
6864 sys_ll_set_ana_reg6_clkbuf_hd(hw, value);
6865 }
6866
6867 /* REG_0x46:ana_reg6->clkbuf_dsel_manu:xtal lpsrr clock buffer power mode selection 0: auto /1:manu ,W,0x46[22]*/
6868 void sys_hal_set_ana_reg6_clkbuf_dsel_manu(sys_hw_t *hw, uint32_t value)
6869 {
6870 sys_ll_set_ana_reg6_clkbuf_dsel_manu(hw, value);
6871 }
6872
6873 /* REG_0x46:ana_reg6->xtal_lpmode_ctrl:xtal core low power mode enable,W,0x46[23]*/
6874 void sys_hal_set_ana_reg6_xtal_lpmode_ctrl(sys_hw_t *hw, uint32_t value)
6875 {
6876 sys_ll_set_ana_reg6_xtal_lpmode_ctrl(hw, value);
6877 }
6878
6879 /* REG_0x46:ana_reg6->rxtal_lp:xtal bias current setting at low power mode ,W,0x46[27:24]*/
6880 void sys_hal_set_ana_reg6_rxtal_lp(sys_hw_t *hw, uint32_t value)
6881 {
6882 sys_ll_set_ana_reg6_rxtal_lp(hw, value);
6883 }
6884
6885 /* REG_0x46:ana_reg6->rxtal_hp:xtal26m bias current setting at high power mode ,W,0x46[31:28]*/
6886 void sys_hal_set_ana_reg6_rxtal_hp(sys_hw_t *hw, uint32_t value)
6887 {
6888 sys_ll_set_ana_reg6_rxtal_hp(hw, value);
6889 }
6890
6891 /* REG_0x47 */
6892
6893 void sys_hal_set_ana_reg7_value(sys_hw_t *hw, uint32_t value)
6894 {
6895 sys_ll_set_ana_reg7_value(hw, value);
6896 }
6897
6898 /* REG_0x47:ana_reg7->rng_tstck_sel:trng setting,W,0x47[0]*/
6899 void sys_hal_set_ana_reg7_rng_tstck_sel(sys_hw_t *hw, uint32_t value)
6900 {
6901 sys_ll_set_ana_reg7_rng_tstck_sel(hw, value);
6902 }
6903
6904 /* REG_0x47:ana_reg7->rng_tsten:trng setting,W,0x47[1]*/
6905 void sys_hal_set_ana_reg7_rng_tsten(sys_hw_t *hw, uint32_t value)
6906 {
6907 sys_ll_set_ana_reg7_rng_tsten(hw, value);
6908 }
6909
6910 /* REG_0x47:ana_reg7->itune_ref:trng setting,W,0x47[4:2]*/
6911 void sys_hal_set_ana_reg7_itune_ref(sys_hw_t *hw, uint32_t value)
6912 {
6913 sys_ll_set_ana_reg7_itune_ref(hw, value);
6914 }
6915
6916 /* REG_0x47:ana_reg7->itune_opa:trng setting,W,0x47[7:5]*/
6917 void sys_hal_set_ana_reg7_itune_opa(sys_hw_t *hw, uint32_t value)
6918 {
6919 sys_ll_set_ana_reg7_itune_opa(hw, value);
6920 }
6921
6922 /* REG_0x47:ana_reg7->itune_cmp:trng setting,W,0x47[10:8]*/
6923 void sys_hal_set_ana_reg7_itune_cmp(sys_hw_t *hw, uint32_t value)
6924 {
6925 sys_ll_set_ana_reg7_itune_cmp(hw, value);
6926 }
6927
6928 /* REG_0x47:ana_reg7->Rnooise_sel:trng setting,W,0x47[11]*/
6929 void sys_hal_set_ana_reg7_rnooise_sel(sys_hw_t *hw, uint32_t value)
6930 {
6931 sys_ll_set_ana_reg7_rnooise_sel(hw, value);
6932 }
6933
6934 /* REG_0x47:ana_reg7->Fslow_sel:trng setting,W,0x47[14:12]*/
6935 void sys_hal_set_ana_reg7_fslow_sel(sys_hw_t *hw, uint32_t value)
6936 {
6937 sys_ll_set_ana_reg7_fslow_sel(hw, value);
6938 }
6939
6940 /* REG_0x47:ana_reg7->Ffast_sel:trng setting,W,0x47[18:15]*/
6941 void sys_hal_set_ana_reg7_ffast_sel(sys_hw_t *hw, uint32_t value)
6942 {
6943 sys_ll_set_ana_reg7_ffast_sel(hw, value);
6944 }
6945
6946 /* REG_0x47:ana_reg7->gadc_cal_sel:gadc calibration mode selection,W,0x47[20:19]*/
6947 void sys_hal_set_ana_reg7_gadc_cal_sel(sys_hw_t *hw, uint32_t value)
6948 {
6949 sys_ll_set_ana_reg7_gadc_cal_sel(hw, value);
6950 }
6951
6952 /* REG_0x47:ana_reg7->gadc_ten:gadc test enable,W,0x47[21]*/
6953 void sys_hal_set_ana_reg7_gadc_ten(sys_hw_t *hw, uint32_t value)
6954 {
6955 sys_ll_set_ana_reg7_gadc_ten(hw, value);
6956 }
6957
6958 /* REG_0x47:ana_reg7->gadc_cmp_ictrl:gadc comparaor current select ,W,0x47[25:22]*/
6959 void sys_hal_set_ana_reg7_gadc_cmp_ictrl(sys_hw_t *hw, uint32_t value)
6960 {
6961 sys_ll_set_ana_reg7_gadc_cmp_ictrl(hw, value);
6962 }
6963
6964 /* REG_0x47:ana_reg7->gadc_buf_ictrl:gadc buffer current select ,W,0x47[29:26]*/
6965 void sys_hal_set_ana_reg7_gadc_buf_ictrl(sys_hw_t *hw, uint32_t value)
6966 {
6967 sys_ll_set_ana_reg7_gadc_buf_ictrl(hw, value);
6968 }
6969
6970 /* REG_0x47:ana_reg7->vref_sel:gadc input reference select, 0：bandgap signal 1:GPIO voltage divided,W,0x47[30]*/
6971 void sys_hal_set_ana_reg7_vref_sel(sys_hw_t *hw, uint32_t value)
6972 {
6973 sys_ll_set_ana_reg7_vref_sel(hw, value);
6974 }
6975
6976 /* REG_0x47:ana_reg7->scal_en:gadc reference scale enable, 0:normal mode,1: scale mode ,W,0x47[31]*/
6977 void sys_hal_set_ana_reg7_scal_en(sys_hw_t *hw, uint32_t value)
6978 {
6979 sys_ll_set_ana_reg7_scal_en(hw, value);
6980 }
6981
6982 /* REG_0x48 */
6983
6984 void sys_hal_set_ana_reg8_value(sys_hw_t *hw, uint32_t value)
6985 {
6986 sys_ll_set_ana_reg8_value(hw, value);
6987 }
6988
6989 /* REG_0x48:ana_reg8->cap_calspi:manul mode ,input cap calibretion value,W,0x48[8:0]*/
6990 void sys_hal_set_ana_reg8_cap_calspi(sys_hw_t *hw, uint32_t value)
6991 {
6992 sys_ll_set_ana_reg8_cap_calspi(hw, value);
6993 }
6994
6995 /* REG_0x48:ana_reg8->gain_s:Sensitivity level selection,W,0x48[10:9]*/
6996 void sys_hal_set_ana_reg8_gain_s(sys_hw_t *hw, uint32_t value)
6997 {
6998 sys_ll_set_ana_reg8_gain_s(hw, value);
6999 }
7000
7001 /* REG_0x48:ana_reg8->pwd_td:power down touch module,W,0x48[11]*/
7002 void sys_hal_set_ana_reg8_pwd_td(sys_hw_t *hw, uint32_t value)
7003 {
7004 sys_ll_set_ana_reg8_pwd_td(hw, value);
7005 }
7006
7007 /* REG_0x48:ana_reg8->en_fsr:low power mode ,enable fast response,W,0x48[12]*/
7008 void sys_hal_set_ana_reg8_en_fsr(sys_hw_t *hw, uint32_t value)
7009 {
7010 sys_ll_set_ana_reg8_en_fsr(hw, value);
7011 }
7012
7013 /* REG_0x48:ana_reg8->en_scm:scan mode enable,W,0x48[13]*/
7014 void sys_hal_set_ana_reg8_en_scm(sys_hw_t *hw, uint32_t value)
7015 {
7016 sys_ll_set_ana_reg8_en_scm(hw, value);
7017 }
7018
7019 /* REG_0x48:ana_reg8->en_adcmode:adc mode enable,W,0x48[14]*/
7020 void sys_hal_set_ana_reg8_en_adcmode(sys_hw_t *hw, uint32_t value)
7021 {
7022 sys_ll_set_ana_reg8_en_adcmode(hw, value);
7023 }
7024
7025 /* REG_0x48:ana_reg8->en_lpmode:low power mode enable,W,0x48[15]*/
7026 void sys_hal_set_ana_reg8_en_lpmode(sys_hw_t *hw, uint32_t value)
7027 {
7028 sys_ll_set_ana_reg8_en_lpmode(hw, value);
7029 }
7030
7031 /* REG_0x48:ana_reg8->chs_scan:scan mode chan selection,W,0x48[31:16]*/
7032 void sys_hal_set_ana_reg8_chs_scan(sys_hw_t *hw, uint32_t value)
7033 {
7034 sys_ll_set_ana_reg8_chs_scan(hw, value);
7035 }
7036
7037 /* REG_0x49 */
7038
7039 void sys_hal_set_ana_reg9_value(sys_hw_t *hw, uint32_t value)
7040 {
7041 sys_ll_set_ana_reg9_value(hw, value);
7042 }
7043
7044 /* REG_0x49:ana_reg9->en_otp_spi:otp ldo spi enable,W,0x49[0]*/
7045 void sys_hal_set_ana_reg9_en_otp_spi(sys_hw_t *hw, uint32_t value)
7046 {
7047 sys_ll_set_ana_reg9_en_otp_spi(hw, value);
7048 }
7049
7050 /* REG_0x49:ana_reg9->digovr_en:digldo over voltage reset enable,W,0x49[13]*/
7051 void sys_hal_set_ana_reg9_digovr_en(sys_hw_t *hw, uint32_t value)
7052 {
7053 sys_ll_set_ana_reg9_digovr_en(hw, value);
7054 }
7055
7056 /* REG_0x49:ana_reg9->usbpen:usb dp driver capability control,W,0x49[17:14]*/
7057 void sys_hal_set_ana_reg9_usbpen(sys_hw_t *hw, uint32_t value)
7058 {
7059 sys_ll_set_ana_reg9_usbpen(hw, value);
7060 }
7061
7062 /* REG_0x49:ana_reg9->usbnen:usb dn driver capability control,W,0x49[21:18]*/
7063 void sys_hal_set_ana_reg9_usbnen(sys_hw_t *hw, uint32_t value)
7064 {
7065 sys_ll_set_ana_reg9_usbnen(hw, value);
7066 }
7067
7068 /* REG_0x49:ana_reg9->usb_speed:usb speed selection,W,0x49[22]*/
7069 void sys_hal_set_ana_reg9_usb_speed(sys_hw_t *hw, uint32_t value)
7070 {
7071 sys_ll_set_ana_reg9_usb_speed(hw, value);
7072 }
7073
7074 /* REG_0x49:ana_reg9->usb_deepsleep:usb deepsleep mode enable by spi,W,0x49[23]*/
7075 void sys_hal_set_ana_reg9_usb_deepsleep(sys_hw_t *hw, uint32_t value)
7076 {
7077 sys_ll_set_ana_reg9_usb_deepsleep(hw, value);
7078 }
7079
7080 /* REG_0x49:ana_reg9->man_mode:manul mode enable,W,0x49[24]*/
7081 void sys_hal_set_ana_reg9_man_mode(sys_hw_t *hw, uint32_t value)
7082 {
7083 sys_ll_set_ana_reg9_man_mode(hw, value);
7084 }
7085
7086 /* REG_0x49:ana_reg9->crg:detect range selection :8pF/12pF/19pF/27pF,W,0x49[26:25]*/
7087 void sys_hal_set_ana_reg9_crg(sys_hw_t *hw, uint32_t value)
7088 {
7089 sys_ll_set_ana_reg9_crg(hw, value);
7090 }
7091
7092 /* REG_0x49:ana_reg9->vrefs:detect threshold selection ,W,0x49[29:27]*/
7093 void sys_hal_set_ana_reg9_vrefs(sys_hw_t *hw, uint32_t value)
7094 {
7095 sys_ll_set_ana_reg9_vrefs(hw, value);
7096 }
7097
7098 /* REG_0x49:ana_reg9->en_cal:calibretion enable,W,0x49[31]*/
7099 void sys_hal_set_ana_reg9_en_cal(sys_hw_t *hw, uint32_t value)
7100 {
7101 sys_ll_set_ana_reg9_en_cal(hw, value);
7102 }
7103
7104 /* REG_0x4a */
7105
7106 void sys_hal_set_ana_reg10_value(sys_hw_t *hw, uint32_t value)
7107 {
7108 sys_ll_set_ana_reg10_value(hw, value);
7109 }
7110
7111 /* REG_0x4a:ana_reg10->sdm_val:audio pll sdm value,W,0x4a[29:0]*/
7112 void sys_hal_set_ana_reg10_sdm_val(sys_hw_t *hw, uint32_t value)
7113 {
7114 sys_ll_set_ana_reg10_sdm_val(hw, value);
7115 }
7116
7117 /* REG_0x4a:ana_reg10->vco_hfreq_enb:audio pll vco high frequency enb,W,0x4a[30]*/
7118 void sys_hal_set_ana_reg10_vco_hfreq_enb(sys_hw_t *hw, uint32_t value)
7119 {
7120 sys_ll_set_ana_reg10_vco_hfreq_enb(hw, value);
7121 }
7122
7123 /* REG_0x4a:ana_reg10->cal_refen:cal_ref enable of audio pll,W,0x4a[31]*/
7124 void sys_hal_set_ana_reg10_cal_refen(sys_hw_t *hw, uint32_t value)
7125 {
7126 sys_ll_set_ana_reg10_cal_refen(hw, value);
7127 }
7128
7129 /* REG_0x4b */
7130
7131 void sys_hal_set_ana_reg11_value(sys_hw_t *hw, uint32_t value)
7132 {
7133 sys_ll_set_ana_reg11_value(hw, value);
7134 }
7135
7136 /* REG_0x4b:ana_reg11->int_mod:DPLL integer mode enable; 0: fractional mode; 1: integer mode,W,0x4b[0]*/
7137 void sys_hal_set_ana_reg11_int_mod(sys_hw_t *hw, uint32_t value)
7138 {
7139 sys_ll_set_ana_reg11_int_mod(hw, value);
7140 }
7141
7142 /* REG_0x4b:ana_reg11->Nsyn:DPLL Ncoutner reset ,W,0x4b[1]*/
7143 void sys_hal_set_ana_reg11_nsyn(sys_hw_t *hw, uint32_t value)
7144 {
7145 sys_ll_set_ana_reg11_nsyn(hw, value);
7146 }
7147
7148 /* REG_0x4b:ana_reg11->selpol:DPLL PFD polarity control,W,0x4b[2]*/
7149 void sys_hal_set_ana_reg11_selpol(sys_hw_t *hw, uint32_t value)
7150 {
7151 sys_ll_set_ana_reg11_selpol(hw, value);
7152 }
7153
7154 /* REG_0x4b:ana_reg11->reset:DPLL reset,W,0x4b[3]*/
7155 void sys_hal_set_ana_reg11_reset(sys_hw_t *hw, uint32_t value)
7156 {
7157 sys_ll_set_ana_reg11_reset(hw, value);
7158 }
7159
7160 /* REG_0x4b:ana_reg11->Ioffset:DPLL charge pump offset current control,W,0x4b[6:4]*/
7161 void sys_hal_set_ana_reg11_ioffset(sys_hw_t *hw, uint32_t value)
7162 {
7163 sys_ll_set_ana_reg11_ioffset(hw, value);
7164 }
7165
7166 /* REG_0x4b:ana_reg11->LPFRz:DPLL Rz control of LPF,W,0x4b[10:7]*/
7167 void sys_hal_set_ana_reg11_lpfrz(sys_hw_t *hw, uint32_t value)
7168 {
7169 sys_ll_set_ana_reg11_lpfrz(hw, value);
7170 }
7171
7172 /* REG_0x4b:ana_reg11->Rp2:DPLL Rp control of LPF,W,0x4b[13:11]*/
7173 void sys_hal_set_ana_reg11_rp2(sys_hw_t *hw, uint32_t value)
7174 {
7175 sys_ll_set_ana_reg11_rp2(hw, value);
7176 }
7177
7178 /* REG_0x4b:ana_reg11->vsel_cal:DPLL vtrl selection during VCO band calibration,W,0x4b[14]*/
7179 void sys_hal_set_ana_reg11_vsel_cal(sys_hw_t *hw, uint32_t value)
7180 {
7181 sys_ll_set_ana_reg11_vsel_cal(hw, value);
7182 }
7183
7184 /* REG_0x4b:ana_reg11->kctrl:DPLL Kvco control,W,0x4b[16:15]*/
7185 void sys_hal_set_ana_reg11_kctrl(sys_hw_t *hw, uint32_t value)
7186 {
7187 sys_ll_set_ana_reg11_kctrl(hw, value);
7188 }
7189
7190 /* REG_0x4b:ana_reg11->ckref_loop_sel:polarity selection of referenc clock to SDM,W,0x4b[17]*/
7191 void sys_hal_set_ana_reg11_ckref_loop_sel(sys_hw_t *hw, uint32_t value)
7192 {
7193 sys_ll_set_ana_reg11_ckref_loop_sel(hw, value);
7194 }
7195
7196 /* REG_0x4b:ana_reg11->spi_trigger:DPLL band calibration spi trigger,W,0x4b[18]*/
7197 void sys_hal_set_ana_reg11_spi_trigger(sys_hw_t *hw, uint32_t value)
7198 {
7199 sys_ll_set_ana_reg11_spi_trigger(hw, value);
7200 }
7201
7202 /* REG_0x4b:ana_reg11->manual:DPLL VCO band manual enable; 0: auto mode; 1: manual mode,W,0x4b[19]*/
7203 void sys_hal_set_ana_reg11_manual(sys_hw_t *hw, uint32_t value)
7204 {
7205 sys_ll_set_ana_reg11_manual(hw, value);
7206 }
7207
7208 /* REG_0x4b:ana_reg11->Icp:DPLL charge pump current control; 000: 5uA; 001: 10uA; 010: 15uA; 011: 20uA; 100: 25uA; 101: 30uA; 110: 35uA; 111: 40uA,W,0x4b[22:20]*/
7209 void sys_hal_set_ana_reg11_icp(sys_hw_t *hw, uint32_t value)
7210 {
7211 sys_ll_set_ana_reg11_icp(hw, value);
7212 }
7213
7214 /* REG_0x4b:ana_reg11->Rsel:DPLL reference clock selection; 0: 13M; 1: 6.5M,W,0x4b[23]*/
7215 void sys_hal_set_ana_reg11_rsel(sys_hw_t *hw, uint32_t value)
7216 {
7217 sys_ll_set_ana_reg11_rsel(hw, value);
7218 }
7219
7220 /* REG_0x4b:ana_reg11->ck26Men:xtal26M clock for audio enable,W,0x4b[24]*/
7221 void sys_hal_set_ana_reg11_ck26men(sys_hw_t *hw, uint32_t value)
7222 {
7223 sys_ll_set_ana_reg11_ck26men(hw, value);
7224 }
7225
7226 /* REG_0x4b:ana_reg11->ckaudio_outen:DPLL clock output to PAD enable,W,0x4b[25]*/
7227 void sys_hal_set_ana_reg11_ckaudio_outen(sys_hw_t *hw, uint32_t value)
7228 {
7229 sys_ll_set_ana_reg11_ckaudio_outen(hw, value);
7230 }
7231
7232 /* REG_0x4b:ana_reg11->divctrl:DPLL divider control; 000: div1; 001: div2; 010: div4; 011: div8; 1xx: div16,W,0x4b[28:26]*/
7233 void sys_hal_set_ana_reg11_divctrl(sys_hw_t *hw, uint32_t value)
7234 {
7235 sys_ll_set_ana_reg11_divctrl(hw, value);
7236 }
7237
7238 /* REG_0x4b:ana_reg11->cksel:DPLL divider control; 0: div3; 1: div4,W,0x4b[29]*/
7239 void sys_hal_set_ana_reg11_cksel(sys_hw_t *hw, uint32_t value)
7240 {
7241 sys_ll_set_ana_reg11_cksel(hw, value);
7242 }
7243
7244 /* REG_0x4b:ana_reg11->usben:DPLL clock for USB enable,W,0x4b[30]*/
7245 void sys_hal_set_ana_reg11_usben(sys_hw_t *hw, uint32_t value)
7246 {
7247 sys_ll_set_ana_reg11_usben(hw, value);
7248 }
7249
7250 /* REG_0x4b:ana_reg11->audioen:DPLL clock for audio enable,W,0x4b[31]*/
7251 void sys_hal_set_ana_reg11_audioen(sys_hw_t *hw, uint32_t value)
7252 {
7253 sys_ll_set_ana_reg11_audioen(hw, value);
7254 }
7255
7256 /* REG_0x4c */
7257
7258 void sys_hal_set_ana_reg12_value(sys_hw_t *hw, uint32_t value)
7259 {
7260 sys_ll_set_ana_reg12_value(hw, value);
7261 }
7262
7263 /* REG_0x4c:ana_reg12->digmic_ckinv:digmic clock inversion enable,W,0x4c[2]*/
7264 void sys_hal_set_ana_reg12_digmic_ckinv(sys_hw_t *hw, uint32_t value)
7265 {
7266 sys_ll_set_ana_reg12_digmic_ckinv(hw, value);
7267 }
7268
7269 /* REG_0x4c:ana_reg12->enmicdig:digmic enable,w,0x4c[3]*/
7270 void sys_hal_set_ana_reg12_enmicdig(sys_hw_t *hw, uint32_t value)
7271 {
7272 sys_ll_set_ana_reg12_enmicdig(hw, value);
7273 }
7274
7275 /* REG_0x4c:ana_reg12->audck_rlcen:audio clock re-latch enable,W,0x4c[4]*/
7276 void sys_hal_set_ana_reg12_audck_rlcen(sys_hw_t *hw, uint32_t value)
7277 {
7278 sys_ll_set_ana_reg12_audck_rlcen(hw, value);
7279 }
7280
7281 /* REG_0x4c:ana_reg12->lchckinven:audio clock re-latch clock inversion enable,W,0x4c[5]*/
7282 void sys_hal_set_ana_reg12_lchckinven(sys_hw_t *hw, uint32_t value)
7283 {
7284 sys_ll_set_ana_reg12_lchckinven(hw, value);
7285 }
7286
7287 /* REG_0x4c:ana_reg12->ldo1v_vsel1v:audio 1.0V LDO selection, 000=0.8, 1X1=1.0,W,0x4c[8:6]*/
7288 void sys_hal_set_ana_reg12_ldo1v_vsel1v(sys_hw_t *hw, uint32_t value)
7289 {
7290 sys_ll_set_ana_reg12_ldo1v_vsel1v(hw, value);
7291 }
7292
7293 /* REG_0x4c:ana_reg12->ldo1v_adj:audio 1.0V LDO output trimming, 00000=min, 11111=max,W,0x4c[13:9]*/
7294 void sys_hal_set_ana_reg12_ldo1v_adj(sys_hw_t *hw, uint32_t value)
7295 {
7296 sys_ll_set_ana_reg12_ldo1v_adj(hw, value);
7297 }
7298
7299 /* REG_0x4c:ana_reg12->audvdd_trm1v:audio 1.5V LDO selection, 00=min, 11=max,W,0x4c[15:14]*/
7300 void sys_hal_set_ana_reg12_audvdd_trm1v(sys_hw_t *hw, uint32_t value)
7301 {
7302 sys_ll_set_ana_reg12_audvdd_trm1v(hw, value);
7303 }
7304
7305 /* REG_0x4c:ana_reg12->audvdd_voc1v:audio 1.5V LDO output trimming, 00000=min, 11111=max,W,0x4c[20:16]*/
7306 void sys_hal_set_ana_reg12_audvdd_voc1v(sys_hw_t *hw, uint32_t value)
7307 {
7308 sys_ll_set_ana_reg12_audvdd_voc1v(hw, value);
7309 }
7310
7311 /* REG_0x4c:ana_reg12->enaudvdd1v:audio 1.0V LDO enable,W,0x4c[21]*/
7312 void sys_hal_set_ana_reg12_enaudvdd1v(sys_hw_t *hw, uint32_t value)
7313 {
7314 sys_ll_set_ana_reg12_enaudvdd1v(hw, value);
7315 }
7316
7317 /* REG_0x4c:ana_reg12->loadhp:audio 1.5V LDO, 1=good stability with small loading,W,0x4c[22]*/
7318 void sys_hal_set_ana_reg12_loadhp(sys_hw_t *hw, uint32_t value)
7319 {
7320 sys_ll_set_ana_reg12_loadhp(hw, value);
7321 }
7322
7323 /* REG_0x4c:ana_reg12->enaudvdd1v5:audio 1.5V LDO enable,W,0x4c[23]*/
7324 void sys_hal_set_ana_reg12_enaudvdd1v5(sys_hw_t *hw, uint32_t value)
7325 {
7326 sys_ll_set_ana_reg12_enaudvdd1v5(hw, value);
7327 }
7328
7329 /* REG_0x4c:ana_reg12->enmicbias1v:micbias enable,W,0x4c[24]*/
7330 void sys_hal_set_ana_reg12_enmicbias1v(sys_hw_t *hw, uint32_t value)
7331 {
7332 sys_ll_set_ana_reg12_enmicbias1v(hw, value);
7333 }
7334
7335 /* REG_0x4c:ana_reg12->micbias_trim:micbias output selection, 00=min, 11=max,W,0x4c[26:25]*/
7336 void sys_hal_set_ana_reg12_micbias_trim(sys_hw_t *hw, uint32_t value)
7337 {
7338 sys_ll_set_ana_reg12_micbias_trim(hw, value);
7339 }
7340
7341 /* REG_0x4c:ana_reg12->micbias_voc1v:micbias output trimming, 00000=min, 11111=max,W,0x4c[31:27]*/
7342 void sys_hal_set_ana_reg12_micbias_voc1v(sys_hw_t *hw, uint32_t value)
7343 {
7344 sys_ll_set_ana_reg12_micbias_voc1v(hw, value);
7345 }
7346
7347 /* REG_0x4d */
7348
7349 void sys_hal_set_ana_reg13_value(sys_hw_t *hw, uint32_t value)
7350 {
7351 sys_ll_set_ana_reg13_value(hw, value);
7352 }
7353
7354 /* REG_0x4d:ana_reg13->byp_dwaadc:adc dwa pass enable,W,0x4d[8]*/
7355 void sys_hal_set_ana_reg13_byp_dwaadc(sys_hw_t *hw, uint32_t value)
7356 {
7357 sys_ll_set_ana_reg13_byp_dwaadc(hw, value);
7358 }
7359
7360 /* REG_0x4d:ana_reg13->rst:rst,W,0x4d[9]*/
7361 void sys_hal_set_ana_reg13_rst(sys_hw_t *hw, uint32_t value)
7362 {
7363 sys_ll_set_ana_reg13_rst(hw, value);
7364 }
7365
7366 /* REG_0x4d:ana_reg13->adcdwa_mode:adc dwa model sel,W,0x4d[10]*/
7367 void sys_hal_set_ana_reg13_adcdwa_mode(sys_hw_t *hw, uint32_t value)
7368 {
7369 sys_ll_set_ana_reg13_adcdwa_mode(hw, value);
7370 }
7371
7372 /* REG_0x4d:ana_reg13->vodadjspi:adc reference manual spi control,W,0x4d[15:11]*/
7373 void sys_hal_set_ana_reg13_vodadjspi(sys_hw_t *hw, uint32_t value)
7374 {
7375 sys_ll_set_ana_reg13_vodadjspi(hw, value);
7376 }
7377
7378 /* REG_0x4d:ana_reg13->refvsel:0= high reference; 1=small reference,W,0x4d[21]*/
7379 void sys_hal_set_ana_reg13_refvsel(sys_hw_t *hw, uint32_t value)
7380 {
7381 sys_ll_set_ana_reg13_refvsel(hw, value);
7382 }
7383
7384 /* REG_0x4d:ana_reg13->capsw1v:munual value for cap trimming,W,0x4d[27:23]*/
7385 void sys_hal_set_ana_reg13_capsw1v(sys_hw_t *hw, uint32_t value)
7386 {
7387 sys_ll_set_ana_reg13_capsw1v(hw, value);
7388 }
7389
7390 /* REG_0x4d:ana_reg13->adcckinven:audio adc clock inversion enable,W,0x4d[30]*/
7391 void sys_hal_set_ana_reg13_adcckinven(sys_hw_t *hw, uint32_t value)
7392 {
7393 sys_ll_set_ana_reg13_adcckinven(hw, value);
7394 }
7395
7396 /* REG_0x4e */
7397
7398 void sys_hal_set_ana_reg14_value(sys_hw_t *hw, uint32_t value)
7399 {
7400 sys_ll_set_ana_reg14_value(hw, value);
7401 }
7402
7403 /* REG_0x4e:ana_reg14->isel:adc bias trimming,W,0x4e[1:0]*/
7404 void sys_hal_set_ana_reg14_isel(sys_hw_t *hw, uint32_t value)
7405 {
7406 sys_ll_set_ana_reg14_isel(hw, value);
7407 }
7408
7409 /* REG_0x4e:ana_reg14->micdcocdin:adc micmode dcoc din,W,0x4e[9:2]*/
7410 void sys_hal_set_ana_reg14_micdcocdin(sys_hw_t *hw, uint32_t value)
7411 {
7412 sys_ll_set_ana_reg14_micdcocdin(hw, value);
7413 }
7414
7415 /* REG_0x4e:ana_reg14->micdcocvc:adc micmode dcoc control,W,0x4e[11:10]*/
7416 void sys_hal_set_ana_reg14_micdcocvc(sys_hw_t *hw, uint32_t value)
7417 {
7418 sys_ll_set_ana_reg14_micdcocvc(hw, value);
7419 }
7420
7421 /* REG_0x4e:ana_reg14->micdcocen_n:adc micmode dcoc enable,W,0x4e[12]*/
7422 void sys_hal_set_ana_reg14_micdcocen_n(sys_hw_t *hw, uint32_t value)
7423 {
7424 sys_ll_set_ana_reg14_micdcocen_n(hw, value);
7425 }
7426
7427 /* REG_0x4e:ana_reg14->micdcocen_p:adc micmode dcoc enable,W,0x4e[13]*/
7428 void sys_hal_set_ana_reg14_micdcocen_p(sys_hw_t *hw, uint32_t value)
7429 {
7430 sys_ll_set_ana_reg14_micdcocen_p(hw, value);
7431 }
7432
7433 /* REG_0x4e:ana_reg14->micsingleEn:adc micmode, single_end enable,W,0x4e[14]*/
7434 void sys_hal_set_ana_reg14_micsingleen(sys_hw_t *hw, uint32_t value)
7435 {
7436 sys_ll_set_ana_reg14_micsingleen(hw, value);
7437 }
7438
7439 /* REG_0x4e:ana_reg14->micGain:adc micmode gain, 0=0dB(17.9K), F=24dB(267.6K), 2dB/step,W,0x4e[18:15]*/
7440 void sys_hal_set_ana_reg14_micgain(sys_hw_t *hw, uint32_t value)
7441 {
7442 sys_ll_set_ana_reg14_micgain(hw, value);
7443 }
7444
7445 /* REG_0x4e:ana_reg14->micdacen:adc micmode micdac enable,W,0x4e[19]*/
7446 void sys_hal_set_ana_reg14_micdacen(sys_hw_t *hw, uint32_t value)
7447 {
7448 sys_ll_set_ana_reg14_micdacen(hw, value);
7449 }
7450
7451 /* REG_0x4e:ana_reg14->micdaciH:adc micmode, micdac input ,W,0x4e[27:20]*/
7452 void sys_hal_set_ana_reg14_micdacih(sys_hw_t *hw, uint32_t value)
7453 {
7454 sys_ll_set_ana_reg14_micdacih(hw, value);
7455 }
7456
7457 /* REG_0x4e:ana_reg14->micdacit:adc micmode, mic_dac Iout Full-range, 00=280uA, 01=320uA, 1X=447uA,W,0x4e[29:28]*/
7458 void sys_hal_set_ana_reg14_micdacit(sys_hw_t *hw, uint32_t value)
7459 {
7460 sys_ll_set_ana_reg14_micdacit(hw, value);
7461 }
7462
7463 /* REG_0x4e:ana_reg14->hcen:adc 1stg op current trimming,W,0x4e[30]*/
7464 void sys_hal_set_ana_reg14_hcen(sys_hw_t *hw, uint32_t value)
7465 {
7466 sys_ll_set_ana_reg14_hcen(hw, value);
7467 }
7468
7469 /* REG_0x4e:ana_reg14->micEn:mic1 mode enable,W,0x4e[31]*/
7470 void sys_hal_set_ana_reg14_micen(sys_hw_t *hw, uint32_t value)
7471 {
7472 sys_ll_set_ana_reg14_micen(hw, value);
7473 }
7474
7475 /* REG_0x4f */
7476
7477 void sys_hal_set_ana_reg15_value(sys_hw_t *hw, uint32_t value)
7478 {
7479 sys_ll_set_ana_reg15_value(hw, value);
7480 }
7481
7482 /* REG_0x4f:ana_reg15->isel:adc bias trimming,W,0x4f[1:0]*/
7483 void sys_hal_set_ana_reg15_isel(sys_hw_t *hw, uint32_t value)
7484 {
7485 sys_ll_set_ana_reg15_isel(hw, value);
7486 }
7487
7488 /* REG_0x4f:ana_reg15->micdcocdin:adc micmode dcoc din,W,0x4f[9:2]*/
7489 void sys_hal_set_ana_reg15_micdcocdin(sys_hw_t *hw, uint32_t value)
7490 {
7491 sys_ll_set_ana_reg15_micdcocdin(hw, value);
7492 }
7493
7494 /* REG_0x4f:ana_reg15->micdcocvc:adc micmode dcoc control,W,0x4f[11:10]*/
7495 void sys_hal_set_ana_reg15_micdcocvc(sys_hw_t *hw, uint32_t value)
7496 {
7497 sys_ll_set_ana_reg15_micdcocvc(hw, value);
7498 }
7499
7500 /* REG_0x4f:ana_reg15->micdcocen_n:adc micmode dcoc enable,W,0x4f[12]*/
7501 void sys_hal_set_ana_reg15_micdcocen_n(sys_hw_t *hw, uint32_t value)
7502 {
7503 sys_ll_set_ana_reg15_micdcocen_n(hw, value);
7504 }
7505
7506 /* REG_0x4f:ana_reg15->micdcocen_p:adc micmode dcoc enable,W,0x4f[13]*/
7507 void sys_hal_set_ana_reg15_micdcocen_p(sys_hw_t *hw, uint32_t value)
7508 {
7509 sys_ll_set_ana_reg15_micdcocen_p(hw, value);
7510 }
7511
7512 /* REG_0x4f:ana_reg15->micsingleEn:adc micmode, single_end enable,W,0x4f[14]*/
7513 void sys_hal_set_ana_reg15_micsingleen(sys_hw_t *hw, uint32_t value)
7514 {
7515 sys_ll_set_ana_reg15_micsingleen(hw, value);
7516 }
7517
7518 /* REG_0x4f:ana_reg15->micGain:adc micmode gain, 0=0dB(17.9K), F=24dB(267.6K), 2dB/step,W,0x4f[18:15]*/
7519 void sys_hal_set_ana_reg15_micgain(sys_hw_t *hw, uint32_t value)
7520 {
7521 sys_ll_set_ana_reg15_micgain(hw, value);
7522 }
7523
7524 /* REG_0x4f:ana_reg15->micdacen:adc micmode micdac enable,W,0x4f[19]*/
7525 void sys_hal_set_ana_reg15_micdacen(sys_hw_t *hw, uint32_t value)
7526 {
7527 sys_ll_set_ana_reg15_micdacen(hw, value);
7528 }
7529
7530 /* REG_0x4f:ana_reg15->micdaciH:adc micmode, micdac input ,W,0x4f[27:20]*/
7531 void sys_hal_set_ana_reg15_micdacih(sys_hw_t *hw, uint32_t value)
7532 {
7533 sys_ll_set_ana_reg15_micdacih(hw, value);
7534 }
7535
7536 /* REG_0x4f:ana_reg15->micdacit:adc micmode, mic_dac Iout Full-range, 00=280uA, 01=320uA, 1X=447uA,W,0x4f[29:28]*/
7537 void sys_hal_set_ana_reg15_micdacit(sys_hw_t *hw, uint32_t value)
7538 {
7539 sys_ll_set_ana_reg15_micdacit(hw, value);
7540 }
7541
7542 /* REG_0x4f:ana_reg15->hcen:adc 1stg op current trimming,W,0x4f[30]*/
7543 void sys_hal_set_ana_reg15_hcen(sys_hw_t *hw, uint32_t value)
7544 {
7545 sys_ll_set_ana_reg15_hcen(hw, value);
7546 }
7547
7548 /* REG_0x4f:ana_reg15->micEn:mic2 mode enable,W,0x4f[31]*/
7549 void sys_hal_set_ana_reg15_micen(sys_hw_t *hw, uint32_t value)
7550 {
7551 sys_ll_set_ana_reg15_micen(hw, value);
7552 }
7553
7554 /* REG_0x50 */
7555
7556 void sys_hal_set_ana_reg16_value(sys_hw_t *hw, uint32_t value)
7557 {
7558 sys_ll_set_ana_reg16_value(hw, value);
7559 }
7560
7561 /* REG_0x50:ana_reg16->hpdac:class ab driver high current mode. "1" high current. ,W,0x50[0]*/
7562 void sys_hal_set_ana_reg16_hpdac(sys_hw_t *hw, uint32_t value)
7563 {
7564 sys_ll_set_ana_reg16_hpdac(hw, value);
7565 }
7566
7567 /* REG_0x50:ana_reg16->vcmsdac:1stg OP input common model voltage selection. "1" low common mode voltage,W,0x50[1]*/
7568 void sys_hal_set_ana_reg16_vcmsdac(sys_hw_t *hw, uint32_t value)
7569 {
7570 sys_ll_set_ana_reg16_vcmsdac(hw, value);
7571 }
7572
7573 /* REG_0x50:ana_reg16->oscdac:threshold current setting for over current protection . "3" maximum current. "0" minimum current,W,0x50[3:2]*/
7574 void sys_hal_set_ana_reg16_oscdac(sys_hw_t *hw, uint32_t value)
7575 {
7576 sys_ll_set_ana_reg16_oscdac(hw, value);
7577 }
7578
7579 /* REG_0x50:ana_reg16->ocendac:over current protection enable. "1" enable.,W,0x50[4]*/
7580 void sys_hal_set_ana_reg16_ocendac(sys_hw_t *hw, uint32_t value)
7581 {
7582 sys_ll_set_ana_reg16_ocendac(hw, value);
7583 }
7584
7585 /* REG_0x50:ana_reg16->isel_idac:idac current sel,W,0x50[5]*/
7586 void sys_hal_set_ana_reg16_isel_idac(sys_hw_t *hw, uint32_t value)
7587 {
7588 sys_ll_set_ana_reg16_isel_idac(hw, value);
7589 }
7590
7591 /* REG_0x50:ana_reg16->adjdacref:audio dac reference voltage adjust.,W,0x50[10:6]*/
7592 void sys_hal_set_ana_reg16_adjdacref(sys_hw_t *hw, uint32_t value)
7593 {
7594 sys_ll_set_ana_reg16_adjdacref(hw, value);
7595 }
7596
7597 /* REG_0x50:ana_reg16->dcochg:dcoc high gain selection. "1" high gain,W,0x50[12]*/
7598 void sys_hal_set_ana_reg16_dcochg(sys_hw_t *hw, uint32_t value)
7599 {
7600 sys_ll_set_ana_reg16_dcochg(hw, value);
7601 }
7602
7603 /* REG_0x50:ana_reg16->diffen:enable differential mode. "1" enable,W,0x50[13]*/
7604 void sys_hal_set_ana_reg16_diffen(sys_hw_t *hw, uint32_t value)
7605 {
7606 sys_ll_set_ana_reg16_diffen(hw, value);
7607 }
7608
7609 /* REG_0x50:ana_reg16->endaccal:enable offset calibration process. "1" enable.,W,0x50[14]*/
7610 void sys_hal_set_ana_reg16_endaccal(sys_hw_t *hw, uint32_t value)
7611 {
7612 sys_ll_set_ana_reg16_endaccal(hw, value);
7613 }
7614
7615 /* REG_0x50:ana_reg16->rendcoc:R-channel dcoc dac enablel. "1" enable,W,0x50[15]*/
7616 void sys_hal_set_ana_reg16_rendcoc(sys_hw_t *hw, uint32_t value)
7617 {
7618 sys_ll_set_ana_reg16_rendcoc(hw, value);
7619 }
7620
7621 /* REG_0x50:ana_reg16->lendcoc:L-channel Dcoc dac enable. "1" enable,W,0x50[16]*/
7622 void sys_hal_set_ana_reg16_lendcoc(sys_hw_t *hw, uint32_t value)
7623 {
7624 sys_ll_set_ana_reg16_lendcoc(hw, value);
7625 }
7626
7627 /* REG_0x50:ana_reg16->renvcmd:R-channel common mode output buffer enable."1" enable,W,0x50[17]*/
7628 void sys_hal_set_ana_reg16_renvcmd(sys_hw_t *hw, uint32_t value)
7629 {
7630 sys_ll_set_ana_reg16_renvcmd(hw, value);
7631 }
7632
7633 /* REG_0x50:ana_reg16->lenvcmd:L-channel common mode output buffer enable. "1" enable,W,0x50[18]*/
7634 void sys_hal_set_ana_reg16_lenvcmd(sys_hw_t *hw, uint32_t value)
7635 {
7636 sys_ll_set_ana_reg16_lenvcmd(hw, value);
7637 }
7638
7639 /* REG_0x50:ana_reg16->dacdrven:dac output driver enable."1" enable,W,0x50[19]*/
7640 void sys_hal_set_ana_reg16_dacdrven(sys_hw_t *hw, uint32_t value)
7641 {
7642 sys_ll_set_ana_reg16_dacdrven(hw, value);
7643 }
7644
7645 /* REG_0x50:ana_reg16->dacRen:dac R-channel enable. "1" enable,W,0x50[20]*/
7646 void sys_hal_set_ana_reg16_dacren(sys_hw_t *hw, uint32_t value)
7647 {
7648 sys_ll_set_ana_reg16_dacren(hw, value);
7649 }
7650
7651 /* REG_0x50:ana_reg16->dacLen:dac L-channel enable. "1" enable,W,0x50[21]*/
7652 void sys_hal_set_ana_reg16_daclen(sys_hw_t *hw, uint32_t value)
7653 {
7654 sys_ll_set_ana_reg16_daclen(hw, value);
7655 }
7656
7657 /* REG_0x50:ana_reg16->dacG:dac gain setting: 000=0dB, 111=8dB,W,0x50[24:22]*/
7658 void sys_hal_set_ana_reg16_dacg(sys_hw_t *hw, uint32_t value)
7659 {
7660 sys_ll_set_ana_reg16_dacg(hw, value);
7661 }
7662
7663 /* REG_0x50:ana_reg16->ck4xsel:dac clock sel ,W,0x50[25]*/
7664 void sys_hal_set_ana_reg16_ck4xsel(sys_hw_t *hw, uint32_t value)
7665 {
7666 sys_ll_set_ana_reg16_ck4xsel(hw, value);
7667 }
7668
7669 /* REG_0x50:ana_reg16->dacmute:dac mute enable. "1" mute enable,W,0x50[26]*/
7670 void sys_hal_set_ana_reg16_dacmute(sys_hw_t *hw, uint32_t value)
7671 {
7672 sys_ll_set_ana_reg16_dacmute(hw, value);
7673 }
7674
7675 /* REG_0x50:ana_reg16->dwamode:dac dwa mode sel,W,0x50[27]*/
7676 void sys_hal_set_ana_reg16_dwamode(sys_hw_t *hw, uint32_t value)
7677 {
7678 sys_ll_set_ana_reg16_dwamode(hw, value);
7679 }
7680
7681 /* REG_0x50:ana_reg16->ckposel:dac sample clock edge selection,W,0x50[28]*/
7682 void sys_hal_set_ana_reg16_ckposel(sys_hw_t *hw, uint32_t value)
7683 {
7684 sys_ll_set_ana_reg16_ckposel(hw, value);
7685 }
7686
7687 /* REG_0x50:ana_reg16->byldo:bypass 1v8 LDO,W,0x50[31]*/
7688 void sys_hal_set_ana_reg16_byldo(sys_hw_t *hw, uint32_t value)
7689 {
7690 sys_ll_set_ana_reg16_byldo(hw, value);
7691 }
7692
7693 /* REG_0x51 */
7694
7695 void sys_hal_set_ana_reg17_value(sys_hw_t *hw, uint32_t value)
7696 {
7697 sys_ll_set_ana_reg17_value(hw, value);
7698 }
7699
7700 /* REG_0x51:ana_reg17->lmdcin:l-cnannel offset cancel dac maumual input.,W,0x51[7:0]*/
7701 void sys_hal_set_ana_reg17_lmdcin(sys_hw_t *hw, uint32_t value)
7702 {
7703 sys_ll_set_ana_reg17_lmdcin(hw, value);
7704 }
7705
7706 /* REG_0x51:ana_reg17->rmdcin:r-channel offset cancel dac manmual input ,W,0x51[15:8]*/
7707 void sys_hal_set_ana_reg17_rmdcin(sys_hw_t *hw, uint32_t value)
7708 {
7709 sys_ll_set_ana_reg17_rmdcin(hw, value);
7710 }
7711
7712 /* REG_0x51:ana_reg17->spirst_ovc:ovc rst,W,0x51[16]*/
7713 void sys_hal_set_ana_reg17_spirst_ovc(sys_hw_t *hw, uint32_t value)
7714 {
7715 sys_ll_set_ana_reg17_spirst_ovc(hw, value);
7716 }
7717
7718 /* REG_0x51:ana_reg17->hc2s0v9:0=current is half,W,0x51[20]*/
7719 void sys_hal_set_ana_reg17_hc2s0v9(sys_hw_t *hw, uint32_t value)
7720 {
7721 sys_ll_set_ana_reg17_hc2s0v9(hw, value);
7722 }
7723
7724 /* REG_0x51:ana_reg17->lvcmsel:low vcm sel,W,0x51[21]*/
7725 void sys_hal_set_ana_reg17_lvcmsel(sys_hw_t *hw, uint32_t value)
7726 {
7727 sys_ll_set_ana_reg17_lvcmsel(hw, value);
7728 }
7729
7730 /* REG_0x51:ana_reg17->loop2sel:2rd loop sel,W,0x51[22]*/
7731 void sys_hal_set_ana_reg17_loop2sel(sys_hw_t *hw, uint32_t value)
7732 {
7733 sys_ll_set_ana_reg17_loop2sel(hw, value);
7734 }
7735
7736 /* REG_0x51:ana_reg17->enbias:dac bias enable,W,0x51[23]*/
7737 void sys_hal_set_ana_reg17_enbias(sys_hw_t *hw, uint32_t value)
7738 {
7739 sys_ll_set_ana_reg17_enbias(hw, value);
7740 }
7741
7742 /* REG_0x51:ana_reg17->calck_sel0v9:offset calibration clock selection. "1" high clock.,W,0x51[24]*/
7743 void sys_hal_set_ana_reg17_calck_sel0v9(sys_hw_t *hw, uint32_t value)
7744 {
7745 sys_ll_set_ana_reg17_calck_sel0v9(hw, value);
7746 }
7747
7748 /* REG_0x51:ana_reg17->bpdwa0v9:bypss audio dac dwa. "1" bypass.,W,0x51[25]*/
7749 void sys_hal_set_ana_reg17_bpdwa0v9(sys_hw_t *hw, uint32_t value)
7750 {
7751 sys_ll_set_ana_reg17_bpdwa0v9(hw, value);
7752 }
7753
7754 /* REG_0x51:ana_reg17->looprst0v9:audio dac integrator capacitor reset. "1" reset.,W,0x51[26]*/
7755 void sys_hal_set_ana_reg17_looprst0v9(sys_hw_t *hw, uint32_t value)
7756 {
7757 sys_ll_set_ana_reg17_looprst0v9(hw, value);
7758 }
7759
7760 /* REG_0x51:ana_reg17->oct0v9:over current delay time setting."11" maximum time. "00" minimum current.,W,0x51[28:27]*/
7761 void sys_hal_set_ana_reg17_oct0v9(sys_hw_t *hw, uint32_t value)
7762 {
7763 sys_ll_set_ana_reg17_oct0v9(hw, value);
7764 }
7765
7766 /* REG_0x51:ana_reg17->sout0v9:short output with 600ohm resistor. "1" short output.,W,0x51[29]*/
7767 void sys_hal_set_ana_reg17_sout0v9(sys_hw_t *hw, uint32_t value)
7768 {
7769 sys_ll_set_ana_reg17_sout0v9(hw, value);
7770 }
7771
7772 /* REG_0x51:ana_reg17->hc0v9:dac current trimming, 00=minimum current, 11=maximum current,W,0x51[31:30]*/
7773 void sys_hal_set_ana_reg17_hc0v9(sys_hw_t *hw, uint32_t value)
7774 {
7775 sys_ll_set_ana_reg17_hc0v9(hw, value);
7776 }
7777
7778 /* REG_0x52 */
7779
7780 void sys_hal_set_ana_reg18_value(sys_hw_t *hw, uint32_t value)
7781 {
7782 sys_ll_set_ana_reg18_value(hw, value);
7783 }
7784
7785 /* REG_0x52:ana_reg18->ictrl_dsppll:26M PLL setting,W,0x52[3:0]*/
7786 void sys_hal_set_ana_reg18_ictrl_dsppll(sys_hw_t *hw, uint32_t value)
7787 {
7788 sys_ll_set_ana_reg18_ictrl_dsppll(hw, value);
7789 }
7790
7791 /* REG_0x52:ana_reg18->FBdivN:26M PLL setting,W,0x52[13:4]*/
7792 void sys_hal_set_ana_reg18_fbdivn(sys_hw_t *hw, uint32_t value)
7793 {
7794 sys_ll_set_ana_reg18_fbdivn(hw, value);
7795 }
7796
7797 /* REG_0x52:ana_reg18->N_mcudsp:26M PLL setting,W,0x52[18:14]*/
7798 void sys_hal_set_ana_reg18_n_mcudsp(sys_hw_t *hw, uint32_t value)
7799 {
7800 sys_ll_set_ana_reg18_n_mcudsp(hw, value);
7801 }
7802
7803 /* REG_0x52:ana_reg18->mode:26M PLL setting,W,0x52[19]*/
7804 void sys_hal_set_ana_reg18_mode(sys_hw_t *hw, uint32_t value)
7805 {
7806 sys_ll_set_ana_reg18_mode(hw, value);
7807 }
7808
7809 /* REG_0x52:ana_reg18->iamsel:26M PLL setting,W,0x52[20]*/
7810 void sys_hal_set_ana_reg18_iamsel(sys_hw_t *hw, uint32_t value)
7811 {
7812 sys_ll_set_ana_reg18_iamsel(hw, value);
7813 }
7814
7815 /* REG_0x52:ana_reg18->hvref:26M PLL setting,W,0x52[22:21]*/
7816 void sys_hal_set_ana_reg18_hvref(sys_hw_t *hw, uint32_t value)
7817 {
7818 sys_ll_set_ana_reg18_hvref(hw, value);
7819 }
7820
7821 /* REG_0x52:ana_reg18->lvref:26M PLL setting,W,0x52[24:23]*/
7822 void sys_hal_set_ana_reg18_lvref(sys_hw_t *hw, uint32_t value)
7823 {
7824 sys_ll_set_ana_reg18_lvref(hw, value);
7825 }
7826
7827 /* REG_0x53 */
7828
7829 void sys_hal_set_ana_reg19_value(sys_hw_t *hw, uint32_t value)
7830 {
7831 sys_ll_set_ana_reg19_value(hw, value);
7832 }
7833
7834 /* REG_0x53:ana_reg19->amsel:26M PLL setting,W,0x53[0]*/
7835 void sys_hal_set_ana_reg19_amsel(sys_hw_t *hw, uint32_t value)
7836 {
7837 sys_ll_set_ana_reg19_amsel(hw, value);
7838 }
7839
7840 /* REG_0x53:ana_reg19->msw:26M PLL setting,W,0x53[9:1]*/
7841 void sys_hal_set_ana_reg19_msw(sys_hw_t *hw, uint32_t value)
7842 {
7843 sys_ll_set_ana_reg19_msw(hw, value);
7844 }
7845
7846 /* REG_0x53:ana_reg19->tstcken_dpll:26M PLL setting,W,0x53[10]*/
7847 void sys_hal_set_ana_reg19_tstcken_dpll(sys_hw_t *hw, uint32_t value)
7848 {
7849 sys_ll_set_ana_reg19_tstcken_dpll(hw, value);
7850 }
7851
7852 /* REG_0x53:ana_reg19->osccal_trig:26M PLL setting,W,0x53[11]*/
7853 void sys_hal_set_ana_reg19_osccal_trig(sys_hw_t *hw, uint32_t value)
7854 {
7855 sys_ll_set_ana_reg19_osccal_trig(hw, value);
7856 }
7857
7858 /* REG_0x53:ana_reg19->cnti:26M PLL setting,W,0x53[20:12]*/
7859 void sys_hal_set_ana_reg19_cnti(sys_hw_t *hw, uint32_t value)
7860 {
7861 sys_ll_set_ana_reg19_cnti(hw, value);
7862 }
7863
7864 /* REG_0x53:ana_reg19->spi_rst:26M PLL setting,W,0x53[22]*/
7865 void sys_hal_set_ana_reg19_spi_rst(sys_hw_t *hw, uint32_t value)
7866 {
7867 sys_ll_set_ana_reg19_spi_rst(hw, value);
7868 }
7869
7870 /* REG_0x53:ana_reg19->closeloop_en:26M PLL setting,W,0x53[23]*/
7871 void sys_hal_set_ana_reg19_closeloop_en(sys_hw_t *hw, uint32_t value)
7872 {
7873 sys_ll_set_ana_reg19_closeloop_en(hw, value);
7874 }
7875
7876 /* REG_0x53:ana_reg19->caltime:26M PLL setting,W,0x53[24]*/
7877 void sys_hal_set_ana_reg19_caltime(sys_hw_t *hw, uint32_t value)
7878 {
7879 sys_ll_set_ana_reg19_caltime(hw, value);
7880 }
7881
7882 /* REG_0x53:ana_reg19->LPFRz:26M PLL setting,W,0x53[26:25]*/
7883 void sys_hal_set_ana_reg19_lpfrz(sys_hw_t *hw, uint32_t value)
7884 {
7885 sys_ll_set_ana_reg19_lpfrz(hw, value);
7886 }
7887
7888 /* REG_0x53:ana_reg19->ICP:26M PLL setting,W,0x53[30:27]*/
7889 void sys_hal_set_ana_reg19_icp(sys_hw_t *hw, uint32_t value)
7890 {
7891 sys_ll_set_ana_reg19_icp(hw, value);
7892 }
7893
7894 /* REG_0x53:ana_reg19->CP2ctrl:26M PLL setting,W,0x53[31]*/
7895 void sys_hal_set_ana_reg19_cp2ctrl(sys_hw_t *hw, uint32_t value)
7896 {
7897 sys_ll_set_ana_reg19_cp2ctrl(hw, value);
7898 }
7899
7900
7901 #endif
7902
sys_hal_set_ana_trxt_tst_enable(uint32_t value)7903 void sys_hal_set_ana_trxt_tst_enable(uint32_t value)
7904
7905 {
7906 sys_ll_set_ana_reg5_trxt_tst_enable(value);
7907 }
7908
7909
sys_hal_set_ana_scal_en(uint32_t value)7910 void sys_hal_set_ana_scal_en(uint32_t value)
7911 {
7912 sys_ll_set_ana_reg7_scal_en(value);
7913 }
7914
7915
sys_hal_set_ana_gadc_buf_ictrl(uint32_t value)7916 void sys_hal_set_ana_gadc_buf_ictrl(uint32_t value)
7917 {
7918 sys_ll_set_ana_reg7_gadc_buf_ictrl(value);
7919 }
7920
sys_hal_set_ana_gadc_cmp_ictrl(uint32_t value)7921 void sys_hal_set_ana_gadc_cmp_ictrl(uint32_t value)
7922 {
7923 sys_ll_set_ana_reg7_gadc_cmp_ictrl(value);
7924 }
7925
sys_hal_set_ana_pwd_gadc_buf(uint32_t value)7926 void sys_hal_set_ana_pwd_gadc_buf(uint32_t value)
7927 {
7928 sys_ll_set_ana_reg6_pwd_gadc_buf(value);
7929 }
7930
sys_hal_set_ana_vref_sel(uint32_t value)7931 void sys_hal_set_ana_vref_sel(uint32_t value)
7932 {
7933 sys_ll_set_ana_reg7_vref_sel(value);
7934 }
sys_hal_set_ana_cb_cal_manu(uint32_t value)7935 void sys_hal_set_ana_cb_cal_manu(uint32_t value)
7936 {
7937 sys_ll_set_ana_reg4_cb_cal_manu(value);
7938 }
7939
sys_hal_set_ana_cb_cal_trig(uint32_t value)7940 void sys_hal_set_ana_cb_cal_trig(uint32_t value)
7941 {
7942 sys_ll_set_ana_reg4_cb_cal_trig(value);
7943 }
7944
sys_hal_set_ana_cb_cal_manu_val(uint32_t value)7945 void sys_hal_set_ana_cb_cal_manu_val(uint32_t value)
7946 {
7947 sys_ll_set_ana_reg4_cb_manu_val(value);
7948 }
7949
sys_hal_set_ana_vlsel_ldodig(uint32_t value)7950 void sys_hal_set_ana_vlsel_ldodig(uint32_t value)
7951 {
7952 sys_ll_set_ana_reg3_vlsel_ldodig(value);
7953 }
sys_hal_set_ana_vhsel_ldodig(uint32_t value)7954 void sys_hal_set_ana_vhsel_ldodig(uint32_t value)
7955 {
7956 sys_ll_set_ana_reg3_vhsel_ldodig(value);
7957 }
sys_hal_set_ana_vctrl_sysldo(uint32_t value)7958 void sys_hal_set_ana_vctrl_sysldo(uint32_t value)
7959 {
7960 sys_ll_set_ana_reg5_vctrl_sysldo(value);
7961 }
7962
7963
sys_hal_set_ana_vtempsel(uint32_t value)7964 void sys_hal_set_ana_vtempsel(uint32_t value)
7965 {
7966 sys_ll_set_ana_reg9_vtempsel(value);
7967 }
7968
7969