1 /* 2 // Copyright (C) 2022 Beken Corporation 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 17 #pragma once 18 19 #include "sys_types.h" 20 #include <driver/hal/hal_uart_types.h> 21 #include <driver/hal/hal_pwm_types.h> 22 #include <driver/hal/hal_timer_types.h> 23 #include <driver/hal/hal_spi_types.h> 24 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 typedef struct { 31 sys_hw_t *hw; 32 } sys_hal_t; 33 34 35 /** Platform Start **/ 36 37 //Platform 38 39 /** Platform Misc Start **/ 40 bk_err_t sys_hal_init(void); 41 /** Platform Misc End **/ 42 43 /** Platform USB Start **/ 44 void sys_hal_usb_enable_clk(bool en); 45 void sys_hal_usb_analog_phy_en(bool en); 46 void sys_hal_usb_analog_speed_en(bool en); 47 void sys_hal_usb_analog_ckmcu_en(bool en); 48 void sys_hal_usb_enable_charge(bool en); 49 void sys_hal_usb_charge_vlcf_cal(); 50 void sys_hal_usb_charge_icp_cal(); 51 void sys_hal_usb_charge_vcv_cal(); 52 void sys_hal_usb_charge_get_cal(); 53 54 /** Platform USB End **/ 55 56 /** Platform PWM Start **/ 57 void sys_hal_pwm_set_clock(uint32_t mode, uint32_t param); 58 /** Platform PWM End **/ 59 60 /** Platform flash Start **/ 61 void sys_hal_flash_set_dco(void); 62 63 void sys_hal_flash_set_dpll(void); 64 65 void sys_hal_flash_set_clk(uint32_t value); 66 67 void sys_hal_flash_set_clk_div(uint32_t value); 68 69 uint32_t sys_hal_flash_get_clk_sel(void); 70 71 uint32_t sys_hal_flash_get_clk_div(void); 72 73 /** Platform flash End **/ 74 75 /** Platform qspi Start **/ 76 void sys_hal_set_qspi_vddram_voltage(uint32_t param); 77 78 void sys_hal_set_qspi_io_voltage(uint32_t param); 79 80 void sys_hal_qspi_clk_sel(uint32_t param); 81 82 void sys_hal_qspi_set_src_clk_div(uint32_t value); 83 84 /** Platform qspi End **/ 85 86 /** Platform SDIO Start **/ 87 void sys_hal_set_sdio_clk_en(uint32_t value); 88 void sys_hal_set_cpu0_sdio_int_en(uint32_t value); 89 void sys_hal_set_cpu1_sdio_int_en(uint32_t value); 90 void sys_hal_set_sdio_clk_div(uint32_t value); 91 uint32_t sys_hal_get_sdio_clk_div(); 92 void sys_hal_set_sdio_clk_sel(uint32_t value); 93 uint32_t sys_hal_get_sdio_clk_sel(); 94 /** Platform SDIO End **/ 95 96 /*low power feature start*/ 97 void sys_hal_enter_deep_sleep(void *param); 98 void sys_hal_enter_normal_sleep(); 99 void sys_hal_enter_normal_wakeup(); 100 #if CONFIG_SOC_BK7256XX 101 __attribute__((section(".itcm_sec_code"))) void sys_hal_enter_low_voltage(void); 102 #else 103 void sys_hal_enter_low_voltage(void); 104 #endif 105 void sys_hal_module_power_ctrl(power_module_name_t module,power_module_state_t power_state); 106 void sys_hal_wakeup_interrupt_clear(wakeup_source_t interrupt_source); 107 void sys_hal_module_power_ctrl(power_module_name_t module,power_module_state_t power_state); 108 void sys_hal_module_RF_power_ctrl (module_name_t module,power_module_state_t power_state); 109 void sys_hal_core_bus_clock_ctrl(high_clock_module_name_t core, uint32_t clksel,uint32_t clkdiv, high_clock_module_name_t bus,uint32_t bus_clksel,uint32_t bus_clkdiv); 110 void sys_hal_cpu0_main_int_ctrl(dev_clk_pwr_ctrl_t clock_state); 111 void sys_hal_cpu1_main_int_ctrl(dev_clk_pwr_ctrl_t clock_state); 112 void sys_hal_set_cpu1_boot_address_offset(uint32_t address_offset); 113 void sys_hal_set_cpu1_reset(uint32_t reset_value); 114 void sys_hal_enable_mac_wakeup_source(); 115 void sys_hal_enable_bt_wakeup_source(); 116 uint32_t sys_hal_all_modules_clk_div_get(clk_div_reg_e reg); 117 void sys_hal_all_modules_clk_div_set(clk_div_reg_e reg, uint32_t value); 118 void sys_hal_usb_wakeup_enable(uint8_t index); 119 void sys_hal_touch_wakeup_enable(uint8_t index); 120 void sys_hal_rtc_wakeup_enable(uint32_t value); 121 void sys_hal_cpu_clk_div_set(uint32_t core_index, uint32_t value); 122 uint32_t sys_hal_cpu_clk_div_get(uint32_t core_index); 123 void sys_hal_low_power_hardware_init(); 124 int32 sys_hal_lp_vol_set(uint32_t value); 125 uint32_t sys_hal_lp_vol_get(); 126 int32 sys_hal_module_power_state_get(power_module_name_t module); 127 128 /*low power feature end*/ 129 uint32 sys_hal_get_chip_id(void); 130 uint32 sys_hal_get_device_id(void); 131 int32 sys_hal_usb_power_down(void); 132 int32 sys_hal_usb_power_up(void); 133 int32 sys_hal_int_disable(uint32 param); 134 int32 sys_hal_int_enable(uint32 param); 135 int32 sys_hal_int_group2_disable(uint32 param); 136 int32 sys_hal_int_group2_enable(uint32 param); 137 int32 sys_hal_fiq_disable(uint32 param); 138 int32 sys_hal_fiq_enable(uint32 param); 139 int32 sys_hal_global_int_disable(uint32 param); 140 int32 sys_hal_global_int_enable(uint32 param); 141 uint32 sys_hal_get_int_status(void); 142 uint32 sys_hal_get_int_group2_status(void); 143 int32 sys_hal_set_int_status(uint32 param); 144 /* REG_0x29:cpu0_int_32_63_status->cpu0_gpio_int_st: ,R,0x29[22]*/ 145 uint32_t sys_hal_get_cpu0_gpio_int_st(void); 146 uint32 sys_hal_get_fiq_reg_status(void); 147 uint32 sys_hal_set_fiq_reg_status(uint32 param); 148 uint32 sys_hal_get_intr_raw_status(void); 149 uint32 sys_hal_set_intr_raw_status(uint32 param); 150 int32 sys_hal_set_jtag_mode(uint32 param); 151 uint32 sys_hal_get_jtag_mode(void); 152 153 /*clock power control start*/ 154 void sys_hal_clk_pwr_ctrl(dev_clk_pwr_id_t dev, dev_clk_pwr_ctrl_t power_up); 155 void sys_hal_set_clk_select(dev_clk_select_id_t dev, dev_clk_select_t clk_sel); 156 dev_clk_select_t sys_hal_get_clk_select(dev_clk_select_id_t dev); 157 //DCO divider is valid for all of the peri-devices. 158 void sys_hal_set_dco_div(dev_clk_dco_div_t div); 159 //DCO divider is valid for all of the peri-devices. 160 dev_clk_dco_div_t sys_hal_get_dco_div(void); 161 /*clock power control end*/ 162 163 /* UART select clock DIRTY **/ 164 void sys_hal_uart_select_clock(uart_id_t id, uart_src_clk_t mode); 165 /* UART select clock DIRTY **/ 166 167 void sys_hal_arm_wakeup_enable(uint32_t param); 168 void sys_hal_arm_wakeup_disable(uint32_t param); 169 uint32_t sys_hal_get_arm_wakeup(void); 170 171 void aon_pmu_hal_set_wakeup_source_reg(uint32_t param); 172 uint32_t aon_pmu_hal_get_wakeup_source_reg(void); 173 174 void sys_hal_set_cksel_sadc(uint32_t value); 175 void sys_hal_set_cksel_pwm(uint32_t value); 176 uint32_t sys_hal_uart_select_clock_get(uart_id_t id); 177 void sys_hal_sadc_int_enable(void); 178 void sys_hal_sadc_int_disable(void); 179 void sys_hal_sadc_pwr_up(void); 180 void sys_hal_sadc_pwr_down(void); 181 void sys_hal_set_clksel_spi(uint32_t value); 182 void sys_hal_timer_select_clock(sys_sel_timer_t num, timer_src_clk_t mode); 183 uint32_t sys_hal_timer_select_clock_get(sys_sel_timer_t id); 184 void sys_hal_spi_select_clock(spi_id_t num, spi_src_clk_t mode); 185 /* PWM select clock DIRTY **/ 186 void sys_hal_pwm_select_clock(sys_sel_pwm_t num, pwm_src_clk_t mode); 187 /* PWM select clock DIRTY **/ 188 189 void sys_hal_en_tempdet(uint32_t value); 190 191 uint32_t sys_hal_nmi_wdt_get_clk_div(void); 192 void sys_hal_nmi_wdt_set_clk_div(uint32_t value); 193 void sys_hal_trng_disckg_set(uint32_t value); 194 /** Platform End **/ 195 196 197 198 199 /** BT Start **/ 200 //BT 201 uint32_t sys_hal_mclk_mux_get(void); 202 uint32_t sys_hal_mclk_div_get(void); 203 void sys_hal_mclk_select(uint32_t value); 204 void sys_hal_mclk_div_set(uint32_t value); 205 206 void sys_hal_bt_power_ctrl(bool power_up); 207 208 void sys_hal_bt_clock_ctrl(bool en); 209 void sys_hal_xvr_clock_ctrl(bool en); 210 211 uint32_t sys_hal_interrupt_status_get(void); 212 void sys_hal_interrupt_status_set(uint32_t value); 213 214 void sys_hal_btdm_interrupt_ctrl(bool en); 215 void sys_hal_ble_interrupt_ctrl(bool en); 216 void sys_hal_bt_interrupt_ctrl(bool en); 217 218 void sys_hal_bt_rf_ctrl(bool en); 219 uint32_t sys_hal_bt_rf_status_get(void); 220 void sys_hal_bt_sleep_exit_ctrl(bool en); 221 222 /** BT End **/ 223 224 225 226 227 /** Audio Start **/ 228 //Audio 229 /** Audio End **/ 230 231 232 233 234 /** Video Start **/ 235 void sys_hal_lcd_disp_clk_en(uint8_t clk_src_sel, uint8_t clk_div_l, uint8_t clk_div_h, uint8_t int_en,uint8_t clk_always_on); 236 void sys_hal_lcd_disp_close(void); 237 void sys_hal_dma2d_clk_en(uint8_t clk_always_on, uint8_t sys_int_en); 238 void sys_hal_jpeg_dec_ctrl(bool clk_always_on, bool int_en); 239 240 /** Video End **/ 241 242 243 244 245 /** WIFI Start **/ 246 //WIFI 247 void sys_hal_cali_dpll_spi_trig_disable(void); 248 void sys_hal_cali_dpll_spi_trig_enable(void); 249 void sys_hal_cali_dpll_spi_detect_disable(void); 250 void sys_hal_cali_dpll_spi_detect_enable(void); 251 uint32_t sys_hal_bias_reg_clean(uint32_t param); 252 uint32_t sys_hal_bias_reg_set(uint32_t param); 253 uint32_t sys_hal_bias_reg_read(void); 254 uint32_t sys_hal_bias_reg_write(uint32_t param); 255 uint32_t sys_hal_analog_reg1_get(void); 256 uint32_t sys_hal_analog_reg2_get(void); 257 uint32_t sys_hal_analog_reg4_get(void); 258 uint32_t sys_hal_analog_reg6_get(void); 259 uint32_t sys_hal_analog_reg7_get(void); 260 uint32_t sys_hal_analog_reg2_set(uint32_t param); 261 uint32_t sys_hal_analog_reg4_set(uint32_t param); 262 void sys_hal_set_xtalh_ctune(uint32_t value); 263 void sys_hal_set_ana_reg1_value(uint32_t value); 264 void sys_hal_set_ana_reg2_value(uint32_t value); 265 void sys_hal_set_ana_reg3_value(uint32_t value); 266 void sys_hal_set_ana_reg4_value(uint32_t value); 267 void sys_hal_set_ana_reg12_value(uint32_t value); 268 void sys_hal_set_ana_reg13_value(uint32_t value); 269 void sys_hal_set_ana_reg14_value(uint32_t value); 270 void sys_hal_set_ana_reg15_value(uint32_t value); 271 void sys_hal_set_ana_reg16_value(uint32_t value); 272 void sys_hal_set_ana_reg17_value(uint32_t value); 273 void sys_hal_analog_reg4_bits_or(uint32_t value); 274 void sys_hal_set_ana_reg6_value(uint32_t value); 275 void sys_hal_set_ana_reg7_value(uint32_t value); 276 uint32_t sys_hal_get_xtalh_ctune(void); 277 uint32_t sys_hal_get_bgcalm(void); 278 void sys_hal_set_bgcalm(uint32_t value); 279 void sys_hal_set_audioen(uint32_t value); 280 void sys_hal_set_dpll_div_cksel(uint32_t value); 281 void sys_hal_set_dpll_reset(uint32_t value); 282 void sys_hal_set_gadc_ten(uint32_t value); 283 void sys_hal_analog_set(analog_reg_t reg, uint32_t value); 284 uint32_t sys_hal_analog_get(analog_reg_t reg); 285 //Yantao Add Start 286 void sys_hal_modem_core_reset(void); 287 void sys_hal_mpif_invert(void); 288 void sys_hal_modem_subsys_reset(void); 289 void sys_hal_mac_subsys_reset(void); 290 void sys_hal_usb_subsys_reset(void); 291 void sys_hal_dsp_subsys_reset(void); 292 void sys_hal_mac_power_ctrl(bool power_up); 293 void sys_hal_modem_power_ctrl(bool power_up); 294 void sys_hal_pta_ctrl(bool pta_en); 295 void sys_hal_modem_bus_clk_ctrl(bool clk_en); 296 void sys_hal_modem_clk_ctrl(bool clk_en); 297 void sys_hal_mac_bus_clk_ctrl(bool clk_en); 298 void sys_hal_mac_clk_ctrl(bool clk_en); 299 void sys_hal_set_vdd_value(uint32_t param); 300 uint32_t sys_hal_get_vdd_value(void); 301 void sys_hal_block_en_mux_set(uint32_t param); 302 void sys_hal_enable_mac_gen_int(void); 303 void sys_hal_enable_mac_prot_int(void); 304 void sys_hal_enable_mac_tx_trigger_int(void); 305 void sys_hal_enable_mac_rx_trigger_int(void); 306 void sys_hal_enable_mac_txrx_misc_int(void); 307 void sys_hal_enable_mac_txrx_timer_int(void); 308 void sys_hal_enable_modem_int(void); 309 void sys_hal_enable_modem_rc_int(void); 310 //Yantao Add End 311 312 void sys_hal_set_ana_vtempsel(uint32_t value); 313 /** WIFI End **/ 314 315 /** Audio Start **/ 316 317 void sys_hal_aud_select_clock(uint32_t value); 318 void sys_hal_aud_clock_en(uint32_t value); 319 void sys_hal_aud_vdd1v_en(uint32_t value); 320 void sys_hal_aud_vdd1v5_en(uint32_t value); 321 void sys_hal_aud_mic1_en(uint32_t value); 322 void sys_hal_aud_mic2_en(uint32_t value); 323 void sys_hal_aud_audpll_en(uint32_t value); 324 void sys_hal_aud_aud_en(uint32_t value); 325 void sys_hal_aud_dacdrv_en(uint32_t value); 326 void sys_hal_aud_bias_en(uint32_t value); 327 void sys_hal_aud_dacr_en(uint32_t value); 328 void sys_hal_aud_dacl_en(uint32_t value); 329 void sys_hal_aud_diffen_en(uint32_t value); 330 void sys_hal_aud_rvcmd_en(uint32_t value); 331 void sys_hal_aud_lvcmd_en(uint32_t value); 332 void sys_hal_aud_micbias1v_en(uint32_t value); 333 void sys_hal_aud_micbias_trim_set(uint32_t value); 334 void sys_hal_aud_mic_rst_set(uint32_t value); 335 void sys_hal_aud_mic1_gain_set(uint32_t value); 336 void sys_hal_aud_mic2_gain_set(uint32_t value); 337 void sys_hal_aud_int_en(uint32_t value); 338 void sys_hal_sbc_int_en(uint32_t value); 339 void sys_hal_aud_power_en(uint32_t value); 340 341 342 /** Audio End **/ 343 344 /** FFT Start **/ 345 346 void sys_hal_fft_disckg_set(uint32_t value); 347 void sys_hal_cpu_fft_int_en(uint32_t value); 348 349 /** FFT End **/ 350 351 /** I2S Start **/ 352 void sys_hal_i2s_select_clock(uint32_t value); 353 void sys_hal_i2s_clock_en(uint32_t value); 354 355 void sys_hal_i2s_disckg_set(uint32_t value); 356 void sys_hal_i2s_int_en(uint32_t value); 357 void sys_hal_apll_en(uint32_t value); 358 void sys_hal_cb_manu_val_set(uint32_t value); 359 void sys_hal_ana_reg11_vsel_set(uint32_t value); 360 void sys_hal_ana_reg10_sdm_val_set(uint32_t value); 361 void sys_hal_ana_reg11_spi_trigger_set(uint32_t value); 362 /** I2S End **/ 363 364 365 /** Touch Start **/ 366 void sys_hal_touch_power_down(uint32_t value); 367 void sys_hal_touch_sensitivity_level_set(uint32_t value); 368 void sys_hal_touch_scan_mode_enable(uint32_t value); 369 void sys_hal_touch_detect_threshold_set(uint32_t value); 370 void sys_hal_touch_detect_range_set(uint32_t value); 371 void sys_hal_touch_calib_enable(uint32_t value); 372 void sys_hal_touch_manul_mode_calib_value_set(uint32_t value); 373 void sys_hal_touch_manul_mode_enable(uint32_t value); 374 void sys_hal_touch_scan_mode_chann_set(uint32_t value); 375 void sys_hal_touch_int_enable(uint32_t value); 376 377 /** Touch End **/ 378 379 380 /** jpeg start **/ 381 void sys_hal_mclk_mux_set(uint32_t value); 382 void sys_hal_set_jpeg_clk_sel(uint32_t value); 383 void sys_hal_set_clk_div_mode1_clkdiv_jpeg(uint32_t value); 384 void sys_hal_set_jpeg_disckg(uint32_t value); 385 void sys_hal_set_cpu_clk_div_mode1_clkdiv_bus(uint32_t value); 386 void sys_hal_video_power_en(uint32_t value); 387 void sys_hal_set_auxs_clk_sel(uint32_t value); 388 void sys_hal_set_auxs_clk_div(uint32_t value); 389 390 /** jpeg end **/ 391 392 /** psram Start **/ 393 void sys_hal_psram_volstage_sel(uint32_t enable); 394 void sys_hal_psram_xtall_osc_enable(uint32_t enable); 395 void sys_hal_psram_doc_enable(uint32_t enable); 396 void sys_hal_psram_dpll_enable(uint32_t enable); 397 void sys_hal_psram_ldo_enable(uint32_t enable); 398 void sys_hal_psram_clk_sel(uint32_t value); 399 void sys_hal_psram_set_clkdiv(uint32_t value); 400 void sys_hal_psram_power_enable(void); 401 void sys_hal_psram_psldo_vsel(uint32_t value); 402 void sys_hal_psram_psldo_vset(uint32_t output_voltage, bool is_add_200mv); 403 404 /** psram End **/ 405 406 uint32_t sys_hal_get_cpu_storage_connect_op_select_flash_sel(void); 407 void sys_hal_set_cpu_storage_connect_op_select_flash_sel(uint32_t value); 408 409 /** Misc Start **/ 410 //Misc 411 /** Misc End **/ 412 413 414 415 /** Temp reserve heare */ 416 417 #if 1 418 void sys_hal_set_btdm_clk_en(bool value); 419 uint32 sys_hal_get_btdm_clk_en(); 420 void sys_hal_set_xvr_clk_en(bool value); 421 uint32 sys_hal_get_xvr_clk_en(); 422 #endif 423 424 425 #if 1 426 void sys_hal_set_power_on_btsp(bool value); 427 uint32 sys_hal_get_power_on_btsp(); 428 #endif 429 430 431 #if 1 432 void sys_hal_set_bts_wakeup_platform_en(bool value); 433 uint32 sys_hal_get_bts_wakeup_platform_en(); 434 void sys_hal_set_bts_sleep_exit_req(bool value); 435 uint32 sys_hal_get_bts_sleep_exit_req(); 436 #endif 437 438 /* generated codes by python tool with address mapping */ 439 #if 0 //just for reference 440 441 /* REG_0x00 */ 442 443 uint32_t sys_hal_get_device_id_value(sys_hw_t *hw); 444 445 /* REG_0x00:device_id->DeviceID: ,RO,0x0[31:0]*/ 446 uint32_t sys_hal_get_device_id_deviceid(sys_hw_t *hw); 447 448 /* REG_0x01 */ 449 450 uint32_t sys_hal_get_version_id_value(sys_hw_t *hw); 451 452 /* REG_0x01:version_id->VersionID: ,RO,0x1[31:0]*/ 453 uint32_t sys_hal_get_version_id_versionid(sys_hw_t *hw); 454 455 /* REG_0x02 */ 456 457 uint32_t sys_hal_get_cpu_current_run_status_value(sys_hw_t *hw); 458 459 /* REG_0x02:cpu_current_run_status->core0_halted:core0 halt indicate,RO,0x2[0]*/ 460 uint32_t sys_hal_get_cpu_current_run_status_core0_halted(sys_hw_t *hw); 461 462 /* REG_0x02:cpu_current_run_status->core1_halted:core1 halt indicate,RO,0x2[1]*/ 463 uint32_t sys_hal_get_cpu_current_run_status_core1_halted(sys_hw_t *hw); 464 465 /* REG_0x02:cpu_current_run_status->cpu0_sw_reset:cpu0_sw_reset indicate,RO,0x2[4]*/ 466 uint32_t sys_hal_get_cpu_current_run_status_cpu0_sw_reset(sys_hw_t *hw); 467 468 /* REG_0x02:cpu_current_run_status->cpu1_sw_reset:cpu1_sw_reset indicate,RO,0x2[5]*/ 469 uint32_t sys_hal_get_cpu_current_run_status_cpu1_sw_reset(sys_hw_t *hw); 470 471 /* REG_0x02:cpu_current_run_status->cpu0_pwr_dw_state:cpu0_pwr_dw_state,RO,0x2[8]*/ 472 uint32_t sys_hal_get_cpu_current_run_status_cpu0_pwr_dw_state(sys_hw_t *hw); 473 474 /* REG_0x02:cpu_current_run_status->cpu1_pwr_dw_state:cpu1_pwr_dw_state,RO,0x2[9]*/ 475 uint32_t sys_hal_get_cpu_current_run_status_cpu1_pwr_dw_state(sys_hw_t *hw); 476 477 /* REG_0x03 */ 478 479 uint32_t sys_hal_get_cpu_storage_connect_op_select_value(sys_hw_t *hw); 480 481 void sys_hal_set_cpu_storage_connect_op_select_value(sys_hw_t *hw, uint32_t value); 482 483 /* REG_0x03:cpu_storage_connect_op_select->boot_mode:0:ROM boot 1:FLASH boot,R/W,0x3[0]*/ 484 uint32_t sys_hal_get_cpu_storage_connect_op_select_boot_mode(sys_hw_t *hw); 485 486 void sys_hal_set_cpu_storage_connect_op_select_boot_mode(sys_hw_t *hw, uint32_t value); 487 488 /* REG_0x03:cpu_storage_connect_op_select->jtag_core_sel:0:jtag connect core0, 1:jtag connect core1,R/W,0x3[8]*/ 489 uint32_t sys_hal_get_cpu_storage_connect_op_select_jtag_core_sel(sys_hw_t *hw); 490 491 void sys_hal_set_cpu_storage_connect_op_select_jtag_core_sel(sys_hw_t *hw, uint32_t value); 492 493 /* REG_0x03:cpu_storage_connect_op_select->flash_sel:0: normal flash operation 1:flash download by spi,R/W,0x3[9]*/ 494 uint32_t sys_hal_get_cpu_storage_connect_op_select_flash_sel(sys_hw_t *hw); 495 496 void sys_hal_set_cpu_storage_connect_op_select_flash_sel(sys_hw_t *hw, uint32_t value); 497 498 /* REG_0x04 */ 499 500 uint32_t sys_hal_get_cpu0_int_halt_clk_op_value(sys_hw_t *hw); 501 502 void sys_hal_set_cpu0_int_halt_clk_op_value(sys_hw_t *hw, uint32_t value); 503 504 /* REG_0x04:cpu0_int_halt_clk_op->cpu0_sw_rst:reserved,R/W,0x4[0]*/ 505 uint32_t sys_hal_get_cpu0_int_halt_clk_op_cpu0_sw_rst(sys_hw_t *hw); 506 507 void sys_hal_set_cpu0_int_halt_clk_op_cpu0_sw_rst(sys_hw_t *hw, uint32_t value); 508 509 /* REG_0x04:cpu0_int_halt_clk_op->cpu0_pwr_dw:reserved,R/W,0x4[1]*/ 510 uint32_t sys_hal_get_cpu0_int_halt_clk_op_cpu0_pwr_dw(sys_hw_t *hw); 511 512 void sys_hal_set_cpu0_int_halt_clk_op_cpu0_pwr_dw(sys_hw_t *hw, uint32_t value); 513 514 /* REG_0x04:cpu0_int_halt_clk_op->cpu0_int_mask:cpu0 int mask,R/W,0x4[2]*/ 515 uint32_t sys_hal_get_cpu0_int_halt_clk_op_cpu0_int_mask(sys_hw_t *hw); 516 517 void sys_hal_set_cpu0_int_halt_clk_op_cpu0_int_mask(sys_hw_t *hw, uint32_t value); 518 519 /* REG_0x04:cpu0_int_halt_clk_op->cpu0_halt:core0 halt indicate,R/W,0x4[3]*/ 520 uint32_t sys_hal_get_cpu0_int_halt_clk_op_cpu0_halt(sys_hw_t *hw); 521 522 void sys_hal_set_cpu0_int_halt_clk_op_cpu0_halt(sys_hw_t *hw, uint32_t value); 523 524 /* REG_0x04:cpu0_int_halt_clk_op->cpu0_clk_div:Frequency division : F/(1+N), N is the data of the reg value,R/W,0x4[7:4]*/ 525 uint32_t sys_hal_get_cpu0_int_halt_clk_op_cpu0_clk_div(sys_hw_t *hw); 526 527 void sys_hal_set_cpu0_int_halt_clk_op_cpu0_clk_div(sys_hw_t *hw, uint32_t value); 528 529 /* REG_0x04:cpu0_int_halt_clk_op->cpu0_offset:reserved,RO,0x4[31:8]*/ 530 uint32_t sys_hal_get_cpu0_int_halt_clk_op_cpu0_offset(sys_hw_t *hw); 531 532 /* REG_0x05 */ 533 534 uint32_t sys_hal_get_cpu1_int_halt_clk_op_value(sys_hw_t *hw); 535 536 void sys_hal_set_cpu1_int_halt_clk_op_value(sys_hw_t *hw, uint32_t value); 537 538 /* REG_0x05:cpu1_int_halt_clk_op->cpu1_sw_rst:reserved,R/W,0x5[0]*/ 539 uint32_t sys_hal_get_cpu1_int_halt_clk_op_cpu1_sw_rst(sys_hw_t *hw); 540 541 void sys_hal_set_cpu1_int_halt_clk_op_cpu1_sw_rst(sys_hw_t *hw, uint32_t value); 542 543 /* REG_0x05:cpu1_int_halt_clk_op->cpu1_pwr_dw:reserved,R/W,0x5[1]*/ 544 uint32_t sys_hal_get_cpu1_int_halt_clk_op_cpu1_pwr_dw(sys_hw_t *hw); 545 546 void sys_hal_set_cpu1_int_halt_clk_op_cpu1_pwr_dw(sys_hw_t *hw, uint32_t value); 547 548 /* REG_0x05:cpu1_int_halt_clk_op->cpu1_int_mask:cpu1 int mask,R/W,0x5[2]*/ 549 uint32_t sys_hal_get_cpu1_int_halt_clk_op_cpu1_int_mask(sys_hw_t *hw); 550 551 void sys_hal_set_cpu1_int_halt_clk_op_cpu1_int_mask(sys_hw_t *hw, uint32_t value); 552 553 /* REG_0x05:cpu1_int_halt_clk_op->cpu1_halt:core1 halt indicate,R/W,0x5[3]*/ 554 uint32_t sys_hal_get_cpu1_int_halt_clk_op_cpu1_halt(sys_hw_t *hw); 555 556 void sys_hal_set_cpu1_int_halt_clk_op_cpu1_halt(sys_hw_t *hw, uint32_t value); 557 558 /* REG_0x05:cpu1_int_halt_clk_op->cpu1_clk_div:Frequency division : F/(1+N), N is the data of the reg value,R/W,0x5[7:4]*/ 559 uint32_t sys_hal_get_cpu1_int_halt_clk_op_cpu1_clk_div(sys_hw_t *hw); 560 561 void sys_hal_set_cpu1_int_halt_clk_op_cpu1_clk_div(sys_hw_t *hw, uint32_t value); 562 563 /* REG_0x05:cpu1_int_halt_clk_op->cpu1_offset:reserved,R/W,0x5[31:8]*/ 564 uint32_t sys_hal_get_cpu1_int_halt_clk_op_cpu1_offset(sys_hw_t *hw); 565 566 void sys_hal_set_cpu1_int_halt_clk_op_cpu1_offset(sys_hw_t *hw, uint32_t value); 567 568 /* REG_0x06 */ 569 570 /* REG_0x08 */ 571 572 uint32_t sys_hal_get_cpu_clk_div_mode1_value(sys_hw_t *hw); 573 574 void sys_hal_set_cpu_clk_div_mode1_value(sys_hw_t *hw, uint32_t value); 575 576 /* REG_0x08:cpu_clk_div_mode1->clkdiv_core:Frequency division : F/(1+N), N is the data of the reg value,R/W,0x8[3:0]*/ 577 uint32_t sys_hal_get_cpu_clk_div_mode1_clkdiv_core(sys_hw_t *hw); 578 579 void sys_hal_set_cpu_clk_div_mode1_clkdiv_core(sys_hw_t *hw, uint32_t value); 580 581 /* REG_0x08:cpu_clk_div_mode1->cksel_core:0: clk_DCO 1 : XTAL 2 : 320M 3 : 480M,R/W,0x8[5:4]*/ 582 uint32_t sys_hal_get_cpu_clk_div_mode1_cksel_core(sys_hw_t *hw); 583 584 void sys_hal_set_cpu_clk_div_mode1_cksel_core(sys_hw_t *hw, uint32_t value); 585 586 /* REG_0x08:cpu_clk_div_mode1->clkdiv_bus:Frequency division : F/(1+N), N is the data of the reg value,R/W,0x8[6]*/ 587 uint32_t sys_hal_get_cpu_clk_div_mode1_clkdiv_bus(sys_hw_t *hw); 588 589 void sys_hal_set_cpu_clk_div_mode1_clkdiv_bus(sys_hw_t *hw, uint32_t value); 590 591 /* REG_0x08:cpu_clk_div_mode1->clkdiv_uart0:Frequency division : 0:/1 1:/2 2:/4 3:/8,R/W,0x8[9:8]*/ 592 uint32_t sys_hal_get_cpu_clk_div_mode1_clkdiv_uart0(sys_hw_t *hw); 593 594 void sys_hal_set_cpu_clk_div_mode1_clkdiv_uart0(sys_hw_t *hw, uint32_t value); 595 596 /* REG_0x08:cpu_clk_div_mode1->clksel_uart0:0:XTAL 1:APLL,R/W,0x8[10]*/ 597 uint32_t sys_hal_get_cpu_clk_div_mode1_clksel_uart0(sys_hw_t *hw); 598 599 void sys_hal_set_cpu_clk_div_mode1_clksel_uart0(sys_hw_t *hw, uint32_t value); 600 601 /* REG_0x08:cpu_clk_div_mode1->clkdiv_uart1:Frequency division : 0:/1 1:/2 2:/4 3:/8,R/W,0x8[12:11]*/ 602 uint32_t sys_hal_get_cpu_clk_div_mode1_clkdiv_uart1(sys_hw_t *hw); 603 604 void sys_hal_set_cpu_clk_div_mode1_clkdiv_uart1(sys_hw_t *hw, uint32_t value); 605 606 /* REG_0x08:cpu_clk_div_mode1->cksel_uart1:0:XTAL 1:APLL,R/W,0x8[13]*/ 607 uint32_t sys_hal_get_cpu_clk_div_mode1_cksel_uart1(sys_hw_t *hw); 608 609 void sys_hal_set_cpu_clk_div_mode1_cksel_uart1(sys_hw_t *hw, uint32_t value); 610 611 /* REG_0x08:cpu_clk_div_mode1->clkdiv_uart2:Frequency division : 0:/1 1:/2 2:/4 3:/8,R/W,0x8[15:14]*/ 612 uint32_t sys_hal_get_cpu_clk_div_mode1_clkdiv_uart2(sys_hw_t *hw); 613 614 void sys_hal_set_cpu_clk_div_mode1_clkdiv_uart2(sys_hw_t *hw, uint32_t value); 615 616 /* REG_0x08:cpu_clk_div_mode1->cksel_uart2:0:XTAL 1:APLL,R/W,0x8[16]*/ 617 uint32_t sys_hal_get_cpu_clk_div_mode1_cksel_uart2(sys_hw_t *hw); 618 619 void sys_hal_set_cpu_clk_div_mode1_cksel_uart2(sys_hw_t *hw, uint32_t value); 620 621 /* REG_0x08:cpu_clk_div_mode1->cksel_sadc:0:XTAL 1:APLL,R/W,0x8[17]*/ 622 uint32_t sys_hal_get_cpu_clk_div_mode1_cksel_sadc(sys_hw_t *hw); 623 624 void sys_hal_set_cpu_clk_div_mode1_cksel_sadc(sys_hw_t *hw, uint32_t value); 625 626 /* REG_0x08:cpu_clk_div_mode1->cksel_pwm0:0:clk32 1:XTAL,R/W,0x8[18]*/ 627 uint32_t sys_hal_get_cpu_clk_div_mode1_cksel_pwm0(sys_hw_t *hw); 628 629 void sys_hal_set_cpu_clk_div_mode1_cksel_pwm0(sys_hw_t *hw, uint32_t value); 630 631 /* REG_0x08:cpu_clk_div_mode1->cksel_pwm1:0:clk32 1:XTAL,R/W,0x8[19]*/ 632 uint32_t sys_hal_get_cpu_clk_div_mode1_cksel_pwm1(sys_hw_t *hw); 633 634 void sys_hal_set_cpu_clk_div_mode1_cksel_pwm1(sys_hw_t *hw, uint32_t value); 635 636 /* REG_0x08:cpu_clk_div_mode1->cksel_timer0:0:clk32 1:XTAL,R/W,0x8[20]*/ 637 uint32_t sys_hal_get_cpu_clk_div_mode1_cksel_timer0(sys_hw_t *hw); 638 639 void sys_hal_set_cpu_clk_div_mode1_cksel_timer0(sys_hw_t *hw, uint32_t value); 640 641 /* REG_0x08:cpu_clk_div_mode1->cksel_timer1:0:clk32 1:XTAL,R/W,0x8[21]*/ 642 uint32_t sys_hal_get_cpu_clk_div_mode1_cksel_timer1(sys_hw_t *hw); 643 644 void sys_hal_set_cpu_clk_div_mode1_cksel_timer1(sys_hw_t *hw, uint32_t value); 645 646 /* REG_0x08:cpu_clk_div_mode1->cksel_timer2:0:clk32 1:XTAL,R/W,0x8[22]*/ 647 uint32_t sys_hal_get_cpu_clk_div_mode1_cksel_timer2(sys_hw_t *hw); 648 649 void sys_hal_set_cpu_clk_div_mode1_cksel_timer2(sys_hw_t *hw, uint32_t value); 650 651 /* REG_0x08:cpu_clk_div_mode1->cksel_i2s:0:XTAL 1:APLL,R/W,0x8[24]*/ 652 uint32_t sys_hal_get_cpu_clk_div_mode1_cksel_i2s(sys_hw_t *hw); 653 654 void sys_hal_set_cpu_clk_div_mode1_cksel_i2s(sys_hw_t *hw, uint32_t value); 655 656 /* REG_0x08:cpu_clk_div_mode1->cksel_aud:0:XTAL 1:APLL,R/W,0x8[25]*/ 657 uint32_t sys_hal_get_cpu_clk_div_mode1_cksel_aud(sys_hw_t *hw); 658 659 void sys_hal_set_cpu_clk_div_mode1_cksel_aud(sys_hw_t *hw, uint32_t value); 660 661 /* REG_0x08:cpu_clk_div_mode1->clkdiv_jpeg:Frequency division : F/(1+N), N is the data of the reg value,R/W,0x8[29:26]*/ 662 uint32_t sys_hal_get_cpu_clk_div_mode1_clkdiv_jpeg(sys_hw_t *hw); 663 664 void sys_hal_set_cpu_clk_div_mode1_clkdiv_jpeg(sys_hw_t *hw, uint32_t value); 665 666 /* REG_0x08:cpu_clk_div_mode1->cksel_jpeg:0:clk_320M 1:clk_480M,R/W,0x8[30]*/ 667 uint32_t sys_hal_get_cpu_clk_div_mode1_cksel_jpeg(sys_hw_t *hw); 668 669 void sys_hal_set_cpu_clk_div_mode1_cksel_jpeg(sys_hw_t *hw, uint32_t value); 670 671 /* REG_0x08:cpu_clk_div_mode1->clkdiv_disp_l:Frequency division : F/(1+clkdiv_disp_l+clkdiv_disp_h*2),R/W,0x8[31]*/ 672 uint32_t sys_hal_get_cpu_clk_div_mode1_clkdiv_disp_l(sys_hw_t *hw); 673 674 void sys_hal_set_cpu_clk_div_mode1_clkdiv_disp_l(sys_hw_t *hw, uint32_t value); 675 676 /* REG_0x09 */ 677 678 uint32_t sys_hal_get_cpu_clk_div_mode2_value(sys_hw_t *hw); 679 680 void sys_hal_set_cpu_clk_div_mode2_value(sys_hw_t *hw, uint32_t value); 681 682 /* REG_0x09:cpu_clk_div_mode2->clkdiv_disp_h:Frequency division : F/(1+clkdiv_disp_l+clkdiv_disp_h*2),R/W,0x9[2:0]*/ 683 uint32_t sys_hal_get_cpu_clk_div_mode2_clkdiv_disp_h(sys_hw_t *hw); 684 685 void sys_hal_set_cpu_clk_div_mode2_clkdiv_disp_h(sys_hw_t *hw, uint32_t value); 686 687 /* REG_0x09:cpu_clk_div_mode2->cksel_disp:0:clk_320M 1:clk_480M,R/W,0x9[3]*/ 688 uint32_t sys_hal_get_cpu_clk_div_mode2_cksel_disp(sys_hw_t *hw); 689 690 void sys_hal_set_cpu_clk_div_mode2_cksel_disp(sys_hw_t *hw, uint32_t value); 691 692 /* REG_0x09:cpu_clk_div_mode2->ckdiv_psram:Frequency division : F/(1+N), N is the data of the reg value,R/W,0x9[4]*/ 693 uint32_t sys_hal_get_cpu_clk_div_mode2_ckdiv_psram(sys_hw_t *hw); 694 695 void sys_hal_set_cpu_clk_div_mode2_ckdiv_psram(sys_hw_t *hw, uint32_t value); 696 697 /* REG_0x09:cpu_clk_div_mode2->cksel_psram:0:clk_320M 1:clk_480M,R/W,0x9[5]*/ 698 uint32_t sys_hal_get_cpu_clk_div_mode2_cksel_psram(sys_hw_t *hw); 699 700 void sys_hal_set_cpu_clk_div_mode2_cksel_psram(sys_hw_t *hw, uint32_t value); 701 702 /* REG_0x09:cpu_clk_div_mode2->ckdiv_qspi0:Frequency division : F/(1+N), N is the data of the reg value,R/W,0x9[9:6]*/ 703 uint32_t sys_hal_get_cpu_clk_div_mode2_ckdiv_qspi0(sys_hw_t *hw); 704 705 void sys_hal_set_cpu_clk_div_mode2_ckdiv_qspi0(sys_hw_t *hw, uint32_t value); 706 707 /* REG_0x09:cpu_clk_div_mode2->ckdiv_sdio:0:/1 1:/2 2:/4 3:/8 4:/16 5:/32 6:/64 7:/256,R/W,0x9[16:14]*/ 708 uint32_t sys_hal_get_cpu_clk_div_mode2_ckdiv_sdio(sys_hw_t *hw); 709 710 void sys_hal_set_cpu_clk_div_mode2_ckdiv_sdio(sys_hw_t *hw, uint32_t value); 711 712 /* REG_0x09:cpu_clk_div_mode2->cksel_sdio:0：XTAL 1：320M,R/W,0x9[17]*/ 713 uint32_t sys_hal_get_cpu_clk_div_mode2_cksel_sdio(sys_hw_t *hw); 714 715 void sys_hal_set_cpu_clk_div_mode2_cksel_sdio(sys_hw_t *hw, uint32_t value); 716 717 /* REG_0x09:cpu_clk_div_mode2->ckdiv_auxs:Frequency division : F/(1+N), N is the data of the reg value,R/W,0x9[21:18]*/ 718 uint32_t sys_hal_get_cpu_clk_div_mode2_ckdiv_auxs(sys_hw_t *hw); 719 720 void sys_hal_set_cpu_clk_div_mode2_ckdiv_auxs(sys_hw_t *hw, uint32_t value); 721 722 /* REG_0x09:cpu_clk_div_mode2->cksel_auxs:0:DCO 1:APLL 2:320M 4:480M,R/W,0x9[23:22]*/ 723 uint32_t sys_hal_get_cpu_clk_div_mode2_cksel_auxs(sys_hw_t *hw); 724 725 void sys_hal_set_cpu_clk_div_mode2_cksel_auxs(sys_hw_t *hw, uint32_t value); 726 727 /* REG_0x09:cpu_clk_div_mode2->cksel_flash:0:XTAL 1:APLL 1x :clk_120M,R/W,0x9[25:24]*/ 728 uint32_t sys_hal_get_cpu_clk_div_mode2_cksel_flash(sys_hw_t *hw); 729 730 void sys_hal_set_cpu_clk_div_mode2_cksel_flash(sys_hw_t *hw, uint32_t value); 731 732 /* REG_0x09:cpu_clk_div_mode2->ckdiv_flash:0:/1 1:/2 2:/4 3:/8,R/W,0x9[27:26]*/ 733 uint32_t sys_hal_get_cpu_clk_div_mode2_ckdiv_flash(sys_hw_t *hw); 734 735 void sys_hal_set_cpu_clk_div_mode2_ckdiv_flash(sys_hw_t *hw, uint32_t value); 736 737 /* REG_0x09:cpu_clk_div_mode2->ckdiv_i2s0:0:/1 1:/2 2:/4 3:/8 4:/16 5:/32 6:/64 7:/256,R/W,0x9[30:28]*/ 738 uint32_t sys_hal_get_cpu_clk_div_mode2_ckdiv_i2s0(sys_hw_t *hw); 739 740 void sys_hal_set_cpu_clk_div_mode2_ckdiv_i2s0(sys_hw_t *hw, uint32_t value); 741 742 /* REG_0x0a */ 743 744 uint32_t sys_hal_get_cpu_26m_wdt_clk_div_value(sys_hw_t *hw); 745 746 void sys_hal_set_cpu_26m_wdt_clk_div_value(sys_hw_t *hw, uint32_t value); 747 748 /* REG_0x0a:cpu_26m_wdt_clk_div->ckdiv_26m:0:/1 1:/2 2:/4 3:/8,R/W,0xa[1:0]*/ 749 uint32_t sys_hal_get_cpu_26m_wdt_clk_div_ckdiv_26m(sys_hw_t *hw); 750 751 void sys_hal_set_cpu_26m_wdt_clk_div_ckdiv_26m(sys_hw_t *hw, uint32_t value); 752 753 /* REG_0x0a:cpu_26m_wdt_clk_div->ckdiv_wdt:0:/2 1:/4 2:/8 3:/16,R/W,0xa[3:2]*/ 754 uint32_t sys_hal_get_cpu_26m_wdt_clk_div_ckdiv_wdt(sys_hw_t *hw); 755 756 void sys_hal_set_cpu_26m_wdt_clk_div_ckdiv_wdt(sys_hw_t *hw, uint32_t value); 757 758 /* REG_0x0b */ 759 760 uint32_t sys_hal_get_cpu_anaspi_freq_value(sys_hw_t *hw); 761 762 void sys_hal_set_cpu_anaspi_freq_value(sys_hw_t *hw, uint32_t value); 763 764 /* REG_0x0b:cpu_anaspi_freq->anaspi_freq: ,R/W,0xb[5:0]*/ 765 uint32_t sys_hal_get_cpu_anaspi_freq_anaspi_freq(sys_hw_t *hw); 766 767 void sys_hal_set_cpu_anaspi_freq_anaspi_freq(sys_hw_t *hw, uint32_t value); 768 769 /* REG_0x0c */ 770 771 uint32_t sys_hal_get_cpu_device_clk_enable_value(sys_hw_t *hw); 772 773 void sys_hal_set_cpu_device_clk_enable_value(sys_hw_t *hw, uint32_t value); 774 775 /* REG_0x0c:cpu_device_clk_enable->i2c0_cken:1:i2c0_clk enable,R/W,0xc[0]*/ 776 uint32_t sys_hal_get_cpu_device_clk_enable_i2c0_cken(sys_hw_t *hw); 777 778 void sys_hal_set_cpu_device_clk_enable_i2c0_cken(sys_hw_t *hw, uint32_t value); 779 780 /* REG_0x0c:cpu_device_clk_enable->spi0_cken:1:spi0_clk enable ,R/W,0xc[1]*/ 781 uint32_t sys_hal_get_cpu_device_clk_enable_spi0_cken(sys_hw_t *hw); 782 783 void sys_hal_set_cpu_device_clk_enable_spi0_cken(sys_hw_t *hw, uint32_t value); 784 785 /* REG_0x0c:cpu_device_clk_enable->uart0_cken:1:uart0_clk enable,R/W,0xc[2]*/ 786 uint32_t sys_hal_get_cpu_device_clk_enable_uart0_cken(sys_hw_t *hw); 787 788 void sys_hal_set_cpu_device_clk_enable_uart0_cken(sys_hw_t *hw, uint32_t value); 789 790 /* REG_0x0c:cpu_device_clk_enable->pwm0_cken:1:pwm0_clk enable ,R/W,0xc[3]*/ 791 uint32_t sys_hal_get_cpu_device_clk_enable_pwm0_cken(sys_hw_t *hw); 792 793 void sys_hal_set_cpu_device_clk_enable_pwm0_cken(sys_hw_t *hw, uint32_t value); 794 795 /* REG_0x0c:cpu_device_clk_enable->tim0_cken:1:tim0_clk enable ,R/W,0xc[4]*/ 796 uint32_t sys_hal_get_cpu_device_clk_enable_tim0_cken(sys_hw_t *hw); 797 798 void sys_hal_set_cpu_device_clk_enable_tim0_cken(sys_hw_t *hw, uint32_t value); 799 800 /* REG_0x0c:cpu_device_clk_enable->sadc_cken:1:sadc_clk enable ,R/W,0xc[5]*/ 801 uint32_t sys_hal_get_cpu_device_clk_enable_sadc_cken(sys_hw_t *hw); 802 803 void sys_hal_set_cpu_device_clk_enable_sadc_cken(sys_hw_t *hw, uint32_t value); 804 805 /* REG_0x0c:cpu_device_clk_enable->irda_cken:1:irda_clk enable ,R/W,0xc[6]*/ 806 uint32_t sys_hal_get_cpu_device_clk_enable_irda_cken(sys_hw_t *hw); 807 808 void sys_hal_set_cpu_device_clk_enable_irda_cken(sys_hw_t *hw, uint32_t value); 809 810 /* REG_0x0c:cpu_device_clk_enable->efuse_cken:1:efuse_clk enable,R/W,0xc[7]*/ 811 uint32_t sys_hal_get_cpu_device_clk_enable_efuse_cken(sys_hw_t *hw); 812 813 void sys_hal_set_cpu_device_clk_enable_efuse_cken(sys_hw_t *hw, uint32_t value); 814 815 /* REG_0x0c:cpu_device_clk_enable->i2c1_cken:1:i2c1_clk enable ,R/W,0xc[8]*/ 816 uint32_t sys_hal_get_cpu_device_clk_enable_i2c1_cken(sys_hw_t *hw); 817 818 void sys_hal_set_cpu_device_clk_enable_i2c1_cken(sys_hw_t *hw, uint32_t value); 819 820 /* REG_0x0c:cpu_device_clk_enable->spi1_cken:1:spi1_clk enable ,R/W,0xc[9]*/ 821 uint32_t sys_hal_get_cpu_device_clk_enable_spi1_cken(sys_hw_t *hw); 822 823 void sys_hal_set_cpu_device_clk_enable_spi1_cken(sys_hw_t *hw, uint32_t value); 824 825 /* REG_0x0c:cpu_device_clk_enable->uart1_cken:1:uart1_clk enable,R/W,0xc[10]*/ 826 uint32_t sys_hal_get_cpu_device_clk_enable_uart1_cken(sys_hw_t *hw); 827 828 void sys_hal_set_cpu_device_clk_enable_uart1_cken(sys_hw_t *hw, uint32_t value); 829 830 /* REG_0x0c:cpu_device_clk_enable->uart2_cken:1:uart2_clk enable,R/W,0xc[11]*/ 831 uint32_t sys_hal_get_cpu_device_clk_enable_uart2_cken(sys_hw_t *hw); 832 833 void sys_hal_set_cpu_device_clk_enable_uart2_cken(sys_hw_t *hw, uint32_t value); 834 835 /* REG_0x0c:cpu_device_clk_enable->pwm1_cken:1:pwm1_clk enable ,R/W,0xc[12]*/ 836 uint32_t sys_hal_get_cpu_device_clk_enable_pwm1_cken(sys_hw_t *hw); 837 838 void sys_hal_set_cpu_device_clk_enable_pwm1_cken(sys_hw_t *hw, uint32_t value); 839 840 /* REG_0x0c:cpu_device_clk_enable->tim1_cken:1:tim1_clk enable ,R/W,0xc[13]*/ 841 uint32_t sys_hal_get_cpu_device_clk_enable_tim1_cken(sys_hw_t *hw); 842 843 void sys_hal_set_cpu_device_clk_enable_tim1_cken(sys_hw_t *hw, uint32_t value); 844 845 /* REG_0x0c:cpu_device_clk_enable->tim2_cken:1:tim2_clk enable ,R/W,0xc[14]*/ 846 uint32_t sys_hal_get_cpu_device_clk_enable_tim2_cken(sys_hw_t *hw); 847 848 void sys_hal_set_cpu_device_clk_enable_tim2_cken(sys_hw_t *hw, uint32_t value); 849 850 /* REG_0x0c:cpu_device_clk_enable->otp_cken:1:otp_clk enable ,R/W,0xc[15]*/ 851 uint32_t sys_hal_get_cpu_device_clk_enable_otp_cken(sys_hw_t *hw); 852 853 void sys_hal_set_cpu_device_clk_enable_otp_cken(sys_hw_t *hw, uint32_t value); 854 855 /* REG_0x0c:cpu_device_clk_enable->i2s_cken:1:i2s_clk enable ,R/W,0xc[16]*/ 856 uint32_t sys_hal_get_cpu_device_clk_enable_i2s_cken(sys_hw_t *hw); 857 858 void sys_hal_set_cpu_device_clk_enable_i2s_cken(sys_hw_t *hw, uint32_t value); 859 860 /* REG_0x0c:cpu_device_clk_enable->usb_cken:1:usb_clk enable ,R/W,0xc[17]*/ 861 uint32_t sys_hal_get_cpu_device_clk_enable_usb_cken(sys_hw_t *hw); 862 863 void sys_hal_set_cpu_device_clk_enable_usb_cken(sys_hw_t *hw, uint32_t value); 864 865 /* REG_0x0c:cpu_device_clk_enable->can_cken:1:can_clk enable ,R/W,0xc[18]*/ 866 uint32_t sys_hal_get_cpu_device_clk_enable_can_cken(sys_hw_t *hw); 867 868 void sys_hal_set_cpu_device_clk_enable_can_cken(sys_hw_t *hw, uint32_t value); 869 870 /* REG_0x0c:cpu_device_clk_enable->psram_cken:1:psram_clk enable,R/W,0xc[19]*/ 871 uint32_t sys_hal_get_cpu_device_clk_enable_psram_cken(sys_hw_t *hw); 872 873 void sys_hal_set_cpu_device_clk_enable_psram_cken(sys_hw_t *hw, uint32_t value); 874 875 /* REG_0x0c:cpu_device_clk_enable->qspi0_cken:1:qspi0_clk enable,R/W,0xc[20]*/ 876 uint32_t sys_hal_get_cpu_device_clk_enable_qspi0_cken(sys_hw_t *hw); 877 878 void sys_hal_set_cpu_device_clk_enable_qspi0_cken(sys_hw_t *hw, uint32_t value); 879 880 /* REG_0x0c:cpu_device_clk_enable->qspi1_cken:1:qspi1_clk enable,R/W,0xc[21]*/ 881 uint32_t sys_hal_get_cpu_device_clk_enable_qspi1_cken(sys_hw_t *hw); 882 883 void sys_hal_set_cpu_device_clk_enable_qspi1_cken(sys_hw_t *hw, uint32_t value); 884 885 /* REG_0x0c:cpu_device_clk_enable->sdio_cken:1:sdio_clk enable ,R/W,0xc[22]*/ 886 uint32_t sys_hal_get_cpu_device_clk_enable_sdio_cken(sys_hw_t *hw); 887 888 void sys_hal_set_cpu_device_clk_enable_sdio_cken(sys_hw_t *hw, uint32_t value); 889 890 /* REG_0x0c:cpu_device_clk_enable->auxs_cken:1:auxs_clk enable ,R/W,0xc[23]*/ 891 uint32_t sys_hal_get_cpu_device_clk_enable_auxs_cken(sys_hw_t *hw); 892 893 void sys_hal_set_cpu_device_clk_enable_auxs_cken(sys_hw_t *hw, uint32_t value); 894 895 /* REG_0x0c:cpu_device_clk_enable->btdm_cken:1:btdm_clk enable ,R/W,0xc[24]*/ 896 uint32_t sys_hal_get_cpu_device_clk_enable_btdm_cken(sys_hw_t *hw); 897 898 void sys_hal_set_cpu_device_clk_enable_btdm_cken(sys_hw_t *hw, uint32_t value); 899 900 /* REG_0x0c:cpu_device_clk_enable->xvr_cken:1:xvr_clk enable ,R/W,0xc[25]*/ 901 uint32_t sys_hal_get_cpu_device_clk_enable_xvr_cken(sys_hw_t *hw); 902 903 void sys_hal_set_cpu_device_clk_enable_xvr_cken(sys_hw_t *hw, uint32_t value); 904 905 /* REG_0x0c:cpu_device_clk_enable->mac_cken:1:mac_clk enable ,R/W,0xc[26]*/ 906 uint32_t sys_hal_get_cpu_device_clk_enable_mac_cken(sys_hw_t *hw); 907 908 void sys_hal_set_cpu_device_clk_enable_mac_cken(sys_hw_t *hw, uint32_t value); 909 910 /* REG_0x0c:cpu_device_clk_enable->phy_cken:1:phy_clk enable ,R/W,0xc[27]*/ 911 uint32_t sys_hal_get_cpu_device_clk_enable_phy_cken(sys_hw_t *hw); 912 913 void sys_hal_set_cpu_device_clk_enable_phy_cken(sys_hw_t *hw, uint32_t value); 914 915 /* REG_0x0c:cpu_device_clk_enable->jpeg_cken:1:jpeg_clk enable ,R/W,0xc[28]*/ 916 uint32_t sys_hal_get_cpu_device_clk_enable_jpeg_cken(sys_hw_t *hw); 917 918 void sys_hal_set_cpu_device_clk_enable_jpeg_cken(sys_hw_t *hw, uint32_t value); 919 920 /* REG_0x0c:cpu_device_clk_enable->disp_cken:1:disp_clk enable ,R/W,0xc[29]*/ 921 uint32_t sys_hal_get_cpu_device_clk_enable_disp_cken(sys_hw_t *hw); 922 923 void sys_hal_set_cpu_device_clk_enable_disp_cken(sys_hw_t *hw, uint32_t value); 924 925 /* REG_0x0c:cpu_device_clk_enable->aud_cken:1:aud_clk enable ,R/W,0xc[30]*/ 926 uint32_t sys_hal_get_cpu_device_clk_enable_aud_cken(sys_hw_t *hw); 927 928 void sys_hal_set_cpu_device_clk_enable_aud_cken(sys_hw_t *hw, uint32_t value); 929 930 /* REG_0x0c:cpu_device_clk_enable->wdt_cken:1:wdt_clk enable ,R/W,0xc[31]*/ 931 uint32_t sys_hal_get_cpu_device_clk_enable_wdt_cken(sys_hw_t *hw); 932 933 void sys_hal_set_cpu_device_clk_enable_wdt_cken(sys_hw_t *hw, uint32_t value); 934 935 /* REG_0x0d */ 936 937 /* REG_0x0e */ 938 939 uint32_t sys_hal_get_cpu_mode_disckg1_value(sys_hw_t *hw); 940 941 void sys_hal_set_cpu_mode_disckg1_value(sys_hw_t *hw, uint32_t value); 942 943 /* REG_0x0e:cpu_mode_disckg1->aon_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[0]*/ 944 uint32_t sys_hal_get_cpu_mode_disckg1_aon_disckg(sys_hw_t *hw); 945 946 void sys_hal_set_cpu_mode_disckg1_aon_disckg(sys_hw_t *hw, uint32_t value); 947 948 /* REG_0x0e:cpu_mode_disckg1->sys_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[1]*/ 949 uint32_t sys_hal_get_cpu_mode_disckg1_sys_disckg(sys_hw_t *hw); 950 951 void sys_hal_set_cpu_mode_disckg1_sys_disckg(sys_hw_t *hw, uint32_t value); 952 953 /* REG_0x0e:cpu_mode_disckg1->dma_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[2]*/ 954 uint32_t sys_hal_get_cpu_mode_disckg1_dma_disckg(sys_hw_t *hw); 955 956 void sys_hal_set_cpu_mode_disckg1_dma_disckg(sys_hw_t *hw, uint32_t value); 957 958 /* REG_0x0e:cpu_mode_disckg1->flash_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[3]*/ 959 uint32_t sys_hal_get_cpu_mode_disckg1_flash_disckg(sys_hw_t *hw); 960 961 void sys_hal_set_cpu_mode_disckg1_flash_disckg(sys_hw_t *hw, uint32_t value); 962 963 /* REG_0x0e:cpu_mode_disckg1->wdt_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[4]*/ 964 uint32_t sys_hal_get_cpu_mode_disckg1_wdt_disckg(sys_hw_t *hw); 965 966 void sys_hal_set_cpu_mode_disckg1_wdt_disckg(sys_hw_t *hw, uint32_t value); 967 968 /* REG_0x0e:cpu_mode_disckg1->tim_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[5]*/ 969 uint32_t sys_hal_get_cpu_mode_disckg1_tim_disckg(sys_hw_t *hw); 970 971 void sys_hal_set_cpu_mode_disckg1_tim_disckg(sys_hw_t *hw, uint32_t value); 972 973 /* REG_0x0e:cpu_mode_disckg1->urt_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[6]*/ 974 uint32_t sys_hal_get_cpu_mode_disckg1_urt_disckg(sys_hw_t *hw); 975 976 void sys_hal_set_cpu_mode_disckg1_urt_disckg(sys_hw_t *hw, uint32_t value); 977 978 /* REG_0x0e:cpu_mode_disckg1->pwm_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[7]*/ 979 uint32_t sys_hal_get_cpu_mode_disckg1_pwm_disckg(sys_hw_t *hw); 980 981 void sys_hal_set_cpu_mode_disckg1_pwm_disckg(sys_hw_t *hw, uint32_t value); 982 983 /* REG_0x0e:cpu_mode_disckg1->i2c_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[8]*/ 984 uint32_t sys_hal_get_cpu_mode_disckg1_i2c_disckg(sys_hw_t *hw); 985 986 void sys_hal_set_cpu_mode_disckg1_i2c_disckg(sys_hw_t *hw, uint32_t value); 987 988 /* REG_0x0e:cpu_mode_disckg1->spi_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[9]*/ 989 uint32_t sys_hal_get_cpu_mode_disckg1_spi_disckg(sys_hw_t *hw); 990 991 void sys_hal_set_cpu_mode_disckg1_spi_disckg(sys_hw_t *hw, uint32_t value); 992 993 /* REG_0x0e:cpu_mode_disckg1->sadc_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[10]*/ 994 uint32_t sys_hal_get_cpu_mode_disckg1_sadc_disckg(sys_hw_t *hw); 995 996 void sys_hal_set_cpu_mode_disckg1_sadc_disckg(sys_hw_t *hw, uint32_t value); 997 998 /* REG_0x0e:cpu_mode_disckg1->efs_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[11]*/ 999 uint32_t sys_hal_get_cpu_mode_disckg1_efs_disckg(sys_hw_t *hw); 1000 1001 void sys_hal_set_cpu_mode_disckg1_efs_disckg(sys_hw_t *hw, uint32_t value); 1002 1003 /* REG_0x0e:cpu_mode_disckg1->irda_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[12]*/ 1004 uint32_t sys_hal_get_cpu_mode_disckg1_irda_disckg(sys_hw_t *hw); 1005 1006 void sys_hal_set_cpu_mode_disckg1_irda_disckg(sys_hw_t *hw, uint32_t value); 1007 1008 /* REG_0x0e:cpu_mode_disckg1->trng_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[13]*/ 1009 uint32_t sys_hal_get_cpu_mode_disckg1_trng_disckg(sys_hw_t *hw); 1010 1011 void sys_hal_set_cpu_mode_disckg1_trng_disckg(sys_hw_t *hw, uint32_t value); 1012 1013 /* REG_0x0e:cpu_mode_disckg1->sdio_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[14]*/ 1014 uint32_t sys_hal_get_cpu_mode_disckg1_sdio_disckg(sys_hw_t *hw); 1015 1016 void sys_hal_set_cpu_mode_disckg1_sdio_disckg(sys_hw_t *hw, uint32_t value); 1017 1018 /* REG_0x0e:cpu_mode_disckg1->LA_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[15]*/ 1019 uint32_t sys_hal_get_cpu_mode_disckg1_la_disckg(sys_hw_t *hw); 1020 1021 void sys_hal_set_cpu_mode_disckg1_la_disckg(sys_hw_t *hw, uint32_t value); 1022 1023 /* REG_0x0e:cpu_mode_disckg1->tim1_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[16]*/ 1024 uint32_t sys_hal_get_cpu_mode_disckg1_tim1_disckg(sys_hw_t *hw); 1025 1026 void sys_hal_set_cpu_mode_disckg1_tim1_disckg(sys_hw_t *hw, uint32_t value); 1027 1028 /* REG_0x0e:cpu_mode_disckg1->urt1_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[17]*/ 1029 uint32_t sys_hal_get_cpu_mode_disckg1_urt1_disckg(sys_hw_t *hw); 1030 1031 void sys_hal_set_cpu_mode_disckg1_urt1_disckg(sys_hw_t *hw, uint32_t value); 1032 1033 /* REG_0x0e:cpu_mode_disckg1->urt2_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[18]*/ 1034 uint32_t sys_hal_get_cpu_mode_disckg1_urt2_disckg(sys_hw_t *hw); 1035 1036 void sys_hal_set_cpu_mode_disckg1_urt2_disckg(sys_hw_t *hw, uint32_t value); 1037 1038 /* REG_0x0e:cpu_mode_disckg1->pwm1_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[19]*/ 1039 uint32_t sys_hal_get_cpu_mode_disckg1_pwm1_disckg(sys_hw_t *hw); 1040 1041 void sys_hal_set_cpu_mode_disckg1_pwm1_disckg(sys_hw_t *hw, uint32_t value); 1042 1043 /* REG_0x0e:cpu_mode_disckg1->i2c1_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[20]*/ 1044 uint32_t sys_hal_get_cpu_mode_disckg1_i2c1_disckg(sys_hw_t *hw); 1045 1046 void sys_hal_set_cpu_mode_disckg1_i2c1_disckg(sys_hw_t *hw, uint32_t value); 1047 1048 /* REG_0x0e:cpu_mode_disckg1->spi1_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[21]*/ 1049 uint32_t sys_hal_get_cpu_mode_disckg1_spi1_disckg(sys_hw_t *hw); 1050 1051 void sys_hal_set_cpu_mode_disckg1_spi1_disckg(sys_hw_t *hw, uint32_t value); 1052 1053 /* REG_0x0e:cpu_mode_disckg1->usb_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[22]*/ 1054 uint32_t sys_hal_get_cpu_mode_disckg1_usb_disckg(sys_hw_t *hw); 1055 1056 void sys_hal_set_cpu_mode_disckg1_usb_disckg(sys_hw_t *hw, uint32_t value); 1057 1058 /* REG_0x0e:cpu_mode_disckg1->can_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[23]*/ 1059 uint32_t sys_hal_get_cpu_mode_disckg1_can_disckg(sys_hw_t *hw); 1060 1061 void sys_hal_set_cpu_mode_disckg1_can_disckg(sys_hw_t *hw, uint32_t value); 1062 1063 /* REG_0x0e:cpu_mode_disckg1->qspi0_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[24]*/ 1064 uint32_t sys_hal_get_cpu_mode_disckg1_qspi0_disckg(sys_hw_t *hw); 1065 1066 void sys_hal_set_cpu_mode_disckg1_qspi0_disckg(sys_hw_t *hw, uint32_t value); 1067 1068 /* REG_0x0e:cpu_mode_disckg1->psram_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[25]*/ 1069 uint32_t sys_hal_get_cpu_mode_disckg1_psram_disckg(sys_hw_t *hw); 1070 1071 void sys_hal_set_cpu_mode_disckg1_psram_disckg(sys_hw_t *hw, uint32_t value); 1072 1073 /* REG_0x0e:cpu_mode_disckg1->fft_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[26]*/ 1074 uint32_t sys_hal_get_cpu_mode_disckg1_fft_disckg(sys_hw_t *hw); 1075 1076 void sys_hal_set_cpu_mode_disckg1_fft_disckg(sys_hw_t *hw, uint32_t value); 1077 1078 /* REG_0x0e:cpu_mode_disckg1->sbc_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[27]*/ 1079 uint32_t sys_hal_get_cpu_mode_disckg1_sbc_disckg(sys_hw_t *hw); 1080 1081 void sys_hal_set_cpu_mode_disckg1_sbc_disckg(sys_hw_t *hw, uint32_t value); 1082 1083 /* REG_0x0e:cpu_mode_disckg1->aud_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[28]*/ 1084 uint32_t sys_hal_get_cpu_mode_disckg1_aud_disckg(sys_hw_t *hw); 1085 1086 void sys_hal_set_cpu_mode_disckg1_aud_disckg(sys_hw_t *hw, uint32_t value); 1087 1088 /* REG_0x0e:cpu_mode_disckg1->i2s_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[29]*/ 1089 uint32_t sys_hal_get_cpu_mode_disckg1_i2s_disckg(sys_hw_t *hw); 1090 1091 void sys_hal_set_cpu_mode_disckg1_i2s_disckg(sys_hw_t *hw, uint32_t value); 1092 1093 /* REG_0x0e:cpu_mode_disckg1->jpeg_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[30]*/ 1094 uint32_t sys_hal_get_cpu_mode_disckg1_jpeg_disckg(sys_hw_t *hw); 1095 1096 void sys_hal_set_cpu_mode_disckg1_jpeg_disckg(sys_hw_t *hw, uint32_t value); 1097 1098 /* REG_0x0e:cpu_mode_disckg1->jpeg_dec_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xe[31]*/ 1099 uint32_t sys_hal_get_cpu_mode_disckg1_jpeg_dec_disckg(sys_hw_t *hw); 1100 1101 void sys_hal_set_cpu_mode_disckg1_jpeg_dec_disckg(sys_hw_t *hw, uint32_t value); 1102 1103 /* REG_0x0f */ 1104 1105 uint32_t sys_hal_get_cpu_mode_disckg2_value(sys_hw_t *hw); 1106 1107 void sys_hal_set_cpu_mode_disckg2_value(sys_hw_t *hw, uint32_t value); 1108 1109 /* REG_0x0f:cpu_mode_disckg2->disp_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xf[0]*/ 1110 uint32_t sys_hal_get_cpu_mode_disckg2_disp_disckg(sys_hw_t *hw); 1111 1112 void sys_hal_set_cpu_mode_disckg2_disp_disckg(sys_hw_t *hw, uint32_t value); 1113 1114 /* REG_0x0f:cpu_mode_disckg2->dma2d_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xf[1]*/ 1115 uint32_t sys_hal_get_cpu_mode_disckg2_dma2d_disckg(sys_hw_t *hw); 1116 1117 void sys_hal_set_cpu_mode_disckg2_dma2d_disckg(sys_hw_t *hw, uint32_t value); 1118 1119 /* REG_0x0f:cpu_mode_disckg2->btdm_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xf[3]*/ 1120 uint32_t sys_hal_get_cpu_mode_disckg2_btdm_disckg(sys_hw_t *hw); 1121 1122 void sys_hal_set_cpu_mode_disckg2_btdm_disckg(sys_hw_t *hw, uint32_t value); 1123 1124 /* REG_0x0f:cpu_mode_disckg2->xver_disckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xf[4]*/ 1125 uint32_t sys_hal_get_cpu_mode_disckg2_xver_disckg(sys_hw_t *hw); 1126 1127 void sys_hal_set_cpu_mode_disckg2_xver_disckg(sys_hw_t *hw, uint32_t value); 1128 1129 /* REG_0x0f:cpu_mode_disckg2->btdm_bps_ckg:BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,R/W,0xf[8:5]*/ 1130 uint32_t sys_hal_get_cpu_mode_disckg2_btdm_bps_ckg(sys_hw_t *hw); 1131 1132 void sys_hal_set_cpu_mode_disckg2_btdm_bps_ckg(sys_hw_t *hw, uint32_t value); 1133 1134 /* REG_0x10 */ 1135 1136 uint32_t sys_hal_get_cpu_power_sleep_wakeup_value(sys_hw_t *hw); 1137 1138 void sys_hal_set_cpu_power_sleep_wakeup_value(sys_hw_t *hw, uint32_t value); 1139 1140 /* REG_0x10:cpu_power_sleep_wakeup->pwd_mem1:0:power on of mem1 ,RW,0x10[0]*/ 1141 uint32_t sys_hal_get_cpu_power_sleep_wakeup_pwd_mem1(sys_hw_t *hw); 1142 1143 void sys_hal_set_cpu_power_sleep_wakeup_pwd_mem1(sys_hw_t *hw, uint32_t value); 1144 1145 /* REG_0x10:cpu_power_sleep_wakeup->pwd_mem2:0:power on of mem2 ,RW,0x10[1]*/ 1146 uint32_t sys_hal_get_cpu_power_sleep_wakeup_pwd_mem2(sys_hw_t *hw); 1147 1148 void sys_hal_set_cpu_power_sleep_wakeup_pwd_mem2(sys_hw_t *hw, uint32_t value); 1149 1150 /* REG_0x10:cpu_power_sleep_wakeup->pwd_mem3:0:power on of mem3 ,RW,0x10[2]*/ 1151 uint32_t sys_hal_get_cpu_power_sleep_wakeup_pwd_mem3(sys_hw_t *hw); 1152 1153 void sys_hal_set_cpu_power_sleep_wakeup_pwd_mem3(sys_hw_t *hw, uint32_t value); 1154 1155 /* REG_0x10:cpu_power_sleep_wakeup->pwd_encp:0:power on of encp ,RW,0x10[3]*/ 1156 uint32_t sys_hal_get_cpu_power_sleep_wakeup_pwd_encp(sys_hw_t *hw); 1157 1158 void sys_hal_set_cpu_power_sleep_wakeup_pwd_encp(sys_hw_t *hw, uint32_t value); 1159 1160 /* REG_0x10:cpu_power_sleep_wakeup->pwd_bakp:0:power on of bakp ,RW,0x10[4]*/ 1161 uint32_t sys_hal_get_cpu_power_sleep_wakeup_pwd_bakp(sys_hw_t *hw); 1162 1163 void sys_hal_set_cpu_power_sleep_wakeup_pwd_bakp(sys_hw_t *hw, uint32_t value); 1164 1165 /* REG_0x10:cpu_power_sleep_wakeup->pwd_ahbp:0:power on of ahbp ,RW,0x10[5]*/ 1166 uint32_t sys_hal_get_cpu_power_sleep_wakeup_pwd_ahbp(sys_hw_t *hw); 1167 1168 void sys_hal_set_cpu_power_sleep_wakeup_pwd_ahbp(sys_hw_t *hw, uint32_t value); 1169 1170 /* REG_0x10:cpu_power_sleep_wakeup->pwd_audp:0:power on of audp ,RW,0x10[6]*/ 1171 uint32_t sys_hal_get_cpu_power_sleep_wakeup_pwd_audp(sys_hw_t *hw); 1172 1173 void sys_hal_set_cpu_power_sleep_wakeup_pwd_audp(sys_hw_t *hw, uint32_t value); 1174 1175 /* REG_0x10:cpu_power_sleep_wakeup->pwd_vidp:0:power on of vidp ,RW,0x10[7]*/ 1176 uint32_t sys_hal_get_cpu_power_sleep_wakeup_pwd_vidp(sys_hw_t *hw); 1177 1178 void sys_hal_set_cpu_power_sleep_wakeup_pwd_vidp(sys_hw_t *hw, uint32_t value); 1179 1180 /* REG_0x10:cpu_power_sleep_wakeup->pwd_btsp:0:power on of btsp ,RW,0x10[8]*/ 1181 uint32_t sys_hal_get_cpu_power_sleep_wakeup_pwd_btsp(sys_hw_t *hw); 1182 1183 void sys_hal_set_cpu_power_sleep_wakeup_pwd_btsp(sys_hw_t *hw, uint32_t value); 1184 1185 /* REG_0x10:cpu_power_sleep_wakeup->pwd_wifp_mac:0:power on of wifp_mac ,RW,0x10[9]*/ 1186 uint32_t sys_hal_get_cpu_power_sleep_wakeup_pwd_wifp_mac(sys_hw_t *hw); 1187 1188 void sys_hal_set_cpu_power_sleep_wakeup_pwd_wifp_mac(sys_hw_t *hw, uint32_t value); 1189 1190 /* REG_0x10:cpu_power_sleep_wakeup->pwd_wifp_phy:0:power on of wifp_phy ,RW,0x10[10]*/ 1191 uint32_t sys_hal_get_cpu_power_sleep_wakeup_pwd_wifp_phy(sys_hw_t *hw); 1192 1193 void sys_hal_set_cpu_power_sleep_wakeup_pwd_wifp_phy(sys_hw_t *hw, uint32_t value); 1194 1195 /* REG_0x10:cpu_power_sleep_wakeup->sleep_en_need_flash_idle:0:sleep_en of flash_idle,RW,0x10[16]*/ 1196 uint32_t sys_hal_get_cpu_power_sleep_wakeup_sleep_en_need_flash_idle(sys_hw_t *hw); 1197 1198 void sys_hal_set_cpu_power_sleep_wakeup_sleep_en_need_flash_idle(sys_hw_t *hw, uint32_t value); 1199 1200 /* REG_0x10:cpu_power_sleep_wakeup->sleep_en_need_cpu1_wfi:0:sleep_en of cpu1_wfi ,RW,0x10[17]*/ 1201 uint32_t sys_hal_get_cpu_power_sleep_wakeup_sleep_en_need_cpu1_wfi(sys_hw_t *hw); 1202 1203 void sys_hal_set_cpu_power_sleep_wakeup_sleep_en_need_cpu1_wfi(sys_hw_t *hw, uint32_t value); 1204 1205 /* REG_0x10:cpu_power_sleep_wakeup->sleep_en_need_cpu0_wfi:0:sleep_en of cpu0_wfi ,RW,0x10[18]*/ 1206 uint32_t sys_hal_get_cpu_power_sleep_wakeup_sleep_en_need_cpu0_wfi(sys_hw_t *hw); 1207 1208 void sys_hal_set_cpu_power_sleep_wakeup_sleep_en_need_cpu0_wfi(sys_hw_t *hw, uint32_t value); 1209 1210 /* REG_0x10:cpu_power_sleep_wakeup->sleep_en_global:0:sleep_en of global ,RW,0x10[19]*/ 1211 uint32_t sys_hal_get_cpu_power_sleep_wakeup_sleep_en_global(sys_hw_t *hw); 1212 1213 void sys_hal_set_cpu_power_sleep_wakeup_sleep_en_global(sys_hw_t *hw, uint32_t value); 1214 1215 /* REG_0x10:cpu_power_sleep_wakeup->wifi_wakeup_platform_en:0:wifi_wakeup_en ,RW,0x10[20]*/ 1216 uint32_t sys_hal_get_cpu_power_sleep_wakeup_wifi_wakeup_platform_en(sys_hw_t *hw); 1217 1218 void sys_hal_set_cpu_power_sleep_wakeup_wifi_wakeup_platform_en(sys_hw_t *hw, uint32_t value); 1219 1220 /* REG_0x10:cpu_power_sleep_wakeup->bts_wakeup_platform_en:0:bts_wakeup_en ,RW,0x10[21]*/ 1221 uint32_t sys_hal_get_cpu_power_sleep_wakeup_bts_wakeup_platform_en(sys_hw_t *hw); 1222 1223 void sys_hal_set_cpu_power_sleep_wakeup_bts_wakeup_platform_en(sys_hw_t *hw, uint32_t value); 1224 1225 /* REG_0x10:cpu_power_sleep_wakeup->bts_sleep_exit_req:0:bt sleep exit request ,RW,0x10[22]*/ 1226 uint32_t sys_hal_get_cpu_power_sleep_wakeup_bts_sleep_exit_req(sys_hw_t *hw); 1227 1228 void sys_hal_set_cpu_power_sleep_wakeup_bts_sleep_exit_req(sys_hw_t *hw, uint32_t value); 1229 1230 /* REG_0x11 */ 1231 1232 /* REG_0x20 */ 1233 1234 uint32_t sys_hal_get_cpu0_int_0_31_en_value(sys_hw_t *hw); 1235 1236 void sys_hal_set_cpu0_int_0_31_en_value(sys_hw_t *hw, uint32_t value); 1237 1238 /* REG_0x20:cpu0_int_0_31_en->cpu0_bmc32_int_en: ,R/W,0x20[0]*/ 1239 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_bmc32_int_en(sys_hw_t *hw); 1240 1241 void sys_hal_set_cpu0_int_0_31_en_cpu0_bmc32_int_en(sys_hw_t *hw, uint32_t value); 1242 1243 /* REG_0x20:cpu0_int_0_31_en->cpu0_host_0_irq_en: ,R/W,0x20[1]*/ 1244 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_host_0_irq_en(sys_hw_t *hw); 1245 1246 void sys_hal_set_cpu0_int_0_31_en_cpu0_host_0_irq_en(sys_hw_t *hw, uint32_t value); 1247 1248 /* REG_0x20:cpu0_int_0_31_en->cpu0_host_0_sec_irq_en: ,R/W,0x20[2]*/ 1249 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_host_0_sec_irq_en(sys_hw_t *hw); 1250 1251 void sys_hal_set_cpu0_int_0_31_en_cpu0_host_0_sec_irq_en(sys_hw_t *hw, uint32_t value); 1252 1253 /* REG_0x20:cpu0_int_0_31_en->cpu0_timer_int_en: ,R/W,0x20[3]*/ 1254 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_timer_int_en(sys_hw_t *hw); 1255 1256 void sys_hal_set_cpu0_int_0_31_en_cpu0_timer_int_en(sys_hw_t *hw, uint32_t value); 1257 1258 /* REG_0x20:cpu0_int_0_31_en->cpu0_uart_int_en: ,R/W,0x20[4]*/ 1259 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_uart_int_en(sys_hw_t *hw); 1260 1261 void sys_hal_set_cpu0_int_0_31_en_cpu0_uart_int_en(sys_hw_t *hw, uint32_t value); 1262 1263 /* REG_0x20:cpu0_int_0_31_en->cpu0_pwm_int_en: ,R/W,0x20[5]*/ 1264 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_pwm_int_en(sys_hw_t *hw); 1265 1266 void sys_hal_set_cpu0_int_0_31_en_cpu0_pwm_int_en(sys_hw_t *hw, uint32_t value); 1267 1268 /* REG_0x20:cpu0_int_0_31_en->cpu0_i2c_int_en: ,R/W,0x20[6]*/ 1269 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_i2c_int_en(sys_hw_t *hw); 1270 1271 void sys_hal_set_cpu0_int_0_31_en_cpu0_i2c_int_en(sys_hw_t *hw, uint32_t value); 1272 1273 /* REG_0x20:cpu0_int_0_31_en->cpu0_spi_int_en: ,R/W,0x20[7]*/ 1274 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_spi_int_en(sys_hw_t *hw); 1275 1276 void sys_hal_set_cpu0_int_0_31_en_cpu0_spi_int_en(sys_hw_t *hw, uint32_t value); 1277 1278 /* REG_0x20:cpu0_int_0_31_en->cpu0_sadc_int_en: ,R/W,0x20[8]*/ 1279 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_sadc_int_en(sys_hw_t *hw); 1280 1281 void sys_hal_set_cpu0_int_0_31_en_cpu0_sadc_int_en(sys_hw_t *hw, uint32_t value); 1282 1283 /* REG_0x20:cpu0_int_0_31_en->cpu0_irda_int_en: ,R/W,0x20[9]*/ 1284 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_irda_int_en(sys_hw_t *hw); 1285 1286 void sys_hal_set_cpu0_int_0_31_en_cpu0_irda_int_en(sys_hw_t *hw, uint32_t value); 1287 1288 /* REG_0x20:cpu0_int_0_31_en->cpu0_sdio_int_en: ,R/W,0x20[10]*/ 1289 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_sdio_int_en(sys_hw_t *hw); 1290 1291 void sys_hal_set_cpu0_int_0_31_en_cpu0_sdio_int_en(sys_hw_t *hw, uint32_t value); 1292 1293 /* REG_0x20:cpu0_int_0_31_en->cpu0_gdma_int_en: ,R/W,0x20[11]*/ 1294 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_gdma_int_en(sys_hw_t *hw); 1295 1296 void sys_hal_set_cpu0_int_0_31_en_cpu0_gdma_int_en(sys_hw_t *hw, uint32_t value); 1297 1298 /* REG_0x20:cpu0_int_0_31_en->cpu0_la_int_en: ,R/W,0x20[12]*/ 1299 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_la_int_en(sys_hw_t *hw); 1300 1301 void sys_hal_set_cpu0_int_0_31_en_cpu0_la_int_en(sys_hw_t *hw, uint32_t value); 1302 1303 /* REG_0x20:cpu0_int_0_31_en->cpu0_timer1_int_en: ,R/W,0x20[13]*/ 1304 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_timer1_int_en(sys_hw_t *hw); 1305 1306 void sys_hal_set_cpu0_int_0_31_en_cpu0_timer1_int_en(sys_hw_t *hw, uint32_t value); 1307 1308 /* REG_0x20:cpu0_int_0_31_en->cpu0_i2c1_int_en: ,R/W,0x20[14]*/ 1309 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_i2c1_int_en(sys_hw_t *hw); 1310 1311 void sys_hal_set_cpu0_int_0_31_en_cpu0_i2c1_int_en(sys_hw_t *hw, uint32_t value); 1312 1313 /* REG_0x20:cpu0_int_0_31_en->cpu0_uart1_int_en: ,R/W,0x20[15]*/ 1314 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_uart1_int_en(sys_hw_t *hw); 1315 1316 void sys_hal_set_cpu0_int_0_31_en_cpu0_uart1_int_en(sys_hw_t *hw, uint32_t value); 1317 1318 /* REG_0x20:cpu0_int_0_31_en->cpu0_uart2_int_en: ,R/W,0x20[16]*/ 1319 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_uart2_int_en(sys_hw_t *hw); 1320 1321 void sys_hal_set_cpu0_int_0_31_en_cpu0_uart2_int_en(sys_hw_t *hw, uint32_t value); 1322 1323 /* REG_0x20:cpu0_int_0_31_en->cpu0_spi1_int_en: ,R/W,0x20[17]*/ 1324 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_spi1_int_en(sys_hw_t *hw); 1325 1326 void sys_hal_set_cpu0_int_0_31_en_cpu0_spi1_int_en(sys_hw_t *hw, uint32_t value); 1327 1328 /* REG_0x20:cpu0_int_0_31_en->cpu0_can_int_en: ,R/W,0x20[18]*/ 1329 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_can_int_en(sys_hw_t *hw); 1330 1331 void sys_hal_set_cpu0_int_0_31_en_cpu0_can_int_en(sys_hw_t *hw, uint32_t value); 1332 1333 /* REG_0x20:cpu0_int_0_31_en->cpu0_usb_int_en: ,R/W,0x20[19]*/ 1334 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_usb_int_en(sys_hw_t *hw); 1335 1336 void sys_hal_set_cpu0_int_0_31_en_cpu0_usb_int_en(sys_hw_t *hw, uint32_t value); 1337 1338 /* REG_0x20:cpu0_int_0_31_en->cpu0_qspi_int_en: ,R/W,0x20[20]*/ 1339 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_qspi_int_en(sys_hw_t *hw); 1340 1341 void sys_hal_set_cpu0_int_0_31_en_cpu0_qspi_int_en(sys_hw_t *hw, uint32_t value); 1342 1343 /* REG_0x20:cpu0_int_0_31_en->cpu0_fft_int_en: ,R/W,0x20[21]*/ 1344 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_fft_int_en(sys_hw_t *hw); 1345 1346 void sys_hal_set_cpu0_int_0_31_en_cpu0_fft_int_en(sys_hw_t *hw, uint32_t value); 1347 1348 /* REG_0x20:cpu0_int_0_31_en->cpu0_sbc_int_en: ,R/W,0x20[22]*/ 1349 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_sbc_int_en(sys_hw_t *hw); 1350 1351 void sys_hal_set_cpu0_int_0_31_en_cpu0_sbc_int_en(sys_hw_t *hw, uint32_t value); 1352 1353 /* REG_0x20:cpu0_int_0_31_en->cpu0_aud_int_en: ,R/W,0x20[23]*/ 1354 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_aud_int_en(sys_hw_t *hw); 1355 1356 void sys_hal_set_cpu0_int_0_31_en_cpu0_aud_int_en(sys_hw_t *hw, uint32_t value); 1357 1358 /* REG_0x20:cpu0_int_0_31_en->cpu0_i2s_int_en: ,R/W,0x20[24]*/ 1359 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_i2s_int_en(sys_hw_t *hw); 1360 1361 void sys_hal_set_cpu0_int_0_31_en_cpu0_i2s_int_en(sys_hw_t *hw, uint32_t value); 1362 1363 /* REG_0x20:cpu0_int_0_31_en->cpu0_jpegenc_int_en: ,R/W,0x20[25]*/ 1364 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_jpegenc_int_en(sys_hw_t *hw); 1365 1366 void sys_hal_set_cpu0_int_0_31_en_cpu0_jpegenc_int_en(sys_hw_t *hw, uint32_t value); 1367 1368 /* REG_0x20:cpu0_int_0_31_en->cpu0_jpegdec_int_en: ,R/W,0x20[26]*/ 1369 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_jpegdec_int_en(sys_hw_t *hw); 1370 1371 void sys_hal_set_cpu0_int_0_31_en_cpu0_jpegdec_int_en(sys_hw_t *hw, uint32_t value); 1372 1373 /* REG_0x20:cpu0_int_0_31_en->cpu0_lcd_int_en: ,R/W,0x20[27]*/ 1374 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_lcd_int_en(sys_hw_t *hw); 1375 1376 void sys_hal_set_cpu0_int_0_31_en_cpu0_lcd_int_en(sys_hw_t *hw, uint32_t value); 1377 1378 /* REG_0x20:cpu0_int_0_31_en->cpu0_wifi_int_phy_en: ,R/W,0x20[29]*/ 1379 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_wifi_int_phy_en(sys_hw_t *hw); 1380 1381 void sys_hal_set_cpu0_int_0_31_en_cpu0_wifi_int_phy_en(sys_hw_t *hw, uint32_t value); 1382 1383 /* REG_0x20:cpu0_int_0_31_en->cpu0_wifi_mac_int_tx_rx_timer_en: ,R/W,0x20[30]*/ 1384 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_wifi_mac_int_tx_rx_timer_en(sys_hw_t *hw); 1385 1386 void sys_hal_set_cpu0_int_0_31_en_cpu0_wifi_mac_int_tx_rx_timer_en(sys_hw_t *hw, uint32_t value); 1387 1388 /* REG_0x20:cpu0_int_0_31_en->cpu0_wifi_mac_int_tx_rx_misc_en: ,R/W,0x20[31]*/ 1389 uint32_t sys_hal_get_cpu0_int_0_31_en_cpu0_wifi_mac_int_tx_rx_misc_en(sys_hw_t *hw); 1390 1391 void sys_hal_set_cpu0_int_0_31_en_cpu0_wifi_mac_int_tx_rx_misc_en(sys_hw_t *hw, uint32_t value); 1392 1393 /* REG_0x21 */ 1394 1395 uint32_t sys_hal_get_cpu0_int_32_63_en_value(sys_hw_t *hw); 1396 1397 void sys_hal_set_cpu0_int_32_63_en_value(sys_hw_t *hw, uint32_t value); 1398 1399 /* REG_0x21:cpu0_int_32_63_en->cpu0_wifi_mac_int_rx_trigger_en: ,R/W,0x21[0]*/ 1400 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_wifi_mac_int_rx_trigger_en(sys_hw_t *hw); 1401 1402 void sys_hal_set_cpu0_int_32_63_en_cpu0_wifi_mac_int_rx_trigger_en(sys_hw_t *hw, uint32_t value); 1403 1404 /* REG_0x21:cpu0_int_32_63_en->cpu0_wifi_mac_int_tx_trigger_en: ,R/W,0x21[1]*/ 1405 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_wifi_mac_int_tx_trigger_en(sys_hw_t *hw); 1406 1407 void sys_hal_set_cpu0_int_32_63_en_cpu0_wifi_mac_int_tx_trigger_en(sys_hw_t *hw, uint32_t value); 1408 1409 /* REG_0x21:cpu0_int_32_63_en->cpu0_wifi_mac_port_trigger_en: ,R/W,0x21[2]*/ 1410 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_wifi_mac_port_trigger_en(sys_hw_t *hw); 1411 1412 void sys_hal_set_cpu0_int_32_63_en_cpu0_wifi_mac_port_trigger_en(sys_hw_t *hw, uint32_t value); 1413 1414 /* REG_0x21:cpu0_int_32_63_en->cpu0_wifi_mac_int_gen_en: ,R/W,0x21[3]*/ 1415 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_wifi_mac_int_gen_en(sys_hw_t *hw); 1416 1417 void sys_hal_set_cpu0_int_32_63_en_cpu0_wifi_mac_int_gen_en(sys_hw_t *hw, uint32_t value); 1418 1419 /* REG_0x21:cpu0_int_32_63_en->cpu0_wifi_hsu_irq_en: ,R/W,0x21[4]*/ 1420 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_wifi_hsu_irq_en(sys_hw_t *hw); 1421 1422 void sys_hal_set_cpu0_int_32_63_en_cpu0_wifi_hsu_irq_en(sys_hw_t *hw, uint32_t value); 1423 1424 /* REG_0x21:cpu0_int_32_63_en->cpu0_wifi_int_mac_wakeup_en: ,R/W,0x21[5]*/ 1425 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_wifi_int_mac_wakeup_en(sys_hw_t *hw); 1426 1427 void sys_hal_set_cpu0_int_32_63_en_cpu0_wifi_int_mac_wakeup_en(sys_hw_t *hw, uint32_t value); 1428 1429 /* REG_0x21:cpu0_int_32_63_en->cpu0_dm_irq_en: ,R/W,0x21[7]*/ 1430 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_dm_irq_en(sys_hw_t *hw); 1431 1432 void sys_hal_set_cpu0_int_32_63_en_cpu0_dm_irq_en(sys_hw_t *hw, uint32_t value); 1433 1434 /* REG_0x21:cpu0_int_32_63_en->cpu0_ble_irq_en: ,R/W,0x21[8]*/ 1435 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_ble_irq_en(sys_hw_t *hw); 1436 1437 void sys_hal_set_cpu0_int_32_63_en_cpu0_ble_irq_en(sys_hw_t *hw, uint32_t value); 1438 1439 /* REG_0x21:cpu0_int_32_63_en->cpu0_bt_irq_en: ,R/W,0x21[9]*/ 1440 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_bt_irq_en(sys_hw_t *hw); 1441 1442 void sys_hal_set_cpu0_int_32_63_en_cpu0_bt_irq_en(sys_hw_t *hw, uint32_t value); 1443 1444 /* REG_0x21:cpu0_int_32_63_en->cpu0_mbox0_int_en: ,R/W,0x21[15]*/ 1445 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_mbox0_int_en(sys_hw_t *hw); 1446 1447 void sys_hal_set_cpu0_int_32_63_en_cpu0_mbox0_int_en(sys_hw_t *hw, uint32_t value); 1448 1449 /* REG_0x21:cpu0_int_32_63_en->cpu0_mbox1_int_en: ,R/W,0x21[16]*/ 1450 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_mbox1_int_en(sys_hw_t *hw); 1451 1452 void sys_hal_set_cpu0_int_32_63_en_cpu0_mbox1_int_en(sys_hw_t *hw, uint32_t value); 1453 1454 /* REG_0x21:cpu0_int_32_63_en->cpu0_bmc64_int_en: ,R/W,0x21[17]*/ 1455 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_bmc64_int_en(sys_hw_t *hw); 1456 1457 void sys_hal_set_cpu0_int_32_63_en_cpu0_bmc64_int_en(sys_hw_t *hw, uint32_t value); 1458 1459 /* REG_0x21:cpu0_int_32_63_en->cpu0_touched_int_en: ,R/W,0x21[19]*/ 1460 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_touched_int_en(sys_hw_t *hw); 1461 1462 void sys_hal_set_cpu0_int_32_63_en_cpu0_touched_int_en(sys_hw_t *hw, uint32_t value); 1463 1464 /* REG_0x21:cpu0_int_32_63_en->cpu0_usbplug_int_en: ,R/W,0x21[20]*/ 1465 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_usbplug_int_en(sys_hw_t *hw); 1466 1467 void sys_hal_set_cpu0_int_32_63_en_cpu0_usbplug_int_en(sys_hw_t *hw, uint32_t value); 1468 1469 /* REG_0x21:cpu0_int_32_63_en->cpu0_rtc_int_en: ,R/W,0x21[21]*/ 1470 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_rtc_int_en(sys_hw_t *hw); 1471 1472 void sys_hal_set_cpu0_int_32_63_en_cpu0_rtc_int_en(sys_hw_t *hw, uint32_t value); 1473 1474 /* REG_0x21:cpu0_int_32_63_en->cpu0_gpio_int_en: ,R/W,0x21[22]*/ 1475 uint32_t sys_hal_get_cpu0_int_32_63_en_cpu0_gpio_int_en(sys_hw_t *hw); 1476 1477 void sys_hal_set_cpu0_int_32_63_en_cpu0_gpio_int_en(sys_hw_t *hw, uint32_t value); 1478 1479 /* REG_0x22 */ 1480 1481 uint32_t sys_hal_get_cpu1_int_0_31_en_value(sys_hw_t *hw); 1482 1483 void sys_hal_set_cpu1_int_0_31_en_value(sys_hw_t *hw, uint32_t value); 1484 1485 /* REG_0x22:cpu1_int_0_31_en->cpu1_bmc32_int_en: ,R/W,0x22[0]*/ 1486 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_bmc32_int_en(sys_hw_t *hw); 1487 1488 void sys_hal_set_cpu1_int_0_31_en_cpu1_bmc32_int_en(sys_hw_t *hw, uint32_t value); 1489 1490 /* REG_0x22:cpu1_int_0_31_en->cpu1_host_0_irq_en: ,R/W,0x22[1]*/ 1491 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_host_0_irq_en(sys_hw_t *hw); 1492 1493 void sys_hal_set_cpu1_int_0_31_en_cpu1_host_0_irq_en(sys_hw_t *hw, uint32_t value); 1494 1495 /* REG_0x22:cpu1_int_0_31_en->cpu1_host_0_sec_irq_en: ,R/W,0x22[2]*/ 1496 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_host_0_sec_irq_en(sys_hw_t *hw); 1497 1498 void sys_hal_set_cpu1_int_0_31_en_cpu1_host_0_sec_irq_en(sys_hw_t *hw, uint32_t value); 1499 1500 /* REG_0x22:cpu1_int_0_31_en->cpu1_timer_int_en: ,R/W,0x22[3]*/ 1501 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_timer_int_en(sys_hw_t *hw); 1502 1503 void sys_hal_set_cpu1_int_0_31_en_cpu1_timer_int_en(sys_hw_t *hw, uint32_t value); 1504 1505 /* REG_0x22:cpu1_int_0_31_en->cpu1_uart_int_en: ,R/W,0x22[4]*/ 1506 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_uart_int_en(sys_hw_t *hw); 1507 1508 void sys_hal_set_cpu1_int_0_31_en_cpu1_uart_int_en(sys_hw_t *hw, uint32_t value); 1509 1510 /* REG_0x22:cpu1_int_0_31_en->cpu1_pwm_int_en: ,R/W,0x22[5]*/ 1511 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_pwm_int_en(sys_hw_t *hw); 1512 1513 void sys_hal_set_cpu1_int_0_31_en_cpu1_pwm_int_en(sys_hw_t *hw, uint32_t value); 1514 1515 /* REG_0x22:cpu1_int_0_31_en->cpu1_i2c_int_en: ,R/W,0x22[6]*/ 1516 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_i2c_int_en(sys_hw_t *hw); 1517 1518 void sys_hal_set_cpu1_int_0_31_en_cpu1_i2c_int_en(sys_hw_t *hw, uint32_t value); 1519 1520 /* REG_0x22:cpu1_int_0_31_en->cpu1_spi_int_en: ,R/W,0x22[7]*/ 1521 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_spi_int_en(sys_hw_t *hw); 1522 1523 void sys_hal_set_cpu1_int_0_31_en_cpu1_spi_int_en(sys_hw_t *hw, uint32_t value); 1524 1525 /* REG_0x22:cpu1_int_0_31_en->cpu1_sadc_int_en: ,R/W,0x22[8]*/ 1526 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_sadc_int_en(sys_hw_t *hw); 1527 1528 void sys_hal_set_cpu1_int_0_31_en_cpu1_sadc_int_en(sys_hw_t *hw, uint32_t value); 1529 1530 /* REG_0x22:cpu1_int_0_31_en->cpu1_irda_int_en: ,R/W,0x22[9]*/ 1531 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_irda_int_en(sys_hw_t *hw); 1532 1533 void sys_hal_set_cpu1_int_0_31_en_cpu1_irda_int_en(sys_hw_t *hw, uint32_t value); 1534 1535 /* REG_0x22:cpu1_int_0_31_en->cpu1_sdio_int_en: ,R/W,0x22[10]*/ 1536 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_sdio_int_en(sys_hw_t *hw); 1537 1538 void sys_hal_set_cpu1_int_0_31_en_cpu1_sdio_int_en(sys_hw_t *hw, uint32_t value); 1539 1540 /* REG_0x22:cpu1_int_0_31_en->cpu1_gdma_int_en: ,R/W,0x22[11]*/ 1541 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_gdma_int_en(sys_hw_t *hw); 1542 1543 void sys_hal_set_cpu1_int_0_31_en_cpu1_gdma_int_en(sys_hw_t *hw, uint32_t value); 1544 1545 /* REG_0x22:cpu1_int_0_31_en->cpu1_la_int_en: ,R/W,0x22[12]*/ 1546 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_la_int_en(sys_hw_t *hw); 1547 1548 void sys_hal_set_cpu1_int_0_31_en_cpu1_la_int_en(sys_hw_t *hw, uint32_t value); 1549 1550 /* REG_0x22:cpu1_int_0_31_en->cpu1_timer1_int_en: ,R/W,0x22[13]*/ 1551 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_timer1_int_en(sys_hw_t *hw); 1552 1553 void sys_hal_set_cpu1_int_0_31_en_cpu1_timer1_int_en(sys_hw_t *hw, uint32_t value); 1554 1555 /* REG_0x22:cpu1_int_0_31_en->cpu1_i2c1_int_en: ,R/W,0x22[14]*/ 1556 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_i2c1_int_en(sys_hw_t *hw); 1557 1558 void sys_hal_set_cpu1_int_0_31_en_cpu1_i2c1_int_en(sys_hw_t *hw, uint32_t value); 1559 1560 /* REG_0x22:cpu1_int_0_31_en->cpu1_uart1_int_en: ,R/W,0x22[15]*/ 1561 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_uart1_int_en(sys_hw_t *hw); 1562 1563 void sys_hal_set_cpu1_int_0_31_en_cpu1_uart1_int_en(sys_hw_t *hw, uint32_t value); 1564 1565 /* REG_0x22:cpu1_int_0_31_en->cpu1_uart2_int_en: ,R/W,0x22[16]*/ 1566 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_uart2_int_en(sys_hw_t *hw); 1567 1568 void sys_hal_set_cpu1_int_0_31_en_cpu1_uart2_int_en(sys_hw_t *hw, uint32_t value); 1569 1570 /* REG_0x22:cpu1_int_0_31_en->cpu1_spi1_int_en: ,R/W,0x22[17]*/ 1571 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_spi1_int_en(sys_hw_t *hw); 1572 1573 void sys_hal_set_cpu1_int_0_31_en_cpu1_spi1_int_en(sys_hw_t *hw, uint32_t value); 1574 1575 /* REG_0x22:cpu1_int_0_31_en->cpu1_can_int_en: ,R/W,0x22[18]*/ 1576 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_can_int_en(sys_hw_t *hw); 1577 1578 void sys_hal_set_cpu1_int_0_31_en_cpu1_can_int_en(sys_hw_t *hw, uint32_t value); 1579 1580 /* REG_0x22:cpu1_int_0_31_en->cpu1_usb_int_en: ,R/W,0x22[19]*/ 1581 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_usb_int_en(sys_hw_t *hw); 1582 1583 void sys_hal_set_cpu1_int_0_31_en_cpu1_usb_int_en(sys_hw_t *hw, uint32_t value); 1584 1585 /* REG_0x22:cpu1_int_0_31_en->cpu1_qspi_int_en: ,R/W,0x22[20]*/ 1586 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_qspi_int_en(sys_hw_t *hw); 1587 1588 void sys_hal_set_cpu1_int_0_31_en_cpu1_qspi_int_en(sys_hw_t *hw, uint32_t value); 1589 1590 /* REG_0x22:cpu1_int_0_31_en->cpu1_fft_int_en: ,R/W,0x22[21]*/ 1591 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_fft_int_en(sys_hw_t *hw); 1592 1593 void sys_hal_set_cpu1_int_0_31_en_cpu1_fft_int_en(sys_hw_t *hw, uint32_t value); 1594 1595 /* REG_0x22:cpu1_int_0_31_en->cpu1_sbc_int_en: ,R/W,0x22[22]*/ 1596 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_sbc_int_en(sys_hw_t *hw); 1597 1598 void sys_hal_set_cpu1_int_0_31_en_cpu1_sbc_int_en(sys_hw_t *hw, uint32_t value); 1599 1600 /* REG_0x22:cpu1_int_0_31_en->cpu1_aud_int_en: ,R/W,0x22[23]*/ 1601 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_aud_int_en(sys_hw_t *hw); 1602 1603 void sys_hal_set_cpu1_int_0_31_en_cpu1_aud_int_en(sys_hw_t *hw, uint32_t value); 1604 1605 /* REG_0x22:cpu1_int_0_31_en->cpu1_i2s_int_en: ,R/W,0x22[24]*/ 1606 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_i2s_int_en(sys_hw_t *hw); 1607 1608 void sys_hal_set_cpu1_int_0_31_en_cpu1_i2s_int_en(sys_hw_t *hw, uint32_t value); 1609 1610 /* REG_0x22:cpu1_int_0_31_en->cpu1_jpegenc_int_en: ,R/W,0x22[25]*/ 1611 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_jpegenc_int_en(sys_hw_t *hw); 1612 1613 void sys_hal_set_cpu1_int_0_31_en_cpu1_jpegenc_int_en(sys_hw_t *hw, uint32_t value); 1614 1615 /* REG_0x22:cpu1_int_0_31_en->cpu1_jpegdec_int_en: ,R/W,0x22[26]*/ 1616 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_jpegdec_int_en(sys_hw_t *hw); 1617 1618 void sys_hal_set_cpu1_int_0_31_en_cpu1_jpegdec_int_en(sys_hw_t *hw, uint32_t value); 1619 1620 /* REG_0x22:cpu1_int_0_31_en->cpu1_lcd_int_en: ,R/W,0x22[27]*/ 1621 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_lcd_int_en(sys_hw_t *hw); 1622 1623 void sys_hal_set_cpu1_int_0_31_en_cpu1_lcd_int_en(sys_hw_t *hw, uint32_t value); 1624 1625 /* REG_0x22:cpu1_int_0_31_en->cpu1_wifi_int_phy_en: ,R/W,0x22[29]*/ 1626 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_wifi_int_phy_en(sys_hw_t *hw); 1627 1628 void sys_hal_set_cpu1_int_0_31_en_cpu1_wifi_int_phy_en(sys_hw_t *hw, uint32_t value); 1629 1630 /* REG_0x22:cpu1_int_0_31_en->cpu1_wifi_mac_int_tx_rx_timer_en: ,R/W,0x22[30]*/ 1631 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_wifi_mac_int_tx_rx_timer_en(sys_hw_t *hw); 1632 1633 void sys_hal_set_cpu1_int_0_31_en_cpu1_wifi_mac_int_tx_rx_timer_en(sys_hw_t *hw, uint32_t value); 1634 1635 /* REG_0x22:cpu1_int_0_31_en->cpu1_wifi_mac_int_tx_rx_misc_en: ,R/W,0x22[31]*/ 1636 uint32_t sys_hal_get_cpu1_int_0_31_en_cpu1_wifi_mac_int_tx_rx_misc_en(sys_hw_t *hw); 1637 1638 void sys_hal_set_cpu1_int_0_31_en_cpu1_wifi_mac_int_tx_rx_misc_en(sys_hw_t *hw, uint32_t value); 1639 1640 /* REG_0x23 */ 1641 1642 uint32_t sys_hal_get_cpu1_int_32_63_en_value(sys_hw_t *hw); 1643 1644 void sys_hal_set_cpu1_int_32_63_en_value(sys_hw_t *hw, uint32_t value); 1645 1646 /* REG_0x23:cpu1_int_32_63_en->cpu1_wifi_mac_int_rx_trigger_en: ,R/W,0x23[0]*/ 1647 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_wifi_mac_int_rx_trigger_en(sys_hw_t *hw); 1648 1649 void sys_hal_set_cpu1_int_32_63_en_cpu1_wifi_mac_int_rx_trigger_en(sys_hw_t *hw, uint32_t value); 1650 1651 /* REG_0x23:cpu1_int_32_63_en->cpu1_wifi_mac_int_tx_trigger_en: ,R/W,0x23[1]*/ 1652 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_wifi_mac_int_tx_trigger_en(sys_hw_t *hw); 1653 1654 void sys_hal_set_cpu1_int_32_63_en_cpu1_wifi_mac_int_tx_trigger_en(sys_hw_t *hw, uint32_t value); 1655 1656 /* REG_0x23:cpu1_int_32_63_en->cpu1_wifi_mac_port_trigger_en: ,R/W,0x23[2]*/ 1657 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_wifi_mac_port_trigger_en(sys_hw_t *hw); 1658 1659 void sys_hal_set_cpu1_int_32_63_en_cpu1_wifi_mac_port_trigger_en(sys_hw_t *hw, uint32_t value); 1660 1661 /* REG_0x23:cpu1_int_32_63_en->cpu1_wifi_mac_int_gen_en: ,R/W,0x23[3]*/ 1662 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_wifi_mac_int_gen_en(sys_hw_t *hw); 1663 1664 void sys_hal_set_cpu1_int_32_63_en_cpu1_wifi_mac_int_gen_en(sys_hw_t *hw, uint32_t value); 1665 1666 /* REG_0x23:cpu1_int_32_63_en->cpu1_wifi_hsu_irq_en: ,R/W,0x23[4]*/ 1667 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_wifi_hsu_irq_en(sys_hw_t *hw); 1668 1669 void sys_hal_set_cpu1_int_32_63_en_cpu1_wifi_hsu_irq_en(sys_hw_t *hw, uint32_t value); 1670 1671 /* REG_0x23:cpu1_int_32_63_en->cpu1_wifi_int_mac_wakeup_en: ,R/W,0x23[5]*/ 1672 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_wifi_int_mac_wakeup_en(sys_hw_t *hw); 1673 1674 void sys_hal_set_cpu1_int_32_63_en_cpu1_wifi_int_mac_wakeup_en(sys_hw_t *hw, uint32_t value); 1675 1676 /* REG_0x23:cpu1_int_32_63_en->cpu1_dm_irq_en: ,R/W,0x23[7]*/ 1677 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_dm_irq_en(sys_hw_t *hw); 1678 1679 void sys_hal_set_cpu1_int_32_63_en_cpu1_dm_irq_en(sys_hw_t *hw, uint32_t value); 1680 1681 /* REG_0x23:cpu1_int_32_63_en->cpu1_ble_irq_en: ,R/W,0x23[8]*/ 1682 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_ble_irq_en(sys_hw_t *hw); 1683 1684 void sys_hal_set_cpu1_int_32_63_en_cpu1_ble_irq_en(sys_hw_t *hw, uint32_t value); 1685 1686 /* REG_0x23:cpu1_int_32_63_en->cpu1_bt_irq_en: ,R/W,0x23[9]*/ 1687 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_bt_irq_en(sys_hw_t *hw); 1688 1689 void sys_hal_set_cpu1_int_32_63_en_cpu1_bt_irq_en(sys_hw_t *hw, uint32_t value); 1690 1691 /* REG_0x23:cpu1_int_32_63_en->cpu1_mbox0_int_en: ,R/W,0x23[15]*/ 1692 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_mbox0_int_en(sys_hw_t *hw); 1693 1694 void sys_hal_set_cpu1_int_32_63_en_cpu1_mbox0_int_en(sys_hw_t *hw, uint32_t value); 1695 1696 /* REG_0x23:cpu1_int_32_63_en->cpu1_mbox1_int_en: ,R/W,0x23[16]*/ 1697 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_mbox1_int_en(sys_hw_t *hw); 1698 1699 void sys_hal_set_cpu1_int_32_63_en_cpu1_mbox1_int_en(sys_hw_t *hw, uint32_t value); 1700 1701 /* REG_0x23:cpu1_int_32_63_en->cpu1_bmc64_int_en: ,R/W,0x23[17]*/ 1702 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_bmc64_int_en(sys_hw_t *hw); 1703 1704 void sys_hal_set_cpu1_int_32_63_en_cpu1_bmc64_int_en(sys_hw_t *hw, uint32_t value); 1705 1706 /* REG_0x23:cpu1_int_32_63_en->cpu1_touched_int_en: ,R/W,0x23[19]*/ 1707 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_touched_int_en(sys_hw_t *hw); 1708 1709 void sys_hal_set_cpu1_int_32_63_en_cpu1_touched_int_en(sys_hw_t *hw, uint32_t value); 1710 1711 /* REG_0x23:cpu1_int_32_63_en->cpu1_usbplug_int_en: ,R/W,0x23[20]*/ 1712 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_usbplug_int_en(sys_hw_t *hw); 1713 1714 void sys_hal_set_cpu1_int_32_63_en_cpu1_usbplug_int_en(sys_hw_t *hw, uint32_t value); 1715 1716 /* REG_0x23:cpu1_int_32_63_en->cpu1_rtc_int_en: ,R/W,0x23[21]*/ 1717 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_rtc_int_en(sys_hw_t *hw); 1718 1719 void sys_hal_set_cpu1_int_32_63_en_cpu1_rtc_int_en(sys_hw_t *hw, uint32_t value); 1720 1721 /* REG_0x23:cpu1_int_32_63_en->cpu1_gpio_int_en: ,R/W,0x23[22]*/ 1722 uint32_t sys_hal_get_cpu1_int_32_63_en_cpu1_gpio_int_en(sys_hw_t *hw); 1723 1724 void sys_hal_set_cpu1_int_32_63_en_cpu1_gpio_int_en(sys_hw_t *hw, uint32_t value); 1725 1726 /* REG_0x28 */ 1727 1728 uint32_t sys_hal_get_cpu0_int_0_31_status_value(sys_hw_t *hw); 1729 1730 /* REG_0x28:cpu0_int_0_31_status->cpu0_bmc32_int_st: ,R,0x28[0]*/ 1731 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_bmc32_int_st(sys_hw_t *hw); 1732 1733 /* REG_0x28:cpu0_int_0_31_status->cpu0_host_0_irq_st: ,R,0x28[1]*/ 1734 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_host_0_irq_st(sys_hw_t *hw); 1735 1736 /* REG_0x28:cpu0_int_0_31_status->cpu0_host_0_sec_irq_st: ,R,0x28[2]*/ 1737 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_host_0_sec_irq_st(sys_hw_t *hw); 1738 1739 /* REG_0x28:cpu0_int_0_31_status->cpu0_timer_int_st: ,R,0x28[3]*/ 1740 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_timer_int_st(sys_hw_t *hw); 1741 1742 /* REG_0x28:cpu0_int_0_31_status->cpu0_uart_int_st: ,R,0x28[4]*/ 1743 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_uart_int_st(sys_hw_t *hw); 1744 1745 /* REG_0x28:cpu0_int_0_31_status->cpu0_pwm_int_st: ,R,0x28[5]*/ 1746 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_pwm_int_st(sys_hw_t *hw); 1747 1748 /* REG_0x28:cpu0_int_0_31_status->cpu0_i2c_int_st: ,R,0x28[6]*/ 1749 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_i2c_int_st(sys_hw_t *hw); 1750 1751 /* REG_0x28:cpu0_int_0_31_status->cpu0_spi_int_st: ,R,0x28[7]*/ 1752 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_spi_int_st(sys_hw_t *hw); 1753 1754 /* REG_0x28:cpu0_int_0_31_status->cpu0_sadc_int_st: ,R,0x28[8]*/ 1755 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_sadc_int_st(sys_hw_t *hw); 1756 1757 /* REG_0x28:cpu0_int_0_31_status->cpu0_irda_int_st: ,R,0x28[9]*/ 1758 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_irda_int_st(sys_hw_t *hw); 1759 1760 /* REG_0x28:cpu0_int_0_31_status->cpu0_sdio_int_st: ,R,0x28[10]*/ 1761 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_sdio_int_st(sys_hw_t *hw); 1762 1763 /* REG_0x28:cpu0_int_0_31_status->cpu0_gdma_int_st: ,R,0x28[11]*/ 1764 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_gdma_int_st(sys_hw_t *hw); 1765 1766 /* REG_0x28:cpu0_int_0_31_status->cpu0_la_int_st: ,R,0x28[12]*/ 1767 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_la_int_st(sys_hw_t *hw); 1768 1769 /* REG_0x28:cpu0_int_0_31_status->cpu0_timer1_int_st: ,R,0x28[13]*/ 1770 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_timer1_int_st(sys_hw_t *hw); 1771 1772 /* REG_0x28:cpu0_int_0_31_status->cpu0_i2c1_int_st: ,R,0x28[14]*/ 1773 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_i2c1_int_st(sys_hw_t *hw); 1774 1775 /* REG_0x28:cpu0_int_0_31_status->cpu0_uart1_int_st: ,R,0x28[15]*/ 1776 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_uart1_int_st(sys_hw_t *hw); 1777 1778 /* REG_0x28:cpu0_int_0_31_status->cpu0_uart2_int_st: ,R,0x28[16]*/ 1779 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_uart2_int_st(sys_hw_t *hw); 1780 1781 /* REG_0x28:cpu0_int_0_31_status->cpu0_spi1_int_st: ,R,0x28[17]*/ 1782 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_spi1_int_st(sys_hw_t *hw); 1783 1784 /* REG_0x28:cpu0_int_0_31_status->cpu0_can_int_st: ,R,0x28[18]*/ 1785 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_can_int_st(sys_hw_t *hw); 1786 1787 /* REG_0x28:cpu0_int_0_31_status->cpu0_usb_int_st: ,R,0x28[19]*/ 1788 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_usb_int_st(sys_hw_t *hw); 1789 1790 /* REG_0x28:cpu0_int_0_31_status->cpu0_qspi_int_st: ,R,0x28[20]*/ 1791 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_qspi_int_st(sys_hw_t *hw); 1792 1793 /* REG_0x28:cpu0_int_0_31_status->cpu0_fft_int_st: ,R,0x28[21]*/ 1794 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_fft_int_st(sys_hw_t *hw); 1795 1796 /* REG_0x28:cpu0_int_0_31_status->cpu0_sbc_int_st: ,R,0x28[22]*/ 1797 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_sbc_int_st(sys_hw_t *hw); 1798 1799 /* REG_0x28:cpu0_int_0_31_status->cpu0_aud_int_st: ,R,0x28[23]*/ 1800 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_aud_int_st(sys_hw_t *hw); 1801 1802 /* REG_0x28:cpu0_int_0_31_status->cpu0_i2s_int_st: ,R,0x28[24]*/ 1803 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_i2s_int_st(sys_hw_t *hw); 1804 1805 /* REG_0x28:cpu0_int_0_31_status->cpu0_jpegenc_int_st: ,R,0x28[25]*/ 1806 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_jpegenc_int_st(sys_hw_t *hw); 1807 1808 /* REG_0x28:cpu0_int_0_31_status->cpu0_jpegdec_int_st: ,R,0x28[26]*/ 1809 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_jpegdec_int_st(sys_hw_t *hw); 1810 1811 /* REG_0x28:cpu0_int_0_31_status->cpu0_lcd_int_st: ,R,0x28[27]*/ 1812 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_lcd_int_st(sys_hw_t *hw); 1813 1814 /* REG_0x28:cpu0_int_0_31_status->cpu0_wifi_int_phy_st: ,R,0x28[29]*/ 1815 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_wifi_int_phy_st(sys_hw_t *hw); 1816 1817 /* REG_0x28:cpu0_int_0_31_status->cpu0_wifi_mac_int_tx_rx_timer_st: ,R,0x28[30]*/ 1818 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_wifi_mac_int_tx_rx_timer_st(sys_hw_t *hw); 1819 1820 /* REG_0x28:cpu0_int_0_31_status->cpu0_wifi_mac_int_tx_rx_misc_st: ,R,0x28[31]*/ 1821 uint32_t sys_hal_get_cpu0_int_0_31_status_cpu0_wifi_mac_int_tx_rx_misc_st(sys_hw_t *hw); 1822 1823 /* REG_0x29 */ 1824 1825 uint32_t sys_hal_get_cpu0_int_32_63_status_value(sys_hw_t *hw); 1826 1827 /* REG_0x29:cpu0_int_32_63_status->cpu0_wifi_mac_int_rx_trigger_st: ,R,0x29[0]*/ 1828 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_wifi_mac_int_rx_trigger_st(sys_hw_t *hw); 1829 1830 /* REG_0x29:cpu0_int_32_63_status->cpu0_wifi_mac_int_tx_trigger_st: ,R,0x29[1]*/ 1831 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_wifi_mac_int_tx_trigger_st(sys_hw_t *hw); 1832 1833 /* REG_0x29:cpu0_int_32_63_status->cpu0_wifi_mac_port_trigger_st: ,R,0x29[2]*/ 1834 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_wifi_mac_port_trigger_st(sys_hw_t *hw); 1835 1836 /* REG_0x29:cpu0_int_32_63_status->cpu0_wifi_mac_int_gen_st: ,R,0x29[3]*/ 1837 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_wifi_mac_int_gen_st(sys_hw_t *hw); 1838 1839 /* REG_0x29:cpu0_int_32_63_status->cpu0_wifi_hsu_irq_st: ,R,0x29[4]*/ 1840 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_wifi_hsu_irq_st(sys_hw_t *hw); 1841 1842 /* REG_0x29:cpu0_int_32_63_status->cpu0_wifi_int_mac_wakeup_st: ,R,0x29[5]*/ 1843 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_wifi_int_mac_wakeup_st(sys_hw_t *hw); 1844 1845 /* REG_0x29:cpu0_int_32_63_status->cpu0_dm_irq_st: ,R,0x29[7]*/ 1846 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_dm_irq_st(sys_hw_t *hw); 1847 1848 /* REG_0x29:cpu0_int_32_63_status->cpu0_ble_irq_st: ,R,0x29[8]*/ 1849 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_ble_irq_st(sys_hw_t *hw); 1850 1851 /* REG_0x29:cpu0_int_32_63_status->cpu0_bt_irq_st: ,R,0x29[9]*/ 1852 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_bt_irq_st(sys_hw_t *hw); 1853 1854 /* REG_0x29:cpu0_int_32_63_status->cpu0_mbox0_int_st: ,R,0x29[15]*/ 1855 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_mbox0_int_st(sys_hw_t *hw); 1856 1857 /* REG_0x29:cpu0_int_32_63_status->cpu0_mbox1_int_st: ,R,0x29[16]*/ 1858 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_mbox1_int_st(sys_hw_t *hw); 1859 1860 /* REG_0x29:cpu0_int_32_63_status->cpu0_bmc64_int_st: ,R,0x29[17]*/ 1861 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_bmc64_int_st(sys_hw_t *hw); 1862 1863 /* REG_0x29:cpu0_int_32_63_status->cpu0_touched_int_st: ,R,0x29[19]*/ 1864 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_touched_int_st(sys_hw_t *hw); 1865 1866 /* REG_0x29:cpu0_int_32_63_status->cpu0_usbplug_int_st: ,R,0x29[20]*/ 1867 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_usbplug_int_st(sys_hw_t *hw); 1868 1869 /* REG_0x29:cpu0_int_32_63_status->cpu0_rtc_int_st: ,R,0x29[21]*/ 1870 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_rtc_int_st(sys_hw_t *hw); 1871 1872 /* REG_0x29:cpu0_int_32_63_status->cpu0_gpio_int_st: ,R,0x29[22]*/ 1873 uint32_t sys_hal_get_cpu0_int_32_63_status_cpu0_gpio_int_st(sys_hw_t *hw); 1874 1875 /* REG_0x2a */ 1876 1877 uint32_t sys_hal_get_cpu1_int_0_31_status_value(sys_hw_t *hw); 1878 1879 /* REG_0x2a:cpu1_int_0_31_status->cpu1_bmc32_int_st: ,R,0x2a[0]*/ 1880 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_bmc32_int_st(sys_hw_t *hw); 1881 1882 /* REG_0x2a:cpu1_int_0_31_status->cpu1_host_0_irq_st: ,R,0x2a[1]*/ 1883 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_host_0_irq_st(sys_hw_t *hw); 1884 1885 /* REG_0x2a:cpu1_int_0_31_status->cpu1_host_0_sec_irq_st: ,R,0x2a[2]*/ 1886 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_host_0_sec_irq_st(sys_hw_t *hw); 1887 1888 /* REG_0x2a:cpu1_int_0_31_status->cpu1_timer_int_st: ,R,0x2a[3]*/ 1889 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_timer_int_st(sys_hw_t *hw); 1890 1891 /* REG_0x2a:cpu1_int_0_31_status->cpu1_uart_int_st: ,R,0x2a[4]*/ 1892 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_uart_int_st(sys_hw_t *hw); 1893 1894 /* REG_0x2a:cpu1_int_0_31_status->cpu1_pwm_int_st: ,R,0x2a[5]*/ 1895 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_pwm_int_st(sys_hw_t *hw); 1896 1897 /* REG_0x2a:cpu1_int_0_31_status->cpu1_i2c_int_st: ,R,0x2a[6]*/ 1898 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_i2c_int_st(sys_hw_t *hw); 1899 1900 /* REG_0x2a:cpu1_int_0_31_status->cpu1_spi_int_st: ,R,0x2a[7]*/ 1901 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_spi_int_st(sys_hw_t *hw); 1902 1903 /* REG_0x2a:cpu1_int_0_31_status->cpu1_sadc_int_st: ,R,0x2a[8]*/ 1904 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_sadc_int_st(sys_hw_t *hw); 1905 1906 /* REG_0x2a:cpu1_int_0_31_status->cpu1_irda_int_st: ,R,0x2a[9]*/ 1907 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_irda_int_st(sys_hw_t *hw); 1908 1909 /* REG_0x2a:cpu1_int_0_31_status->cpu1_sdio_int_st: ,R,0x2a[10]*/ 1910 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_sdio_int_st(sys_hw_t *hw); 1911 1912 /* REG_0x2a:cpu1_int_0_31_status->cpu1_gdma_int_st: ,R,0x2a[11]*/ 1913 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_gdma_int_st(sys_hw_t *hw); 1914 1915 /* REG_0x2a:cpu1_int_0_31_status->cpu1_la_int_st: ,R,0x2a[12]*/ 1916 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_la_int_st(sys_hw_t *hw); 1917 1918 /* REG_0x2a:cpu1_int_0_31_status->cpu1_timer1_int_st: ,R,0x2a[13]*/ 1919 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_timer1_int_st(sys_hw_t *hw); 1920 1921 /* REG_0x2a:cpu1_int_0_31_status->cpu1_i2c1_int_st: ,R,0x2a[14]*/ 1922 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_i2c1_int_st(sys_hw_t *hw); 1923 1924 /* REG_0x2a:cpu1_int_0_31_status->cpu1_uart1_int_st: ,R,0x2a[15]*/ 1925 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_uart1_int_st(sys_hw_t *hw); 1926 1927 /* REG_0x2a:cpu1_int_0_31_status->cpu1_uart2_int_st: ,R,0x2a[16]*/ 1928 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_uart2_int_st(sys_hw_t *hw); 1929 1930 /* REG_0x2a:cpu1_int_0_31_status->cpu1_spi1_int_st: ,R,0x2a[17]*/ 1931 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_spi1_int_st(sys_hw_t *hw); 1932 1933 /* REG_0x2a:cpu1_int_0_31_status->cpu1_can_int_st: ,R,0x2a[18]*/ 1934 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_can_int_st(sys_hw_t *hw); 1935 1936 /* REG_0x2a:cpu1_int_0_31_status->cpu1_usb_int_st: ,R,0x2a[19]*/ 1937 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_usb_int_st(sys_hw_t *hw); 1938 1939 /* REG_0x2a:cpu1_int_0_31_status->cpu1_qspi_int_st: ,R,0x2a[20]*/ 1940 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_qspi_int_st(sys_hw_t *hw); 1941 1942 /* REG_0x2a:cpu1_int_0_31_status->cpu1_fft_int_st: ,R,0x2a[21]*/ 1943 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_fft_int_st(sys_hw_t *hw); 1944 1945 /* REG_0x2a:cpu1_int_0_31_status->cpu1_sbc_int_st: ,R,0x2a[22]*/ 1946 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_sbc_int_st(sys_hw_t *hw); 1947 1948 /* REG_0x2a:cpu1_int_0_31_status->cpu1_aud_int_st: ,R,0x2a[23]*/ 1949 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_aud_int_st(sys_hw_t *hw); 1950 1951 /* REG_0x2a:cpu1_int_0_31_status->cpu1_i2s_int_st: ,R,0x2a[24]*/ 1952 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_i2s_int_st(sys_hw_t *hw); 1953 1954 /* REG_0x2a:cpu1_int_0_31_status->cpu1_jpegenc_int_st: ,R,0x2a[25]*/ 1955 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_jpegenc_int_st(sys_hw_t *hw); 1956 1957 /* REG_0x2a:cpu1_int_0_31_status->cpu1_jpegdec_int_st: ,R,0x2a[26]*/ 1958 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_jpegdec_int_st(sys_hw_t *hw); 1959 1960 /* REG_0x2a:cpu1_int_0_31_status->cpu1_lcd_int_st: ,R,0x2a[27]*/ 1961 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_lcd_int_st(sys_hw_t *hw); 1962 1963 /* REG_0x2a:cpu1_int_0_31_status->cpu1_wifi_int_phy_st: ,R,0x2a[29]*/ 1964 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_wifi_int_phy_st(sys_hw_t *hw); 1965 1966 /* REG_0x2a:cpu1_int_0_31_status->cpu1_wifi_mac_int_tx_rx_timer_st: ,R,0x2a[30]*/ 1967 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_wifi_mac_int_tx_rx_timer_st(sys_hw_t *hw); 1968 1969 /* REG_0x2a:cpu1_int_0_31_status->cpu1_wifi_mac_int_tx_rx_misc_st: ,R,0x2a[31]*/ 1970 uint32_t sys_hal_get_cpu1_int_0_31_status_cpu1_wifi_mac_int_tx_rx_misc_st(sys_hw_t *hw); 1971 1972 /* REG_0x2b */ 1973 1974 uint32_t sys_hal_get_cpu1_int_32_63_status_value(sys_hw_t *hw); 1975 1976 /* REG_0x2b:cpu1_int_32_63_status->cpu1_wifi_mac_int_rx_trigger_st: ,R,0x2b[0]*/ 1977 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_wifi_mac_int_rx_trigger_st(sys_hw_t *hw); 1978 1979 /* REG_0x2b:cpu1_int_32_63_status->cpu1_wifi_mac_int_tx_trigger_st: ,R,0x2b[1]*/ 1980 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_wifi_mac_int_tx_trigger_st(sys_hw_t *hw); 1981 1982 /* REG_0x2b:cpu1_int_32_63_status->cpu1_wifi_mac_port_trigger_st: ,R,0x2b[2]*/ 1983 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_wifi_mac_port_trigger_st(sys_hw_t *hw); 1984 1985 /* REG_0x2b:cpu1_int_32_63_status->cpu1_wifi_mac_int_gen_st: ,R,0x2b[3]*/ 1986 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_wifi_mac_int_gen_st(sys_hw_t *hw); 1987 1988 /* REG_0x2b:cpu1_int_32_63_status->cpu1_wifi_hsu_irq_st: ,R,0x2b[4]*/ 1989 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_wifi_hsu_irq_st(sys_hw_t *hw); 1990 1991 /* REG_0x2b:cpu1_int_32_63_status->cpu1_wifi_int_mac_wakeup_st: ,R,0x2b[5]*/ 1992 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_wifi_int_mac_wakeup_st(sys_hw_t *hw); 1993 1994 /* REG_0x2b:cpu1_int_32_63_status->cpu1_dm_irq_st: ,R,0x2b[7]*/ 1995 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_dm_irq_st(sys_hw_t *hw); 1996 1997 /* REG_0x2b:cpu1_int_32_63_status->cpu1_ble_irq_st: ,R,0x2b[8]*/ 1998 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_ble_irq_st(sys_hw_t *hw); 1999 2000 /* REG_0x2b:cpu1_int_32_63_status->cpu1_bt_irq_st: ,R,0x2b[9]*/ 2001 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_bt_irq_st(sys_hw_t *hw); 2002 2003 /* REG_0x2b:cpu1_int_32_63_status->cpu1_mbox0_int_st: ,R,0x2b[15]*/ 2004 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_mbox0_int_st(sys_hw_t *hw); 2005 2006 /* REG_0x2b:cpu1_int_32_63_status->cpu1_mbox1_int_st: ,R,0x2b[16]*/ 2007 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_mbox1_int_st(sys_hw_t *hw); 2008 2009 /* REG_0x2b:cpu1_int_32_63_status->cpu1_bmc64_int_st: ,R,0x2b[17]*/ 2010 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_bmc64_int_st(sys_hw_t *hw); 2011 2012 /* REG_0x2b:cpu1_int_32_63_status->cpu1_touched_int_st: ,R,0x2b[19]*/ 2013 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_touched_int_st(sys_hw_t *hw); 2014 2015 /* REG_0x2b:cpu1_int_32_63_status->cpu1_usbplug_int_st: ,R,0x2b[20]*/ 2016 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_usbplug_int_st(sys_hw_t *hw); 2017 2018 /* REG_0x2b:cpu1_int_32_63_status->cpu1_rtc_int_st: ,R,0x2b[21]*/ 2019 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_rtc_int_st(sys_hw_t *hw); 2020 2021 /* REG_0x2b:cpu1_int_32_63_status->cpu1_gpio_int_st: ,R,0x2b[22]*/ 2022 uint32_t sys_hal_get_cpu1_int_32_63_status_cpu1_gpio_int_st(sys_hw_t *hw); 2023 2024 /* REG_0x30 */ 2025 2026 uint32_t sys_hal_get_gpio_config0_value(sys_hw_t *hw); 2027 2028 void sys_hal_set_gpio_config0_value(sys_hw_t *hw, uint32_t value); 2029 2030 /* REG_0x30:gpio_config0->sys_gpio0:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x30[3:0]*/ 2031 uint32_t sys_hal_get_gpio_config0_sys_gpio0(sys_hw_t *hw); 2032 2033 void sys_hal_set_gpio_config0_sys_gpio0(sys_hw_t *hw, uint32_t value); 2034 2035 /* REG_0x30:gpio_config0->sys_gpio1:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x30[7:4]*/ 2036 uint32_t sys_hal_get_gpio_config0_sys_gpio1(sys_hw_t *hw); 2037 2038 void sys_hal_set_gpio_config0_sys_gpio1(sys_hw_t *hw, uint32_t value); 2039 2040 /* REG_0x30:gpio_config0->sys_gpio2:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x30[11:8]*/ 2041 uint32_t sys_hal_get_gpio_config0_sys_gpio2(sys_hw_t *hw); 2042 2043 void sys_hal_set_gpio_config0_sys_gpio2(sys_hw_t *hw, uint32_t value); 2044 2045 /* REG_0x30:gpio_config0->sys_gpio3:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x30[15:12]*/ 2046 uint32_t sys_hal_get_gpio_config0_sys_gpio3(sys_hw_t *hw); 2047 2048 void sys_hal_set_gpio_config0_sys_gpio3(sys_hw_t *hw, uint32_t value); 2049 2050 /* REG_0x30:gpio_config0->sys_gpio4:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x30[19:16]*/ 2051 uint32_t sys_hal_get_gpio_config0_sys_gpio4(sys_hw_t *hw); 2052 2053 void sys_hal_set_gpio_config0_sys_gpio4(sys_hw_t *hw, uint32_t value); 2054 2055 /* REG_0x30:gpio_config0->sys_gpio5:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x30[23:20]*/ 2056 uint32_t sys_hal_get_gpio_config0_sys_gpio5(sys_hw_t *hw); 2057 2058 void sys_hal_set_gpio_config0_sys_gpio5(sys_hw_t *hw, uint32_t value); 2059 2060 /* REG_0x30:gpio_config0->sys_gpio6:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x30[27:24]*/ 2061 uint32_t sys_hal_get_gpio_config0_sys_gpio6(sys_hw_t *hw); 2062 2063 void sys_hal_set_gpio_config0_sys_gpio6(sys_hw_t *hw, uint32_t value); 2064 2065 /* REG_0x30:gpio_config0->sys_gpio7:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x30[31:28]*/ 2066 uint32_t sys_hal_get_gpio_config0_sys_gpio7(sys_hw_t *hw); 2067 2068 void sys_hal_set_gpio_config0_sys_gpio7(sys_hw_t *hw, uint32_t value); 2069 2070 /* REG_0x31 */ 2071 2072 uint32_t sys_hal_get_gpio_config1_value(sys_hw_t *hw); 2073 2074 void sys_hal_set_gpio_config1_value(sys_hw_t *hw, uint32_t value); 2075 2076 /* REG_0x31:gpio_config1->sys_gpio8:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x31[3:0]*/ 2077 uint32_t sys_hal_get_gpio_config1_sys_gpio8(sys_hw_t *hw); 2078 2079 void sys_hal_set_gpio_config1_sys_gpio8(sys_hw_t *hw, uint32_t value); 2080 2081 /* REG_0x31:gpio_config1->sys_gpio9:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x31[7:4]*/ 2082 uint32_t sys_hal_get_gpio_config1_sys_gpio9(sys_hw_t *hw); 2083 2084 void sys_hal_set_gpio_config1_sys_gpio9(sys_hw_t *hw, uint32_t value); 2085 2086 /* REG_0x31:gpio_config1->sys_gpio10:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x31[11:8]*/ 2087 uint32_t sys_hal_get_gpio_config1_sys_gpio10(sys_hw_t *hw); 2088 2089 void sys_hal_set_gpio_config1_sys_gpio10(sys_hw_t *hw, uint32_t value); 2090 2091 /* REG_0x31:gpio_config1->sys_gpio11:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x31[15:12]*/ 2092 uint32_t sys_hal_get_gpio_config1_sys_gpio11(sys_hw_t *hw); 2093 2094 void sys_hal_set_gpio_config1_sys_gpio11(sys_hw_t *hw, uint32_t value); 2095 2096 /* REG_0x31:gpio_config1->sys_gpio12:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x31[19:16]*/ 2097 uint32_t sys_hal_get_gpio_config1_sys_gpio12(sys_hw_t *hw); 2098 2099 void sys_hal_set_gpio_config1_sys_gpio12(sys_hw_t *hw, uint32_t value); 2100 2101 /* REG_0x31:gpio_config1->sys_gpio13:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x31[23:20]*/ 2102 uint32_t sys_hal_get_gpio_config1_sys_gpio13(sys_hw_t *hw); 2103 2104 void sys_hal_set_gpio_config1_sys_gpio13(sys_hw_t *hw, uint32_t value); 2105 2106 /* REG_0x31:gpio_config1->sys_gpio14:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x31[27:24]*/ 2107 uint32_t sys_hal_get_gpio_config1_sys_gpio14(sys_hw_t *hw); 2108 2109 void sys_hal_set_gpio_config1_sys_gpio14(sys_hw_t *hw, uint32_t value); 2110 2111 /* REG_0x31:gpio_config1->sys_gpio15:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x31[31:28]*/ 2112 uint32_t sys_hal_get_gpio_config1_sys_gpio15(sys_hw_t *hw); 2113 2114 void sys_hal_set_gpio_config1_sys_gpio15(sys_hw_t *hw, uint32_t value); 2115 2116 /* REG_0x32 */ 2117 2118 uint32_t sys_hal_get_gpio_config2_value(sys_hw_t *hw); 2119 2120 void sys_hal_set_gpio_config2_value(sys_hw_t *hw, uint32_t value); 2121 2122 /* REG_0x32:gpio_config2->sys_gpio16:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x32[3:0]*/ 2123 uint32_t sys_hal_get_gpio_config2_sys_gpio16(sys_hw_t *hw); 2124 2125 void sys_hal_set_gpio_config2_sys_gpio16(sys_hw_t *hw, uint32_t value); 2126 2127 /* REG_0x32:gpio_config2->sys_gpio17:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x32[7:4]*/ 2128 uint32_t sys_hal_get_gpio_config2_sys_gpio17(sys_hw_t *hw); 2129 2130 void sys_hal_set_gpio_config2_sys_gpio17(sys_hw_t *hw, uint32_t value); 2131 2132 /* REG_0x32:gpio_config2->sys_gpio18:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x32[11:8]*/ 2133 uint32_t sys_hal_get_gpio_config2_sys_gpio18(sys_hw_t *hw); 2134 2135 void sys_hal_set_gpio_config2_sys_gpio18(sys_hw_t *hw, uint32_t value); 2136 2137 /* REG_0x32:gpio_config2->sys_gpio19:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x32[15:12]*/ 2138 uint32_t sys_hal_get_gpio_config2_sys_gpio19(sys_hw_t *hw); 2139 2140 void sys_hal_set_gpio_config2_sys_gpio19(sys_hw_t *hw, uint32_t value); 2141 2142 /* REG_0x32:gpio_config2->sys_gpio20:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x32[19:16]*/ 2143 uint32_t sys_hal_get_gpio_config2_sys_gpio20(sys_hw_t *hw); 2144 2145 void sys_hal_set_gpio_config2_sys_gpio20(sys_hw_t *hw, uint32_t value); 2146 2147 /* REG_0x32:gpio_config2->sys_gpio21:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x32[23:20]*/ 2148 uint32_t sys_hal_get_gpio_config2_sys_gpio21(sys_hw_t *hw); 2149 2150 void sys_hal_set_gpio_config2_sys_gpio21(sys_hw_t *hw, uint32_t value); 2151 2152 /* REG_0x32:gpio_config2->sys_gpio22:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x32[27:24]*/ 2153 uint32_t sys_hal_get_gpio_config2_sys_gpio22(sys_hw_t *hw); 2154 2155 void sys_hal_set_gpio_config2_sys_gpio22(sys_hw_t *hw, uint32_t value); 2156 2157 /* REG_0x32:gpio_config2->sys_gpio23:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x32[31:28]*/ 2158 uint32_t sys_hal_get_gpio_config2_sys_gpio23(sys_hw_t *hw); 2159 2160 void sys_hal_set_gpio_config2_sys_gpio23(sys_hw_t *hw, uint32_t value); 2161 2162 /* REG_0x33 */ 2163 2164 uint32_t sys_hal_get_gpio_config3_value(sys_hw_t *hw); 2165 2166 void sys_hal_set_gpio_config3_value(sys_hw_t *hw, uint32_t value); 2167 2168 /* REG_0x33:gpio_config3->sys_gpio24:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x33[3:0]*/ 2169 uint32_t sys_hal_get_gpio_config3_sys_gpio24(sys_hw_t *hw); 2170 2171 void sys_hal_set_gpio_config3_sys_gpio24(sys_hw_t *hw, uint32_t value); 2172 2173 /* REG_0x33:gpio_config3->sys_gpio25:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x33[7:4]*/ 2174 uint32_t sys_hal_get_gpio_config3_sys_gpio25(sys_hw_t *hw); 2175 2176 void sys_hal_set_gpio_config3_sys_gpio25(sys_hw_t *hw, uint32_t value); 2177 2178 /* REG_0x33:gpio_config3->sys_gpio26:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x33[11:8]*/ 2179 uint32_t sys_hal_get_gpio_config3_sys_gpio26(sys_hw_t *hw); 2180 2181 void sys_hal_set_gpio_config3_sys_gpio26(sys_hw_t *hw, uint32_t value); 2182 2183 /* REG_0x33:gpio_config3->sys_gpio27:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x33[15:12]*/ 2184 uint32_t sys_hal_get_gpio_config3_sys_gpio27(sys_hw_t *hw); 2185 2186 void sys_hal_set_gpio_config3_sys_gpio27(sys_hw_t *hw, uint32_t value); 2187 2188 /* REG_0x33:gpio_config3->sys_gpio28:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x33[19:16]*/ 2189 uint32_t sys_hal_get_gpio_config3_sys_gpio28(sys_hw_t *hw); 2190 2191 void sys_hal_set_gpio_config3_sys_gpio28(sys_hw_t *hw, uint32_t value); 2192 2193 /* REG_0x33:gpio_config3->sys_gpio29:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x33[23:20]*/ 2194 uint32_t sys_hal_get_gpio_config3_sys_gpio29(sys_hw_t *hw); 2195 2196 void sys_hal_set_gpio_config3_sys_gpio29(sys_hw_t *hw, uint32_t value); 2197 2198 /* REG_0x33:gpio_config3->sys_gpio30:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x33[27:24]*/ 2199 uint32_t sys_hal_get_gpio_config3_sys_gpio30(sys_hw_t *hw); 2200 2201 void sys_hal_set_gpio_config3_sys_gpio30(sys_hw_t *hw, uint32_t value); 2202 2203 /* REG_0x33:gpio_config3->sys_gpio31:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x33[31:28]*/ 2204 uint32_t sys_hal_get_gpio_config3_sys_gpio31(sys_hw_t *hw); 2205 2206 void sys_hal_set_gpio_config3_sys_gpio31(sys_hw_t *hw, uint32_t value); 2207 2208 /* REG_0x34 */ 2209 2210 uint32_t sys_hal_get_gpio_config4_value(sys_hw_t *hw); 2211 2212 void sys_hal_set_gpio_config4_value(sys_hw_t *hw, uint32_t value); 2213 2214 /* REG_0x34:gpio_config4->sys_gpio32:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x34[3:0]*/ 2215 uint32_t sys_hal_get_gpio_config4_sys_gpio32(sys_hw_t *hw); 2216 2217 void sys_hal_set_gpio_config4_sys_gpio32(sys_hw_t *hw, uint32_t value); 2218 2219 /* REG_0x34:gpio_config4->sys_gpio33:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x34[7:4]*/ 2220 uint32_t sys_hal_get_gpio_config4_sys_gpio33(sys_hw_t *hw); 2221 2222 void sys_hal_set_gpio_config4_sys_gpio33(sys_hw_t *hw, uint32_t value); 2223 2224 /* REG_0x34:gpio_config4->sys_gpio34:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x34[11:8]*/ 2225 uint32_t sys_hal_get_gpio_config4_sys_gpio34(sys_hw_t *hw); 2226 2227 void sys_hal_set_gpio_config4_sys_gpio34(sys_hw_t *hw, uint32_t value); 2228 2229 /* REG_0x34:gpio_config4->sys_gpio35:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x34[15:12]*/ 2230 uint32_t sys_hal_get_gpio_config4_sys_gpio35(sys_hw_t *hw); 2231 2232 void sys_hal_set_gpio_config4_sys_gpio35(sys_hw_t *hw, uint32_t value); 2233 2234 /* REG_0x34:gpio_config4->sys_gpio36:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x34[19:16]*/ 2235 uint32_t sys_hal_get_gpio_config4_sys_gpio36(sys_hw_t *hw); 2236 2237 void sys_hal_set_gpio_config4_sys_gpio36(sys_hw_t *hw, uint32_t value); 2238 2239 /* REG_0x34:gpio_config4->sys_gpio37:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x34[23:20]*/ 2240 uint32_t sys_hal_get_gpio_config4_sys_gpio37(sys_hw_t *hw); 2241 2242 void sys_hal_set_gpio_config4_sys_gpio37(sys_hw_t *hw, uint32_t value); 2243 2244 /* REG_0x34:gpio_config4->sys_gpio38:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x34[27:24]*/ 2245 uint32_t sys_hal_get_gpio_config4_sys_gpio38(sys_hw_t *hw); 2246 2247 void sys_hal_set_gpio_config4_sys_gpio38(sys_hw_t *hw, uint32_t value); 2248 2249 /* REG_0x34:gpio_config4->sys_gpio39:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x34[31:28]*/ 2250 uint32_t sys_hal_get_gpio_config4_sys_gpio39(sys_hw_t *hw); 2251 2252 void sys_hal_set_gpio_config4_sys_gpio39(sys_hw_t *hw, uint32_t value); 2253 2254 /* REG_0x35 */ 2255 2256 uint32_t sys_hal_get_gpio_config5_value(sys_hw_t *hw); 2257 2258 void sys_hal_set_gpio_config5_value(sys_hw_t *hw, uint32_t value); 2259 2260 /* REG_0x35:gpio_config5->sys_gpio40:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x35[3:0]*/ 2261 uint32_t sys_hal_get_gpio_config5_sys_gpio40(sys_hw_t *hw); 2262 2263 void sys_hal_set_gpio_config5_sys_gpio40(sys_hw_t *hw, uint32_t value); 2264 2265 /* REG_0x35:gpio_config5->sys_gpio41:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x35[7:4]*/ 2266 uint32_t sys_hal_get_gpio_config5_sys_gpio41(sys_hw_t *hw); 2267 2268 void sys_hal_set_gpio_config5_sys_gpio41(sys_hw_t *hw, uint32_t value); 2269 2270 /* REG_0x35:gpio_config5->sys_gpio42:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x35[11:8]*/ 2271 uint32_t sys_hal_get_gpio_config5_sys_gpio42(sys_hw_t *hw); 2272 2273 void sys_hal_set_gpio_config5_sys_gpio42(sys_hw_t *hw, uint32_t value); 2274 2275 /* REG_0x35:gpio_config5->sys_gpio43:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x35[15:12]*/ 2276 uint32_t sys_hal_get_gpio_config5_sys_gpio43(sys_hw_t *hw); 2277 2278 void sys_hal_set_gpio_config5_sys_gpio43(sys_hw_t *hw, uint32_t value); 2279 2280 /* REG_0x35:gpio_config5->sys_gpio44:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x35[19:16]*/ 2281 uint32_t sys_hal_get_gpio_config5_sys_gpio44(sys_hw_t *hw); 2282 2283 void sys_hal_set_gpio_config5_sys_gpio44(sys_hw_t *hw, uint32_t value); 2284 2285 /* REG_0x35:gpio_config5->sys_gpio45:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x35[23:20]*/ 2286 uint32_t sys_hal_get_gpio_config5_sys_gpio45(sys_hw_t *hw); 2287 2288 void sys_hal_set_gpio_config5_sys_gpio45(sys_hw_t *hw, uint32_t value); 2289 2290 /* REG_0x35:gpio_config5->sys_gpio46:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x35[27:24]*/ 2291 uint32_t sys_hal_get_gpio_config5_sys_gpio46(sys_hw_t *hw); 2292 2293 void sys_hal_set_gpio_config5_sys_gpio46(sys_hw_t *hw, uint32_t value); 2294 2295 /* REG_0x35:gpio_config5->sys_gpio47:0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5,R/W,0x35[31:28]*/ 2296 uint32_t sys_hal_get_gpio_config5_sys_gpio47(sys_hw_t *hw); 2297 2298 void sys_hal_set_gpio_config5_sys_gpio47(sys_hw_t *hw, uint32_t value); 2299 2300 /* REG_0x38 */ 2301 2302 uint32_t sys_hal_get_sys_debug_config0_value(sys_hw_t *hw); 2303 2304 void sys_hal_set_sys_debug_config0_value(sys_hw_t *hw, uint32_t value); 2305 2306 /* REG_0x38:sys_debug_config0->dbug_config0: ,R/W,0x38[31:0]*/ 2307 uint32_t sys_hal_get_sys_debug_config0_dbug_config0(sys_hw_t *hw); 2308 2309 void sys_hal_set_sys_debug_config0_dbug_config0(sys_hw_t *hw, uint32_t value); 2310 2311 /* REG_0x39 */ 2312 2313 uint32_t sys_hal_get_sys_debug_config1_value(sys_hw_t *hw); 2314 2315 void sys_hal_set_sys_debug_config1_value(sys_hw_t *hw, uint32_t value); 2316 2317 /* REG_0x39:sys_debug_config1->dbug_config1:0: btsp_debug[0:32] 1: btsp_debug[32+:32] 2: btsp_debug[64+:32] 4:btsp_debug[96+:6] 5:wifip_mac_dbg[31:0] 6: wifip_phy_dbg[31:0] default: dbug_config0 ,R/W,0x39[31:0]*/ 2318 uint32_t sys_hal_get_sys_debug_config1_dbug_config1(sys_hw_t *hw); 2319 2320 void sys_hal_set_sys_debug_config1_dbug_config1(sys_hw_t *hw, uint32_t value); 2321 2322 /* REG_0x40 */ 2323 2324 void sys_hal_set_ana_reg0_value(sys_hw_t *hw, uint32_t value); 2325 2326 /* REG_0x40:ana_reg0->ck2652sel:1:26MHz/0:52MHz,W,0x40[0]*/ 2327 void sys_hal_set_ana_reg0_ck2652sel(sys_hw_t *hw, uint32_t value); 2328 2329 /* REG_0x40:ana_reg0->cp:cp curent control 0to 350uA 50uA step,W,0x40[3:1]*/ 2330 void sys_hal_set_ana_reg0_cp(sys_hw_t *hw, uint32_t value); 2331 2332 /* REG_0x40:ana_reg0->spideten:unlock detect enable fron spi 1:enable,W,0x40[4]*/ 2333 void sys_hal_set_ana_reg0_spideten(sys_hw_t *hw, uint32_t value); 2334 2335 /* REG_0x40:ana_reg0->hvref:high vth control for unlock detect 00:0.85V;01:0.9V;10:0.95V;11:1.05V,W,0x40[6:5]*/ 2336 void sys_hal_set_ana_reg0_hvref(sys_hw_t *hw, uint32_t value); 2337 2338 /* REG_0x40:ana_reg0->lvref:low vth control for unlock detect 00:0.2V;01:0.3V;10:0.35V;11:0.4V,W,0x40[8:7]*/ 2339 void sys_hal_set_ana_reg0_lvref(sys_hw_t *hw, uint32_t value); 2340 2341 /* REG_0x40:ana_reg0->Rzctrl26M:Rz ctrl in 26M mode:1:normal;0:add 14K,W,0x40[9]*/ 2342 void sys_hal_set_ana_reg0_rzctrl26m(sys_hw_t *hw, uint32_t value); 2343 2344 /* REG_0x40:ana_reg0->LoopRzctrl:Rz ctrl:2K to 17K,1K step,W,0x40[13:10]*/ 2345 void sys_hal_set_ana_reg0_looprzctrl(sys_hw_t *hw, uint32_t value); 2346 2347 /* REG_0x40:ana_reg0->rpc:second pole Rp ctrl:00:30K;01:10K;10:22K;11:2K,W,0x40[15:14]*/ 2348 void sys_hal_set_ana_reg0_rpc(sys_hw_t *hw, uint32_t value); 2349 2350 /* REG_0x40:ana_reg0->nsyn:N divider rst,W,0x40[16]*/ 2351 void sys_hal_set_ana_reg0_nsyn(sys_hw_t *hw, uint32_t value); 2352 2353 /* REG_0x40:ana_reg0->cksel:0:26M;1:40M;2:24M;3:19.2M,W,0x40[18:17]*/ 2354 void sys_hal_set_ana_reg0_cksel(sys_hw_t *hw, uint32_t value); 2355 2356 /* REG_0x40:ana_reg0->spitrig:SPI band selection trigger signal,W,0x40[19]*/ 2357 void sys_hal_set_ana_reg0_spitrig(sys_hw_t *hw, uint32_t value); 2358 2359 /* REG_0x40:ana_reg0->band:band manual value/band[0] ,W,0x40[24:20]*/ 2360 void sys_hal_set_ana_reg0_band(sys_hw_t *hw, uint32_t value); 2361 2362 /* REG_0x40:ana_reg0->bandmanual:1:band manual;0:band auto,W,0x40[25]*/ 2363 void sys_hal_set_ana_reg0_bandmanual(sys_hw_t *hw, uint32_t value); 2364 2365 /* REG_0x40:ana_reg0->dsptrig:band selection trigger signal,W,0x40[26]*/ 2366 void sys_hal_set_ana_reg0_dsptrig(sys_hw_t *hw, uint32_t value); 2367 2368 /* REG_0x40:ana_reg0->lpen_dpll:dpll low power mode enable,W,0x40[27]*/ 2369 void sys_hal_set_ana_reg0_lpen_dpll(sys_hw_t *hw, uint32_t value); 2370 2371 /* REG_0x40:ana_reg0->xamp:xtal OSC amp control/xamp<0> shared with pll_cktst_en,W,0x40[31:28]*/ 2372 void sys_hal_set_ana_reg0_xamp(sys_hw_t *hw, uint32_t value); 2373 2374 /* REG_0x41 */ 2375 2376 void sys_hal_set_ana_reg1_value(sys_hw_t *hw, uint32_t value); 2377 2378 /* REG_0x41:ana_reg1->dpll_vrefsel:dpll ldo reference voltage selection 0:vbg_aon/1:vbg_cal,W,0x41[1]*/ 2379 void sys_hal_set_ana_reg1_dpll_vrefsel(sys_hw_t *hw, uint32_t value); 2380 2381 /* REG_0x41:ana_reg1->msw:set the frequency of DCO manual,W,0x41[10:2]*/ 2382 void sys_hal_set_ana_reg1_msw(sys_hw_t *hw, uint32_t value); 2383 2384 /* REG_0x41:ana_reg1->ictrl:controlling the bias cuttent of DCO core,W,0x41[13:11]*/ 2385 void sys_hal_set_ana_reg1_ictrl(sys_hw_t *hw, uint32_t value); 2386 2387 /* REG_0x41:ana_reg1->osc_trig:reset the DCO core by spi to make it oscillate again,W,0x41[14]*/ 2388 void sys_hal_set_ana_reg1_osc_trig(sys_hw_t *hw, uint32_t value); 2389 2390 /* REG_0x41:ana_reg1->osccal_trig:trigger the action of callibration in the DCO,W,0x41[15]*/ 2391 void sys_hal_set_ana_reg1_osccal_trig(sys_hw_t *hw, uint32_t value); 2392 2393 /* REG_0x41:ana_reg1->cnti:set the controlling work of calibration in the DCO block to get the different frequency,W,0x41[24:16]*/ 2394 void sys_hal_set_ana_reg1_cnti(sys_hw_t *hw, uint32_t value); 2395 2396 /* REG_0x41:ana_reg1->spi_rst:reset the calibration block of DCO by spi,W,0x41[25]*/ 2397 void sys_hal_set_ana_reg1_spi_rst(sys_hw_t *hw, uint32_t value); 2398 2399 /* REG_0x41:ana_reg1->amsel:disable the calibration function of the DCO,set the frequency of DCO manual,W,0x41[26]*/ 2400 void sys_hal_set_ana_reg1_amsel(sys_hw_t *hw, uint32_t value); 2401 2402 /* REG_0x41:ana_reg1->divctrl:controlling the value of divider in the DCO to get the different frequency,W,0x41[29:27]*/ 2403 void sys_hal_set_ana_reg1_divctrl(sys_hw_t *hw, uint32_t value); 2404 2405 /* REG_0x41:ana_reg1->dco_tsten:dco test enable,W,0x41[30]*/ 2406 void sys_hal_set_ana_reg1_dco_tsten(sys_hw_t *hw, uint32_t value); 2407 2408 /* REG_0x41:ana_reg1->rosc_tsten:rosc test enable,W,0x41[31]*/ 2409 void sys_hal_set_ana_reg1_rosc_tsten(sys_hw_t *hw, uint32_t value); 2410 2411 /* REG_0x42 */ 2412 2413 void sys_hal_set_ana_reg2_value(sys_hw_t *hw, uint32_t value); 2414 2415 /* REG_0x42:ana_reg2->pwmscmen:buck nmos disable,W,0x42[0]*/ 2416 void sys_hal_set_ana_reg2_pwmscmen(sys_hw_t *hw, uint32_t value); 2417 2418 /* REG_0x42:ana_reg2->buck_fasten:buck EA fast transient enable(=1),W,0x42[1]*/ 2419 void sys_hal_set_ana_reg2_buck_fasten(sys_hw_t *hw, uint32_t value); 2420 2421 /* REG_0x42:ana_reg2->cls:buck current limit setting,W,0x42[4:2]*/ 2422 void sys_hal_set_ana_reg2_cls(sys_hw_t *hw, uint32_t value); 2423 2424 /* REG_0x42:ana_reg2->pfms:buck freewheeling damping enable(=1) ,W,0x42[9:5]*/ 2425 void sys_hal_set_ana_reg2_pfms(sys_hw_t *hw, uint32_t value); 2426 2427 /* REG_0x42:ana_reg2->ripc:buck pfm mode voltage ripple control setting,W,0x42[12:10]*/ 2428 void sys_hal_set_ana_reg2_ripc(sys_hw_t *hw, uint32_t value); 2429 2430 /* REG_0x42:ana_reg2->rampc:buck ramping compensation setting,W,0x42[16:13]*/ 2431 void sys_hal_set_ana_reg2_rampc(sys_hw_t *hw, uint32_t value); 2432 2433 /* REG_0x42:ana_reg2->rampcen:buck ramping compensation enable(=1),W,0x42[17]*/ 2434 void sys_hal_set_ana_reg2_rampcen(sys_hw_t *hw, uint32_t value); 2435 2436 /* REG_0x42:ana_reg2->dpfmen:buck pfm mode current reduce enable(=1),W,0x42[18]*/ 2437 void sys_hal_set_ana_reg2_dpfmen(sys_hw_t *hw, uint32_t value); 2438 2439 /* REG_0x42:ana_reg2->pfmen:buck pfm mode enable(=1),W,0x42[19]*/ 2440 void sys_hal_set_ana_reg2_pfmen(sys_hw_t *hw, uint32_t value); 2441 2442 /* REG_0x42:ana_reg2->forcepfm:buck force pfm mode(=1),W,0x42[20]*/ 2443 void sys_hal_set_ana_reg2_forcepfm(sys_hw_t *hw, uint32_t value); 2444 2445 /* REG_0x42:ana_reg2->swrsten:buck freewheeling damping enable(=1) ,W,0x42[21]*/ 2446 void sys_hal_set_ana_reg2_swrsten(sys_hw_t *hw, uint32_t value); 2447 2448 /* REG_0x42:ana_reg2->tmposel:buck mpo pulse width control 0--shortest 3---longest,W,0x42[23:22]*/ 2449 void sys_hal_set_ana_reg2_tmposel(sys_hw_t *hw, uint32_t value); 2450 2451 /* REG_0x42:ana_reg2->mpoen:buck mpo mode enable( =1),W,0x42[24]*/ 2452 void sys_hal_set_ana_reg2_mpoen(sys_hw_t *hw, uint32_t value); 2453 2454 /* REG_0x42:ana_reg2->spi_latchb:spi latch disable 0:latch;1:no latch,W,0x42[25]*/ 2455 void sys_hal_set_ana_reg2_spi_latchb(sys_hw_t *hw, uint32_t value); 2456 2457 /* REG_0x42:ana_reg2->ldosel:ldo/buck select, 0:buck;1:LDO,W,0x42[26]*/ 2458 void sys_hal_set_ana_reg2_ldosel(sys_hw_t *hw, uint32_t value); 2459 2460 /* REG_0x42:ana_reg2->iovoc:ioldo output voltage select 0:2.9V,….7:3.6V,W,0x42[29:27]*/ 2461 void sys_hal_set_ana_reg2_iovoc(sys_hw_t *hw, uint32_t value); 2462 2463 /* REG_0x42:ana_reg2->vbpbuf_hp:vbspbuffer high power enable,W,0x42[30]*/ 2464 void sys_hal_set_ana_reg2_vbpbuf_hp(sys_hw_t *hw, uint32_t value); 2465 2466 /* REG_0x42:ana_reg2->bypassen:ioldo bypass enable,W,0x42[31]*/ 2467 void sys_hal_set_ana_reg2_bypassen(sys_hw_t *hw, uint32_t value); 2468 2469 /* REG_0x43 */ 2470 2471 void sys_hal_set_ana_reg3_value(sys_hw_t *hw, uint32_t value); 2472 2473 /* REG_0x43:ana_reg3->zcdta:buck zcd delay tune setting,W,0x43[4:0]*/ 2474 void sys_hal_set_ana_reg3_zcdta(sys_hw_t *hw, uint32_t value); 2475 2476 /* REG_0x43:ana_reg3->zcdcala:buck zcd offset cali setting,W,0x43[10:5]*/ 2477 void sys_hal_set_ana_reg3_zcdcala(sys_hw_t *hw, uint32_t value); 2478 2479 /* REG_0x43:ana_reg3->zcdmen:buck zcd manual cali enable(=1),W,0x43[11]*/ 2480 void sys_hal_set_ana_reg3_zcdmen(sys_hw_t *hw, uint32_t value); 2481 2482 /* REG_0x43:ana_reg3->zcdcalen:buck zcd calibration enable(=1),W,0x43[12]*/ 2483 void sys_hal_set_ana_reg3_zcdcalen(sys_hw_t *hw, uint32_t value); 2484 2485 /* REG_0x43:ana_reg3->zcdcal_tri:buck zcd auto cali triggle(0-->1),W,0x43[13]*/ 2486 void sys_hal_set_ana_reg3_zcdcal_tri(sys_hw_t *hw, uint32_t value); 2487 2488 /* REG_0x43:ana_reg3->mroscsel:buck oscillator manual cali. enable(=1),W,0x43[14]*/ 2489 void sys_hal_set_ana_reg3_mroscsel(sys_hw_t *hw, uint32_t value); 2490 2491 /* REG_0x43:ana_reg3->mfsel:buck oscillator manual fsel ,W,0x43[17:15]*/ 2492 void sys_hal_set_ana_reg3_mfsel(sys_hw_t *hw, uint32_t value); 2493 2494 /* REG_0x43:ana_reg3->mroscbcal:buck oscillator manual cap_cal 0xA---500k 0xB--1M 0x9---2M,W,0x43[21:18]*/ 2495 void sys_hal_set_ana_reg3_mroscbcal(sys_hw_t *hw, uint32_t value); 2496 2497 /* REG_0x43:ana_reg3->osccaltrig:buck oscillator manual cali. enable(=1),W,0x43[22]*/ 2498 void sys_hal_set_ana_reg3_osccaltrig(sys_hw_t *hw, uint32_t value); 2499 2500 /* REG_0x43:ana_reg3->ckintsel:buck clock source select 1-- ring oscillator 0--divider,W,0x43[23]*/ 2501 void sys_hal_set_ana_reg3_ckintsel(sys_hw_t *hw, uint32_t value); 2502 2503 /* REG_0x43:ana_reg3->ckfs:buck output clock freq. select 0--500k 1---1M 2--2M 3--4M,W,0x43[25:24]*/ 2504 void sys_hal_set_ana_reg3_ckfs(sys_hw_t *hw, uint32_t value); 2505 2506 /* REG_0x43:ana_reg3->vlsel_ldodig:digldo output voltage select(low power) 0:0.6V,…..7:1.4V,W,0x43[28:26]*/ 2507 void sys_hal_set_ana_reg3_vlsel_ldodig(sys_hw_t *hw, uint32_t value); 2508 2509 /* REG_0x43:ana_reg3->vhsel_ldodig:digldo output voltage select(high power) 0:0.6V,…..7:1.4V,W,0x43[31:29]*/ 2510 void sys_hal_set_ana_reg3_vhsel_ldodig(sys_hw_t *hw, uint32_t value); 2511 2512 /* REG_0x44 */ 2513 2514 void sys_hal_set_ana_reg4_value(sys_hw_t *hw, uint32_t value); 2515 2516 /* REG_0x44:ana_reg4->cb_manu_val:CB Calibration Manual Value,W,0x44[9:5]*/ 2517 void sys_hal_set_ana_reg4_cb_manu_val(sys_hw_t *hw, uint32_t value); 2518 2519 /* REG_0x44:ana_reg4->cb_cal_trig:CB Calibration Trigger,W,0x44[10]*/ 2520 void sys_hal_set_ana_reg4_cb_cal_trig(sys_hw_t *hw, uint32_t value); 2521 2522 /* REG_0x44:ana_reg4->cb_cal_manu:CB Calibration Manual Mode ,W,0x44[11]*/ 2523 void sys_hal_set_ana_reg4_cb_cal_manu(sys_hw_t *hw, uint32_t value); 2524 2525 /* REG_0x44:ana_reg4->rosc_cal_intval:Rosc Calibration Interlval 0.25s~2s,W,0x44[14:12]*/ 2526 void sys_hal_set_ana_reg4_rosc_cal_intval(sys_hw_t *hw, uint32_t value); 2527 2528 /* REG_0x44:ana_reg4->manu_cin:Rosc Calibration Manual Cin,W,0x44[21:15]*/ 2529 void sys_hal_set_ana_reg4_manu_cin(sys_hw_t *hw, uint32_t value); 2530 2531 /* REG_0x44:ana_reg4->manu_fin:Rosc Calibration Manual Fin,W,0x44[26:22]*/ 2532 void sys_hal_set_ana_reg4_manu_fin(sys_hw_t *hw, uint32_t value); 2533 2534 /* REG_0x44:ana_reg4->rosc_cal_mode:Rosc Calibration Mode:; 0x1: 32K; 0x0: 31.25K,W,0x44[27]*/ 2535 void sys_hal_set_ana_reg4_rosc_cal_mode(sys_hw_t *hw, uint32_t value); 2536 2537 /* REG_0x44:ana_reg4->rosc_cal_trig:Rosc Calibration Trigger,W,0x44[28]*/ 2538 void sys_hal_set_ana_reg4_rosc_cal_trig(sys_hw_t *hw, uint32_t value); 2539 2540 /* REG_0x44:ana_reg4->rosc_cal_en:Rosc Calibration Enable,W,0x44[29]*/ 2541 void sys_hal_set_ana_reg4_rosc_cal_en(sys_hw_t *hw, uint32_t value); 2542 2543 /* REG_0x44:ana_reg4->rosc_manu_en:Rosc Calibration Manual Mode ,W,0x44[30]*/ 2544 void sys_hal_set_ana_reg4_rosc_manu_en(sys_hw_t *hw, uint32_t value); 2545 2546 /* REG_0x44:ana_reg4->rosc_tsten:Rosc test enable,W,0x44[31]*/ 2547 void sys_hal_set_ana_reg4_rosc_tsten(sys_hw_t *hw, uint32_t value); 2548 2549 /* REG_0x45 */ 2550 2551 void sys_hal_set_ana_reg5_value(sys_hw_t *hw, uint32_t value); 2552 2553 /* REG_0x45:ana_reg5->vref_scale:gadc reference voltage scale enable,W,0x45[0]*/ 2554 void sys_hal_set_ana_reg5_vref_scale(sys_hw_t *hw, uint32_t value); 2555 2556 /* REG_0x45:ana_reg5->dccal_en:gadc DC calibration enable,W,0x45[1]*/ 2557 void sys_hal_set_ana_reg5_dccal_en(sys_hw_t *hw, uint32_t value); 2558 2559 /* REG_0x45:ana_reg5->xtalh_ctune:xtalh load cap tuning,W,0x45[8:2]*/ 2560 void sys_hal_set_ana_reg5_xtalh_ctune(sys_hw_t *hw, uint32_t value); 2561 2562 /* REG_0x45:ana_reg5->cktst_sel:clock test signal selection rosc/xtall/dco/dpll,W,0x45[10:9]*/ 2563 void sys_hal_set_ana_reg5_cktst_sel(sys_hw_t *hw, uint32_t value); 2564 2565 /* REG_0x45:ana_reg5->ck_tst_enbale:system clock test enable,W,0x45[11]*/ 2566 void sys_hal_set_ana_reg5_ck_tst_enbale(sys_hw_t *hw, uint32_t value); 2567 2568 /* REG_0x45:ana_reg5->trxt_tst_enable:wifi trx test enable,W,0x45[12]*/ 2569 void sys_hal_set_ana_reg5_trxt_tst_enable(sys_hw_t *hw, uint32_t value); 2570 2571 /* REG_0x45:ana_reg5->encb:global central bias enable,W,0x45[13]*/ 2572 void sys_hal_set_ana_reg5_encb(sys_hw_t *hw, uint32_t value); 2573 2574 /* REG_0x45:ana_reg5->vctrl_dpllldo:dpll ldo output selection,W,0x45[15:14]*/ 2575 void sys_hal_set_ana_reg5_vctrl_dpllldo(sys_hw_t *hw, uint32_t value); 2576 2577 /* REG_0x45:ana_reg5->vctrl_sysldo:sys ldo output selection,W,0x45[17:16]*/ 2578 void sys_hal_set_ana_reg5_vctrl_sysldo(sys_hw_t *hw, uint32_t value); 2579 2580 /* REG_0x45:ana_reg5->temptst_en:tempdet test enable,W,0x45[18]*/ 2581 void sys_hal_set_ana_reg5_temptst_en(sys_hw_t *hw, uint32_t value); 2582 2583 /* REG_0x45:ana_reg5->gadc_tsel:gadc test signal selection,W,0x45[21:19]*/ 2584 void sys_hal_set_ana_reg5_gadc_tsel(sys_hw_t *hw, uint32_t value); 2585 2586 /* REG_0x45:ana_reg5->xtalh_ictrl:xtalh current control,W,0x45[22]*/ 2587 void sys_hal_set_ana_reg5_xtalh_ictrl(sys_hw_t *hw, uint32_t value); 2588 2589 /* REG_0x45:ana_reg5->bgcalm:bandgap calibration manual setting,W,0x45[28:23]*/ 2590 void sys_hal_set_ana_reg5_bgcalm(sys_hw_t *hw, uint32_t value); 2591 2592 /* REG_0x45:ana_reg5->bgcal_trig:bandgap calibrarion trig,W,0x45[29]*/ 2593 void sys_hal_set_ana_reg5_bgcal_trig(sys_hw_t *hw, uint32_t value); 2594 2595 /* REG_0x45:ana_reg5->bgcal_manu:bandgap calibration manual mode enable,W,0x45[30]*/ 2596 void sys_hal_set_ana_reg5_bgcal_manu(sys_hw_t *hw, uint32_t value); 2597 2598 /* REG_0x45:ana_reg5->bgcal_en:bandgap calibration enable,W,0x45[31]*/ 2599 void sys_hal_set_ana_reg5_bgcal_en(sys_hw_t *hw, uint32_t value); 2600 2601 /* REG_0x46 */ 2602 2603 void sys_hal_set_ana_reg6_value(sys_hw_t *hw, uint32_t value); 2604 2605 /* REG_0x46:ana_reg6->itune_xtall:xtall core current control,W,0x46[3:0]*/ 2606 void sys_hal_set_ana_reg6_itune_xtall(sys_hw_t *hw, uint32_t value); 2607 2608 /* REG_0x46:ana_reg6->xtall_ten:xtall test enable,W,0x46[4]*/ 2609 void sys_hal_set_ana_reg6_xtall_ten(sys_hw_t *hw, uint32_t value); 2610 2611 /* REG_0x46:ana_reg6->psldo_vsel:ps ldo output voltage selection,0:VIO /1:1.8V,W,0x46[5]*/ 2612 void sys_hal_set_ana_reg6_psldo_vsel(sys_hw_t *hw, uint32_t value); 2613 2614 /* REG_0x46:ana_reg6->en_usb:usb phy enable,W,0x46[6]*/ 2615 void sys_hal_set_ana_reg6_en_usb(sys_hw_t *hw, uint32_t value); 2616 2617 /* REG_0x46:ana_reg6->en_xtall:xtall oscillator enable,W,0x46[7]*/ 2618 void sys_hal_set_ana_reg6_en_xtall(sys_hw_t *hw, uint32_t value); 2619 2620 /* REG_0x46:ana_reg6->en_dco:dco enable,W,0x46[8]*/ 2621 void sys_hal_set_ana_reg6_en_dco(sys_hw_t *hw, uint32_t value); 2622 2623 /* REG_0x46:ana_reg6->en_psram_ldo:psram ldo enable,W,0x46[9]*/ 2624 void sys_hal_set_ana_reg6_en_psram_ldo(sys_hw_t *hw, uint32_t value); 2625 2626 /* REG_0x46:ana_reg6->en_tempdet:tempreture det enable,W,0x46[10]*/ 2627 void sys_hal_set_ana_reg6_en_tempdet(sys_hw_t *hw, uint32_t value); 2628 2629 /* REG_0x46:ana_reg6->en_audpll:audio pll enable,W,0x46[11]*/ 2630 void sys_hal_set_ana_reg6_en_audpll(sys_hw_t *hw, uint32_t value); 2631 2632 /* REG_0x46:ana_reg6->en_dpll:dpll enable,W,0x46[12]*/ 2633 void sys_hal_set_ana_reg6_en_dpll(sys_hw_t *hw, uint32_t value); 2634 2635 /* REG_0x46:ana_reg6->en_sysldo:sysldo enable,W,0x46[13]*/ 2636 void sys_hal_set_ana_reg6_en_sysldo(sys_hw_t *hw, uint32_t value); 2637 2638 /* REG_0x46:ana_reg6->pwd_gadc_buf:gadc input buffer pwd,W,0x46[17]*/ 2639 void sys_hal_set_ana_reg6_pwd_gadc_buf(sys_hw_t *hw, uint32_t value); 2640 2641 /* REG_0x46:ana_reg6->xtal_hpsrr_en:xtal high psrr buffer enable,W,0x46[18]*/ 2642 void sys_hal_set_ana_reg6_xtal_hpsrr_en(sys_hw_t *hw, uint32_t value); 2643 2644 /* REG_0x46:ana_reg6->en_xtal2rf:xtal clock to rfpll gate enable ,W,0x46[19]*/ 2645 void sys_hal_set_ana_reg6_en_xtal2rf(sys_hw_t *hw, uint32_t value); 2646 2647 /* REG_0x46:ana_reg6->en_sleep:xtal sleep enable,W,0x46[20]*/ 2648 void sys_hal_set_ana_reg6_en_sleep(sys_hw_t *hw, uint32_t value); 2649 2650 /* REG_0x46:ana_reg6->clkbuf_hd:xtal lpsrr clock buffer high power mode ,W,0x46[21]*/ 2651 void sys_hal_set_ana_reg6_clkbuf_hd(sys_hw_t *hw, uint32_t value); 2652 2653 /* REG_0x46:ana_reg6->clkbuf_dsel_manu:xtal lpsrr clock buffer power mode selection 0: auto /1:manu ,W,0x46[22]*/ 2654 void sys_hal_set_ana_reg6_clkbuf_dsel_manu(sys_hw_t *hw, uint32_t value); 2655 2656 /* REG_0x46:ana_reg6->xtal_lpmode_ctrl:xtal core low power mode enable,W,0x46[23]*/ 2657 void sys_hal_set_ana_reg6_xtal_lpmode_ctrl(sys_hw_t *hw, uint32_t value); 2658 2659 /* REG_0x46:ana_reg6->rxtal_lp:xtal bias current setting at low power mode ,W,0x46[27:24]*/ 2660 void sys_hal_set_ana_reg6_rxtal_lp(sys_hw_t *hw, uint32_t value); 2661 2662 /* REG_0x46:ana_reg6->rxtal_hp:xtal26m bias current setting at high power mode ,W,0x46[31:28]*/ 2663 void sys_hal_set_ana_reg6_rxtal_hp(sys_hw_t *hw, uint32_t value); 2664 2665 /* REG_0x47 */ 2666 2667 void sys_hal_set_ana_reg7_value(sys_hw_t *hw, uint32_t value); 2668 2669 /* REG_0x47:ana_reg7->rng_tstck_sel:trng setting,W,0x47[0]*/ 2670 void sys_hal_set_ana_reg7_rng_tstck_sel(sys_hw_t *hw, uint32_t value); 2671 2672 /* REG_0x47:ana_reg7->rng_tsten:trng setting,W,0x47[1]*/ 2673 void sys_hal_set_ana_reg7_rng_tsten(sys_hw_t *hw, uint32_t value); 2674 2675 /* REG_0x47:ana_reg7->itune_ref:trng setting,W,0x47[4:2]*/ 2676 void sys_hal_set_ana_reg7_itune_ref(sys_hw_t *hw, uint32_t value); 2677 2678 /* REG_0x47:ana_reg7->itune_opa:trng setting,W,0x47[7:5]*/ 2679 void sys_hal_set_ana_reg7_itune_opa(sys_hw_t *hw, uint32_t value); 2680 2681 /* REG_0x47:ana_reg7->itune_cmp:trng setting,W,0x47[10:8]*/ 2682 void sys_hal_set_ana_reg7_itune_cmp(sys_hw_t *hw, uint32_t value); 2683 2684 /* REG_0x47:ana_reg7->Rnooise_sel:trng setting,W,0x47[11]*/ 2685 void sys_hal_set_ana_reg7_rnooise_sel(sys_hw_t *hw, uint32_t value); 2686 2687 /* REG_0x47:ana_reg7->Fslow_sel:trng setting,W,0x47[14:12]*/ 2688 void sys_hal_set_ana_reg7_fslow_sel(sys_hw_t *hw, uint32_t value); 2689 2690 /* REG_0x47:ana_reg7->Ffast_sel:trng setting,W,0x47[18:15]*/ 2691 void sys_hal_set_ana_reg7_ffast_sel(sys_hw_t *hw, uint32_t value); 2692 2693 /* REG_0x47:ana_reg7->gadc_cal_sel:gadc calibration mode selection,W,0x47[20:19]*/ 2694 void sys_hal_set_ana_reg7_gadc_cal_sel(sys_hw_t *hw, uint32_t value); 2695 2696 /* REG_0x47:ana_reg7->gadc_ten:gadc test enable,W,0x47[21]*/ 2697 void sys_hal_set_ana_reg7_gadc_ten(sys_hw_t *hw, uint32_t value); 2698 2699 /* REG_0x47:ana_reg7->gadc_cmp_ictrl:gadc comparaor current select ,W,0x47[25:22]*/ 2700 void sys_hal_set_ana_reg7_gadc_cmp_ictrl(sys_hw_t *hw, uint32_t value); 2701 2702 /* REG_0x47:ana_reg7->gadc_buf_ictrl:gadc buffer current select ,W,0x47[29:26]*/ 2703 void sys_hal_set_ana_reg7_gadc_buf_ictrl(sys_hw_t *hw, uint32_t value); 2704 2705 /* REG_0x47:ana_reg7->vref_sel:gadc input reference select, 0：bandgap signal 1:GPIO voltage divided,W,0x47[30]*/ 2706 void sys_hal_set_ana_reg7_vref_sel(sys_hw_t *hw, uint32_t value); 2707 2708 /* REG_0x47:ana_reg7->scal_en:gadc reference scale enable, 0:normal mode,1: scale mode ,W,0x47[31]*/ 2709 void sys_hal_set_ana_reg7_scal_en(sys_hw_t *hw, uint32_t value); 2710 2711 /* REG_0x48 */ 2712 2713 void sys_hal_set_ana_reg8_value(sys_hw_t *hw, uint32_t value); 2714 2715 /* REG_0x48:ana_reg8->cap_calspi:manul mode ,input cap calibretion value,W,0x48[8:0]*/ 2716 void sys_hal_set_ana_reg8_cap_calspi(sys_hw_t *hw, uint32_t value); 2717 2718 /* REG_0x48:ana_reg8->gain_s:Sensitivity level selection,W,0x48[10:9]*/ 2719 void sys_hal_set_ana_reg8_gain_s(sys_hw_t *hw, uint32_t value); 2720 2721 /* REG_0x48:ana_reg8->pwd_td:power down touch module,W,0x48[11]*/ 2722 void sys_hal_set_ana_reg8_pwd_td(sys_hw_t *hw, uint32_t value); 2723 2724 /* REG_0x48:ana_reg8->en_fsr:low power mode ,enable fast response,W,0x48[12]*/ 2725 void sys_hal_set_ana_reg8_en_fsr(sys_hw_t *hw, uint32_t value); 2726 2727 /* REG_0x48:ana_reg8->en_scm:scan mode enable,W,0x48[13]*/ 2728 void sys_hal_set_ana_reg8_en_scm(sys_hw_t *hw, uint32_t value); 2729 2730 /* REG_0x48:ana_reg8->en_adcmode:adc mode enable,W,0x48[14]*/ 2731 void sys_hal_set_ana_reg8_en_adcmode(sys_hw_t *hw, uint32_t value); 2732 2733 /* REG_0x48:ana_reg8->en_lpmode:low power mode enable,W,0x48[15]*/ 2734 void sys_hal_set_ana_reg8_en_lpmode(sys_hw_t *hw, uint32_t value); 2735 2736 /* REG_0x48:ana_reg8->chs_scan:scan mode chan selection,W,0x48[31:16]*/ 2737 void sys_hal_set_ana_reg8_chs_scan(sys_hw_t *hw, uint32_t value); 2738 2739 /* REG_0x49 */ 2740 2741 void sys_hal_set_ana_reg9_value(sys_hw_t *hw, uint32_t value); 2742 2743 /* REG_0x49:ana_reg9->en_otp_spi:otp ldo spi enable,W,0x49[0]*/ 2744 void sys_hal_set_ana_reg9_en_otp_spi(sys_hw_t *hw, uint32_t value); 2745 2746 /* REG_0x49:ana_reg9->digovr_en:digldo over voltage reset enable,W,0x49[13]*/ 2747 void sys_hal_set_ana_reg9_digovr_en(sys_hw_t *hw, uint32_t value); 2748 2749 /* REG_0x49:ana_reg9->usbpen:usb dp driver capability control,W,0x49[17:14]*/ 2750 void sys_hal_set_ana_reg9_usbpen(sys_hw_t *hw, uint32_t value); 2751 2752 /* REG_0x49:ana_reg9->usbnen:usb dn driver capability control,W,0x49[21:18]*/ 2753 void sys_hal_set_ana_reg9_usbnen(sys_hw_t *hw, uint32_t value); 2754 2755 /* REG_0x49:ana_reg9->usb_speed:usb speed selection,W,0x49[22]*/ 2756 void sys_hal_set_ana_reg9_usb_speed(sys_hw_t *hw, uint32_t value); 2757 2758 /* REG_0x49:ana_reg9->usb_deepsleep:usb deepsleep mode enable by spi,W,0x49[23]*/ 2759 void sys_hal_set_ana_reg9_usb_deepsleep(sys_hw_t *hw, uint32_t value); 2760 2761 /* REG_0x49:ana_reg9->man_mode:manul mode enable,W,0x49[24]*/ 2762 void sys_hal_set_ana_reg9_man_mode(sys_hw_t *hw, uint32_t value); 2763 2764 /* REG_0x49:ana_reg9->crg:detect range selection :8pF/12pF/19pF/27pF,W,0x49[26:25]*/ 2765 void sys_hal_set_ana_reg9_crg(sys_hw_t *hw, uint32_t value); 2766 2767 /* REG_0x49:ana_reg9->vrefs:detect threshold selection ,W,0x49[29:27]*/ 2768 void sys_hal_set_ana_reg9_vrefs(sys_hw_t *hw, uint32_t value); 2769 2770 /* REG_0x49:ana_reg9->en_cal:calibretion enable,W,0x49[31]*/ 2771 void sys_hal_set_ana_reg9_en_cal(sys_hw_t *hw, uint32_t value); 2772 2773 /* REG_0x4a */ 2774 2775 void sys_hal_set_ana_reg10_value(sys_hw_t *hw, uint32_t value); 2776 2777 /* REG_0x4a:ana_reg10->sdm_val:audio pll sdm value,W,0x4a[29:0]*/ 2778 void sys_hal_set_ana_reg10_sdm_val(sys_hw_t *hw, uint32_t value); 2779 2780 /* REG_0x4a:ana_reg10->vco_hfreq_enb:audio pll vco high frequency enb,W,0x4a[30]*/ 2781 void sys_hal_set_ana_reg10_vco_hfreq_enb(sys_hw_t *hw, uint32_t value); 2782 2783 /* REG_0x4a:ana_reg10->cal_refen:cal_ref enable of audio pll,W,0x4a[31]*/ 2784 void sys_hal_set_ana_reg10_cal_refen(sys_hw_t *hw, uint32_t value); 2785 2786 /* REG_0x4b */ 2787 2788 void sys_hal_set_ana_reg11_value(sys_hw_t *hw, uint32_t value); 2789 2790 /* REG_0x4b:ana_reg11->int_mod:DPLL integer mode enable; 0: fractional mode; 1: integer mode,W,0x4b[0]*/ 2791 void sys_hal_set_ana_reg11_int_mod(sys_hw_t *hw, uint32_t value); 2792 2793 /* REG_0x4b:ana_reg11->Nsyn:DPLL Ncoutner reset ,W,0x4b[1]*/ 2794 void sys_hal_set_ana_reg11_nsyn(sys_hw_t *hw, uint32_t value); 2795 2796 /* REG_0x4b:ana_reg11->selpol:DPLL PFD polarity control,W,0x4b[2]*/ 2797 void sys_hal_set_ana_reg11_selpol(sys_hw_t *hw, uint32_t value); 2798 2799 /* REG_0x4b:ana_reg11->reset:DPLL reset,W,0x4b[3]*/ 2800 void sys_hal_set_ana_reg11_reset(sys_hw_t *hw, uint32_t value); 2801 2802 /* REG_0x4b:ana_reg11->Ioffset:DPLL charge pump offset current control,W,0x4b[6:4]*/ 2803 void sys_hal_set_ana_reg11_ioffset(sys_hw_t *hw, uint32_t value); 2804 2805 /* REG_0x4b:ana_reg11->LPFRz:DPLL Rz control of LPF,W,0x4b[10:7]*/ 2806 void sys_hal_set_ana_reg11_lpfrz(sys_hw_t *hw, uint32_t value); 2807 2808 /* REG_0x4b:ana_reg11->Rp2:DPLL Rp control of LPF,W,0x4b[13:11]*/ 2809 void sys_hal_set_ana_reg11_rp2(sys_hw_t *hw, uint32_t value); 2810 2811 /* REG_0x4b:ana_reg11->vsel_cal:DPLL vtrl selection during VCO band calibration,W,0x4b[14]*/ 2812 void sys_hal_set_ana_reg11_vsel_cal(sys_hw_t *hw, uint32_t value); 2813 2814 /* REG_0x4b:ana_reg11->kctrl:DPLL Kvco control,W,0x4b[16:15]*/ 2815 void sys_hal_set_ana_reg11_kctrl(sys_hw_t *hw, uint32_t value); 2816 2817 /* REG_0x4b:ana_reg11->ckref_loop_sel:polarity selection of referenc clock to SDM,W,0x4b[17]*/ 2818 void sys_hal_set_ana_reg11_ckref_loop_sel(sys_hw_t *hw, uint32_t value); 2819 2820 /* REG_0x4b:ana_reg11->spi_trigger:DPLL band calibration spi trigger,W,0x4b[18]*/ 2821 void sys_hal_set_ana_reg11_spi_trigger(sys_hw_t *hw, uint32_t value); 2822 2823 /* REG_0x4b:ana_reg11->manual:DPLL VCO band manual enable; 0: auto mode; 1: manual mode,W,0x4b[19]*/ 2824 void sys_hal_set_ana_reg11_manual(sys_hw_t *hw, uint32_t value); 2825 2826 /* REG_0x4b:ana_reg11->Icp:DPLL charge pump current control; 000: 5uA; 001: 10uA; 010: 15uA; 011: 20uA; 100: 25uA; 101: 30uA; 110: 35uA; 111: 40uA,W,0x4b[22:20]*/ 2827 void sys_hal_set_ana_reg11_icp(sys_hw_t *hw, uint32_t value); 2828 2829 /* REG_0x4b:ana_reg11->Rsel:DPLL reference clock selection; 0: 13M; 1: 6.5M,W,0x4b[23]*/ 2830 void sys_hal_set_ana_reg11_rsel(sys_hw_t *hw, uint32_t value); 2831 2832 /* REG_0x4b:ana_reg11->ck26Men:xtal26M clock for audio enable,W,0x4b[24]*/ 2833 void sys_hal_set_ana_reg11_ck26men(sys_hw_t *hw, uint32_t value); 2834 2835 /* REG_0x4b:ana_reg11->ckaudio_outen:DPLL clock output to PAD enable,W,0x4b[25]*/ 2836 void sys_hal_set_ana_reg11_ckaudio_outen(sys_hw_t *hw, uint32_t value); 2837 2838 /* REG_0x4b:ana_reg11->divctrl:DPLL divider control; 000: div1; 001: div2; 010: div4; 011: div8; 1xx: div16,W,0x4b[28:26]*/ 2839 void sys_hal_set_ana_reg11_divctrl(sys_hw_t *hw, uint32_t value); 2840 2841 /* REG_0x4b:ana_reg11->cksel:DPLL divider control; 0: div3; 1: div4,W,0x4b[29]*/ 2842 void sys_hal_set_ana_reg11_cksel(sys_hw_t *hw, uint32_t value); 2843 2844 /* REG_0x4b:ana_reg11->usben:DPLL clock for USB enable,W,0x4b[30]*/ 2845 void sys_hal_set_ana_reg11_usben(sys_hw_t *hw, uint32_t value); 2846 2847 /* REG_0x4b:ana_reg11->audioen:DPLL clock for audio enable,W,0x4b[31]*/ 2848 void sys_hal_set_ana_reg11_audioen(sys_hw_t *hw, uint32_t value); 2849 2850 /* REG_0x4c */ 2851 2852 void sys_hal_set_ana_reg12_value(sys_hw_t *hw, uint32_t value); 2853 2854 /* REG_0x4c:ana_reg12->digmic_ckinv:digmic clock inversion enable,W,0x4c[2]*/ 2855 void sys_hal_set_ana_reg12_digmic_ckinv(sys_hw_t *hw, uint32_t value); 2856 2857 /* REG_0x4c:ana_reg12->enmicdig:digmic enable,w,0x4c[3]*/ 2858 void sys_hal_set_ana_reg12_enmicdig(sys_hw_t *hw, uint32_t value); 2859 2860 /* REG_0x4c:ana_reg12->audck_rlcen:audio clock re-latch enable,W,0x4c[4]*/ 2861 void sys_hal_set_ana_reg12_audck_rlcen(sys_hw_t *hw, uint32_t value); 2862 2863 /* REG_0x4c:ana_reg12->lchckinven:audio clock re-latch clock inversion enable,W,0x4c[5]*/ 2864 void sys_hal_set_ana_reg12_lchckinven(sys_hw_t *hw, uint32_t value); 2865 2866 /* REG_0x4c:ana_reg12->ldo1v_vsel1v:audio 1.0V LDO selection, 000=0.8, 1X1=1.0,W,0x4c[8:6]*/ 2867 void sys_hal_set_ana_reg12_ldo1v_vsel1v(sys_hw_t *hw, uint32_t value); 2868 2869 /* REG_0x4c:ana_reg12->ldo1v_adj:audio 1.0V LDO output trimming, 00000=min, 11111=max,W,0x4c[13:9]*/ 2870 void sys_hal_set_ana_reg12_ldo1v_adj(sys_hw_t *hw, uint32_t value); 2871 2872 /* REG_0x4c:ana_reg12->audvdd_trm1v:audio 1.5V LDO selection, 00=min, 11=max,W,0x4c[15:14]*/ 2873 void sys_hal_set_ana_reg12_audvdd_trm1v(sys_hw_t *hw, uint32_t value); 2874 2875 /* REG_0x4c:ana_reg12->audvdd_voc1v:audio 1.5V LDO output trimming, 00000=min, 11111=max,W,0x4c[20:16]*/ 2876 void sys_hal_set_ana_reg12_audvdd_voc1v(sys_hw_t *hw, uint32_t value); 2877 2878 /* REG_0x4c:ana_reg12->enaudvdd1v:audio 1.0V LDO enable,W,0x4c[21]*/ 2879 void sys_hal_set_ana_reg12_enaudvdd1v(sys_hw_t *hw, uint32_t value); 2880 2881 /* REG_0x4c:ana_reg12->loadhp:audio 1.5V LDO, 1=good stability with small loading,W,0x4c[22]*/ 2882 void sys_hal_set_ana_reg12_loadhp(sys_hw_t *hw, uint32_t value); 2883 2884 /* REG_0x4c:ana_reg12->enaudvdd1v5:audio 1.5V LDO enable,W,0x4c[23]*/ 2885 void sys_hal_set_ana_reg12_enaudvdd1v5(sys_hw_t *hw, uint32_t value); 2886 2887 /* REG_0x4c:ana_reg12->enmicbias1v:micbias enable,W,0x4c[24]*/ 2888 void sys_hal_set_ana_reg12_enmicbias1v(sys_hw_t *hw, uint32_t value); 2889 2890 /* REG_0x4c:ana_reg12->micbias_trim:micbias output selection, 00=min, 11=max,W,0x4c[26:25]*/ 2891 void sys_hal_set_ana_reg12_micbias_trim(sys_hw_t *hw, uint32_t value); 2892 2893 /* REG_0x4c:ana_reg12->micbias_voc1v:micbias output trimming, 00000=min, 11111=max,W,0x4c[31:27]*/ 2894 void sys_hal_set_ana_reg12_micbias_voc1v(sys_hw_t *hw, uint32_t value); 2895 2896 /* REG_0x4d */ 2897 2898 void sys_hal_set_ana_reg13_value(sys_hw_t *hw, uint32_t value); 2899 2900 /* REG_0x4d:ana_reg13->byp_dwaadc:adc dwa pass enable,W,0x4d[8]*/ 2901 void sys_hal_set_ana_reg13_byp_dwaadc(sys_hw_t *hw, uint32_t value); 2902 2903 /* REG_0x4d:ana_reg13->rst:rst,W,0x4d[9]*/ 2904 void sys_hal_set_ana_reg13_rst(sys_hw_t *hw, uint32_t value); 2905 2906 /* REG_0x4d:ana_reg13->adcdwa_mode:adc dwa model sel,W,0x4d[10]*/ 2907 void sys_hal_set_ana_reg13_adcdwa_mode(sys_hw_t *hw, uint32_t value); 2908 2909 /* REG_0x4d:ana_reg13->vodadjspi:adc reference manual spi control,W,0x4d[15:11]*/ 2910 void sys_hal_set_ana_reg13_vodadjspi(sys_hw_t *hw, uint32_t value); 2911 2912 /* REG_0x4d:ana_reg13->refvsel:0= high reference; 1=small reference,W,0x4d[21]*/ 2913 void sys_hal_set_ana_reg13_refvsel(sys_hw_t *hw, uint32_t value); 2914 2915 /* REG_0x4d:ana_reg13->capsw1v:munual value for cap trimming,W,0x4d[27:23]*/ 2916 void sys_hal_set_ana_reg13_capsw1v(sys_hw_t *hw, uint32_t value); 2917 2918 /* REG_0x4d:ana_reg13->adcckinven:audio adc clock inversion enable,W,0x4d[30]*/ 2919 void sys_hal_set_ana_reg13_adcckinven(sys_hw_t *hw, uint32_t value); 2920 2921 /* REG_0x4e */ 2922 2923 void sys_hal_set_ana_reg14_value(sys_hw_t *hw, uint32_t value); 2924 2925 /* REG_0x4e:ana_reg14->isel:adc bias trimming,W,0x4e[1:0]*/ 2926 void sys_hal_set_ana_reg14_isel(sys_hw_t *hw, uint32_t value); 2927 2928 /* REG_0x4e:ana_reg14->micdcocdin:adc micmode dcoc din,W,0x4e[9:2]*/ 2929 void sys_hal_set_ana_reg14_micdcocdin(sys_hw_t *hw, uint32_t value); 2930 2931 /* REG_0x4e:ana_reg14->micdcocvc:adc micmode dcoc control,W,0x4e[11:10]*/ 2932 void sys_hal_set_ana_reg14_micdcocvc(sys_hw_t *hw, uint32_t value); 2933 2934 /* REG_0x4e:ana_reg14->micdcocen_n:adc micmode dcoc enable,W,0x4e[12]*/ 2935 void sys_hal_set_ana_reg14_micdcocen_n(sys_hw_t *hw, uint32_t value); 2936 2937 /* REG_0x4e:ana_reg14->micdcocen_p:adc micmode dcoc enable,W,0x4e[13]*/ 2938 void sys_hal_set_ana_reg14_micdcocen_p(sys_hw_t *hw, uint32_t value); 2939 2940 /* REG_0x4e:ana_reg14->micsingleEn:adc micmode, single_end enable,W,0x4e[14]*/ 2941 void sys_hal_set_ana_reg14_micsingleen(sys_hw_t *hw, uint32_t value); 2942 2943 /* REG_0x4e:ana_reg14->micGain:adc micmode gain, 0=0dB(17.9K), F=24dB(267.6K), 2dB/step,W,0x4e[18:15]*/ 2944 void sys_hal_set_ana_reg14_micgain(sys_hw_t *hw, uint32_t value); 2945 2946 /* REG_0x4e:ana_reg14->micdacen:adc micmode micdac enable,W,0x4e[19]*/ 2947 void sys_hal_set_ana_reg14_micdacen(sys_hw_t *hw, uint32_t value); 2948 2949 /* REG_0x4e:ana_reg14->micdaciH:adc micmode, micdac input ,W,0x4e[27:20]*/ 2950 void sys_hal_set_ana_reg14_micdacih(sys_hw_t *hw, uint32_t value); 2951 2952 /* REG_0x4e:ana_reg14->micdacit:adc micmode, mic_dac Iout Full-range, 00=280uA, 01=320uA, 1X=447uA,W,0x4e[29:28]*/ 2953 void sys_hal_set_ana_reg14_micdacit(sys_hw_t *hw, uint32_t value); 2954 2955 /* REG_0x4e:ana_reg14->hcen:adc 1stg op current trimming,W,0x4e[30]*/ 2956 void sys_hal_set_ana_reg14_hcen(sys_hw_t *hw, uint32_t value); 2957 2958 /* REG_0x4e:ana_reg14->micEn:mic1 mode enable,W,0x4e[31]*/ 2959 void sys_hal_set_ana_reg14_micen(sys_hw_t *hw, uint32_t value); 2960 2961 /* REG_0x4f */ 2962 2963 void sys_hal_set_ana_reg15_value(sys_hw_t *hw, uint32_t value); 2964 2965 /* REG_0x4f:ana_reg15->isel:adc bias trimming,W,0x4f[1:0]*/ 2966 void sys_hal_set_ana_reg15_isel(sys_hw_t *hw, uint32_t value); 2967 2968 /* REG_0x4f:ana_reg15->micdcocdin:adc micmode dcoc din,W,0x4f[9:2]*/ 2969 void sys_hal_set_ana_reg15_micdcocdin(sys_hw_t *hw, uint32_t value); 2970 2971 /* REG_0x4f:ana_reg15->micdcocvc:adc micmode dcoc control,W,0x4f[11:10]*/ 2972 void sys_hal_set_ana_reg15_micdcocvc(sys_hw_t *hw, uint32_t value); 2973 2974 /* REG_0x4f:ana_reg15->micdcocen_n:adc micmode dcoc enable,W,0x4f[12]*/ 2975 void sys_hal_set_ana_reg15_micdcocen_n(sys_hw_t *hw, uint32_t value); 2976 2977 /* REG_0x4f:ana_reg15->micdcocen_p:adc micmode dcoc enable,W,0x4f[13]*/ 2978 void sys_hal_set_ana_reg15_micdcocen_p(sys_hw_t *hw, uint32_t value); 2979 2980 /* REG_0x4f:ana_reg15->micsingleEn:adc micmode, single_end enable,W,0x4f[14]*/ 2981 void sys_hal_set_ana_reg15_micsingleen(sys_hw_t *hw, uint32_t value); 2982 2983 /* REG_0x4f:ana_reg15->micGain:adc micmode gain, 0=0dB(17.9K), F=24dB(267.6K), 2dB/step,W,0x4f[18:15]*/ 2984 void sys_hal_set_ana_reg15_micgain(sys_hw_t *hw, uint32_t value); 2985 2986 /* REG_0x4f:ana_reg15->micdacen:adc micmode micdac enable,W,0x4f[19]*/ 2987 void sys_hal_set_ana_reg15_micdacen(sys_hw_t *hw, uint32_t value); 2988 2989 /* REG_0x4f:ana_reg15->micdaciH:adc micmode, micdac input ,W,0x4f[27:20]*/ 2990 void sys_hal_set_ana_reg15_micdacih(sys_hw_t *hw, uint32_t value); 2991 2992 /* REG_0x4f:ana_reg15->micdacit:adc micmode, mic_dac Iout Full-range, 00=280uA, 01=320uA, 1X=447uA,W,0x4f[29:28]*/ 2993 void sys_hal_set_ana_reg15_micdacit(sys_hw_t *hw, uint32_t value); 2994 2995 /* REG_0x4f:ana_reg15->hcen:adc 1stg op current trimming,W,0x4f[30]*/ 2996 void sys_hal_set_ana_reg15_hcen(sys_hw_t *hw, uint32_t value); 2997 2998 /* REG_0x4f:ana_reg15->micEn:mic2 mode enable,W,0x4f[31]*/ 2999 void sys_hal_set_ana_reg15_micen(sys_hw_t *hw, uint32_t value); 3000 3001 /* REG_0x50 */ 3002 3003 void sys_hal_set_ana_reg16_value(sys_hw_t *hw, uint32_t value); 3004 3005 /* REG_0x50:ana_reg16->hpdac:class ab driver high current mode. "1" high current. ,W,0x50[0]*/ 3006 void sys_hal_set_ana_reg16_hpdac(sys_hw_t *hw, uint32_t value); 3007 3008 /* REG_0x50:ana_reg16->vcmsdac:1stg OP input common model voltage selection. "1" low common mode voltage,W,0x50[1]*/ 3009 void sys_hal_set_ana_reg16_vcmsdac(sys_hw_t *hw, uint32_t value); 3010 3011 /* REG_0x50:ana_reg16->oscdac:threshold current setting for over current protection . "3" maximum current. "0" minimum current,W,0x50[3:2]*/ 3012 void sys_hal_set_ana_reg16_oscdac(sys_hw_t *hw, uint32_t value); 3013 3014 /* REG_0x50:ana_reg16->ocendac:over current protection enable. "1" enable.,W,0x50[4]*/ 3015 void sys_hal_set_ana_reg16_ocendac(sys_hw_t *hw, uint32_t value); 3016 3017 /* REG_0x50:ana_reg16->isel_idac:idac current sel,W,0x50[5]*/ 3018 void sys_hal_set_ana_reg16_isel_idac(sys_hw_t *hw, uint32_t value); 3019 3020 /* REG_0x50:ana_reg16->adjdacref:audio dac reference voltage adjust.,W,0x50[10:6]*/ 3021 void sys_hal_set_ana_reg16_adjdacref(sys_hw_t *hw, uint32_t value); 3022 3023 /* REG_0x50:ana_reg16->dcochg:dcoc high gain selection. "1" high gain,W,0x50[12]*/ 3024 void sys_hal_set_ana_reg16_dcochg(sys_hw_t *hw, uint32_t value); 3025 3026 /* REG_0x50:ana_reg16->diffen:enable differential mode. "1" enable,W,0x50[13]*/ 3027 void sys_hal_set_ana_reg16_diffen(sys_hw_t *hw, uint32_t value); 3028 3029 /* REG_0x50:ana_reg16->endaccal:enable offset calibration process. "1" enable.,W,0x50[14]*/ 3030 void sys_hal_set_ana_reg16_endaccal(sys_hw_t *hw, uint32_t value); 3031 3032 /* REG_0x50:ana_reg16->rendcoc:R-channel dcoc dac enablel. "1" enable,W,0x50[15]*/ 3033 void sys_hal_set_ana_reg16_rendcoc(sys_hw_t *hw, uint32_t value); 3034 3035 /* REG_0x50:ana_reg16->lendcoc:L-channel Dcoc dac enable. "1" enable,W,0x50[16]*/ 3036 void sys_hal_set_ana_reg16_lendcoc(sys_hw_t *hw, uint32_t value); 3037 3038 /* REG_0x50:ana_reg16->renvcmd:R-channel common mode output buffer enable."1" enable,W,0x50[17]*/ 3039 void sys_hal_set_ana_reg16_renvcmd(sys_hw_t *hw, uint32_t value); 3040 3041 /* REG_0x50:ana_reg16->lenvcmd:L-channel common mode output buffer enable. "1" enable,W,0x50[18]*/ 3042 void sys_hal_set_ana_reg16_lenvcmd(sys_hw_t *hw, uint32_t value); 3043 3044 /* REG_0x50:ana_reg16->dacdrven:dac output driver enable."1" enable,W,0x50[19]*/ 3045 void sys_hal_set_ana_reg16_dacdrven(sys_hw_t *hw, uint32_t value); 3046 3047 /* REG_0x50:ana_reg16->dacRen:dac R-channel enable. "1" enable,W,0x50[20]*/ 3048 void sys_hal_set_ana_reg16_dacren(sys_hw_t *hw, uint32_t value); 3049 3050 /* REG_0x50:ana_reg16->dacLen:dac L-channel enable. "1" enable,W,0x50[21]*/ 3051 void sys_hal_set_ana_reg16_daclen(sys_hw_t *hw, uint32_t value); 3052 3053 /* REG_0x50:ana_reg16->dacG:dac gain setting: 000=0dB, 111=8dB,W,0x50[24:22]*/ 3054 void sys_hal_set_ana_reg16_dacg(sys_hw_t *hw, uint32_t value); 3055 3056 /* REG_0x50:ana_reg16->ck4xsel:dac clock sel ,W,0x50[25]*/ 3057 void sys_hal_set_ana_reg16_ck4xsel(sys_hw_t *hw, uint32_t value); 3058 3059 /* REG_0x50:ana_reg16->dacmute:dac mute enable. "1" mute enable,W,0x50[26]*/ 3060 void sys_hal_set_ana_reg16_dacmute(sys_hw_t *hw, uint32_t value); 3061 3062 /* REG_0x50:ana_reg16->dwamode:dac dwa mode sel,W,0x50[27]*/ 3063 void sys_hal_set_ana_reg16_dwamode(sys_hw_t *hw, uint32_t value); 3064 3065 /* REG_0x50:ana_reg16->ckposel:dac sample clock edge selection,W,0x50[28]*/ 3066 void sys_hal_set_ana_reg16_ckposel(sys_hw_t *hw, uint32_t value); 3067 3068 /* REG_0x50:ana_reg16->byldo:bypass 1v8 LDO,W,0x50[31]*/ 3069 void sys_hal_set_ana_reg16_byldo(sys_hw_t *hw, uint32_t value); 3070 3071 /* REG_0x51 */ 3072 3073 void sys_hal_set_ana_reg17_value(sys_hw_t *hw, uint32_t value); 3074 3075 /* REG_0x51:ana_reg17->lmdcin:l-cnannel offset cancel dac maumual input.,W,0x51[7:0]*/ 3076 void sys_hal_set_ana_reg17_lmdcin(sys_hw_t *hw, uint32_t value); 3077 3078 /* REG_0x51:ana_reg17->rmdcin:r-channel offset cancel dac manmual input ,W,0x51[15:8]*/ 3079 void sys_hal_set_ana_reg17_rmdcin(sys_hw_t *hw, uint32_t value); 3080 3081 /* REG_0x51:ana_reg17->spirst_ovc:ovc rst,W,0x51[16]*/ 3082 void sys_hal_set_ana_reg17_spirst_ovc(sys_hw_t *hw, uint32_t value); 3083 3084 /* REG_0x51:ana_reg17->hc2s0v9:0=current is half,W,0x51[20]*/ 3085 void sys_hal_set_ana_reg17_hc2s0v9(sys_hw_t *hw, uint32_t value); 3086 3087 /* REG_0x51:ana_reg17->lvcmsel:low vcm sel,W,0x51[21]*/ 3088 void sys_hal_set_ana_reg17_lvcmsel(sys_hw_t *hw, uint32_t value); 3089 3090 /* REG_0x51:ana_reg17->loop2sel:2rd loop sel,W,0x51[22]*/ 3091 void sys_hal_set_ana_reg17_loop2sel(sys_hw_t *hw, uint32_t value); 3092 3093 /* REG_0x51:ana_reg17->enbias:dac bias enable,W,0x51[23]*/ 3094 void sys_hal_set_ana_reg17_enbias(sys_hw_t *hw, uint32_t value); 3095 3096 /* REG_0x51:ana_reg17->calck_sel0v9:offset calibration clock selection. "1" high clock.,W,0x51[24]*/ 3097 void sys_hal_set_ana_reg17_calck_sel0v9(sys_hw_t *hw, uint32_t value); 3098 3099 /* REG_0x51:ana_reg17->bpdwa0v9:bypss audio dac dwa. "1" bypass.,W,0x51[25]*/ 3100 void sys_hal_set_ana_reg17_bpdwa0v9(sys_hw_t *hw, uint32_t value); 3101 3102 /* REG_0x51:ana_reg17->looprst0v9:audio dac integrator capacitor reset. "1" reset.,W,0x51[26]*/ 3103 void sys_hal_set_ana_reg17_looprst0v9(sys_hw_t *hw, uint32_t value); 3104 3105 /* REG_0x51:ana_reg17->oct0v9:over current delay time setting."11" maximum time. "00" minimum current.,W,0x51[28:27]*/ 3106 void sys_hal_set_ana_reg17_oct0v9(sys_hw_t *hw, uint32_t value); 3107 3108 /* REG_0x51:ana_reg17->sout0v9:short output with 600ohm resistor. "1" short output.,W,0x51[29]*/ 3109 void sys_hal_set_ana_reg17_sout0v9(sys_hw_t *hw, uint32_t value); 3110 3111 /* REG_0x51:ana_reg17->hc0v9:dac current trimming, 00=minimum current, 11=maximum current,W,0x51[31:30]*/ 3112 void sys_hal_set_ana_reg17_hc0v9(sys_hw_t *hw, uint32_t value); 3113 3114 /* REG_0x52 */ 3115 3116 void sys_hal_set_ana_reg18_value(sys_hw_t *hw, uint32_t value); 3117 3118 /* REG_0x52:ana_reg18->ictrl_dsppll:26M PLL setting,W,0x52[3:0]*/ 3119 void sys_hal_set_ana_reg18_ictrl_dsppll(sys_hw_t *hw, uint32_t value); 3120 3121 /* REG_0x52:ana_reg18->FBdivN:26M PLL setting,W,0x52[13:4]*/ 3122 void sys_hal_set_ana_reg18_fbdivn(sys_hw_t *hw, uint32_t value); 3123 3124 /* REG_0x52:ana_reg18->N_mcudsp:26M PLL setting,W,0x52[18:14]*/ 3125 void sys_hal_set_ana_reg18_n_mcudsp(sys_hw_t *hw, uint32_t value); 3126 3127 /* REG_0x52:ana_reg18->mode:26M PLL setting,W,0x52[19]*/ 3128 void sys_hal_set_ana_reg18_mode(sys_hw_t *hw, uint32_t value); 3129 3130 /* REG_0x52:ana_reg18->iamsel:26M PLL setting,W,0x52[20]*/ 3131 void sys_hal_set_ana_reg18_iamsel(sys_hw_t *hw, uint32_t value); 3132 3133 /* REG_0x52:ana_reg18->hvref:26M PLL setting,W,0x52[22:21]*/ 3134 void sys_hal_set_ana_reg18_hvref(sys_hw_t *hw, uint32_t value); 3135 3136 /* REG_0x52:ana_reg18->lvref:26M PLL setting,W,0x52[24:23]*/ 3137 void sys_hal_set_ana_reg18_lvref(sys_hw_t *hw, uint32_t value); 3138 3139 /* REG_0x53 */ 3140 3141 void sys_hal_set_ana_reg19_value(sys_hw_t *hw, uint32_t value); 3142 3143 /* REG_0x53:ana_reg19->amsel:26M PLL setting,W,0x53[0]*/ 3144 void sys_hal_set_ana_reg19_amsel(sys_hw_t *hw, uint32_t value); 3145 3146 /* REG_0x53:ana_reg19->msw:26M PLL setting,W,0x53[9:1]*/ 3147 void sys_hal_set_ana_reg19_msw(sys_hw_t *hw, uint32_t value); 3148 3149 /* REG_0x53:ana_reg19->tstcken_dpll:26M PLL setting,W,0x53[10]*/ 3150 void sys_hal_set_ana_reg19_tstcken_dpll(sys_hw_t *hw, uint32_t value); 3151 3152 /* REG_0x53:ana_reg19->osccal_trig:26M PLL setting,W,0x53[11]*/ 3153 void sys_hal_set_ana_reg19_osccal_trig(sys_hw_t *hw, uint32_t value); 3154 3155 /* REG_0x53:ana_reg19->cnti:26M PLL setting,W,0x53[20:12]*/ 3156 void sys_hal_set_ana_reg19_cnti(sys_hw_t *hw, uint32_t value); 3157 3158 /* REG_0x53:ana_reg19->spi_rst:26M PLL setting,W,0x53[22]*/ 3159 void sys_hal_set_ana_reg19_spi_rst(sys_hw_t *hw, uint32_t value); 3160 3161 /* REG_0x53:ana_reg19->closeloop_en:26M PLL setting,W,0x53[23]*/ 3162 void sys_hal_set_ana_reg19_closeloop_en(sys_hw_t *hw, uint32_t value); 3163 3164 /* REG_0x53:ana_reg19->caltime:26M PLL setting,W,0x53[24]*/ 3165 void sys_hal_set_ana_reg19_caltime(sys_hw_t *hw, uint32_t value); 3166 3167 /* REG_0x53:ana_reg19->LPFRz:26M PLL setting,W,0x53[26:25]*/ 3168 void sys_hal_set_ana_reg19_lpfrz(sys_hw_t *hw, uint32_t value); 3169 3170 /* REG_0x53:ana_reg19->ICP:26M PLL setting,W,0x53[30:27]*/ 3171 void sys_hal_set_ana_reg19_icp(sys_hw_t *hw, uint32_t value); 3172 3173 /* REG_0x53:ana_reg19->CP2ctrl:26M PLL setting,W,0x53[31]*/ 3174 void sys_hal_set_ana_reg19_cp2ctrl(sys_hw_t *hw, uint32_t value); 3175 3176 #endif 3177 3178 void sys_hal_set_ana_trxt_tst_enable(uint32_t value); 3179 void sys_hal_set_ana_scal_en(uint32_t value); 3180 void sys_hal_set_ana_gadc_buf_ictrl(uint32_t value); 3181 void sys_hal_set_ana_gadc_cmp_ictrl(uint32_t value); 3182 void sys_hal_set_ana_pwd_gadc_buf(uint32_t value); 3183 void sys_hal_set_ana_vref_sel(uint32_t value); 3184 void sys_hal_set_ana_cb_cal_manu(uint32_t value); 3185 void sys_hal_set_ana_cb_cal_trig(uint32_t value); 3186 void sys_hal_set_ana_cb_cal_manu_val(uint32_t value); 3187 void sys_hal_set_ana_vlsel_ldodig(uint32_t value); 3188 void sys_hal_set_ana_vhsel_ldodig(uint32_t value); 3189 void sys_hal_set_ana_vctrl_sysldo(uint32_t value); 3190 3191 3192 3193 #ifdef __cplusplus 3194 } 3195 #endif 3196 3197 3198