1 /**
2 * Copyright (c) 2021-2023 HPMicro
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8 #ifndef HPM_SYSCTL_DRV_H
9 #define HPM_SYSCTL_DRV_H
10
11 #include "hpm_common.h"
12 #include "hpm_sysctl_regs.h"
13
14 /**
15 *
16 * @brief SYSCTL driver APIs
17 * @defgroup sysctl_interface SYSCTL driver APIs
18 * @ingroup io_interfaces
19 * @{
20 */
21
22 /**
23 * @brief Retention domains
24 */
25 typedef enum {
26 sysctl_retention_domain_sys = 0,
27 sysctl_retention_domain_cpu0 = 2,
28 sysctl_retention_domain_con = 4,
29 sysctl_retention_domain_vis = 5,
30 sysctl_retention_domain_gpu = 7,
31 sysctl_retention_domain_xtal24m = 9,
32 sysctl_retention_domain_pll0 = 10,
33 sysctl_retention_domain_pll1 = 11,
34 sysctl_retention_domain_pll2 = 12,
35 sysctl_retention_domain_pll3 = 13,
36 sysctl_retention_domain_pll4 = 14,
37 } sysctl_retention_domain_t;
38
39 /**
40 * @brief Clock presets
41 */
42 typedef enum {
43 sysctl_preset_0 = 1 << 0,
44 sysctl_preset_1 = 1 << 1,
45 sysctl_preset_2 = 1 << 2,
46 sysctl_preset_3 = 1 << 3,
47 } sysctl_preset_t;
48
49 /**
50 * @brief Reset domains
51 */
52 typedef enum {
53 sysctl_reset_domain_soc = 0,
54 sysctl_reset_domain_con,
55 sysctl_reset_domain_vis,
56 sysctl_reset_domain_cpu0,
57 sysctl_reset_domain_gpu
58 } sysctl_reset_domain_t;
59
60 /**
61 * @brief Resource
62 */
63 typedef enum {
64 sysctl_resource_cpu0 = SYSCTL_RESOURCE_CPU0,
65 sysctl_resource_cpx0 = SYSCTL_RESOURCE_CPX0,
66 sysctl_resource_pow_cpu0 = SYSCTL_RESOURCE_POW_CPU0,
67 sysctl_resource_rst_soc = SYSCTL_RESOURCE_RST_SOC,
68 sysctl_resource_rst_cpu0 = SYSCTL_RESOURCE_RST_CPU0,
69 sysctl_resource_xtal = SYSCTL_RESOURCE_CLK_SRC_XTAL,
70 sysctl_resource_pll0 = SYSCTL_RESOURCE_CLK_SRC_PLL0,
71 sysctl_resource_clk0_pll0 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0,
72 sysctl_resource_pll1 = SYSCTL_RESOURCE_CLK_SRC_PLL1,
73 sysctl_resource_clk0_pll1 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1,
74 sysctl_resource_clk1_pll1 = SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1,
75 sysctl_resource_pll2 = SYSCTL_RESOURCE_CLK_SRC_PLL2,
76 sysctl_resource_clk0_pll2 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL2,
77 sysctl_resource_clk1_pll2 = SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL2,
78 sysctl_resource_pll3 = SYSCTL_RESOURCE_CLK_SRC_PLL3,
79 sysctl_resource_clk0_pll3 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL3,
80 sysctl_resource_pll4 = SYSCTL_RESOURCE_CLK_SRC_PLL4,
81 sysctl_resource_clk0_pll4 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL4,
82 sysctl_resource_pll0_ref = SYSCTL_RESOURCE_CLK_SRC_PLL0_REF,
83 sysctl_resource_pll1_ref = SYSCTL_RESOURCE_CLK_SRC_PLL1_REF,
84 sysctl_resource_pll2_ref = SYSCTL_RESOURCE_CLK_SRC_PLL2_REF,
85 sysctl_resource_pll3_ref = SYSCTL_RESOURCE_CLK_SRC_PLL3_REF,
86 sysctl_resource_pll4_ref = SYSCTL_RESOURCE_CLK_SRC_PLL4_REF,
87
88 sysctl_resource_clk_top_cpu0 = SYSCTL_RESOURCE_CLK_TOP_CPU0,
89 sysctl_resource_clk_top_mchtmr0 = SYSCTL_RESOURCE_CLK_TOP_MCT0,
90 sysctl_resource_clk_top_gpu0 = SYSCTL_RESOURCE_CLK_TOP_GPU0,
91 sysctl_resource_clk_top_axif = SYSCTL_RESOURCE_CLK_TOP_AXIF,
92 sysctl_resource_clk_top_axis = SYSCTL_RESOURCE_CLK_TOP_AXIS,
93 sysctl_resource_clk_top_axic = SYSCTL_RESOURCE_CLK_TOP_AXIC,
94 sysctl_resource_clk_top_axiv = SYSCTL_RESOURCE_CLK_TOP_AXIV,
95 sysctl_resource_clk_top_axid = SYSCTL_RESOURCE_CLK_TOP_AXID,
96 sysctl_resource_clk_top_can0 = SYSCTL_RESOURCE_CLK_TOP_CAN0,
97 sysctl_resource_clk_top_can1 = SYSCTL_RESOURCE_CLK_TOP_CAN1,
98 sysctl_resource_clk_top_can2 = SYSCTL_RESOURCE_CLK_TOP_CAN2,
99 sysctl_resource_clk_top_can3 = SYSCTL_RESOURCE_CLK_TOP_CAN3,
100 sysctl_resource_clk_top_can4 = SYSCTL_RESOURCE_CLK_TOP_CAN4,
101 sysctl_resource_clk_top_can5 = SYSCTL_RESOURCE_CLK_TOP_CAN5,
102 sysctl_resource_clk_top_can6 = SYSCTL_RESOURCE_CLK_TOP_CAN6,
103 sysctl_resource_clk_top_can7 = SYSCTL_RESOURCE_CLK_TOP_CAN7,
104 sysctl_resource_clk_top_lin0 = SYSCTL_RESOURCE_CLK_TOP_LIN0,
105 sysctl_resource_clk_top_lin1 = SYSCTL_RESOURCE_CLK_TOP_LIN1,
106 sysctl_resource_clk_top_lin2 = SYSCTL_RESOURCE_CLK_TOP_LIN2,
107 sysctl_resource_clk_top_lin3 = SYSCTL_RESOURCE_CLK_TOP_LIN3,
108 sysctl_resource_clk_top_lin4 = SYSCTL_RESOURCE_CLK_TOP_LIN4,
109 sysctl_resource_clk_top_lin5 = SYSCTL_RESOURCE_CLK_TOP_LIN5,
110 sysctl_resource_clk_top_lin6 = SYSCTL_RESOURCE_CLK_TOP_LIN6,
111 sysctl_resource_clk_top_lin7 = SYSCTL_RESOURCE_CLK_TOP_LIN7,
112 sysctl_resource_clk_top_i2c0 = SYSCTL_RESOURCE_CLK_TOP_I2C0,
113 sysctl_resource_clk_top_i2c1 = SYSCTL_RESOURCE_CLK_TOP_I2C1,
114 sysctl_resource_clk_top_i2c2 = SYSCTL_RESOURCE_CLK_TOP_I2C2,
115 sysctl_resource_clk_top_i2c3 = SYSCTL_RESOURCE_CLK_TOP_I2C3,
116 sysctl_resource_clk_top_spi0 = SYSCTL_RESOURCE_CLK_TOP_SPI0,
117 sysctl_resource_clk_top_spi1 = SYSCTL_RESOURCE_CLK_TOP_SPI1,
118 sysctl_resource_clk_top_spi2 = SYSCTL_RESOURCE_CLK_TOP_SPI2,
119 sysctl_resource_clk_top_spi3 = SYSCTL_RESOURCE_CLK_TOP_SPI3,
120 sysctl_resource_clk_top_uart0 = SYSCTL_RESOURCE_CLK_TOP_URT0,
121 sysctl_resource_clk_top_uart1 = SYSCTL_RESOURCE_CLK_TOP_URT1,
122 sysctl_resource_clk_top_uart2 = SYSCTL_RESOURCE_CLK_TOP_URT2,
123 sysctl_resource_clk_top_uart3 = SYSCTL_RESOURCE_CLK_TOP_URT3,
124 sysctl_resource_clk_top_uart4 = SYSCTL_RESOURCE_CLK_TOP_URT4,
125 sysctl_resource_clk_top_uart5 = SYSCTL_RESOURCE_CLK_TOP_URT5,
126 sysctl_resource_clk_top_uart6 = SYSCTL_RESOURCE_CLK_TOP_URT6,
127 sysctl_resource_clk_top_uart7 = SYSCTL_RESOURCE_CLK_TOP_URT7,
128 sysctl_resource_clk_top_gptmr0 = SYSCTL_RESOURCE_CLK_TOP_TMR0,
129 sysctl_resource_clk_top_gptmr1 = SYSCTL_RESOURCE_CLK_TOP_TMR1,
130 sysctl_resource_clk_top_gptmr2 = SYSCTL_RESOURCE_CLK_TOP_TMR2,
131 sysctl_resource_clk_top_gptmr3 = SYSCTL_RESOURCE_CLK_TOP_TMR3,
132 sysctl_resource_clk_top_gptmr4 = SYSCTL_RESOURCE_CLK_TOP_TMR4,
133 sysctl_resource_clk_top_gptmr5 = SYSCTL_RESOURCE_CLK_TOP_TMR5,
134 sysctl_resource_clk_top_gptmr6 = SYSCTL_RESOURCE_CLK_TOP_TMR6,
135 sysctl_resource_clk_top_gptmr7 = SYSCTL_RESOURCE_CLK_TOP_TMR7,
136 sysctl_resource_clk_top_xpi0 = SYSCTL_RESOURCE_CLK_TOP_XPI0,
137 sysctl_resource_clk_top_xram = SYSCTL_RESOURCE_CLK_TOP_XRAM,
138 sysctl_resource_clk_top_ana0 = SYSCTL_RESOURCE_CLK_TOP_ANA0,
139 sysctl_resource_clk_top_ana1 = SYSCTL_RESOURCE_CLK_TOP_ANA1,
140 sysctl_resource_clk_top_aud0 = SYSCTL_RESOURCE_CLK_TOP_AUD0,
141 sysctl_resource_clk_top_aud1 = SYSCTL_RESOURCE_CLK_TOP_AUD1,
142 sysctl_resource_clk_top_aud2 = SYSCTL_RESOURCE_CLK_TOP_AUD2,
143 sysctl_resource_clk_top_aud3 = SYSCTL_RESOURCE_CLK_TOP_AUD3,
144 sysctl_resource_clk_top_eth0 = SYSCTL_RESOURCE_CLK_TOP_ETH0,
145 sysctl_resource_clk_top_ptp0 = SYSCTL_RESOURCE_CLK_TOP_PTP0,
146 sysctl_resource_clk_top_sdc0 = SYSCTL_RESOURCE_CLK_TOP_SDC0,
147 sysctl_resource_clk_top_sdc1 = SYSCTL_RESOURCE_CLK_TOP_SDC1,
148 sysctl_resource_clk_top_ntm0 = SYSCTL_RESOURCE_CLK_TOP_NTM0,
149 sysctl_resource_clk_top_ref0 = SYSCTL_RESOURCE_CLK_TOP_REF0,
150 sysctl_resource_clk_top_ref1 = SYSCTL_RESOURCE_CLK_TOP_REF1,
151 sysctl_resource_clk_top_cam0 = SYSCTL_RESOURCE_CLK_TOP_CAM0,
152 sysctl_resource_clk_top_cam1 = SYSCTL_RESOURCE_CLK_TOP_CAM1,
153 sysctl_resource_clk_top_lcd0 = SYSCTL_RESOURCE_CLK_TOP_LCD0,
154 sysctl_resource_clk_top_lcd1 = SYSCTL_RESOURCE_CLK_TOP_LCD1,
155 sysctl_resource_clk_top_csi0 = SYSCTL_RESOURCE_CLK_TOP_CSI0,
156 sysctl_resource_clk_top_csi1 = SYSCTL_RESOURCE_CLK_TOP_CSI1,
157 sysctl_resource_clk_top_adc0 = SYSCTL_RESOURCE_CLK_TOP_ADC0,
158 sysctl_resource_clk_top_adc1 = SYSCTL_RESOURCE_CLK_TOP_ADC1,
159 sysctl_resource_clk_top_i2s0 = SYSCTL_RESOURCE_CLK_TOP_I2S0,
160 sysctl_resource_clk_top_i2s1 = SYSCTL_RESOURCE_CLK_TOP_I2S1,
161 sysctl_resource_clk_top_i2s2 = SYSCTL_RESOURCE_CLK_TOP_I2S2,
162 sysctl_resource_clk_top_i2s3 = SYSCTL_RESOURCE_CLK_TOP_I2S3,
163
164
165 sysctl_resource_linkable_start = 256,
166 sysctl_resource_axis = SYSCTL_RESOURCE_AXIS,
167 sysctl_resource_axic = SYSCTL_RESOURCE_AXIC,
168 sysctl_resource_axiv = SYSCTL_RESOURCE_AXIV,
169 sysctl_resource_axig = SYSCTL_RESOURCE_AXIG,
170 sysctl_resource_lmm0 = SYSCTL_RESOURCE_LMM0,
171 sysctl_resource_mchtmr0 = SYSCTL_RESOURCE_MCT0,
172 sysctl_resource_rom0 = SYSCTL_RESOURCE_ROM0,
173 sysctl_resource_ddr0 = SYSCTL_RESOURCE_DDR0,
174 sysctl_resource_xram = SYSCTL_RESOURCE_XRAM,
175 sysctl_resource_can0 = SYSCTL_RESOURCE_CAN0,
176 sysctl_resource_can1 = SYSCTL_RESOURCE_CAN1,
177 sysctl_resource_can2 = SYSCTL_RESOURCE_CAN2,
178 sysctl_resource_can3 = SYSCTL_RESOURCE_CAN3,
179 sysctl_resource_can4 = SYSCTL_RESOURCE_CAN4,
180 sysctl_resource_can5 = SYSCTL_RESOURCE_CAN5,
181 sysctl_resource_can6 = SYSCTL_RESOURCE_CAN6,
182 sysctl_resource_can7 = SYSCTL_RESOURCE_CAN7,
183 sysctl_resource_ptpc = SYSCTL_RESOURCE_PTPC,
184 sysctl_resource_crc0 = SYSCTL_RESOURCE_CRC0,
185 sysctl_resource_oamp = SYSCTL_RESOURCE_OAMP,
186 sysctl_resource_lin0 = SYSCTL_RESOURCE_LIN0,
187 sysctl_resource_lin1 = SYSCTL_RESOURCE_LIN1,
188 sysctl_resource_lin2 = SYSCTL_RESOURCE_LIN2,
189 sysctl_resource_lin3 = SYSCTL_RESOURCE_LIN3,
190 sysctl_resource_lin4 = SYSCTL_RESOURCE_LIN4,
191 sysctl_resource_lin5 = SYSCTL_RESOURCE_LIN5,
192 sysctl_resource_lin6 = SYSCTL_RESOURCE_LIN6,
193 sysctl_resource_lin7 = SYSCTL_RESOURCE_LIN7,
194 sysctl_resource_i2c0 = SYSCTL_RESOURCE_I2C0,
195 sysctl_resource_i2c1 = SYSCTL_RESOURCE_I2C1,
196 sysctl_resource_i2c2 = SYSCTL_RESOURCE_I2C2,
197 sysctl_resource_i2c3 = SYSCTL_RESOURCE_I2C3,
198 sysctl_resource_spi0 = SYSCTL_RESOURCE_SPI0,
199 sysctl_resource_spi1 = SYSCTL_RESOURCE_SPI1,
200 sysctl_resource_spi2 = SYSCTL_RESOURCE_SPI2,
201 sysctl_resource_spi3 = SYSCTL_RESOURCE_SPI3,
202 sysctl_resource_uart0 = SYSCTL_RESOURCE_URT0,
203 sysctl_resource_uart1 = SYSCTL_RESOURCE_URT1,
204 sysctl_resource_uart2 = SYSCTL_RESOURCE_URT2,
205 sysctl_resource_uart3 = SYSCTL_RESOURCE_URT3,
206 sysctl_resource_uart4 = SYSCTL_RESOURCE_URT4,
207 sysctl_resource_uart5 = SYSCTL_RESOURCE_URT5,
208 sysctl_resource_uart6 = SYSCTL_RESOURCE_URT6,
209 sysctl_resource_uart7 = SYSCTL_RESOURCE_URT7,
210 sysctl_resource_wdg0 = SYSCTL_RESOURCE_WDG0,
211 sysctl_resource_wdg1 = SYSCTL_RESOURCE_WDG1,
212 sysctl_resource_mbx0 = SYSCTL_RESOURCE_MBX0,
213 sysctl_resource_mbx1 = SYSCTL_RESOURCE_MBX1,
214 sysctl_resource_gptmr0 = SYSCTL_RESOURCE_TMR0,
215 sysctl_resource_gptmr1 = SYSCTL_RESOURCE_TMR1,
216 sysctl_resource_gptmr2 = SYSCTL_RESOURCE_TMR2,
217 sysctl_resource_gptmr3 = SYSCTL_RESOURCE_TMR3,
218 sysctl_resource_gptmr4 = SYSCTL_RESOURCE_TMR4,
219 sysctl_resource_gptmr5 = SYSCTL_RESOURCE_TMR5,
220 sysctl_resource_gptmr6 = SYSCTL_RESOURCE_TMR6,
221 sysctl_resource_gptmr7 = SYSCTL_RESOURCE_TMR7,
222 sysctl_resource_i2s0 = SYSCTL_RESOURCE_I2S0,
223 sysctl_resource_i2s1 = SYSCTL_RESOURCE_I2S1,
224 sysctl_resource_i2s2 = SYSCTL_RESOURCE_I2S2,
225 sysctl_resource_i2s3 = SYSCTL_RESOURCE_I2S3,
226 sysctl_resource_pdm0 = SYSCTL_RESOURCE_PDM0,
227 sysctl_resource_dao0 = SYSCTL_RESOURCE_DAO0,
228 sysctl_resource_smix = SYSCTL_RESOURCE_SMIX,
229 sysctl_resource_rng0 = SYSCTL_RESOURCE_RNG0,
230 sysctl_resource_sdp0 = SYSCTL_RESOURCE_SDP0,
231 sysctl_resource_kman = SYSCTL_RESOURCE_KMAN,
232 sysctl_resource_gpio = SYSCTL_RESOURCE_GPIO,
233 sysctl_resource_adc0 = SYSCTL_RESOURCE_ADC0,
234 sysctl_resource_adc1 = SYSCTL_RESOURCE_ADC1,
235 sysctl_resource_sdm0 = SYSCTL_RESOURCE_SDM0,
236 sysctl_resource_dma0 = SYSCTL_RESOURCE_HDMA,
237 sysctl_resource_dma1 = SYSCTL_RESOURCE_XDMA,
238 sysctl_resource_xpi0 = SYSCTL_RESOURCE_XPI0,
239 sysctl_resource_ffa0 = SYSCTL_RESOURCE_FFA0,
240 sysctl_resource_tsns = SYSCTL_RESOURCE_TSNS,
241 sysctl_resource_eth0 = SYSCTL_RESOURCE_ETH0,
242 sysctl_resource_usb0 = SYSCTL_RESOURCE_USB0,
243 sysctl_resource_sdc0 = SYSCTL_RESOURCE_SDC0,
244 sysctl_resource_sdc1 = SYSCTL_RESOURCE_SDC1,
245 sysctl_resource_ntm0 = SYSCTL_RESOURCE_NTM0,
246 sysctl_resource_ref0 = SYSCTL_RESOURCE_REF0,
247 sysctl_resource_ref1 = SYSCTL_RESOURCE_REF1,
248 sysctl_resource_cam0 = SYSCTL_RESOURCE_CAM0,
249 sysctl_resource_cam1 = SYSCTL_RESOURCE_CAM1,
250 sysctl_resource_pdma = SYSCTL_RESOURCE_PDMA,
251 sysctl_resource_jpeg = SYSCTL_RESOURCE_JPEG,
252 sysctl_resource_lcd0 = SYSCTL_RESOURCE_LCD0,
253 sysctl_resource_lcd1 = SYSCTL_RESOURCE_LCD1,
254 sysctl_resource_gwc0 = SYSCTL_RESOURCE_GWC0,
255 sysctl_resource_gwc1 = SYSCTL_RESOURCE_GWC1,
256 sysctl_resource_csi0 = SYSCTL_RESOURCE_CSI0,
257 sysctl_resource_csi1 = SYSCTL_RESOURCE_CSI1,
258 sysctl_resource_dsi0 = SYSCTL_RESOURCE_DSI0,
259 sysctl_resource_dsi1 = SYSCTL_RESOURCE_DSI1,
260 sysctl_resource_lvb0 = SYSCTL_RESOURCE_LVB0,
261 sysctl_resource_lcb0 = SYSCTL_RESOURCE_LCB0,
262 sysctl_resource_gpu0 = SYSCTL_RESOURCE_GPU0,
263 sysctl_resource_linkable_end,
264 sysctl_resource_end = sysctl_resource_linkable_end,
265 } sysctl_resource_t;
266
267 /**
268 * @brief Resource modes
269 */
270 typedef enum {
271 sysctl_resource_mode_auto = 0,
272 sysctl_resource_mode_force_on,
273 sysctl_resource_mode_force_off,
274 } sysctl_resource_mode_t;
275
276 /**
277 * @brief Clock nodes
278 */
279 typedef enum {
280 clock_node_cpu0 = SYSCTL_CLOCK_CLK_TOP_CPU0,
281 clock_node_mchtmr0 = SYSCTL_CLOCK_CLK_TOP_MCT0,
282 clock_node_gpu0 = SYSCTL_CLOCK_CLK_TOP_GPU0,
283 clock_node_axif,
284 clock_node_axis,
285 clock_node_axic,
286 clock_node_axiv,
287 clock_node_axid,
288 clock_node_can0 = SYSCTL_CLOCK_CLK_TOP_CAN0,
289 clock_node_can1 = SYSCTL_CLOCK_CLK_TOP_CAN1,
290 clock_node_can2 = SYSCTL_CLOCK_CLK_TOP_CAN2,
291 clock_node_can3 = SYSCTL_CLOCK_CLK_TOP_CAN3,
292 clock_node_can4,
293 clock_node_can5,
294 clock_node_can6,
295 clock_node_can7,
296 clock_node_lin0 = SYSCTL_CLOCK_CLK_TOP_LIN0,
297 clock_node_lin1 = SYSCTL_CLOCK_CLK_TOP_LIN1,
298 clock_node_lin2 = SYSCTL_CLOCK_CLK_TOP_LIN2,
299 clock_node_lin3 = SYSCTL_CLOCK_CLK_TOP_LIN3,
300 clock_node_lin4,
301 clock_node_lin5,
302 clock_node_lin6,
303 clock_node_lin7,
304 clock_node_i2c0 = SYSCTL_CLOCK_CLK_TOP_I2C0,
305 clock_node_i2c1 = SYSCTL_CLOCK_CLK_TOP_I2C1,
306 clock_node_i2c2 = SYSCTL_CLOCK_CLK_TOP_I2C2,
307 clock_node_i2c3 = SYSCTL_CLOCK_CLK_TOP_I2C3,
308 clock_node_spi0 = SYSCTL_CLOCK_CLK_TOP_SPI0,
309 clock_node_spi1 = SYSCTL_CLOCK_CLK_TOP_SPI1,
310 clock_node_spi2 = SYSCTL_CLOCK_CLK_TOP_SPI2,
311 clock_node_spi3 = SYSCTL_CLOCK_CLK_TOP_SPI3,
312 clock_node_uart0 = SYSCTL_CLOCK_CLK_TOP_URT0,
313 clock_node_uart1 = SYSCTL_CLOCK_CLK_TOP_URT1,
314 clock_node_uart2 = SYSCTL_CLOCK_CLK_TOP_URT2,
315 clock_node_uart3 = SYSCTL_CLOCK_CLK_TOP_URT3,
316 clock_node_uart4 = SYSCTL_CLOCK_CLK_TOP_URT4,
317 clock_node_uart5 = SYSCTL_CLOCK_CLK_TOP_URT5,
318 clock_node_uart6 = SYSCTL_CLOCK_CLK_TOP_URT6,
319 clock_node_uart7 = SYSCTL_CLOCK_CLK_TOP_URT7,
320
321 clock_node_gptmr0 = SYSCTL_CLOCK_CLK_TOP_TMR0,
322 clock_node_gptmr1 = SYSCTL_CLOCK_CLK_TOP_TMR1,
323 clock_node_gptmr2 = SYSCTL_CLOCK_CLK_TOP_TMR2,
324 clock_node_gptmr3 = SYSCTL_CLOCK_CLK_TOP_TMR3,
325 clock_node_gptmr4 = SYSCTL_CLOCK_CLK_TOP_TMR4,
326 clock_node_gptmr5 = SYSCTL_CLOCK_CLK_TOP_TMR5,
327 clock_node_gptmr6 = SYSCTL_CLOCK_CLK_TOP_TMR6,
328 clock_node_gptmr7 = SYSCTL_CLOCK_CLK_TOP_TMR7,
329 clock_node_xpi0 = SYSCTL_CLOCK_CLK_TOP_XPI0,
330 clock_node_xram,
331 clock_node_ana0 = SYSCTL_CLOCK_CLK_TOP_ANA0,
332 clock_node_ana1 = SYSCTL_CLOCK_CLK_TOP_ANA1,
333 clock_node_aud0,
334 clock_node_aud1,
335 clock_node_aud2,
336 clock_node_aud3,
337 clock_node_eth0,
338 clock_node_ptp0,
339 clock_node_sdc0,
340 clock_node_sdc1,
341 clock_node_ntm0,
342 clock_node_ref0 = SYSCTL_CLOCK_CLK_TOP_REF0,
343 clock_node_ref1 = SYSCTL_CLOCK_CLK_TOP_REF1,
344 clock_node_cam0,
345 clock_node_cam1,
346 clock_node_lcd0,
347 clock_node_lcd1,
348 clock_node_csi0,
349 clock_node_csi1,
350
351 clock_node_adc_start,
352 clock_node_adc0 = clock_node_adc_start,
353 clock_node_adc1,
354
355 clock_node_i2s_start,
356 clock_node_i2s0 = clock_node_i2s_start,
357 clock_node_i2s1,
358 clock_node_i2s2,
359 clock_node_i2s3,
360
361 clock_node_end,
362 clock_node_invalid = 0xff,
363 } clock_node_t;
364
365 /**
366 * @brief General clock sources
367 */
368 typedef enum {
369 clock_source_osc0_clk0 = 0,
370 clock_source_pll0_clk0 = 1,
371 clock_source_pll1_clk0 = 2,
372 clock_source_pll1_clk1 = 3,
373 clock_source_pll2_clk0 = 4,
374 clock_source_pll2_clk1 = 5,
375 clock_source_pll3_clk0 = 6,
376 clock_source_pll4_clk0 = 7,
377 clock_source_general_source_end,
378 } clock_source_t;
379
380 /**
381 * @brief ADC clock sources
382 */
383 typedef enum {
384 clock_source_adc_ana_clock = 0,
385 clock_source_adc_ahb_clock = 1,
386 clock_source_adc_clk_end,
387 } clock_source_adc_t;
388
389 /**
390 * @brief I2S clock sources
391 */
392 typedef enum {
393 clock_source_i2s_aud_clock = 0,
394 clock_source_i2s_ahb_clock = 1,
395 clock_source_i2s_clk_end,
396 } clock_source_i2s_t;
397
398 /**
399 * @brief CPU low power mode
400 */
401 typedef enum {
402 cpu_lp_mode_gate_cpu_clock = 0,
403 cpu_lp_mode_trigger_system_lp = 0x1,
404 cpu_lp_mode_ungate_cpu_clock = 0x2,
405 } cpu_lp_mode_t;
406
407 /**
408 * @brief Monitor targets
409 */
410 /* FIXME */
411 typedef enum {
412 monitor_target_clk_32k = 0,
413 monitor_target_clk_irc24m = 1,
414 monitor_target_clk_xtal_24m = 2,
415 monitor_target_clk_usb0_phy = 3,
416 monitor_target_clk_usb1_phy = 4,
417 monitor_target_clk0_osc0 = 8,
418 monitor_target_clk0_pll0 = 9,
419 monitor_target_clk0_pll1 = 10,
420 monitor_target_clk1_pll1 = 11,
421 monitor_target_clk0_pll2 = 12,
422 monitor_target_clk1_pll2 = 13,
423 monitor_target_clk0_pll3 = 14,
424 monitor_target_clk0_pll4 = 15,
425 monitor_target_clk_top_cpu0 = 128,
426 monitor_target_clk_top_mchtmr0 = 129,
427 monitor_target_clk_top_cpu1 = 130,
428 monitor_target_clk_top_mchtmr1 = 131,
429 monitor_target_clk_top_axi0 = 132,
430 monitor_target_clk_top_axi1 = 133,
431 monitor_target_clk_top_axi2 = 134,
432 monitor_target_clk_top_ahb0 = 135,
433 monitor_target_clk_top_dram = 136,
434 monitor_target_clk_top_xpi0 = 137,
435 monitor_target_clk_top_xpi1 = 138,
436 monitor_target_clk_top_gptmr0 = 139,
437 monitor_target_clk_top_gptmr1 = 140,
438 monitor_target_clk_top_gptmr2 = 141,
439 monitor_target_clk_top_gptmr3 = 142,
440 monitor_target_clk_top_gptmr4 = 143,
441 monitor_target_clk_top_gptmr5 = 144,
442 monitor_target_clk_top_gptmr6 = 145,
443 monitor_target_clk_top_gptmr7 = 146,
444 monitor_target_clk_top_uart0 = 147,
445 monitor_target_clk_top_uart1 = 148,
446 monitor_target_clk_top_uart2 = 149,
447 monitor_target_clk_top_uart3 = 150,
448 monitor_target_clk_top_uart4 = 151,
449 monitor_target_clk_top_uart5 = 152,
450 monitor_target_clk_top_uart6 = 153,
451 monitor_target_clk_top_uart7 = 154,
452 monitor_target_clk_top_uart8 = 155,
453 monitor_target_clk_top_uart9 = 156,
454 monitor_target_clk_top_uarta = 157,
455 monitor_target_clk_top_uartb = 158,
456 monitor_target_clk_top_uartc = 159,
457 monitor_target_clk_top_uartd = 160,
458 monitor_target_clk_top_uarte = 161,
459 monitor_target_clk_top_uartf = 162,
460 monitor_target_clk_top_i2c0 = 163,
461 monitor_target_clk_top_i2c1 = 164,
462 monitor_target_clk_top_i2c2 = 165,
463 monitor_target_clk_top_i2c3 = 166,
464 monitor_target_clk_top_spi0 = 167,
465 monitor_target_clk_top_spi1 = 168,
466 monitor_target_clk_top_spi2 = 169,
467 monitor_target_clk_top_spi3 = 170,
468 monitor_target_clk_top_can0 = 171,
469 monitor_target_clk_top_can1 = 172,
470 monitor_target_clk_top_can2 = 173,
471 monitor_target_clk_top_can3 = 174,
472 monitor_target_clk_top_ptpc = 175,
473 monitor_target_clk_top_ana0 = 176,
474 monitor_target_clk_top_ana1 = 177,
475 monitor_target_clk_top_ana2 = 178,
476 monitor_target_clk_top_aud0 = 179,
477 monitor_target_clk_top_aud1 = 180,
478 monitor_target_clk_top_aud2 = 181,
479 monitor_target_clk_top_dis0 = 182,
480 monitor_target_clk_top_cam0 = 183,
481 monitor_target_clk_top_cam1 = 184,
482 monitor_target_clk_top_eth0 = 185,
483 monitor_target_clk_top_eth1 = 186,
484 monitor_target_clk_top_ptp0 = 187,
485 monitor_target_clk_top_ptp1 = 188,
486 monitor_target_clk_top_ref0 = 189,
487 monitor_target_clk_top_ref1 = 190,
488 monitor_target_clk_top_ntmr0 = 191,
489 monitor_target_clk_top_ntmr1 = 192,
490 monitor_target_clk_top_sdxc0 = 193,
491 monitor_target_clk_top_sdxc1 = 194,
492 } monitor_target_t;
493
494 /**
495 * @brief Monitor work mode
496 */
497 typedef enum {
498 monitor_work_mode_compare = 0,
499 monitor_work_mode_record = 1,
500 } monitor_work_mode_t;
501
502 /**
503 * @brief Monitor accuracy
504 */
505 typedef enum {
506 monitor_accuracy_1khz = 0,
507 monitor_accuracy_1hz = 1,
508 } monitor_accuracy_t;
509
510 /**
511 * @brief Monitor reference clock source
512 */
513 typedef enum {
514 monitor_reference_32khz = 0,
515 monitor_reference_24mhz = 1,
516 } monitor_reference_t;
517
518 /**
519 * @brief Monitor config
520 */
521 typedef struct monitor_config {
522 uint8_t divide_by; /**< Divider to be used for OBS output to pads */
523 monitor_work_mode_t mode; /**< Monitor work mode */
524 monitor_accuracy_t accuracy; /**< Monitor reference accuracy */
525 monitor_reference_t reference; /**< Monitor reference clock source */
526 monitor_target_t target; /**< Monitor target */
527 bool start_measure; /**< Start flag */
528 bool enable_output; /**< Enable output to pads if true */
529 uint32_t high_limit; /**< Maximum frequency at compare mode */
530 uint32_t low_limit; /**< Minimum frequency at compare mode */
531 } monitor_config_t;
532
533 typedef enum {
534 cpu_event_flag_mask_reset = SYSCTL_CPU_LP_RESET_FLAG_MASK,
535 cpu_event_flag_mask_sleep = SYSCTL_CPU_LP_SLEEP_FLAG_MASK,
536 cpu_event_flag_mask_wake = SYSCTL_CPU_LP_WAKE_FLAG_MASK,
537 cpu_event_flag_mask_all = SYSCTL_CPU_LP_RESET_FLAG_MASK | SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK,
538 } cpu_event_flag_mask_t;
539
540 #ifdef __cplusplus
541 extern "C" {
542 #endif
543
544 /**
545 * @brief Check if monitor result is valid
546 *
547 * @param[in] ptr SYSCTL_Type base address
548 * @param[in] monitor_index specific monitor instance to be used
549 *
550 * @return true if it is valid
551 */
sysctl_monitor_result_is_valid(SYSCTL_Type * ptr,uint8_t monitor_index)552 static inline bool sysctl_monitor_result_is_valid(SYSCTL_Type *ptr, uint8_t monitor_index)
553 {
554 return SYSCTL_MONITOR_CONTROL_VALID_GET(ptr->MONITOR[monitor_index].CONTROL);
555 }
556
557 /**
558 * @brief Get target monitor instance result
559 *
560 * @param[in] ptr SYSCTL_Type base address
561 * @param[in] monitor_index specific monitor instance to be used
562 * @return value of monitor result measured
563 */
sysctl_monitor_get_current_result(SYSCTL_Type * ptr,uint8_t monitor_index)564 static inline uint32_t sysctl_monitor_get_current_result(SYSCTL_Type *ptr, uint8_t monitor_index)
565 {
566 while (!sysctl_monitor_result_is_valid(ptr, monitor_index)) {
567 }
568 return ptr->MONITOR[monitor_index].CURRENT;
569 }
570
571 /**
572 * @brief Set work mode for target monitor instance
573 *
574 * @param[in] ptr SYSCTL_Type base address
575 * @param[in] monitor_index specific monitor instance to be used
576 * @param[in] mode monitor_work_mode_compare, monitor_work_mode_record
577 */
sysctl_monitor_set_work_mode(SYSCTL_Type * ptr,uint8_t monitor_index,monitor_work_mode_t mode)578 static inline void sysctl_monitor_set_work_mode(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_work_mode_t mode)
579 {
580 ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & ~SYSCTL_MONITOR_CONTROL_MODE_MASK) |
581 (SYSCTL_MONITOR_CONTROL_MODE_SET(mode));
582 }
583
584 /**
585 * @brief Set minimum frequency for target monitor instance
586 *
587 * @param[in] ptr SYSCTL_Type base address
588 * @param[in] monitor_index specific monitor instance to be used
589 * @param[in] limit measurement low limit
590 */
sysctl_monitor_set_limit_low(SYSCTL_Type * ptr,uint8_t monitor_index,uint32_t limit)591 static inline hpm_stat_t sysctl_monitor_set_limit_low(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit)
592 {
593 if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) {
594 return status_invalid_argument;
595 }
596 ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit);
597 return status_success;
598 }
599
600 /**
601 * @brief Set maximum frequency for target monitor instance
602 *
603 * @param[in] ptr SYSCTL_Type base address
604 * @param[in] monitor_index specific monitor instance to be used
605 * @param[in] limit measurement high limit
606 */
sysctl_monitor_set_limit_high(SYSCTL_Type * ptr,uint8_t monitor_index,uint32_t limit)607 static inline hpm_stat_t sysctl_monitor_set_limit_high(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit)
608 {
609 if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) {
610 return status_invalid_argument;
611 }
612 ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit);
613 return status_success;
614 }
615
616 /**
617 * @brief Set frequency limit for target monitor instance
618 *
619 * @param[in] ptr SYSCTL_Type base address
620 * @param[in] monitor_index specific monitor instance to be used
621 * @param[in] limit_high measurement high limit
622 * @param[in] limit_low measurement low limit
623 */
sysctl_monitor_set_limit(SYSCTL_Type * ptr,uint8_t monitor_index,uint32_t limit_high,uint32_t limit_low)624 static inline hpm_stat_t sysctl_monitor_set_limit(SYSCTL_Type *ptr,
625 uint8_t monitor_index,
626 uint32_t limit_high,
627 uint32_t limit_low)
628 {
629 if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) {
630 return status_invalid_argument;
631 }
632 ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit_high);
633 ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit_low);
634 return status_success;
635 }
636
637 /**
638 * @brief Get maximum frequency for target monitor instance
639 *
640 * @param[in] ptr SYSCTL_Type base address
641 * @param[in] monitor_index specific monitor instance to be used
642 * @return current high limit value
643 */
sysctl_monitor_get_limit_high(SYSCTL_Type * ptr,uint32_t monitor_index)644 static inline uint32_t sysctl_monitor_get_limit_high(SYSCTL_Type *ptr, uint32_t monitor_index)
645 {
646 return SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(ptr->MONITOR[monitor_index].HIGH_LIMIT);
647 }
648
649 /**
650 * @brief Get minimum frequency for target monitor instance
651 *
652 * @param[in] ptr SYSCTL_Type base address
653 * @param[in] monitor_index specific monitor instance to be used
654 * @return current low limit value
655 */
sysctl_monitor_get_limit_low(SYSCTL_Type * ptr,uint32_t monitor_index)656 static inline uint32_t sysctl_monitor_get_limit_low(SYSCTL_Type *ptr, uint32_t monitor_index)
657 {
658 return SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(ptr->MONITOR[monitor_index].LOW_LIMIT);
659 }
660
661 /**
662 * @brief Measure specific target frequency
663 *
664 * @param[in] ptr SYSCTL_Type base address
665 * @param[in] monitor_index specific monitor instance to be used
666 * @param[in] target monitor target to be measured
667 * @param[in] enable_output enable clock obs output
668 * @return frequency of monitor target measured
669 */
670 uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr,
671 uint8_t monitor_index,
672 monitor_target_t target,
673 bool enable_output);
674
675 /**
676 * @brief Link current CPU core its own group
677 *
678 * Once it is linked, peripherals state in that group will keep on as long as this core is not in low power mode
679 *
680 * @param[in] ptr SYSCTL_Type base address
681 * @param[in] cpu_index cpu index to enable its own affiliated group
682 */
sysctl_set_enable_cpu_affiliate(SYSCTL_Type * ptr,uint8_t cpu_index)683 static inline void sysctl_set_enable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index)
684 {
685 ptr->AFFILIATE[cpu_index].SET = 1 << cpu_index;
686 }
687
688 /**
689 * @brief Unlink current CPU core with its own group
690 *
691 * @param[in] ptr SYSCTL_Type base address
692 * @param[in] cpu_index cpu index to enable its own affiliated group
693 */
sysctl_set_disable_cpu_affiliate(SYSCTL_Type * ptr,uint8_t cpu_index)694 static inline void sysctl_set_disable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index)
695 {
696 ptr->AFFILIATE[cpu_index].CLEAR = 1 << cpu_index;
697 }
698
699 /**
700 * @brief Check if any resource is busy
701 *
702 * @param[in] ptr SYSCTL_Type base address
703 * @return true if any resource is busy
704 */
sysctl_resource_any_is_busy(SYSCTL_Type * ptr)705 static inline bool sysctl_resource_any_is_busy(SYSCTL_Type *ptr)
706 {
707 return ptr->RESOURCE[0] & SYSCTL_RESOURCE_GLB_BUSY_MASK;
708 }
709
710 /**
711 * @brief Check if specific target is busy
712 *
713 * @param[in] ptr SYSCTL_Type base address
714 * @param[in] resource target resource index
715 * @return true if target resource is busy
716 */
sysctl_resource_target_is_busy(SYSCTL_Type * ptr,sysctl_resource_t resource)717 static inline bool sysctl_resource_target_is_busy(SYSCTL_Type *ptr, sysctl_resource_t resource)
718 {
719 return ptr->RESOURCE[resource] & SYSCTL_RESOURCE_LOC_BUSY_MASK;
720 }
721
722 /**
723 * @brief Set target mode
724 *
725 * @param[in] ptr SYSCTL_Type base address
726 * @param[in] resource target resource index
727 * @param[in] mode target resource mode
728 */
sysctl_resource_target_set_mode(SYSCTL_Type * ptr,sysctl_resource_t resource,sysctl_resource_mode_t mode)729 static inline void sysctl_resource_target_set_mode(SYSCTL_Type *ptr,
730 sysctl_resource_t resource,
731 sysctl_resource_mode_t mode)
732 {
733 ptr->RESOURCE[resource] = (ptr->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | SYSCTL_RESOURCE_MODE_SET(mode);
734 }
735
736 /**
737 * @brief Get target mode
738 *
739 * @param[in] ptr SYSCTL_Type base address
740 * @param[in] resource target resource index
741 * @return target resource mode
742 */
sysctl_resource_target_get_mode(SYSCTL_Type * ptr,sysctl_resource_t resource)743 static inline uint8_t sysctl_resource_target_get_mode(SYSCTL_Type *ptr,
744 sysctl_resource_t resource)
745 {
746 return SYSCTL_RESOURCE_MODE_GET(ptr->RESOURCE[resource]);
747 }
748
749 /**
750 * @brief Disable resource retention when specific CPU enters stop mode
751 *
752 * @param[in] ptr SYSCTL_Type base address
753 * @param[in] cpu_index cpu index
754 * @param[in] mask bit mask to clear
755 */
sysctl_cpu_lp_clear_retention_with_mask(SYSCTL_Type * ptr,uint8_t cpu_index,uint32_t mask)756 static inline void sysctl_cpu_lp_clear_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask)
757 {
758 ptr->RETENTION[cpu_index].CLEAR = mask;
759 }
760
761 /**
762 * @brief Enable resource retention when specific CPU enters stop mode
763 *
764 * @param[in] ptr SYSCTL_Type base address
765 * @param[in] cpu_index cpu index
766 * @param[in] mask bit mask to set
767 */
sysctl_cpu_lp_set_retention_with_mask(SYSCTL_Type * ptr,uint8_t cpu_index,uint32_t mask)768 static inline void sysctl_cpu_lp_set_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask)
769 {
770 ptr->RETENTION[cpu_index].SET = mask;
771 }
772
773 /**
774 * @brief Retain target domain for specific CPU
775 *
776 * @param[in] ptr SYSCTL_Type base address
777 * @param[in] cpu_index CPU index
778 * @param[in] domain target domain power to be retained
779 * @param[in] retain_mem set true to retain memory/register of target domain
780 */
sysctl_cpu_lp_retain_domain(SYSCTL_Type * ptr,uint8_t cpu_index,sysctl_retention_domain_t domain,bool retain_mem)781 static inline void sysctl_cpu_lp_retain_domain(SYSCTL_Type *ptr,
782 uint8_t cpu_index,
783 sysctl_retention_domain_t domain,
784 bool retain_mem)
785 {
786 uint8_t set_mask = 0x1;
787 if ((domain < sysctl_retention_domain_xtal24m) && (domain != sysctl_retention_domain_con)) {
788 set_mask = retain_mem ? 0x3 : 0x1;
789 }
790 ptr->RETENTION[cpu_index].SET = (set_mask << domain);
791 }
792
793 /**
794 * @brief Enable resource retention when specific CPU enters stop mode
795 *
796 * @param[in] ptr SYSCTL_Type base address
797 * @param[in] cpu_index cpu index
798 * @param[in] value value to be set
799 */
sysctl_set_cpu_lp_retention(SYSCTL_Type * ptr,uint8_t cpu_index,uint32_t value)800 static inline void sysctl_set_cpu_lp_retention(SYSCTL_Type *ptr,
801 uint8_t cpu_index,
802 uint32_t value)
803 {
804 ptr->RETENTION[cpu_index].VALUE = value;
805 }
806
807 /**
808 * @brief Enable resource retention when CPU0 enters stop mode
809 *
810 * @param[in] ptr SYSCTL_Type base address
811 * @param[in] value value to be set
812 */
sysctl_set_cpu0_lp_retention(SYSCTL_Type * ptr,uint32_t value)813 static inline void sysctl_set_cpu0_lp_retention(SYSCTL_Type *ptr, uint32_t value)
814 {
815 sysctl_set_cpu_lp_retention(ptr, 0, value);
816 }
817
818
819 /**
820 * @brief Check if any clock is busy
821 *
822 * @param[in] ptr SYSCTL_Type base address
823 * @return true if any clock is busy
824 */
sysctl_clock_any_is_busy(SYSCTL_Type * ptr)825 static inline bool sysctl_clock_any_is_busy(SYSCTL_Type *ptr)
826 {
827 return ptr->CLOCK[0] & SYSCTL_CLOCK_GLB_BUSY_MASK;
828 }
829
830 /**
831 * @brief Clear CPU event flags
832 *
833 * @param[in] ptr SYSCTL_Type base address
834 * @param[in] cpu_index CPU index
835 * @param[in] flags flag mask to be cleared
836 */
sysctl_clear_cpu_flags(SYSCTL_Type * ptr,uint8_t cpu_index,cpu_event_flag_mask_t flags)837 static inline void sysctl_clear_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_event_flag_mask_t flags)
838 {
839 ptr->CPU[cpu_index].LP |= ((SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK) & flags);
840 }
841
842 /**
843 * @brief Clear CPU0 event flags
844 *
845 * @param[in] ptr SYSCTL_Type base address
846 * @param[in] flags flag mask to be cleared
847 */
sysctl_clear_cpu0_flags(SYSCTL_Type * ptr,cpu_event_flag_mask_t flags)848 static inline void sysctl_clear_cpu0_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags)
849 {
850 sysctl_clear_cpu_flags(ptr, 0, flags);
851 }
852
853 /**
854 * @brief Check if target clock is busy
855 *
856 * @param[in] ptr SYSCTL_Type base address
857 * @param[in] clock target clock
858 * @return true if target clock is busy
859 */
sysctl_clock_target_is_busy(SYSCTL_Type * ptr,uint32_t clock)860 static inline bool sysctl_clock_target_is_busy(SYSCTL_Type *ptr, uint32_t clock)
861 {
862 return ptr->CLOCK[clock] & SYSCTL_CLOCK_LOC_BUSY_MASK;
863 }
864
865 /**
866 * @brief Set clock preset
867 *
868 * @param[in] ptr SYSCTL_Type base address
869 * @param[in] preset preset
870 */
sysctl_clock_set_preset(SYSCTL_Type * ptr,sysctl_preset_t preset)871 static inline void sysctl_clock_set_preset(SYSCTL_Type *ptr, sysctl_preset_t preset)
872 {
873 ptr->GLOBAL00 = (ptr->GLOBAL00 & ~SYSCTL_GLOBAL00_MUX_MASK) | SYSCTL_GLOBAL00_MUX_SET(preset);
874 }
875
876 /**
877 * @brief Check if target reset domain wakeup status
878 *
879 * @param[in] ptr SYSCTL_Type base address
880 * @param[in] domain target domain to be checked
881 * @return true if target domain was taken wakeup reset
882 */
sysctl_reset_check_target_domain_wakeup_flag(SYSCTL_Type * ptr,sysctl_reset_domain_t domain)883 static inline bool sysctl_reset_check_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain)
884 {
885 return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK;
886 }
887
888 /**
889 * @brief Clear target reset domain wakeup status
890 *
891 * @param[in] ptr SYSCTL_Type base address
892 * @param[in] domain target domain to be checked
893 */
sysctl_reset_clear_target_domain_wakeup_flag(SYSCTL_Type * ptr,sysctl_reset_domain_t domain)894 static inline void sysctl_reset_clear_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain)
895 {
896 ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK;
897 }
898
899 /**
900 * @brief Clear target reset domain reset status
901 *
902 * @param[in] ptr SYSCTL_Type base address
903 * @param[in] domain target domain to be checked
904 * @return true if target domain was taken reset
905 */
sysctl_reset_check_target_domain_flag(SYSCTL_Type * ptr,sysctl_reset_domain_t domain)906 static inline bool sysctl_reset_check_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain)
907 {
908 return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_MASK;
909 }
910
911 /**
912 * @brief Clear target reset domain reset status
913 *
914 * @param[in] ptr SYSCTL_Type base address
915 * @param[in] domain target domain to be checked
916 */
sysctl_reset_clear_target_domain_flag(SYSCTL_Type * ptr,sysctl_reset_domain_t domain)917 static inline void sysctl_reset_clear_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain)
918 {
919 ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK;
920 }
921
922 /**
923 * @brief Clear target reset domain for all reset status
924 *
925 * @param[in] ptr SYSCTL_Type base address
926 * @param[in] domain target domain to be checked
927 */
sysctl_reset_clear_target_domain_all_flags(SYSCTL_Type * ptr,sysctl_reset_domain_t domain)928 static inline void sysctl_reset_clear_target_domain_all_flags(SYSCTL_Type *ptr, sysctl_reset_domain_t domain)
929 {
930 ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK | SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK;
931 }
932
933 /**
934 * @brief Get target CPU wakeup source status
935 *
936 * @param[in] ptr SYSCTL_Type base address
937 * @param[in] cpu_index CPU index
938 * @param[in] status_index wakeup status index 0 - 7
939 * @return wakeup source status mask
940 */
sysctl_get_wakeup_source_status(SYSCTL_Type * ptr,uint8_t cpu_index,uint8_t status_index)941 static inline uint32_t sysctl_get_wakeup_source_status(SYSCTL_Type *ptr, uint8_t cpu_index, uint8_t status_index)
942 {
943 return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index];
944 }
945
946 /**
947 * @brief Check wakeup source status with mask
948 *
949 * @param[in] ptr SYSCTL_Type base address
950 * @param[in] cpu_index CPU index
951 * @param[in] status_index wakeup status index 0 - 7
952 * @param[in] mask expected status mask
953 * @return wakeup status according to given bit mask
954 */
sysctl_check_wakeup_source_status_with_mask(SYSCTL_Type * ptr,uint8_t cpu_index,uint8_t status_index,uint32_t mask)955 static inline uint32_t sysctl_check_wakeup_source_status_with_mask(SYSCTL_Type *ptr,
956 uint8_t cpu_index,
957 uint8_t status_index,
958 uint32_t mask)
959 {
960 return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index] & mask;
961 }
962
963 /**
964 * @brief Enable wakeup source status with mask
965 *
966 * @param[in] ptr SYSCTL_Type base address
967 * @param[in] cpu_index CPU index
968 * @param[in] enable_index wakeup enable index 0 - 7
969 * @param[in] mask expected status mask
970 */
sysctl_enable_wakeup_source_with_mask(SYSCTL_Type * ptr,uint8_t cpu_index,uint8_t enable_index,uint32_t mask)971 static inline void sysctl_enable_wakeup_source_with_mask(SYSCTL_Type *ptr,
972 uint8_t cpu_index,
973 uint8_t enable_index,
974 uint32_t mask)
975 {
976 ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] |= mask;
977 }
978
979 /**
980 * @brief Disable wakeup source status with mask
981 *
982 * @param[in] ptr SYSCTL_Type base address
983 * @param[in] cpu_index CPU index
984 * @param[in] enable_index wakeup enable index 0 - 7
985 * @param[in] mask expected status mask
986 */
sysctl_disable_wakeup_source_with_mask(SYSCTL_Type * ptr,uint8_t cpu_index,uint8_t enable_index,uint32_t mask)987 static inline void sysctl_disable_wakeup_source_with_mask(SYSCTL_Type *ptr,
988 uint8_t cpu_index,
989 uint8_t enable_index,
990 uint32_t mask)
991 {
992 ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] &= ~mask;
993 }
994
995 /**
996 * @brief Disable wakeup source status with irq
997 *
998 * @param[in] ptr SYSCTL_Type base address
999 * @param[in] cpu_index CPU index
1000 * @param[in] irq_num irq number to be set as wakeup source
1001 */
sysctl_disable_wakeup_source_with_irq(SYSCTL_Type * ptr,uint8_t cpu_index,uint16_t irq_num)1002 static inline void sysctl_disable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num)
1003 {
1004 ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num >> 2] &= ~(1UL << (irq_num % 32));
1005 }
1006
1007 /**
1008 * @brief Enable wakeup source status with irq
1009 *
1010 * @param[in] ptr SYSCTL_Type base address
1011 * @param[in] cpu_index CPU index
1012 * @param[in] irq_num irq number to be set as wakeup source
1013 */
sysctl_enable_wakeup_source_with_irq(SYSCTL_Type * ptr,uint8_t cpu_index,uint16_t irq_num)1014 static inline void sysctl_enable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num)
1015 {
1016 ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num / 32] |= 1UL << (irq_num % 32);
1017 }
1018
1019 /**
1020 * @brief Enable CPU0 wakeup source status with irq
1021 *
1022 * @param[in] ptr SYSCTL_Type base address
1023 * @param[in] irq_num irq number to be set as wakeup source
1024 */
sysctl_enable_cpu0_wakeup_source_with_irq(SYSCTL_Type * ptr,uint16_t irq_num)1025 static inline void sysctl_enable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr,
1026 uint16_t irq_num)
1027 {
1028 sysctl_enable_wakeup_source_with_irq(ptr, 0, irq_num);
1029 }
1030
1031 /**
1032 * @brief Lock CPU0 gpr with mask
1033 *
1034 * @param[in] ptr SYSCTL_Type base address
1035 * @param[in] gpr_mask bit mask of gpr registers to be locked
1036 */
sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type * ptr,uint16_t gpr_mask)1037 static inline void sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type *ptr, uint16_t gpr_mask)
1038 {
1039 ptr->CPU[0].LOCK |= SYSCTL_CPU_LOCK_GPR_SET(gpr_mask);
1040 }
1041
1042 /**
1043 * @brief Lock CPU0 lock
1044 *
1045 * @param[in] ptr SYSCTL_Type base address
1046 */
sysctl_cpu0_lock(SYSCTL_Type * ptr)1047 static inline void sysctl_cpu0_lock(SYSCTL_Type *ptr)
1048 {
1049 ptr->CPU[0].LOCK |= SYSCTL_CPU_LOCK_LOCK_MASK;
1050 }
1051
1052 /**
1053 * @brief Config lock
1054 *
1055 * @param[in] ptr SYSCTL_Type base address
1056 * @param[in] node clock node to be configured
1057 * @param[in] source clock source to be used
1058 * @param[in] divide_by clock frequency divider
1059 * @return status_success if everything is okay
1060 */
1061 hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by);
1062
1063 /**
1064 * @brief Set ADC clock mux
1065 *
1066 * @param[in] ptr SYSCTL_Type base address
1067 * @param[in] node clock node to be configured
1068 * @param[in] source clock source to be used
1069 * @return status_success if everything is okay
1070 */
1071 hpm_stat_t sysctl_set_adc_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_t source);
1072
1073
1074 /**
1075 * @brief Set I2S clock mux
1076 *
1077 * @param[in] ptr SYSCTL_Type base address
1078 * @param[in] node clock node to be configured
1079 * @param[in] source clock source to be used
1080 * @return status_success if everything is okay
1081 */
1082 hpm_stat_t sysctl_set_i2s_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_i2s_t source);
1083
1084 /**
1085 * @brief Set CPU0 low power mode
1086 *
1087 * @param[in] ptr SYSCTL_Type base address
1088 * @param[in] cpu0_index cpu index
1089 * @param[in] mode target mode to set
1090 * @return status_success if everything is okay
1091 */
1092 hpm_stat_t sysctl_set_cpu0_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode);
1093
1094 /**
1095 * @brief Enable group resource
1096 *
1097 * @param[in] ptr SYSCTL_Type base address
1098 * @param[in] group target group to be modified
1099 * @param[in] resource target resource to be added/removed from group
1100 * @param[in] enable set true to add resource, remove otherwise
1101 * @return status_success if everything is okay
1102 */
1103 hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource, bool enable);
1104
1105 /**
1106 * @brief Check group resource enable status
1107 *
1108 * @param[in] ptr SYSCTL_Type base address
1109 * @param[in] group target group to be checked
1110 * @param[in] resource target resource to be checked from group
1111 * @return enable true if resource enable, false if resource disable
1112 */
1113 bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t linkable_resource);
1114
1115 /**
1116 * @brief Get group resource value
1117 *
1118 * @param[in] ptr SYSCTL_Type base address
1119 * @param[in] group target group to be getted
1120 * @param[in] index target group index
1121 * @return group index value
1122 */
1123 uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index);
1124
1125 /**
1126 * @brief Add resource to CPU0
1127 *
1128 * @param[in] ptr SYSCTL_Type base address
1129 * @param[in] resource resource to be added to CPU0
1130 * @return status_success if everything is okay
1131 */
1132 hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource);
1133
1134 /**
1135 * @brief Remove resource from CPU0
1136 *
1137 * @param[in] ptr SYSCTL_Type base address
1138 * @param[in] resource Resource to be removed to CPU0
1139 * @return status_success if everything is okay
1140 */
1141 hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource);
1142
1143 /**
1144 * @brief Get default monitor config
1145 *
1146 * @param[in] ptr SYSCTL_Type base address
1147 * @param[in] config Monitor config structure pointer
1148 */
1149 void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config);
1150
1151 /**
1152 * @brief Initialize Monitor
1153 *
1154 * @param[in] ptr SYSCTL_Type base address
1155 * @param[in] monitor_index Monitor instance to be initialized
1156 * @param[in] config Monitor config structure pointer
1157 */
1158 void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config);
1159
1160 /**
1161 * @brief Save data to CPU0 GPR starting from given index
1162 *
1163 * @param[in] ptr SYSCTL_Type base address
1164 * @param[in] start Starting GPR index
1165 * @param[in] count Number of GPR registers to set
1166 * @param[in] data Pointer to data buffer
1167 * @param[in] lock Set true to lock written GPR registers after setting
1168 * @return status_success if everything is okay
1169 */
1170 hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock);
1171
1172 /**
1173 * @brief Get data saved from CPU0 GPR starting from given index
1174 *
1175 * @param[in] ptr SYSCTL_Type base address
1176 * @param[in] start Starting GPR index
1177 * @param[in] count Number of GPR registers to set
1178 * @param[out] data Pointer of buffer to save data
1179 * @return status_success if everything is okay
1180 */
1181 hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data);
1182
1183 /**
1184 * @brief Set entry point on CPU0 wakeup
1185 *
1186 * @param[in] ptr SYSCTL_Type base address
1187 * @param[in] entry Entry address for CPU0 on its wakeup
1188 * @return status_success if everything is okay
1189 */
1190 hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry);
1191
1192
1193 #ifdef __cplusplus
1194 }
1195 #endif
1196 /**
1197 * @}
1198 */
1199 #endif /* HPM_SYSCTL_DRV_H */
1200