1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_MCPWM_STRUCT_H__ 15 #define _SOC_MCPWM_STRUCT_H__ 16 17 #include <stdint.h> 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 typedef volatile struct mcpwm_dev_s { 24 union { 25 struct { 26 uint32_t prescale: 8; /*Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/ 27 uint32_t reserved8: 24; 28 }; 29 uint32_t val; 30 }clk_cfg; 31 struct { 32 union { 33 struct { 34 uint32_t prescale: 8; /*period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)*/ 35 uint32_t period: 16; /*period shadow reg of PWM timer0*/ 36 uint32_t upmethod: 2; /*Update method for active reg of PWM timer0 period 0: immediate 1: TEZ 2: sync 3: TEZ | sync. TEZ here and below means timer equal zero event*/ 37 uint32_t reserved26: 6; 38 }; 39 uint32_t val; 40 }period; 41 union { 42 struct { 43 uint32_t start: 3; /*PWM timer0 start and stop control. 0: stop @ TEZ 1: stop @ TEP 2: free run 3: start and stop @ next TEZ 4: start and stop @ next TEP. TEP here and below means timer equal period event*/ 44 uint32_t mode: 2; /*PWM timer0 working mode 0: freeze 1: increase mod 2: decrease mod 3: up-down mod*/ 45 uint32_t reserved5: 27; 46 }; 47 uint32_t val; 48 }mode; 49 union { 50 struct { 51 uint32_t in_en: 1; /*when set timer reload with phase on sync input event is enabled*/ 52 uint32_t sync_sw: 1; /*write the negate value will trigger a software sync*/ 53 uint32_t out_sel: 2; /*PWM timer0 synco selection 0: synci 1: TEZ 2: TEP else 0*/ 54 uint32_t timer_phase: 17; /*phase for timer reload on sync event*/ 55 uint32_t reserved21: 11; 56 }; 57 uint32_t val; 58 }sync; 59 union { 60 struct { 61 uint32_t value: 16; /*current PWM timer0 counter value*/ 62 uint32_t direction: 1; /*current PWM timer0 counter direction 0: increment 1: decrement*/ 63 uint32_t reserved17: 15; 64 }; 65 uint32_t val; 66 }status; 67 }timer[3]; 68 69 70 union { 71 struct { 72 uint32_t t0_in_sel: 3; /*select sync input for PWM timer0 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/ 73 uint32_t t1_in_sel: 3; /*select sync input for PWM timer1 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/ 74 uint32_t t2_in_sel: 3; /*select sync input for PWM timer2 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/ 75 uint32_t ext_in0_inv: 1; /*invert SYNC0 from GPIO matrix*/ 76 uint32_t ext_in1_inv: 1; /*invert SYNC1 from GPIO matrix*/ 77 uint32_t ext_in2_inv: 1; /*invert SYNC2 from GPIO matrix*/ 78 uint32_t reserved12: 20; 79 }; 80 uint32_t val; 81 }timer_synci_cfg; 82 union { 83 struct { 84 uint32_t operator0_sel: 2; /*Select which PWM timer's is the timing reference for PWM operator0 0: timer0 1: timer1 2: timer2*/ 85 uint32_t operator1_sel: 2; /*Select which PWM timer's is the timing reference for PWM operator1 0: timer0 1: timer1 2: timer2*/ 86 uint32_t operator2_sel: 2; /*Select which PWM timer's is the timing reference for PWM operator2 0: timer0 1: timer1 2: timer2*/ 87 uint32_t reserved6: 26; 88 }; 89 uint32_t val; 90 }timer_sel; 91 92 93 struct { 94 union { 95 struct { 96 uint32_t a_upmethod: 4; /*Update method for PWM compare0 A's active reg. 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: freeze*/ 97 uint32_t b_upmethod: 4; /*Update method for PWM compare0 B's active reg. 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: freeze*/ 98 uint32_t a_shdw_full: 1; /*Set and reset by hardware. If set PWM compare0 A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared A's active reg has been updated with shadow reg latest value*/ 99 uint32_t b_shdw_full: 1; /*Set and reset by hardware. If set PWM compare0 B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared B's active reg has been updated with shadow reg latest value*/ 100 uint32_t reserved10: 22; 101 }; 102 uint32_t val; 103 }cmpr_cfg; 104 union { 105 struct { 106 uint32_t cmpr_val: 16; /*PWM compare0 A's shadow reg*/ 107 uint32_t reserved16:16; 108 }; 109 uint32_t val; 110 }cmpr_value[2]; 111 union { 112 struct { 113 uint32_t upmethod: 4; /*Update method for PWM generate0's active reg of configuration. 0: immediate bit0: TEZ bit1: TEP bit2: sync. bit3: freeze*/ 114 uint32_t t0_sel: 3; /*Source selection for PWM generate0 event_t0 take effect immediately 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ 115 uint32_t t1_sel: 3; /*Source selection for PWM generate0 event_t1 take effect immediately 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ 116 uint32_t reserved10: 22; 117 }; 118 uint32_t val; 119 }gen_cfg0; 120 union { 121 struct { 122 uint32_t cntu_force_upmethod: 6; /*Update method for continuous software force of PWM generate0. 0: immediate bit0: TEZ bit1: TEP bit2: TEA bit3: TEB bit4: sync bit5: freeze. (TEA/B here and below means timer equals A/B event)*/ 123 uint32_t a_cntuforce_mode: 2; /*Continuous software force mode for PWM0A. 0: disabled 1: low 2: high 3: disabled*/ 124 uint32_t b_cntuforce_mode: 2; /*Continuous software force mode for PWM0B. 0: disabled 1: low 2: high 3: disabled*/ 125 uint32_t a_nciforce: 1; /*non-continuous immediate software force trigger for PWM0A a toggle will trigger a force event*/ 126 uint32_t a_nciforce_mode: 2; /*non-continuous immediate software force mode for PWM0A 0: disabled 1: low 2: high 3: disabled*/ 127 uint32_t b_nciforce: 1; /*non-continuous immediate software force trigger for PWM0B a toggle will trigger a force event*/ 128 uint32_t b_nciforce_mode: 2; /*non-continuous immediate software force mode for PWM0B 0: disabled 1: low 2: high 3: disabled*/ 129 uint32_t reserved16: 16; 130 }; 131 uint32_t val; 132 }gen_force; 133 union { 134 struct { 135 uint32_t utez: 2; /*Action on PWM0A triggered by event TEZ when timer increasing*/ 136 uint32_t utep: 2; /*Action on PWM0A triggered by event TEP when timer increasing*/ 137 uint32_t utea: 2; /*Action on PWM0A triggered by event TEA when timer increasing*/ 138 uint32_t uteb: 2; /*Action on PWM0A triggered by event TEB when timer increasing*/ 139 uint32_t ut0: 2; /*Action on PWM0A triggered by event_t0 when timer increasing*/ 140 uint32_t ut1: 2; /*Action on PWM0A triggered by event_t1 when timer increasing*/ 141 uint32_t dtez: 2; /*Action on PWM0A triggered by event TEZ when timer decreasing*/ 142 uint32_t dtep: 2; /*Action on PWM0A triggered by event TEP when timer decreasing*/ 143 uint32_t dtea: 2; /*Action on PWM0A triggered by event TEA when timer decreasing*/ 144 uint32_t dteb: 2; /*Action on PWM0A triggered by event TEB when timer decreasing*/ 145 uint32_t dt0: 2; /*Action on PWM0A triggered by event_t0 when timer decreasing*/ 146 uint32_t dt1: 2; /*Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change 1: low 2: high 3: toggle*/ 147 uint32_t reserved24: 8; 148 }; 149 uint32_t val; 150 }generator[2]; 151 union { 152 struct { 153 uint32_t fed_upmethod: 4; /*Update method for FED (falling edge delay) active reg. 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ 154 uint32_t red_upmethod: 4; /*Update method for RED (rising edge delay) active reg. 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ 155 uint32_t deb_mode: 1; /*S8 in documentation dual-edge B mode 0: fed/red take effect on different path separately 1: fed/red take effect on B path A out is in bypass or dulpB mode*/ 156 uint32_t a_outswap: 1; /*S6 in documentation*/ 157 uint32_t b_outswap: 1; /*S7 in documentation*/ 158 uint32_t red_insel: 1; /*S4 in documentation*/ 159 uint32_t fed_insel: 1; /*S5 in documentation*/ 160 uint32_t red_outinvert: 1; /*S2 in documentation*/ 161 uint32_t fed_outinvert: 1; /*S3 in documentation*/ 162 uint32_t a_outbypass: 1; /*S1 in documentation*/ 163 uint32_t b_outbypass: 1; /*S0 in documentation*/ 164 uint32_t clk_sel: 1; /*Dead band0 clock selection. 0: PWM_clk 1: PT_clk*/ 165 uint32_t reserved18: 14; 166 }; 167 uint32_t val; 168 }db_cfg; 169 union { 170 struct { 171 uint32_t fed: 16; /*Shadow reg for FED*/ 172 uint32_t reserved16:16; 173 }; 174 uint32_t val; 175 }db_fed_cfg; 176 union { 177 struct { 178 uint32_t red: 16; /*Shadow reg for RED*/ 179 uint32_t reserved16:16; 180 }; 181 uint32_t val; 182 }db_red_cfg; 183 union { 184 struct { 185 uint32_t en: 1; /*When set carrier0 function is enabled. When reset carrier0 is bypassed*/ 186 uint32_t prescale: 4; /*carrier0 clk (CP_clk) prescale value. Period of CP_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)*/ 187 uint32_t duty: 3; /*carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8*/ 188 uint32_t oshtwth: 4; /*width of the fist pulse in number of periods of the carrier*/ 189 uint32_t out_invert: 1; /*when set invert the output of PWM0A and PWM0B for this submodule*/ 190 uint32_t in_invert: 1; /*when set invert the input of PWM0A and PWM0B for this submodule*/ 191 uint32_t reserved14: 18; 192 }; 193 uint32_t val; 194 }carrier_cfg; 195 union { 196 struct { 197 uint32_t sw_cbc: 1; /*Cycle-by-cycle tripping software force event will trigger cycle-by-cycle trip event. 0: disable 1: enable*/ 198 uint32_t f2_cbc: 1; /*event_f2 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/ 199 uint32_t f1_cbc: 1; /*event_f1 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/ 200 uint32_t f0_cbc: 1; /*event_f0 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/ 201 uint32_t sw_ost: 1; /*one-shot tripping software force event will trigger one-shot trip event. 0: disable 1: enable*/ 202 uint32_t f2_ost: 1; /*event_f2 will trigger one-shot trip event. 0: disable 1: enable*/ 203 uint32_t f1_ost: 1; /*event_f1 will trigger one-shot trip event. 0: disable 1: enable*/ 204 uint32_t f0_ost: 1; /*event_f0 will trigger one-shot trip event. 0: disable 1: enable*/ 205 uint32_t a_cbc_d: 2; /*Action on PWM0A when cycle-by-cycle trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ 206 uint32_t a_cbc_u: 2; /*Action on PWM0A when cycle-by-cycle trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ 207 uint32_t a_ost_d: 2; /*Action on PWM0A when one-shot trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ 208 uint32_t a_ost_u: 2; /*Action on PWM0A when one-shot trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ 209 uint32_t b_cbc_d: 2; /*Action on PWM0B when cycle-by-cycle trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ 210 uint32_t b_cbc_u: 2; /*Action on PWM0B when cycle-by-cycle trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ 211 uint32_t b_ost_d: 2; /*Action on PWM0B when one-shot trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ 212 uint32_t b_ost_u: 2; /*Action on PWM0B when one-shot trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ 213 uint32_t reserved24: 8; 214 }; 215 uint32_t val; 216 }tz_cfg0; 217 union { 218 struct { 219 uint32_t clr_ost: 1; /*a toggle will clear on going one-shot tripping*/ 220 uint32_t cbcpulse: 2; /*cycle-by-cycle tripping refresh moment selection. Bit0: TEZ bit1:TEP*/ 221 uint32_t force_cbc: 1; /*a toggle trigger a cycle-by-cycle tripping software force event*/ 222 uint32_t force_ost: 1; /*a toggle (software negate its value) trigger a one-shot tripping software force event*/ 223 uint32_t reserved5: 27; 224 }; 225 uint32_t val; 226 }tz_cfg1; 227 union { 228 struct { 229 uint32_t cbc_on: 1; /*Set and reset by hardware. If set an cycle-by-cycle trip event is on going*/ 230 uint32_t ost_on: 1; /*Set and reset by hardware. If set an one-shot trip event is on going*/ 231 uint32_t reserved2: 30; 232 }; 233 uint32_t val; 234 }tz_status; 235 }channel[3]; 236 237 union { 238 struct { 239 uint32_t f0_en: 1; /*When set event_f0 generation is enabled*/ 240 uint32_t f1_en: 1; /*When set event_f1 generation is enabled*/ 241 uint32_t f2_en: 1; /*When set event_f2 generation is enabled*/ 242 uint32_t f0_pole: 1; /*Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/ 243 uint32_t f1_pole: 1; /*Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/ 244 uint32_t f2_pole: 1; /*Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/ 245 uint32_t event_f0: 1; /*Set and reset by hardware. If set event_f0 is on going*/ 246 uint32_t event_f1: 1; /*Set and reset by hardware. If set event_f1 is on going*/ 247 uint32_t event_f2: 1; /*Set and reset by hardware. If set event_f2 is on going*/ 248 uint32_t reserved9: 23; 249 }; 250 uint32_t val; 251 }fault_detect; 252 union { 253 struct { 254 uint32_t timer_en: 1; /*When set capture timer incrementing under APB_clk is enabled.*/ 255 uint32_t synci_en: 1; /*When set capture timer sync is enabled.*/ 256 uint32_t synci_sel: 3; /*capture module sync input selection. 0: none 1: timer0 synco 2: timer1 synco 3: timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix*/ 257 uint32_t sync_sw: 1; /*Write 1 will force a capture timer sync capture timer is loaded with value in phase register.*/ 258 uint32_t reserved6: 26; 259 }; 260 uint32_t val; 261 }cap_timer_cfg; 262 uint32_t cap_timer_phase; /*Phase value for capture timer sync operation.*/ 263 union { 264 struct { 265 uint32_t en: 1; /*When set capture on channel 0 is enabled*/ 266 uint32_t mode: 2; /*Edge of capture on channel 0 after prescale. bit0: negedge cap en bit1: posedge cap en*/ 267 uint32_t prescale: 8; /*Value of prescale on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1*/ 268 uint32_t in_invert: 1; /*when set CAP0 form GPIO matrix is inverted before prescale*/ 269 uint32_t sw: 1; /*Write 1 will trigger a software forced capture on channel 0*/ 270 uint32_t reserved13: 19; 271 }; 272 uint32_t val; 273 }cap_cfg_ch[3]; 274 uint32_t cap_val_ch[3]; /*Value of last capture on channel 0*/ 275 union { 276 struct { 277 uint32_t cap0_edge: 1; /*Edge of last capture trigger on channel 0 0: posedge 1: negedge*/ 278 uint32_t cap1_edge: 1; /*Edge of last capture trigger on channel 1 0: posedge 1: negedge*/ 279 uint32_t cap2_edge: 1; /*Edge of last capture trigger on channel 2 0: posedge 1: negedge*/ 280 uint32_t reserved3: 29; 281 }; 282 uint32_t val; 283 }cap_status; 284 union { 285 struct { 286 uint32_t global_up_en: 1; /*The global enable of update of all active registers in MCPWM module*/ 287 uint32_t global_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module*/ 288 uint32_t op0_up_en: 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 0 are enabled*/ 289 uint32_t op0_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0*/ 290 uint32_t op1_up_en: 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 1 are enabled*/ 291 uint32_t op1_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1*/ 292 uint32_t op2_up_en: 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 2 are enabled*/ 293 uint32_t op2_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2*/ 294 uint32_t reserved8: 24; 295 }; 296 uint32_t val; 297 }update_cfg; 298 union { 299 struct { 300 uint32_t timer0_stop_int_ena: 1; /*Interrupt when timer 0 stops*/ 301 uint32_t timer1_stop_int_ena: 1; /*Interrupt when timer 1 stops*/ 302 uint32_t timer2_stop_int_ena: 1; /*Interrupt when timer 2 stops*/ 303 uint32_t timer0_tez_int_ena: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/ 304 uint32_t timer1_tez_int_ena: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/ 305 uint32_t timer2_tez_int_ena: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/ 306 uint32_t timer0_tep_int_ena: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/ 307 uint32_t timer1_tep_int_ena: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/ 308 uint32_t timer2_tep_int_ena: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/ 309 uint32_t fault0_int_ena: 1; /*Interrupt when event_f0 starts*/ 310 uint32_t fault1_int_ena: 1; /*Interrupt when event_f1 starts*/ 311 uint32_t fault2_int_ena: 1; /*Interrupt when event_f2 starts*/ 312 uint32_t fault0_clr_int_ena: 1; /*Interrupt when event_f0 ends*/ 313 uint32_t fault1_clr_int_ena: 1; /*Interrupt when event_f1 ends*/ 314 uint32_t fault2_clr_int_ena: 1; /*Interrupt when event_f2 ends*/ 315 uint32_t cmpr0_tea_int_ena: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/ 316 uint32_t cmpr1_tea_int_ena: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/ 317 uint32_t cmpr2_tea_int_ena: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/ 318 uint32_t cmpr0_teb_int_ena: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/ 319 uint32_t cmpr1_teb_int_ena: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/ 320 uint32_t cmpr2_teb_int_ena: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/ 321 uint32_t tz0_cbc_int_ena: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/ 322 uint32_t tz1_cbc_int_ena: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/ 323 uint32_t tz2_cbc_int_ena: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/ 324 uint32_t tz0_ost_int_ena: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/ 325 uint32_t tz1_ost_int_ena: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/ 326 uint32_t tz2_ost_int_ena: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/ 327 uint32_t cap0_int_ena: 1; /*A capture on channel 0 will trigger this interrupt*/ 328 uint32_t cap1_int_ena: 1; /*A capture on channel 1 will trigger this interrupt*/ 329 uint32_t cap2_int_ena: 1; /*A capture on channel 2 will trigger this interrupt*/ 330 uint32_t reserved30: 2; 331 }; 332 uint32_t val; 333 }int_ena; 334 union { 335 struct { 336 uint32_t timer0_stop_int_raw: 1; /*Interrupt when timer 0 stops*/ 337 uint32_t timer1_stop_int_raw: 1; /*Interrupt when timer 1 stops*/ 338 uint32_t timer2_stop_int_raw: 1; /*Interrupt when timer 2 stops*/ 339 uint32_t timer0_tez_int_raw: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/ 340 uint32_t timer1_tez_int_raw: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/ 341 uint32_t timer2_tez_int_raw: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/ 342 uint32_t timer0_tep_int_raw: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/ 343 uint32_t timer1_tep_int_raw: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/ 344 uint32_t timer2_tep_int_raw: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/ 345 uint32_t fault0_int_raw: 1; /*Interrupt when event_f0 starts*/ 346 uint32_t fault1_int_raw: 1; /*Interrupt when event_f1 starts*/ 347 uint32_t fault2_int_raw: 1; /*Interrupt when event_f2 starts*/ 348 uint32_t fault0_clr_int_raw: 1; /*Interrupt when event_f0 ends*/ 349 uint32_t fault1_clr_int_raw: 1; /*Interrupt when event_f1 ends*/ 350 uint32_t fault2_clr_int_raw: 1; /*Interrupt when event_f2 ends*/ 351 uint32_t cmpr0_tea_int_raw: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/ 352 uint32_t cmpr1_tea_int_raw: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/ 353 uint32_t cmpr2_tea_int_raw: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/ 354 uint32_t cmpr0_teb_int_raw: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/ 355 uint32_t cmpr1_teb_int_raw: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/ 356 uint32_t cmpr2_teb_int_raw: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/ 357 uint32_t tz0_cbc_int_raw: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/ 358 uint32_t tz1_cbc_int_raw: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/ 359 uint32_t tz2_cbc_int_raw: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/ 360 uint32_t tz0_ost_int_raw: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/ 361 uint32_t tz1_ost_int_raw: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/ 362 uint32_t tz2_ost_int_raw: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/ 363 uint32_t cap0_int_raw: 1; /*A capture on channel 0 will trigger this interrupt*/ 364 uint32_t cap1_int_raw: 1; /*A capture on channel 1 will trigger this interrupt*/ 365 uint32_t cap2_int_raw: 1; /*A capture on channel 2 will trigger this interrupt*/ 366 uint32_t reserved30: 2; 367 }; 368 uint32_t val; 369 }int_raw; 370 union { 371 struct { 372 uint32_t timer0_stop_int_st: 1; /*Interrupt when timer 0 stops*/ 373 uint32_t timer1_stop_int_st: 1; /*Interrupt when timer 1 stops*/ 374 uint32_t timer2_stop_int_st: 1; /*Interrupt when timer 2 stops*/ 375 uint32_t timer0_tez_int_st: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/ 376 uint32_t timer1_tez_int_st: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/ 377 uint32_t timer2_tez_int_st: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/ 378 uint32_t timer0_tep_int_st: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/ 379 uint32_t timer1_tep_int_st: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/ 380 uint32_t timer2_tep_int_st: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/ 381 uint32_t fault0_int_st: 1; /*Interrupt when event_f0 starts*/ 382 uint32_t fault1_int_st: 1; /*Interrupt when event_f1 starts*/ 383 uint32_t fault2_int_st: 1; /*Interrupt when event_f2 starts*/ 384 uint32_t fault0_clr_int_st: 1; /*Interrupt when event_f0 ends*/ 385 uint32_t fault1_clr_int_st: 1; /*Interrupt when event_f1 ends*/ 386 uint32_t fault2_clr_int_st: 1; /*Interrupt when event_f2 ends*/ 387 uint32_t cmpr0_tea_int_st: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/ 388 uint32_t cmpr1_tea_int_st: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/ 389 uint32_t cmpr2_tea_int_st: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/ 390 uint32_t cmpr0_teb_int_st: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/ 391 uint32_t cmpr1_teb_int_st: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/ 392 uint32_t cmpr2_teb_int_st: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/ 393 uint32_t tz0_cbc_int_st: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/ 394 uint32_t tz1_cbc_int_st: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/ 395 uint32_t tz2_cbc_int_st: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/ 396 uint32_t tz0_ost_int_st: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/ 397 uint32_t tz1_ost_int_st: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/ 398 uint32_t tz2_ost_int_st: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/ 399 uint32_t cap0_int_st: 1; /*A capture on channel 0 will trigger this interrupt*/ 400 uint32_t cap1_int_st: 1; /*A capture on channel 1 will trigger this interrupt*/ 401 uint32_t cap2_int_st: 1; /*A capture on channel 2 will trigger this interrupt*/ 402 uint32_t reserved30: 2; 403 }; 404 uint32_t val; 405 }int_st; 406 union { 407 struct { 408 uint32_t timer0_stop_int_clr: 1; /*Interrupt when timer 0 stops*/ 409 uint32_t timer1_stop_int_clr: 1; /*Interrupt when timer 1 stops*/ 410 uint32_t timer2_stop_int_clr: 1; /*Interrupt when timer 2 stops*/ 411 uint32_t timer0_tez_int_clr: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/ 412 uint32_t timer1_tez_int_clr: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/ 413 uint32_t timer2_tez_int_clr: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/ 414 uint32_t timer0_tep_int_clr: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/ 415 uint32_t timer1_tep_int_clr: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/ 416 uint32_t timer2_tep_int_clr: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/ 417 uint32_t fault0_int_clr: 1; /*Interrupt when event_f0 starts*/ 418 uint32_t fault1_int_clr: 1; /*Interrupt when event_f1 starts*/ 419 uint32_t fault2_int_clr: 1; /*Interrupt when event_f2 starts*/ 420 uint32_t fault0_clr_int_clr: 1; /*Interrupt when event_f0 ends*/ 421 uint32_t fault1_clr_int_clr: 1; /*Interrupt when event_f1 ends*/ 422 uint32_t fault2_clr_int_clr: 1; /*Interrupt when event_f2 ends*/ 423 uint32_t cmpr0_tea_int_clr: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/ 424 uint32_t cmpr1_tea_int_clr: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/ 425 uint32_t cmpr2_tea_int_clr: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/ 426 uint32_t cmpr0_teb_int_clr: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/ 427 uint32_t cmpr1_teb_int_clr: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/ 428 uint32_t cmpr2_teb_int_clr: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/ 429 uint32_t tz0_cbc_int_clr: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/ 430 uint32_t tz1_cbc_int_clr: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/ 431 uint32_t tz2_cbc_int_clr: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/ 432 uint32_t tz0_ost_int_clr: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/ 433 uint32_t tz1_ost_int_clr: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/ 434 uint32_t tz2_ost_int_clr: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/ 435 uint32_t cap0_int_clr: 1; /*A capture on channel 0 will trigger this interrupt*/ 436 uint32_t cap1_int_clr: 1; /*A capture on channel 1 will trigger this interrupt*/ 437 uint32_t cap2_int_clr: 1; /*A capture on channel 2 will trigger this interrupt*/ 438 uint32_t reserved30: 2; 439 }; 440 uint32_t val; 441 }int_clr; 442 union { 443 struct { 444 uint32_t clk_en: 1; /*Force clock on for this reg file*/ 445 uint32_t reserved1: 31; 446 }; 447 uint32_t val; 448 }reg_clk; 449 union { 450 struct { 451 uint32_t date: 28; /*Version of this reg file*/ 452 uint32_t reserved28: 4; 453 }; 454 uint32_t val; 455 }version; 456 } mcpwm_dev_t; 457 extern mcpwm_dev_t MCPWM0; 458 extern mcpwm_dev_t MCPWM1; 459 460 #ifdef __cplusplus 461 } 462 #endif 463 464 #endif /* _SOC_MCPWM_STRUCT_H__ */ 465