1 // Copyright (C) 2022 Beken Corporation
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include "uart_hal.h"
16 #include "uart_ll.h"
17
uart_hal_init(uart_hal_t * hal)18 bk_err_t uart_hal_init(uart_hal_t *hal)
19 {
20 hal->hw = (uart_hw_t *)UART_LL_REG_BASE(hal->id);
21 uart_ll_init(hal->hw);
22 return BK_OK;
23 }
24
25 /* 1. disable int
26 * 2. set config: tx,rx en; idra; data_bits; parity; stop_bits; clk_div
27 * 3. set fifo_config: fifo_threshold; stop_detect_time
28 * 4. disable flow_control
29 * 5. disable wake_en
30 * 6. enable int
31 */
uart_hal_init_uart(uart_hal_t * hal,uart_id_t id,const uart_config_t * config)32 bk_err_t uart_hal_init_uart(uart_hal_t *hal, uart_id_t id, const uart_config_t *config)
33 {
34 uart_ll_reset_int_en_to_default(hal->hw, id);
35 uart_ll_reset_fifo_port_to_default(hal->hw, id);
36
37 uart_ll_set_mode_uart(hal->hw, id);
38 uart_ll_set_data_bits(hal->hw, id, config->data_bits);
39 uart_ll_set_stop_bits(hal->hw, id, config->stop_bits);
40 uart_hal_set_parity(hal, id, config->parity);
41 uart_hal_set_baud_rate(hal, id, config->src_clk, config->baud_rate);
42
43 uart_ll_set_tx_fifo_threshold(hal->hw, id, UART_TX_FIFO_THRESHOLD);
44 uart_ll_set_rx_fifo_threshold(hal->hw, id, UART_RX_FIFO_THRESHOLD);
45 uart_ll_set_rx_stop_detect_time(hal->hw, id, UART_RX_STOP_DETECT_TIME_32_BITS);
46
47 uart_ll_reset_flow_control_to_default(hal->hw, id);
48 if (config->flow_ctrl != UART_FLOWCTRL_DISABLE) {
49 uart_hal_set_hw_flow_ctrl(hal, id, CONFIG_KFIFO_SIZE & 0xff);
50 uart_ll_enable_flow_control(hal->hw, id);
51 }
52 uart_ll_reset_wake_config_to_default(hal->hw, id);
53
54 return BK_OK;
55 }
56
uart_hal_start_common(uart_hal_t * hal,uart_id_t id)57 bk_err_t uart_hal_start_common(uart_hal_t *hal, uart_id_t id)
58 {
59 uart_ll_enable_tx(hal->hw, id);
60 uart_ll_enable_rx(hal->hw, id);
61 return BK_OK;
62 }
63
uart_hal_stop_common(uart_hal_t * hal,uart_id_t id)64 bk_err_t uart_hal_stop_common(uart_hal_t *hal, uart_id_t id)
65 {
66 uart_ll_reset_int_en_to_default(hal->hw, id);
67 uart_ll_clear_id_interrupt_status(hal->hw, id);
68 uart_ll_disable_tx(hal->hw, id);
69 uart_ll_disable_rx(hal->hw, id);
70 return BK_OK;
71 }
72
uart_hal_flush_fifo(uart_hal_t * hal,uart_id_t id)73 bk_err_t uart_hal_flush_fifo(uart_hal_t *hal, uart_id_t id)
74 {
75 uart_ll_disable_tx(hal->hw, id);
76 uart_ll_disable_rx(hal->hw, id);
77
78 uart_ll_enable_tx(hal->hw, id);
79 uart_ll_enable_rx(hal->hw, id);
80
81 return BK_OK;
82 }
83
uart_hal_set_baud_rate(uart_hal_t * hal,uart_id_t id,uint32_t sclk,uint32_t baud_rate)84 bk_err_t uart_hal_set_baud_rate(uart_hal_t *hal, uart_id_t id, uint32_t sclk, uint32_t baud_rate)
85 {
86 uint32_t clk_div = 0;
87 if (sclk == UART_SCLK_DCO) {
88 clk_div = UART_CLOCK_FREQ_120M / baud_rate - 1;
89 } else {
90 clk_div = UART_CLOCK / baud_rate - 1;
91 }
92 uart_ll_set_clk_div(hal->hw, id, clk_div);
93
94 return BK_OK;
95 }
96
uart_hal_set_parity(uart_hal_t * hal,uart_id_t id,uart_parity_t parity)97 bk_err_t uart_hal_set_parity(uart_hal_t *hal, uart_id_t id, uart_parity_t parity)
98 {
99 if (parity == UART_PARITY_NONE) {
100 uart_ll_disable_parity(hal->hw, id);
101 } else {
102 uart_ll_enable_parity(hal->hw, id);
103 }
104 uart_ll_set_parity(hal->hw, id, parity);
105 return BK_OK;
106 }
107
uart_hal_set_hw_flow_ctrl(uart_hal_t * hal,uart_id_t id,uint8_t rx_threshold)108 bk_err_t uart_hal_set_hw_flow_ctrl(uart_hal_t *hal, uart_id_t id, uint8_t rx_threshold)
109 {
110 uart_ll_set_flow_control_low_cnt(hal->hw, id, 0);
111 uart_ll_set_flow_control_high_cnt(hal->hw, id, rx_threshold);
112 uart_ll_set_rts_polarity(hal->hw, id, 1);
113 uart_ll_set_cts_polarity(hal->hw, id, 1);
114 return BK_OK;
115 }
116
uart_hal_disable_hw_flow_ctrl(uart_hal_t * hal,uart_id_t id)117 bk_err_t uart_hal_disable_hw_flow_ctrl(uart_hal_t *hal, uart_id_t id)
118 {
119 uart_ll_disable_flow_control(hal->hw, id);
120 uart_ll_reset_flow_control_to_default(hal->hw, id);
121 return BK_OK;
122 }
123
124