1 // Copyright (C) 2022 Beken Corporation 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 #include <common/bk_err.h> 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 #define UART_BAUDRATE_3250000 3250000 24 #define UART_BAUDRATE_2000000 2000000 25 #define UART_BAUDRATE_921600 921600 26 #define UART_BAUDRATE_460800 460800 27 #define UART_BAUDRATE_230400 230400 28 #define UART_BAUDRATE_115200 115200 //default 29 #define UART_BAUDRATE_3000 3250 30 #define UART_BAUDRATE_19200 19200 31 32 #define UART_BAUD_RATE UART_BAUDRATE_115200 33 34 #define UART_CLOCK_FREQ_10M 10000000 35 #define UART_CLOCK_FREQ_48M 48000000 36 #define UART_CLOCK_FREQ_24M 24000000 37 #define UART_CLOCK_FREQ_26M 26000000 38 #define UART_CLOCK_FREQ_52M 52000000 39 #define UART_CLOCK_FREQ_120M 120000000 40 41 #if (CONFIG_FPGA) 42 #define UART_CLOCK UART_CLOCK_FREQ_24M 43 #else 44 #define UART_CLOCK CONFIG_XTAL_FREQ 45 #endif 46 47 #define UART_TX_FIFO_THRESHOLD (0x20) 48 #define UART_RX_FIFO_THRESHOLD (0x40) 49 50 typedef uint8_t uart_unit_t; /**< uart uint id */ 51 52 typedef enum { 53 UART_ID_0 = 0, /**< UART id 0 */ 54 UART_ID_1, /**< UART id 1 */ 55 UART_ID_2, /**< UART id 2 */ 56 UART_ID_MAX /**< UART id max */ 57 } uart_id_t; 58 59 typedef enum { 60 UART_SCLK_DCO = 0, /**< UART source clock dco */ 61 UART_SCLK_XTAL_26M, /**< UART source clock xtal 26M */ 62 UART_SCLK_APLL, /**< UART source clock apll */ 63 } uart_src_clk_t; 64 65 typedef enum { 66 UART_MODE_UART = 0, /**< UART frame mode uart */ 67 UART_MODE_IDRA, /**< UART frame mode idra */ 68 } uart_frame_mode_t; 69 70 typedef enum { 71 UART_DATA_5_BITS = 0, /**< UART data bits 5bits */ 72 UART_DATA_6_BITS, /**< UART data bits 6bits */ 73 UART_DATA_7_BITS, /**< UART data bits 7bits */ 74 UART_DATA_8_BITS, /**< UART data bits 8bits */ 75 } uart_data_bits_t; 76 77 typedef enum { 78 UART_PARITY_NONE = 0, /**< UART parity none */ 79 UART_PARITY_ODD, /**< UART parity odd */ 80 UART_PARITY_EVEN, /**< UART parity even */ 81 } uart_parity_t; 82 83 typedef enum { 84 UART_STOP_BITS_1 = 0, /**< UART stop bits 1bit */ 85 UART_STOP_BITS_2, /**< UART stop bits 2bits */ 86 } uart_stop_bits_t; 87 88 typedef enum { 89 UART_FLOWCTRL_DISABLE = 0, /**< UART flow control disable */ 90 UART_FLOWCTRL_CTS_RTS, /**< UART flow control cts rts */ 91 } uart_flow_control_t; 92 93 typedef enum { 94 UART_RX_STOP_DETECT_TIME_32_BITS = 0, /**< UART rx stop time 32 bits */ 95 UART_RX_STOP_DETECT_TIME_64_BITS, /**< UART rx stop time 64 bits */ 96 UART_RX_STOP_DETECT_TIME_128_BITS, /**< UART rx stop time 128 bits */ 97 UART_RX_STOP_DETECT_TIME_256_BITS /**< UART rx stop time 256 bits */ 98 } uart_rx_stop_detect_time_t; 99 100 typedef struct { 101 uint32_t baud_rate; /**< UART baud rate */ 102 uart_data_bits_t data_bits; /**< UART data bits */ 103 uart_parity_t parity; /**< UART parity */ 104 uart_stop_bits_t stop_bits; /**< UART stop bits */ 105 uart_flow_control_t flow_ctrl; /**< UART flow control */ 106 uart_src_clk_t src_clk; /**< UART source clock */ 107 } uart_config_t; 108 109 #ifdef __cplusplus 110 } 111 #endif 112 113