1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_adc_ex.c
4 * @author MCD Application Team
5 * @brief This file provides firmware functions to manage the following
6 * functionalities of the ADC extension peripheral:
7 * + Extended features functions
8 *
9 @verbatim
10 ==============================================================================
11 ##### How to use this driver #####
12 ==============================================================================
13 [..]
14 (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
15 (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
16 (##) ADC pins configuration
17 (+++) Enable the clock for the ADC GPIOs using the following function:
18 __HAL_RCC_GPIOx_CLK_ENABLE()
19 (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
20 (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
21 (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
22 (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
23 (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
24 (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
25 (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
26 (+++) Configure and enable two DMA streams stream for managing data
27 transfer from peripheral to memory (output stream)
28 (+++) Associate the initialized DMA handle to the ADC DMA handle
29 using __HAL_LINKDMA()
30 (+++) Configure the priority and enable the NVIC for the transfer complete
31 interrupt on the two DMA Streams. The output stream should have higher
32 priority than the input stream.
33 (#) Configure the ADC Prescaler, conversion resolution and data alignment
34 using the HAL_ADC_Init() function.
35
36 (#) Configure the ADC Injected channels group features, use HAL_ADC_Init()
37 and HAL_ADC_ConfigChannel() functions.
38
39 (#) Three operation modes are available within this driver:
40
41 *** Polling mode IO operation ***
42 =================================
43 [..]
44 (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart()
45 (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
46 user can specify the value of timeout according to his end application
47 (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function.
48 (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop()
49
50 *** Interrupt mode IO operation ***
51 ===================================
52 [..]
53 (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT()
54 (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
55 (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
56 add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
57 (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
58 add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
59 (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT()
60
61 *** Multi mode ADCs Regular channels configuration ***
62 ======================================================
63 [..]
64 (+) Select the Multi mode ADC regular channels features (dual or triple mode)
65 and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions.
66 (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length
67 of data to be transferred at each end of conversion
68 (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function.
69
70
71 @endverbatim
72 ******************************************************************************
73 * @attention
74 *
75 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
76 * All rights reserved.</center></h2>
77 *
78 * This software component is licensed by ST under BSD 3-Clause license,
79 * the "License"; You may not use this file except in compliance with the
80 * License. You may obtain a copy of the License at:
81 * opensource.org/licenses/BSD-3-Clause
82 *
83 ******************************************************************************
84 */
85
86 /* Includes ------------------------------------------------------------------*/
87 #include "stm32f4xx_hal.h"
88
89 /** @addtogroup STM32F4xx_HAL_Driver
90 * @{
91 */
92
93 /** @defgroup ADCEx ADCEx
94 * @brief ADC Extended driver modules
95 * @{
96 */
97
98 #ifdef HAL_ADC_MODULE_ENABLED
99
100 /* Private typedef -----------------------------------------------------------*/
101 /* Private define ------------------------------------------------------------*/
102 /* Private macro -------------------------------------------------------------*/
103 /* Private variables ---------------------------------------------------------*/
104 /** @addtogroup ADCEx_Private_Functions
105 * @{
106 */
107 /* Private function prototypes -----------------------------------------------*/
108 static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma);
109 static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma);
110 static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma);
111 /**
112 * @}
113 */
114
115 /* Exported functions --------------------------------------------------------*/
116 /** @defgroup ADCEx_Exported_Functions ADC Exported Functions
117 * @{
118 */
119
120 /** @defgroup ADCEx_Exported_Functions_Group1 Extended features functions
121 * @brief Extended features functions
122 *
123 @verbatim
124 ===============================================================================
125 ##### Extended features functions #####
126 ===============================================================================
127 [..] This section provides functions allowing to:
128 (+) Start conversion of injected channel.
129 (+) Stop conversion of injected channel.
130 (+) Start multimode and enable DMA transfer.
131 (+) Stop multimode and disable DMA transfer.
132 (+) Get result of injected channel conversion.
133 (+) Get result of multimode conversion.
134 (+) Configure injected channels.
135 (+) Configure multimode.
136
137 @endverbatim
138 * @{
139 */
140
141 /**
142 * @brief Enables the selected ADC software start conversion of the injected channels.
143 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
144 * the configuration information for the specified ADC.
145 * @retval HAL status
146 */
HAL_ADCEx_InjectedStart(ADC_HandleTypeDef * hadc)147 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
148 {
149 __IO uint32_t counter = 0U;
150 uint32_t tmp1 = 0U, tmp2 = 0U;
151 ADC_Common_TypeDef *tmpADC_Common;
152
153 /* Process locked */
154 __HAL_LOCK(hadc);
155
156 /* Enable the ADC peripheral */
157
158 /* Check if ADC peripheral is disabled in order to enable it and wait during
159 Tstab time the ADC's stabilization */
160 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
161 {
162 /* Enable the Peripheral */
163 __HAL_ADC_ENABLE(hadc);
164
165 /* Delay for ADC stabilization time */
166 /* Compute number of CPU cycles to wait for */
167 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
168 while(counter != 0U)
169 {
170 counter--;
171 }
172 }
173
174 /* Start conversion if ADC is effectively enabled */
175 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
176 {
177 /* Set ADC state */
178 /* - Clear state bitfield related to injected group conversion results */
179 /* - Set state bitfield related to injected operation */
180 ADC_STATE_CLR_SET(hadc->State,
181 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
182 HAL_ADC_STATE_INJ_BUSY);
183
184 /* Check if a regular conversion is ongoing */
185 /* Note: On this device, there is no ADC error code fields related to */
186 /* conversions on group injected only. In case of conversion on */
187 /* going on group regular, no error code is reset. */
188 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
189 {
190 /* Reset ADC all error code fields */
191 ADC_CLEAR_ERRORCODE(hadc);
192 }
193
194 /* Process unlocked */
195 /* Unlock before starting ADC conversions: in case of potential */
196 /* interruption, to let the process to ADC IRQ Handler. */
197 __HAL_UNLOCK(hadc);
198
199 /* Clear injected group conversion flag */
200 /* (To ensure of no unknown state from potential previous ADC operations) */
201 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
202
203 /* Pointer to the common control register to which is belonging hadc */
204 /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
205 /* control register) */
206 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
207
208 /* Check if Multimode enabled */
209 if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
210 {
211 tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
212 tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
213 if(tmp1 && tmp2)
214 {
215 /* Enable the selected ADC software conversion for injected group */
216 hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
217 }
218 }
219 else
220 {
221 tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
222 tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
223 if((hadc->Instance == ADC1) && tmp1 && tmp2)
224 {
225 /* Enable the selected ADC software conversion for injected group */
226 hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
227 }
228 }
229 }
230 else
231 {
232 /* Update ADC state machine to error */
233 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
234
235 /* Set ADC error code to ADC IP internal error */
236 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
237 }
238
239 /* Return function status */
240 return HAL_OK;
241 }
242
243 /**
244 * @brief Enables the interrupt and starts ADC conversion of injected channels.
245 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
246 * the configuration information for the specified ADC.
247 *
248 * @retval HAL status.
249 */
HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef * hadc)250 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
251 {
252 __IO uint32_t counter = 0U;
253 uint32_t tmp1 = 0U, tmp2 = 0U;
254 ADC_Common_TypeDef *tmpADC_Common;
255
256 /* Process locked */
257 __HAL_LOCK(hadc);
258
259 /* Enable the ADC peripheral */
260
261 /* Check if ADC peripheral is disabled in order to enable it and wait during
262 Tstab time the ADC's stabilization */
263 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
264 {
265 /* Enable the Peripheral */
266 __HAL_ADC_ENABLE(hadc);
267
268 /* Delay for ADC stabilization time */
269 /* Compute number of CPU cycles to wait for */
270 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
271 while(counter != 0U)
272 {
273 counter--;
274 }
275 }
276
277 /* Start conversion if ADC is effectively enabled */
278 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
279 {
280 /* Set ADC state */
281 /* - Clear state bitfield related to injected group conversion results */
282 /* - Set state bitfield related to injected operation */
283 ADC_STATE_CLR_SET(hadc->State,
284 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
285 HAL_ADC_STATE_INJ_BUSY);
286
287 /* Check if a regular conversion is ongoing */
288 /* Note: On this device, there is no ADC error code fields related to */
289 /* conversions on group injected only. In case of conversion on */
290 /* going on group regular, no error code is reset. */
291 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
292 {
293 /* Reset ADC all error code fields */
294 ADC_CLEAR_ERRORCODE(hadc);
295 }
296
297 /* Process unlocked */
298 /* Unlock before starting ADC conversions: in case of potential */
299 /* interruption, to let the process to ADC IRQ Handler. */
300 __HAL_UNLOCK(hadc);
301
302 /* Clear injected group conversion flag */
303 /* (To ensure of no unknown state from potential previous ADC operations) */
304 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
305
306 /* Enable end of conversion interrupt for injected channels */
307 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
308
309 /* Pointer to the common control register to which is belonging hadc */
310 /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
311 /* control register) */
312 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
313
314 /* Check if Multimode enabled */
315 if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
316 {
317 tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
318 tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
319 if(tmp1 && tmp2)
320 {
321 /* Enable the selected ADC software conversion for injected group */
322 hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
323 }
324 }
325 else
326 {
327 tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
328 tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
329 if((hadc->Instance == ADC1) && tmp1 && tmp2)
330 {
331 /* Enable the selected ADC software conversion for injected group */
332 hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
333 }
334 }
335 }
336 else
337 {
338 /* Update ADC state machine to error */
339 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
340
341 /* Set ADC error code to ADC IP internal error */
342 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
343 }
344
345 /* Return function status */
346 return HAL_OK;
347 }
348
349 /**
350 * @brief Stop conversion of injected channels. Disable ADC peripheral if
351 * no regular conversion is on going.
352 * @note If ADC must be disabled and if conversion is on going on
353 * regular group, function HAL_ADC_Stop must be used to stop both
354 * injected and regular groups, and disable the ADC.
355 * @note If injected group mode auto-injection is enabled,
356 * function HAL_ADC_Stop must be used.
357 * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
358 * @param hadc ADC handle
359 * @retval None
360 */
HAL_ADCEx_InjectedStop(ADC_HandleTypeDef * hadc)361 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
362 {
363 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
364
365 /* Check the parameters */
366 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
367
368 /* Process locked */
369 __HAL_LOCK(hadc);
370
371 /* Stop potential conversion and disable ADC peripheral */
372 /* Conditioned to: */
373 /* - No conversion on the other group (regular group) is intended to */
374 /* continue (injected and regular groups stop conversion and ADC disable */
375 /* are common) */
376 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
377 if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
378 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
379 {
380 /* Stop potential conversion on going, on regular and injected groups */
381 /* Disable ADC peripheral */
382 __HAL_ADC_DISABLE(hadc);
383
384 /* Check if ADC is effectively disabled */
385 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
386 {
387 /* Set ADC state */
388 ADC_STATE_CLR_SET(hadc->State,
389 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
390 HAL_ADC_STATE_READY);
391 }
392 }
393 else
394 {
395 /* Update ADC state machine to error */
396 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
397
398 tmp_hal_status = HAL_ERROR;
399 }
400
401 /* Process unlocked */
402 __HAL_UNLOCK(hadc);
403
404 /* Return function status */
405 return tmp_hal_status;
406 }
407
408 /**
409 * @brief Poll for injected conversion complete
410 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
411 * the configuration information for the specified ADC.
412 * @param Timeout Timeout value in millisecond.
413 * @retval HAL status
414 */
HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef * hadc,uint32_t Timeout)415 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
416 {
417 uint32_t tickstart = 0U;
418
419 /* Get tick */
420 tickstart = HAL_GetTick();
421
422 /* Check End of conversion flag */
423 while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))
424 {
425 /* Check for the Timeout */
426 if(Timeout != HAL_MAX_DELAY)
427 {
428 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
429 {
430 /* New check to avoid false timeout detection in case of preemption */
431 if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))
432 {
433 hadc->State= HAL_ADC_STATE_TIMEOUT;
434 /* Process unlocked */
435 __HAL_UNLOCK(hadc);
436 return HAL_TIMEOUT;
437 }
438 }
439 }
440 }
441
442 /* Clear injected group conversion flag */
443 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC);
444
445 /* Update ADC state machine */
446 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
447
448 /* Determine whether any further conversion upcoming on group injected */
449 /* by external trigger, continuous mode or scan sequence on going. */
450 /* Note: On STM32F4, there is no independent flag of end of sequence. */
451 /* The test of scan sequence on going is done either with scan */
452 /* sequence disabled or with end of conversion flag set to */
453 /* of end of sequence. */
454 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
455 (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
456 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) &&
457 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
458 (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
459 (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
460 {
461 /* Set ADC state */
462 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
463
464 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
465 {
466 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
467 }
468 }
469
470 /* Return ADC state */
471 return HAL_OK;
472 }
473
474 /**
475 * @brief Stop conversion of injected channels, disable interruption of
476 * end-of-conversion. Disable ADC peripheral if no regular conversion
477 * is on going.
478 * @note If ADC must be disabled and if conversion is on going on
479 * regular group, function HAL_ADC_Stop must be used to stop both
480 * injected and regular groups, and disable the ADC.
481 * @note If injected group mode auto-injection is enabled,
482 * function HAL_ADC_Stop must be used.
483 * @param hadc ADC handle
484 * @retval None
485 */
HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef * hadc)486 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
487 {
488 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
489
490 /* Check the parameters */
491 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
492
493 /* Process locked */
494 __HAL_LOCK(hadc);
495
496 /* Stop potential conversion and disable ADC peripheral */
497 /* Conditioned to: */
498 /* - No conversion on the other group (regular group) is intended to */
499 /* continue (injected and regular groups stop conversion and ADC disable */
500 /* are common) */
501 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
502 if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
503 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
504 {
505 /* Stop potential conversion on going, on regular and injected groups */
506 /* Disable ADC peripheral */
507 __HAL_ADC_DISABLE(hadc);
508
509 /* Check if ADC is effectively disabled */
510 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
511 {
512 /* Disable ADC end of conversion interrupt for injected channels */
513 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
514
515 /* Set ADC state */
516 ADC_STATE_CLR_SET(hadc->State,
517 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
518 HAL_ADC_STATE_READY);
519 }
520 }
521 else
522 {
523 /* Update ADC state machine to error */
524 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
525
526 tmp_hal_status = HAL_ERROR;
527 }
528
529 /* Process unlocked */
530 __HAL_UNLOCK(hadc);
531
532 /* Return function status */
533 return tmp_hal_status;
534 }
535
536 /**
537 * @brief Gets the converted value from data register of injected channel.
538 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
539 * the configuration information for the specified ADC.
540 * @param InjectedRank the ADC injected rank.
541 * This parameter can be one of the following values:
542 * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
543 * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
544 * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
545 * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
546 * @retval None
547 */
HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef * hadc,uint32_t InjectedRank)548 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
549 {
550 __IO uint32_t tmp = 0U;
551
552 /* Check the parameters */
553 assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
554
555 /* Clear injected group conversion flag to have similar behaviour as */
556 /* regular group: reading data register also clears end of conversion flag. */
557 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
558
559 /* Return the selected ADC converted value */
560 switch(InjectedRank)
561 {
562 case ADC_INJECTED_RANK_4:
563 {
564 tmp = hadc->Instance->JDR4;
565 }
566 break;
567 case ADC_INJECTED_RANK_3:
568 {
569 tmp = hadc->Instance->JDR3;
570 }
571 break;
572 case ADC_INJECTED_RANK_2:
573 {
574 tmp = hadc->Instance->JDR2;
575 }
576 break;
577 case ADC_INJECTED_RANK_1:
578 {
579 tmp = hadc->Instance->JDR1;
580 }
581 break;
582 default:
583 break;
584 }
585 return tmp;
586 }
587
588 /**
589 * @brief Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral
590 *
591 * @note Caution: This function must be used only with the ADC master.
592 *
593 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
594 * the configuration information for the specified ADC.
595 * @param pData Pointer to buffer in which transferred from ADC peripheral to memory will be stored.
596 * @param Length The length of data to be transferred from ADC peripheral to memory.
597 * @retval HAL status
598 */
HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef * hadc,uint32_t * pData,uint32_t Length)599 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
600 {
601 __IO uint32_t counter = 0U;
602 ADC_Common_TypeDef *tmpADC_Common;
603
604 /* Check the parameters */
605 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
606 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
607 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
608
609 /* Process locked */
610 __HAL_LOCK(hadc);
611
612 /* Check if ADC peripheral is disabled in order to enable it and wait during
613 Tstab time the ADC's stabilization */
614 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
615 {
616 /* Enable the Peripheral */
617 __HAL_ADC_ENABLE(hadc);
618
619 /* Delay for temperature sensor stabilization time */
620 /* Compute number of CPU cycles to wait for */
621 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
622 while(counter != 0U)
623 {
624 counter--;
625 }
626 }
627
628 /* Start conversion if ADC is effectively enabled */
629 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
630 {
631 /* Set ADC state */
632 /* - Clear state bitfield related to regular group conversion results */
633 /* - Set state bitfield related to regular group operation */
634 ADC_STATE_CLR_SET(hadc->State,
635 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
636 HAL_ADC_STATE_REG_BUSY);
637
638 /* If conversions on group regular are also triggering group injected, */
639 /* update ADC state. */
640 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
641 {
642 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
643 }
644
645 /* State machine update: Check if an injected conversion is ongoing */
646 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
647 {
648 /* Reset ADC error code fields related to conversions on group regular */
649 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
650 }
651 else
652 {
653 /* Reset ADC all error code fields */
654 ADC_CLEAR_ERRORCODE(hadc);
655 }
656
657 /* Process unlocked */
658 /* Unlock before starting ADC conversions: in case of potential */
659 /* interruption, to let the process to ADC IRQ Handler. */
660 __HAL_UNLOCK(hadc);
661
662 /* Set the DMA transfer complete callback */
663 hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;
664
665 /* Set the DMA half transfer complete callback */
666 hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;
667
668 /* Set the DMA error callback */
669 hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;
670
671 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
672 /* start (in case of SW start): */
673
674 /* Clear regular group conversion flag and overrun flag */
675 /* (To ensure of no unknown state from potential previous ADC operations) */
676 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
677
678 /* Enable ADC overrun interrupt */
679 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
680
681 /* Pointer to the common control register to which is belonging hadc */
682 /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
683 /* control register) */
684 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
685
686 if (hadc->Init.DMAContinuousRequests != DISABLE)
687 {
688 /* Enable the selected ADC DMA request after last transfer */
689 tmpADC_Common->CCR |= ADC_CCR_DDS;
690 }
691 else
692 {
693 /* Disable the selected ADC EOC rising on each regular channel conversion */
694 tmpADC_Common->CCR &= ~ADC_CCR_DDS;
695 }
696
697 /* Enable the DMA Stream */
698 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
699
700 /* if no external trigger present enable software conversion of regular channels */
701 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
702 {
703 /* Enable the selected ADC software conversion for regular group */
704 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
705 }
706 }
707 else
708 {
709 /* Update ADC state machine to error */
710 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
711
712 /* Set ADC error code to ADC IP internal error */
713 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
714 }
715
716 /* Return function status */
717 return HAL_OK;
718 }
719
720 /**
721 * @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral
722 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
723 * the configuration information for the specified ADC.
724 * @retval HAL status
725 */
HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef * hadc)726 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
727 {
728 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
729 ADC_Common_TypeDef *tmpADC_Common;
730
731 /* Check the parameters */
732 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
733
734 /* Process locked */
735 __HAL_LOCK(hadc);
736
737 /* Stop potential conversion on going, on regular and injected groups */
738 /* Disable ADC peripheral */
739 __HAL_ADC_DISABLE(hadc);
740
741 /* Pointer to the common control register to which is belonging hadc */
742 /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
743 /* control register) */
744 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
745
746 /* Check if ADC is effectively disabled */
747 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
748 {
749 /* Disable the selected ADC DMA mode for multimode */
750 tmpADC_Common->CCR &= ~ADC_CCR_DDS;
751
752 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
753 /* DMA transfer is on going) */
754 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
755
756 /* Disable ADC overrun interrupt */
757 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
758
759 /* Set ADC state */
760 ADC_STATE_CLR_SET(hadc->State,
761 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
762 HAL_ADC_STATE_READY);
763 }
764
765 /* Process unlocked */
766 __HAL_UNLOCK(hadc);
767
768 /* Return function status */
769 return tmp_hal_status;
770 }
771
772 /**
773 * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results
774 * data in the selected multi mode.
775 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
776 * the configuration information for the specified ADC.
777 * @retval The converted data value.
778 */
HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef * hadc)779 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
780 {
781 ADC_Common_TypeDef *tmpADC_Common;
782
783 /* Pointer to the common control register to which is belonging hadc */
784 /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
785 /* control register) */
786 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
787
788 /* Return the multi mode conversion value */
789 return tmpADC_Common->CDR;
790 }
791
792 /**
793 * @brief Injected conversion complete callback in non blocking mode
794 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
795 * the configuration information for the specified ADC.
796 * @retval None
797 */
HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef * hadc)798 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
799 {
800 /* Prevent unused argument(s) compilation warning */
801 UNUSED(hadc);
802 /* NOTE : This function Should not be modified, when the callback is needed,
803 the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file
804 */
805 }
806
807 /**
808 * @brief Configures for the selected ADC injected channel its corresponding
809 * rank in the sequencer and its sample time.
810 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
811 * the configuration information for the specified ADC.
812 * @param sConfigInjected ADC configuration structure for injected channel.
813 * @retval None
814 */
HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef * hadc,ADC_InjectionConfTypeDef * sConfigInjected)815 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
816 {
817
818 #ifdef USE_FULL_ASSERT
819 uint32_t tmp = 0U;
820
821 #endif /* USE_FULL_ASSERT */
822
823 ADC_Common_TypeDef *tmpADC_Common;
824
825 /* Check the parameters */
826 assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
827 assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
828 assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
829 assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv));
830 assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion));
831 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
832 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
833
834 #ifdef USE_FULL_ASSERT
835 tmp = ADC_GET_RESOLUTION(hadc);
836 assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));
837 #endif /* USE_FULL_ASSERT */
838
839 if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
840 {
841 assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
842 }
843
844 /* Process locked */
845 __HAL_LOCK(hadc);
846
847 /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
848 if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9)
849 {
850 /* Clear the old sample time */
851 hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel);
852
853 /* Set the new sample time */
854 hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
855 }
856 else /* ADC_Channel include in ADC_Channel_[0..9] */
857 {
858 /* Clear the old sample time */
859 hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel);
860
861 /* Set the new sample time */
862 hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
863 }
864
865 /*---------------------------- ADCx JSQR Configuration -----------------*/
866 hadc->Instance->JSQR &= ~(ADC_JSQR_JL);
867 hadc->Instance->JSQR |= ADC_SQR1(sConfigInjected->InjectedNbrOfConversion);
868
869 /* Rank configuration */
870
871 /* Clear the old SQx bits for the selected rank */
872 hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
873
874 /* Set the SQx bits for the selected rank */
875 hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
876
877 /* Enable external trigger if trigger selection is different of software */
878 /* start. */
879 /* Note: This configuration keeps the hardware feature of parameter */
880 /* ExternalTrigConvEdge "trigger edge none" equivalent to */
881 /* software start. */
882 if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
883 {
884 /* Select external trigger to start conversion */
885 hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
886 hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv;
887
888 /* Select external trigger polarity */
889 hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
890 hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
891 }
892 else
893 {
894 /* Reset the external trigger */
895 hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
896 hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
897 }
898
899 if (sConfigInjected->AutoInjectedConv != DISABLE)
900 {
901 /* Enable the selected ADC automatic injected group conversion */
902 hadc->Instance->CR1 |= ADC_CR1_JAUTO;
903 }
904 else
905 {
906 /* Disable the selected ADC automatic injected group conversion */
907 hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO);
908 }
909
910 if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE)
911 {
912 /* Enable the selected ADC injected discontinuous mode */
913 hadc->Instance->CR1 |= ADC_CR1_JDISCEN;
914 }
915 else
916 {
917 /* Disable the selected ADC injected discontinuous mode */
918 hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN);
919 }
920
921 switch(sConfigInjected->InjectedRank)
922 {
923 case 1U:
924 /* Set injected channel 1 offset */
925 hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1);
926 hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset;
927 break;
928 case 2U:
929 /* Set injected channel 2 offset */
930 hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2);
931 hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset;
932 break;
933 case 3U:
934 /* Set injected channel 3 offset */
935 hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3);
936 hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset;
937 break;
938 default:
939 /* Set injected channel 4 offset */
940 hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4);
941 hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset;
942 break;
943 }
944
945 /* Pointer to the common control register to which is belonging hadc */
946 /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
947 /* control register) */
948 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
949
950 /* if ADC1 Channel_18 is selected enable VBAT Channel */
951 if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT))
952 {
953 /* Enable the VBAT channel*/
954 tmpADC_Common->CCR |= ADC_CCR_VBATE;
955 }
956
957 /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
958 if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)))
959 {
960 /* Enable the TSVREFE channel*/
961 tmpADC_Common->CCR |= ADC_CCR_TSVREFE;
962 }
963
964 /* Process unlocked */
965 __HAL_UNLOCK(hadc);
966
967 /* Return function status */
968 return HAL_OK;
969 }
970
971 /**
972 * @brief Configures the ADC multi-mode
973 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
974 * the configuration information for the specified ADC.
975 * @param multimode pointer to an ADC_MultiModeTypeDef structure that contains
976 * the configuration information for multimode.
977 * @retval HAL status
978 */
HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef * hadc,ADC_MultiModeTypeDef * multimode)979 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
980 {
981
982 ADC_Common_TypeDef *tmpADC_Common;
983
984 /* Check the parameters */
985 assert_param(IS_ADC_MODE(multimode->Mode));
986 assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));
987 assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
988
989 /* Process locked */
990 __HAL_LOCK(hadc);
991
992 /* Pointer to the common control register to which is belonging hadc */
993 /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
994 /* control register) */
995 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
996
997 /* Set ADC mode */
998 tmpADC_Common->CCR &= ~(ADC_CCR_MULTI);
999 tmpADC_Common->CCR |= multimode->Mode;
1000
1001 /* Set the ADC DMA access mode */
1002 tmpADC_Common->CCR &= ~(ADC_CCR_DMA);
1003 tmpADC_Common->CCR |= multimode->DMAAccessMode;
1004
1005 /* Set delay between two sampling phases */
1006 tmpADC_Common->CCR &= ~(ADC_CCR_DELAY);
1007 tmpADC_Common->CCR |= multimode->TwoSamplingDelay;
1008
1009 /* Process unlocked */
1010 __HAL_UNLOCK(hadc);
1011
1012 /* Return function status */
1013 return HAL_OK;
1014 }
1015
1016 /**
1017 * @}
1018 */
1019
1020 /**
1021 * @brief DMA transfer complete callback.
1022 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1023 * the configuration information for the specified DMA module.
1024 * @retval None
1025 */
ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef * hdma)1026 static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)
1027 {
1028 /* Retrieve ADC handle corresponding to current DMA handle */
1029 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
1030
1031 /* Update state machine on conversion status if not in error state */
1032 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
1033 {
1034 /* Update ADC state machine */
1035 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
1036
1037 /* Determine whether any further conversion upcoming on group regular */
1038 /* by external trigger, continuous mode or scan sequence on going. */
1039 /* Note: On STM32F4, there is no independent flag of end of sequence. */
1040 /* The test of scan sequence on going is done either with scan */
1041 /* sequence disabled or with end of conversion flag set to */
1042 /* of end of sequence. */
1043 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
1044 (hadc->Init.ContinuousConvMode == DISABLE) &&
1045 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
1046 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
1047 {
1048 /* Disable ADC end of single conversion interrupt on group regular */
1049 /* Note: Overrun interrupt was enabled with EOC interrupt in */
1050 /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
1051 /* by overrun IRQ process below. */
1052 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
1053
1054 /* Set ADC state */
1055 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1056
1057 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1058 {
1059 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1060 }
1061 }
1062
1063 /* Conversion complete callback */
1064 HAL_ADC_ConvCpltCallback(hadc);
1065 }
1066 else
1067 {
1068 /* Call DMA error callback */
1069 hadc->DMA_Handle->XferErrorCallback(hdma);
1070 }
1071 }
1072
1073 /**
1074 * @brief DMA half transfer complete callback.
1075 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1076 * the configuration information for the specified DMA module.
1077 * @retval None
1078 */
ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef * hdma)1079 static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma)
1080 {
1081 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
1082 /* Conversion complete callback */
1083 HAL_ADC_ConvHalfCpltCallback(hadc);
1084 }
1085
1086 /**
1087 * @brief DMA error callback
1088 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1089 * the configuration information for the specified DMA module.
1090 * @retval None
1091 */
ADC_MultiModeDMAError(DMA_HandleTypeDef * hdma)1092 static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma)
1093 {
1094 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
1095 hadc->State= HAL_ADC_STATE_ERROR_DMA;
1096 /* Set ADC error code to DMA error */
1097 hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
1098 HAL_ADC_ErrorCallback(hadc);
1099 }
1100
1101 /**
1102 * @}
1103 */
1104
1105 #endif /* HAL_ADC_MODULE_ENABLED */
1106 /**
1107 * @}
1108 */
1109
1110 /**
1111 * @}
1112 */
1113
1114 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1115