1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_i2c.c
4 * @author MCD Application Team
5 * @brief I2C HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Inter Integrated Circuit (I2C) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State, Mode and Error functions
11 *
12 @verbatim
13 ==============================================================================
14 ##### How to use this driver #####
15 ==============================================================================
16 [..]
17 The I2C HAL driver can be used as follows:
18
19 (#) Declare a I2C_HandleTypeDef handle structure, for example:
20 I2C_HandleTypeDef hi2c;
21
22 (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
23 (##) Enable the I2Cx interface clock
24 (##) I2C pins configuration
25 (+++) Enable the clock for the I2C GPIOs
26 (+++) Configure I2C pins as alternate function open-drain
27 (##) NVIC configuration if you need to use interrupt process
28 (+++) Configure the I2Cx interrupt priority
29 (+++) Enable the NVIC I2C IRQ Channel
30 (##) DMA Configuration if you need to use DMA process
31 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
32 (+++) Enable the DMAx interface clock using
33 (+++) Configure the DMA handle parameters
34 (+++) Configure the DMA Tx or Rx stream
35 (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
36 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
37 the DMA Tx or Rx stream
38
39 (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
40 Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
41
42 (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
43 (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit() API.
44
45 (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
46
47 (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
48
49 *** Polling mode IO operation ***
50 =================================
51 [..]
52 (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
53 (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
54 (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
55 (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
56
57 *** Polling mode IO MEM operation ***
58 =====================================
59 [..]
60 (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
61 (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
62
63
64 *** Interrupt mode IO operation ***
65 ===================================
66 [..]
67 (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
68 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
69 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
70 (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
71 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
72 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
73 (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
74 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
75 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
76 (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
77 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
78 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
79 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
80 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
81 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
82 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
83 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
84
85 *** Interrupt mode or DMA mode IO sequential operation ***
86 ==========================================================
87 [..]
88 (@) These interfaces allow to manage a sequential transfer with a repeated start condition
89 when a direction change during transfer
90 [..]
91 (+) A specific option field manage the different steps of a sequential transfer
92 (+) Option field values are defined through I2C_XferOptions_definition and are listed below:
93 (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode
94 (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
95 and data to transfer without a final stop condition
96 (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
97 and data to transfer without a final stop condition, an then permit a call the same master sequential interface
98 several times (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
99 or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
100 (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
101 and with new data to transfer if the direction change or manage only the new data to transfer
102 if no direction change and without a final stop condition in both cases
103 (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
104 and with new data to transfer if the direction change or manage only the new data to transfer
105 if no direction change and with a final stop condition in both cases
106 (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
107 interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
108 Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
109 or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
110 or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
111 or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
112 Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit
113 without stopping the communication and so generate a restart condition.
114 (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
115 interface.
116 Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
117 or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
118 or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
119 or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
120 Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
121
122 (+) Different sequential I2C interfaces are listed below:
123 (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Seq_Transmit_IT()
124 or using HAL_I2C_Master_Seq_Transmit_DMA()
125 (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
126 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
127 (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Seq_Receive_IT()
128 or using HAL_I2C_Master_Seq_Receive_DMA()
129 (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
130 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
131 (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
132 (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
133 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
134 (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
135 (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
136 add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
137 (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
138 add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
139 (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Seq_Transmit_IT()
140 or using HAL_I2C_Slave_Seq_Transmit_DMA()
141 (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
142 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
143 (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Seq_Receive_IT()
144 or using HAL_I2C_Slave_Seq_Receive_DMA()
145 (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
146 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
147 (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
148 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
149
150 *** Interrupt mode IO MEM operation ***
151 =======================================
152 [..]
153 (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
154 HAL_I2C_Mem_Write_IT()
155 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
156 add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
157 (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
158 HAL_I2C_Mem_Read_IT()
159 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
160 add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
161 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
162 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
163
164 *** DMA mode IO operation ***
165 ==============================
166 [..]
167 (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
168 HAL_I2C_Master_Transmit_DMA()
169 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
170 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
171 (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
172 HAL_I2C_Master_Receive_DMA()
173 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
174 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
175 (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
176 HAL_I2C_Slave_Transmit_DMA()
177 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
178 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
179 (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
180 HAL_I2C_Slave_Receive_DMA()
181 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
182 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
183 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
184 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
185 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
186 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
187 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
188
189 *** DMA mode IO MEM operation ***
190 =================================
191 [..]
192 (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
193 HAL_I2C_Mem_Write_DMA()
194 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
195 add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
196 (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
197 HAL_I2C_Mem_Read_DMA()
198 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
199 add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
200 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
201 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
202
203
204 *** I2C HAL driver macros list ***
205 ==================================
206 [..]
207 Below the list of most used macros in I2C HAL driver.
208
209 (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
210 (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
211 (+) __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not
212 (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
213 (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
214 (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
215
216 *** Callback registration ***
217 =============================================
218 [..]
219 The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
220 allows the user to configure dynamically the driver callbacks.
221 Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
222 to register an interrupt callback.
223 [..]
224 Function HAL_I2C_RegisterCallback() allows to register following callbacks:
225 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
226 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
227 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
228 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
229 (+) ListenCpltCallback : callback for end of listen mode.
230 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
231 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
232 (+) ErrorCallback : callback for error detection.
233 (+) AbortCpltCallback : callback for abort completion process.
234 (+) MspInitCallback : callback for Msp Init.
235 (+) MspDeInitCallback : callback for Msp DeInit.
236 This function takes as parameters the HAL peripheral handle, the Callback ID
237 and a pointer to the user callback function.
238 [..]
239 For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
240 [..]
241 Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
242 weak function.
243 HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
244 and the Callback ID.
245 This function allows to reset following callbacks:
246 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
247 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
248 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
249 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
250 (+) ListenCpltCallback : callback for end of listen mode.
251 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
252 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
253 (+) ErrorCallback : callback for error detection.
254 (+) AbortCpltCallback : callback for abort completion process.
255 (+) MspInitCallback : callback for Msp Init.
256 (+) MspDeInitCallback : callback for Msp DeInit.
257 [..]
258 For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
259 [..]
260 By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
261 all callbacks are set to the corresponding weak functions:
262 examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
263 Exception done for MspInit and MspDeInit functions that are
264 reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
265 these callbacks are null (not registered beforehand).
266 If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
267 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
268 [..]
269 Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
270 Exception done MspInit/MspDeInit functions that can be registered/unregistered
271 in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
272 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
273 Then, the user first registers the MspInit/MspDeInit user callbacks
274 using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
275 or HAL_I2C_Init() function.
276 [..]
277 When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
278 not defined, the callback registration feature is not available and all callbacks
279 are set to the corresponding weak functions.
280
281
282
283 [..]
284 (@) You can refer to the I2C HAL driver header file for more useful macros
285
286 @endverbatim
287 ******************************************************************************
288 * @attention
289 *
290 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
291 * All rights reserved.</center></h2>
292 *
293 * This software component is licensed by ST under BSD 3-Clause license,
294 * the "License"; You may not use this file except in compliance with the
295 * License. You may obtain a copy of the License at:
296 * opensource.org/licenses/BSD-3-Clause
297 *
298 ******************************************************************************
299 */
300
301 /* Includes ------------------------------------------------------------------*/
302 #include "stm32f4xx_hal.h"
303
304 /** @addtogroup STM32F4xx_HAL_Driver
305 * @{
306 */
307
308 /** @defgroup I2C I2C
309 * @brief I2C HAL module driver
310 * @{
311 */
312
313 #ifdef HAL_I2C_MODULE_ENABLED
314
315 /* Private typedef -----------------------------------------------------------*/
316 /* Private define ------------------------------------------------------------*/
317 /** @addtogroup I2C_Private_Define
318 * @{
319 */
320 #define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */
321 #define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */
322 #define I2C_TIMEOUT_STOP_FLAG 5U /*!< Timeout 5 ms */
323 #define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */
324
325 /* Private define for @ref PreviousState usage */
326 #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */
327 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */
328 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
329 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
330 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
331 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
332
333 /**
334 * @}
335 */
336
337 /* Private macro -------------------------------------------------------------*/
338 /* Private variables ---------------------------------------------------------*/
339 /* Private function prototypes -----------------------------------------------*/
340
341 /** @defgroup I2C_Private_Functions I2C Private Functions
342 * @{
343 */
344 /* Private functions to handle DMA transfer */
345 static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma);
346 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
347 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
348
349 static void I2C_ITError(I2C_HandleTypeDef *hi2c);
350
351 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
352 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
353 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
354 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
355
356 /* Private functions to handle flags during polling transfer */
357 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
358 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart);
359 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
360 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
361 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
362 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
363 static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c);
364 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
365
366 /* Private functions for I2C transfer IRQ handler */
367 static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
368 static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
369 static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
370 static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
371 static void I2C_Master_SB(I2C_HandleTypeDef *hi2c);
372 static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c);
373 static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);
374
375 static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
376 static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
377 static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
378 static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
379 static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags);
380 static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
381 static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
382
383 static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c);
384
385 /* Private function to Convert Specific options */
386 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
387 /**
388 * @}
389 */
390
391 /* Exported functions --------------------------------------------------------*/
392
393 /** @defgroup I2C_Exported_Functions I2C Exported Functions
394 * @{
395 */
396
397 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
398 * @brief Initialization and Configuration functions
399 *
400 @verbatim
401 ===============================================================================
402 ##### Initialization and de-initialization functions #####
403 ===============================================================================
404 [..] This subsection provides a set of functions allowing to initialize and
405 deinitialize the I2Cx peripheral:
406
407 (+) User must Implement HAL_I2C_MspInit() function in which he configures
408 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
409
410 (+) Call the function HAL_I2C_Init() to configure the selected device with
411 the selected configuration:
412 (++) Communication Speed
413 (++) Duty cycle
414 (++) Addressing mode
415 (++) Own Address 1
416 (++) Dual Addressing mode
417 (++) Own Address 2
418 (++) General call mode
419 (++) Nostretch mode
420
421 (+) Call the function HAL_I2C_DeInit() to restore the default configuration
422 of the selected I2Cx peripheral.
423
424 @endverbatim
425 * @{
426 */
427
428 /**
429 * @brief Initializes the I2C according to the specified parameters
430 * in the I2C_InitTypeDef and initialize the associated handle.
431 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
432 * the configuration information for the specified I2C.
433 * @retval HAL status
434 */
HAL_I2C_Init(I2C_HandleTypeDef * hi2c)435 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
436 {
437 uint32_t freqrange;
438 uint32_t pclk1;
439
440 /* Check the I2C handle allocation */
441 if (hi2c == NULL)
442 {
443 return HAL_ERROR;
444 }
445
446 /* Check the parameters */
447 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
448 assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed));
449 assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle));
450 assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
451 assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
452 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
453 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
454 assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
455 assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
456
457 if (hi2c->State == HAL_I2C_STATE_RESET)
458 {
459 /* Allocate lock resource and initialize it */
460 hi2c->Lock = HAL_UNLOCKED;
461
462 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
463 /* Init the I2C Callback settings */
464 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
465 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
466 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
467 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
468 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
469 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
470 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
471 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
472 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
473 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
474
475 if (hi2c->MspInitCallback == NULL)
476 {
477 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
478 }
479
480 /* Init the low level hardware : GPIO, CLOCK, NVIC */
481 hi2c->MspInitCallback(hi2c);
482 #else
483 /* Init the low level hardware : GPIO, CLOCK, NVIC */
484 HAL_I2C_MspInit(hi2c);
485 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
486 }
487
488 hi2c->State = HAL_I2C_STATE_BUSY;
489
490 /* Disable the selected I2C peripheral */
491 __HAL_I2C_DISABLE(hi2c);
492
493 /*Reset I2C*/
494 hi2c->Instance->CR1 |= I2C_CR1_SWRST;
495 hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
496
497 /* Get PCLK1 frequency */
498 pclk1 = HAL_RCC_GetPCLK1Freq();
499
500 /* Check the minimum allowed PCLK1 frequency */
501 if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
502 {
503 return HAL_ERROR;
504 }
505
506 /* Calculate frequency range */
507 freqrange = I2C_FREQRANGE(pclk1);
508
509 /*---------------------------- I2Cx CR2 Configuration ----------------------*/
510 /* Configure I2Cx: Frequency range */
511 MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
512
513 /*---------------------------- I2Cx TRISE Configuration --------------------*/
514 /* Configure I2Cx: Rise Time */
515 MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
516
517 /*---------------------------- I2Cx CCR Configuration ----------------------*/
518 /* Configure I2Cx: Speed */
519 MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
520
521 /*---------------------------- I2Cx CR1 Configuration ----------------------*/
522 /* Configure I2Cx: Generalcall and NoStretch mode */
523 MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
524
525 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
526 /* Configure I2Cx: Own Address1 and addressing mode */
527 MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
528
529 /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
530 /* Configure I2Cx: Dual mode and Own Address2 */
531 MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
532
533 /* Enable the selected I2C peripheral */
534 __HAL_I2C_ENABLE(hi2c);
535
536 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
537 hi2c->State = HAL_I2C_STATE_READY;
538 hi2c->PreviousState = I2C_STATE_NONE;
539 hi2c->Mode = HAL_I2C_MODE_NONE;
540
541 return HAL_OK;
542 }
543
544 /**
545 * @brief DeInitialize the I2C peripheral.
546 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
547 * the configuration information for the specified I2C.
548 * @retval HAL status
549 */
HAL_I2C_DeInit(I2C_HandleTypeDef * hi2c)550 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
551 {
552 /* Check the I2C handle allocation */
553 if (hi2c == NULL)
554 {
555 return HAL_ERROR;
556 }
557
558 /* Check the parameters */
559 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
560
561 hi2c->State = HAL_I2C_STATE_BUSY;
562
563 /* Disable the I2C Peripheral Clock */
564 __HAL_I2C_DISABLE(hi2c);
565
566 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
567 if (hi2c->MspDeInitCallback == NULL)
568 {
569 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
570 }
571
572 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
573 hi2c->MspDeInitCallback(hi2c);
574 #else
575 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
576 HAL_I2C_MspDeInit(hi2c);
577 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
578
579 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
580 hi2c->State = HAL_I2C_STATE_RESET;
581 hi2c->PreviousState = I2C_STATE_NONE;
582 hi2c->Mode = HAL_I2C_MODE_NONE;
583
584 /* Release Lock */
585 __HAL_UNLOCK(hi2c);
586
587 return HAL_OK;
588 }
589
590 /**
591 * @brief Initialize the I2C MSP.
592 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
593 * the configuration information for the specified I2C.
594 * @retval None
595 */
HAL_I2C_MspInit(I2C_HandleTypeDef * hi2c)596 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
597 {
598 /* Prevent unused argument(s) compilation warning */
599 UNUSED(hi2c);
600
601 /* NOTE : This function should not be modified, when the callback is needed,
602 the HAL_I2C_MspInit could be implemented in the user file
603 */
604 }
605
606 /**
607 * @brief DeInitialize the I2C MSP.
608 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
609 * the configuration information for the specified I2C.
610 * @retval None
611 */
HAL_I2C_MspDeInit(I2C_HandleTypeDef * hi2c)612 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
613 {
614 /* Prevent unused argument(s) compilation warning */
615 UNUSED(hi2c);
616
617 /* NOTE : This function should not be modified, when the callback is needed,
618 the HAL_I2C_MspDeInit could be implemented in the user file
619 */
620 }
621
622 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
623 /**
624 * @brief Register a User I2C Callback
625 * To be used instead of the weak predefined callback
626 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
627 * the configuration information for the specified I2C.
628 * @param CallbackID ID of the callback to be registered
629 * This parameter can be one of the following values:
630 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
631 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
632 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
633 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
634 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
635 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
636 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
637 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
638 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
639 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
640 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
641 * @param pCallback pointer to the Callback function
642 * @retval HAL status
643 */
HAL_I2C_RegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID,pI2C_CallbackTypeDef pCallback)644 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
645 {
646 HAL_StatusTypeDef status = HAL_OK;
647
648 if (pCallback == NULL)
649 {
650 /* Update the error code */
651 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
652
653 return HAL_ERROR;
654 }
655 /* Process locked */
656 __HAL_LOCK(hi2c);
657
658 if (HAL_I2C_STATE_READY == hi2c->State)
659 {
660 switch (CallbackID)
661 {
662 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
663 hi2c->MasterTxCpltCallback = pCallback;
664 break;
665
666 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
667 hi2c->MasterRxCpltCallback = pCallback;
668 break;
669
670 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
671 hi2c->SlaveTxCpltCallback = pCallback;
672 break;
673
674 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
675 hi2c->SlaveRxCpltCallback = pCallback;
676 break;
677
678 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
679 hi2c->ListenCpltCallback = pCallback;
680 break;
681
682 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
683 hi2c->MemTxCpltCallback = pCallback;
684 break;
685
686 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
687 hi2c->MemRxCpltCallback = pCallback;
688 break;
689
690 case HAL_I2C_ERROR_CB_ID :
691 hi2c->ErrorCallback = pCallback;
692 break;
693
694 case HAL_I2C_ABORT_CB_ID :
695 hi2c->AbortCpltCallback = pCallback;
696 break;
697
698 case HAL_I2C_MSPINIT_CB_ID :
699 hi2c->MspInitCallback = pCallback;
700 break;
701
702 case HAL_I2C_MSPDEINIT_CB_ID :
703 hi2c->MspDeInitCallback = pCallback;
704 break;
705
706 default :
707 /* Update the error code */
708 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
709
710 /* Return error status */
711 status = HAL_ERROR;
712 break;
713 }
714 }
715 else if (HAL_I2C_STATE_RESET == hi2c->State)
716 {
717 switch (CallbackID)
718 {
719 case HAL_I2C_MSPINIT_CB_ID :
720 hi2c->MspInitCallback = pCallback;
721 break;
722
723 case HAL_I2C_MSPDEINIT_CB_ID :
724 hi2c->MspDeInitCallback = pCallback;
725 break;
726
727 default :
728 /* Update the error code */
729 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
730
731 /* Return error status */
732 status = HAL_ERROR;
733 break;
734 }
735 }
736 else
737 {
738 /* Update the error code */
739 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
740
741 /* Return error status */
742 status = HAL_ERROR;
743 }
744
745 /* Release Lock */
746 __HAL_UNLOCK(hi2c);
747 return status;
748 }
749
750 /**
751 * @brief Unregister an I2C Callback
752 * I2C callback is redirected to the weak predefined callback
753 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
754 * the configuration information for the specified I2C.
755 * @param CallbackID ID of the callback to be unregistered
756 * This parameter can be one of the following values:
757 * This parameter can be one of the following values:
758 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
759 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
760 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
761 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
762 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
763 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
764 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
765 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
766 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
767 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
768 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
769 * @retval HAL status
770 */
HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID)771 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
772 {
773 HAL_StatusTypeDef status = HAL_OK;
774
775 /* Process locked */
776 __HAL_LOCK(hi2c);
777
778 if (HAL_I2C_STATE_READY == hi2c->State)
779 {
780 switch (CallbackID)
781 {
782 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
783 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
784 break;
785
786 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
787 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
788 break;
789
790 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
791 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
792 break;
793
794 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
795 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
796 break;
797
798 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
799 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
800 break;
801
802 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
803 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
804 break;
805
806 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
807 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
808 break;
809
810 case HAL_I2C_ERROR_CB_ID :
811 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
812 break;
813
814 case HAL_I2C_ABORT_CB_ID :
815 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
816 break;
817
818 case HAL_I2C_MSPINIT_CB_ID :
819 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
820 break;
821
822 case HAL_I2C_MSPDEINIT_CB_ID :
823 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
824 break;
825
826 default :
827 /* Update the error code */
828 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
829
830 /* Return error status */
831 status = HAL_ERROR;
832 break;
833 }
834 }
835 else if (HAL_I2C_STATE_RESET == hi2c->State)
836 {
837 switch (CallbackID)
838 {
839 case HAL_I2C_MSPINIT_CB_ID :
840 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
841 break;
842
843 case HAL_I2C_MSPDEINIT_CB_ID :
844 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
845 break;
846
847 default :
848 /* Update the error code */
849 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
850
851 /* Return error status */
852 status = HAL_ERROR;
853 break;
854 }
855 }
856 else
857 {
858 /* Update the error code */
859 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
860
861 /* Return error status */
862 status = HAL_ERROR;
863 }
864
865 /* Release Lock */
866 __HAL_UNLOCK(hi2c);
867 return status;
868 }
869
870 /**
871 * @brief Register the Slave Address Match I2C Callback
872 * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
873 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
874 * the configuration information for the specified I2C.
875 * @param pCallback pointer to the Address Match Callback function
876 * @retval HAL status
877 */
HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef * hi2c,pI2C_AddrCallbackTypeDef pCallback)878 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
879 {
880 HAL_StatusTypeDef status = HAL_OK;
881
882 if (pCallback == NULL)
883 {
884 /* Update the error code */
885 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
886
887 return HAL_ERROR;
888 }
889 /* Process locked */
890 __HAL_LOCK(hi2c);
891
892 if (HAL_I2C_STATE_READY == hi2c->State)
893 {
894 hi2c->AddrCallback = pCallback;
895 }
896 else
897 {
898 /* Update the error code */
899 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
900
901 /* Return error status */
902 status = HAL_ERROR;
903 }
904
905 /* Release Lock */
906 __HAL_UNLOCK(hi2c);
907 return status;
908 }
909
910 /**
911 * @brief UnRegister the Slave Address Match I2C Callback
912 * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
913 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
914 * the configuration information for the specified I2C.
915 * @retval HAL status
916 */
HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef * hi2c)917 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
918 {
919 HAL_StatusTypeDef status = HAL_OK;
920
921 /* Process locked */
922 __HAL_LOCK(hi2c);
923
924 if (HAL_I2C_STATE_READY == hi2c->State)
925 {
926 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
927 }
928 else
929 {
930 /* Update the error code */
931 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
932
933 /* Return error status */
934 status = HAL_ERROR;
935 }
936
937 /* Release Lock */
938 __HAL_UNLOCK(hi2c);
939 return status;
940 }
941
942 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
943
944 /**
945 * @}
946 */
947
948 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
949 * @brief Data transfers functions
950 *
951 @verbatim
952 ===============================================================================
953 ##### IO operation functions #####
954 ===============================================================================
955 [..]
956 This subsection provides a set of functions allowing to manage the I2C data
957 transfers.
958
959 (#) There are two modes of transfer:
960 (++) Blocking mode : The communication is performed in the polling mode.
961 The status of all data processing is returned by the same function
962 after finishing transfer.
963 (++) No-Blocking mode : The communication is performed using Interrupts
964 or DMA. These functions return the status of the transfer startup.
965 The end of the data processing will be indicated through the
966 dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
967 using DMA mode.
968
969 (#) Blocking mode functions are :
970 (++) HAL_I2C_Master_Transmit()
971 (++) HAL_I2C_Master_Receive()
972 (++) HAL_I2C_Slave_Transmit()
973 (++) HAL_I2C_Slave_Receive()
974 (++) HAL_I2C_Mem_Write()
975 (++) HAL_I2C_Mem_Read()
976 (++) HAL_I2C_IsDeviceReady()
977
978 (#) No-Blocking mode functions with Interrupt are :
979 (++) HAL_I2C_Master_Transmit_IT()
980 (++) HAL_I2C_Master_Receive_IT()
981 (++) HAL_I2C_Slave_Transmit_IT()
982 (++) HAL_I2C_Slave_Receive_IT()
983 (++) HAL_I2C_Mem_Write_IT()
984 (++) HAL_I2C_Mem_Read_IT()
985 (++) HAL_I2C_Master_Seq_Transmit_IT()
986 (++) HAL_I2C_Master_Seq_Receive_IT()
987 (++) HAL_I2C_Slave_Seq_Transmit_IT()
988 (++) HAL_I2C_Slave_Seq_Receive_IT()
989 (++) HAL_I2C_EnableListen_IT()
990 (++) HAL_I2C_DisableListen_IT()
991 (++) HAL_I2C_Master_Abort_IT()
992
993 (#) No-Blocking mode functions with DMA are :
994 (++) HAL_I2C_Master_Transmit_DMA()
995 (++) HAL_I2C_Master_Receive_DMA()
996 (++) HAL_I2C_Slave_Transmit_DMA()
997 (++) HAL_I2C_Slave_Receive_DMA()
998 (++) HAL_I2C_Mem_Write_DMA()
999 (++) HAL_I2C_Mem_Read_DMA()
1000 (++) HAL_I2C_Master_Seq_Transmit_DMA()
1001 (++) HAL_I2C_Master_Seq_Receive_DMA()
1002 (++) HAL_I2C_Slave_Seq_Transmit_DMA()
1003 (++) HAL_I2C_Slave_Seq_Receive_DMA()
1004
1005 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
1006 (++) HAL_I2C_MasterTxCpltCallback()
1007 (++) HAL_I2C_MasterRxCpltCallback()
1008 (++) HAL_I2C_SlaveTxCpltCallback()
1009 (++) HAL_I2C_SlaveRxCpltCallback()
1010 (++) HAL_I2C_MemTxCpltCallback()
1011 (++) HAL_I2C_MemRxCpltCallback()
1012 (++) HAL_I2C_AddrCallback()
1013 (++) HAL_I2C_ListenCpltCallback()
1014 (++) HAL_I2C_ErrorCallback()
1015 (++) HAL_I2C_AbortCpltCallback()
1016
1017 @endverbatim
1018 * @{
1019 */
1020
1021 /**
1022 * @brief Transmits in master mode an amount of data in blocking mode.
1023 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1024 * the configuration information for the specified I2C.
1025 * @param DevAddress Target device address: The device 7 bits address value
1026 * in datasheet must be shifted to the left before calling the interface
1027 * @param pData Pointer to data buffer
1028 * @param Size Amount of data to be sent
1029 * @param Timeout Timeout duration
1030 * @retval HAL status
1031 */
HAL_I2C_Master_Transmit(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1032 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1033 {
1034 /* Init tickstart for timeout management*/
1035 uint32_t tickstart = HAL_GetTick();
1036
1037 if (hi2c->State == HAL_I2C_STATE_READY)
1038 {
1039 /* Wait until BUSY flag is reset */
1040 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
1041 {
1042 return HAL_BUSY;
1043 }
1044
1045 /* Process Locked */
1046 __HAL_LOCK(hi2c);
1047
1048 /* Check if the I2C is already enabled */
1049 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1050 {
1051 /* Enable I2C peripheral */
1052 __HAL_I2C_ENABLE(hi2c);
1053 }
1054
1055 /* Disable Pos */
1056 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1057
1058 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1059 hi2c->Mode = HAL_I2C_MODE_MASTER;
1060 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1061
1062 /* Prepare transfer parameters */
1063 hi2c->pBuffPtr = pData;
1064 hi2c->XferCount = Size;
1065 hi2c->XferSize = hi2c->XferCount;
1066 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1067
1068 /* Send Slave Address */
1069 if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
1070 {
1071 return HAL_ERROR;
1072 }
1073
1074 /* Clear ADDR flag */
1075 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1076
1077 while (hi2c->XferSize > 0U)
1078 {
1079 /* Wait until TXE flag is set */
1080 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1081 {
1082 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1083 {
1084 /* Generate Stop */
1085 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1086 }
1087 return HAL_ERROR;
1088 }
1089
1090 /* Write data to DR */
1091 hi2c->Instance->DR = *hi2c->pBuffPtr;
1092
1093 /* Increment Buffer pointer */
1094 hi2c->pBuffPtr++;
1095
1096 /* Update counter */
1097 hi2c->XferCount--;
1098 hi2c->XferSize--;
1099
1100 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
1101 {
1102 /* Write data to DR */
1103 hi2c->Instance->DR = *hi2c->pBuffPtr;
1104
1105 /* Increment Buffer pointer */
1106 hi2c->pBuffPtr++;
1107
1108 /* Update counter */
1109 hi2c->XferCount--;
1110 hi2c->XferSize--;
1111 }
1112
1113 /* Wait until BTF flag is set */
1114 if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1115 {
1116 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1117 {
1118 /* Generate Stop */
1119 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1120 }
1121 return HAL_ERROR;
1122 }
1123 }
1124
1125 /* Generate Stop */
1126 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1127
1128 hi2c->State = HAL_I2C_STATE_READY;
1129 hi2c->Mode = HAL_I2C_MODE_NONE;
1130
1131 /* Process Unlocked */
1132 __HAL_UNLOCK(hi2c);
1133
1134 return HAL_OK;
1135 }
1136 else
1137 {
1138 return HAL_BUSY;
1139 }
1140 }
1141
1142 /**
1143 * @brief Receives in master mode an amount of data in blocking mode.
1144 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1145 * the configuration information for the specified I2C.
1146 * @param DevAddress Target device address: The device 7 bits address value
1147 * in datasheet must be shifted to the left before calling the interface
1148 * @param pData Pointer to data buffer
1149 * @param Size Amount of data to be sent
1150 * @param Timeout Timeout duration
1151 * @retval HAL status
1152 */
HAL_I2C_Master_Receive(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1153 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1154 {
1155 /* Init tickstart for timeout management*/
1156 uint32_t tickstart = HAL_GetTick();
1157
1158 if (hi2c->State == HAL_I2C_STATE_READY)
1159 {
1160 /* Wait until BUSY flag is reset */
1161 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
1162 {
1163 return HAL_BUSY;
1164 }
1165
1166 /* Process Locked */
1167 __HAL_LOCK(hi2c);
1168
1169 /* Check if the I2C is already enabled */
1170 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1171 {
1172 /* Enable I2C peripheral */
1173 __HAL_I2C_ENABLE(hi2c);
1174 }
1175
1176 /* Disable Pos */
1177 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1178
1179 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1180 hi2c->Mode = HAL_I2C_MODE_MASTER;
1181 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1182
1183 /* Prepare transfer parameters */
1184 hi2c->pBuffPtr = pData;
1185 hi2c->XferCount = Size;
1186 hi2c->XferSize = hi2c->XferCount;
1187 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1188
1189 /* Send Slave Address */
1190 if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
1191 {
1192 return HAL_ERROR;
1193 }
1194
1195 if (hi2c->XferSize == 0U)
1196 {
1197 /* Clear ADDR flag */
1198 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1199
1200 /* Generate Stop */
1201 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1202 }
1203 else if (hi2c->XferSize == 1U)
1204 {
1205 /* Disable Acknowledge */
1206 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1207
1208 /* Clear ADDR flag */
1209 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1210
1211 /* Generate Stop */
1212 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1213 }
1214 else if (hi2c->XferSize == 2U)
1215 {
1216 /* Disable Acknowledge */
1217 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1218
1219 /* Enable Pos */
1220 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1221
1222 /* Clear ADDR flag */
1223 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1224 }
1225 else
1226 {
1227 /* Enable Acknowledge */
1228 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1229
1230 /* Clear ADDR flag */
1231 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1232 }
1233
1234 while (hi2c->XferSize > 0U)
1235 {
1236 if (hi2c->XferSize <= 3U)
1237 {
1238 /* One byte */
1239 if (hi2c->XferSize == 1U)
1240 {
1241 /* Wait until RXNE flag is set */
1242 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1243 {
1244 return HAL_ERROR;
1245 }
1246
1247 /* Read data from DR */
1248 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1249
1250 /* Increment Buffer pointer */
1251 hi2c->pBuffPtr++;
1252
1253 /* Update counter */
1254 hi2c->XferSize--;
1255 hi2c->XferCount--;
1256 }
1257 /* Two bytes */
1258 else if (hi2c->XferSize == 2U)
1259 {
1260 /* Wait until BTF flag is set */
1261 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
1262 {
1263 return HAL_ERROR;
1264 }
1265
1266 /* Generate Stop */
1267 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1268
1269 /* Read data from DR */
1270 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1271
1272 /* Increment Buffer pointer */
1273 hi2c->pBuffPtr++;
1274
1275 /* Update counter */
1276 hi2c->XferSize--;
1277 hi2c->XferCount--;
1278
1279 /* Read data from DR */
1280 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1281
1282 /* Increment Buffer pointer */
1283 hi2c->pBuffPtr++;
1284
1285 /* Update counter */
1286 hi2c->XferSize--;
1287 hi2c->XferCount--;
1288 }
1289 /* 3 Last bytes */
1290 else
1291 {
1292 /* Wait until BTF flag is set */
1293 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
1294 {
1295 return HAL_ERROR;
1296 }
1297
1298 /* Disable Acknowledge */
1299 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1300
1301 /* Read data from DR */
1302 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1303
1304 /* Increment Buffer pointer */
1305 hi2c->pBuffPtr++;
1306
1307 /* Update counter */
1308 hi2c->XferSize--;
1309 hi2c->XferCount--;
1310
1311 /* Wait until BTF flag is set */
1312 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
1313 {
1314 return HAL_ERROR;
1315 }
1316
1317 /* Generate Stop */
1318 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1319
1320 /* Read data from DR */
1321 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1322
1323 /* Increment Buffer pointer */
1324 hi2c->pBuffPtr++;
1325
1326 /* Update counter */
1327 hi2c->XferSize--;
1328 hi2c->XferCount--;
1329
1330 /* Read data from DR */
1331 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1332
1333 /* Increment Buffer pointer */
1334 hi2c->pBuffPtr++;
1335
1336 /* Update counter */
1337 hi2c->XferSize--;
1338 hi2c->XferCount--;
1339 }
1340 }
1341 else
1342 {
1343 /* Wait until RXNE flag is set */
1344 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1345 {
1346 return HAL_ERROR;
1347 }
1348
1349 /* Read data from DR */
1350 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1351
1352 /* Increment Buffer pointer */
1353 hi2c->pBuffPtr++;
1354
1355 /* Update counter */
1356 hi2c->XferSize--;
1357 hi2c->XferCount--;
1358
1359 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
1360 {
1361 /* Read data from DR */
1362 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1363
1364 /* Increment Buffer pointer */
1365 hi2c->pBuffPtr++;
1366
1367 /* Update counter */
1368 hi2c->XferSize--;
1369 hi2c->XferCount--;
1370 }
1371 }
1372 }
1373
1374 hi2c->State = HAL_I2C_STATE_READY;
1375 hi2c->Mode = HAL_I2C_MODE_NONE;
1376
1377 /* Process Unlocked */
1378 __HAL_UNLOCK(hi2c);
1379
1380 return HAL_OK;
1381 }
1382 else
1383 {
1384 return HAL_BUSY;
1385 }
1386 }
1387
1388 /**
1389 * @brief Transmits in slave mode an amount of data in blocking mode.
1390 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1391 * the configuration information for the specified I2C.
1392 * @param pData Pointer to data buffer
1393 * @param Size Amount of data to be sent
1394 * @param Timeout Timeout duration
1395 * @retval HAL status
1396 */
HAL_I2C_Slave_Transmit(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1397 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1398 {
1399 /* Init tickstart for timeout management*/
1400 uint32_t tickstart = HAL_GetTick();
1401
1402 if (hi2c->State == HAL_I2C_STATE_READY)
1403 {
1404 if ((pData == NULL) || (Size == 0U))
1405 {
1406 return HAL_ERROR;
1407 }
1408
1409 /* Process Locked */
1410 __HAL_LOCK(hi2c);
1411
1412 /* Check if the I2C is already enabled */
1413 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1414 {
1415 /* Enable I2C peripheral */
1416 __HAL_I2C_ENABLE(hi2c);
1417 }
1418
1419 /* Disable Pos */
1420 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1421
1422 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1423 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1424 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1425
1426 /* Prepare transfer parameters */
1427 hi2c->pBuffPtr = pData;
1428 hi2c->XferCount = Size;
1429 hi2c->XferSize = hi2c->XferCount;
1430 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1431
1432 /* Enable Address Acknowledge */
1433 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1434
1435 /* Wait until ADDR flag is set */
1436 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1437 {
1438 return HAL_ERROR;
1439 }
1440
1441 /* Clear ADDR flag */
1442 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1443
1444 /* If 10bit addressing mode is selected */
1445 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
1446 {
1447 /* Wait until ADDR flag is set */
1448 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1449 {
1450 return HAL_ERROR;
1451 }
1452
1453 /* Clear ADDR flag */
1454 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1455 }
1456
1457 while (hi2c->XferSize > 0U)
1458 {
1459 /* Wait until TXE flag is set */
1460 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1461 {
1462 /* Disable Address Acknowledge */
1463 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1464
1465 return HAL_ERROR;
1466 }
1467
1468 /* Write data to DR */
1469 hi2c->Instance->DR = *hi2c->pBuffPtr;
1470
1471 /* Increment Buffer pointer */
1472 hi2c->pBuffPtr++;
1473
1474 /* Update counter */
1475 hi2c->XferCount--;
1476 hi2c->XferSize--;
1477
1478 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
1479 {
1480 /* Write data to DR */
1481 hi2c->Instance->DR = *hi2c->pBuffPtr;
1482
1483 /* Increment Buffer pointer */
1484 hi2c->pBuffPtr++;
1485
1486 /* Update counter */
1487 hi2c->XferCount--;
1488 hi2c->XferSize--;
1489 }
1490 }
1491
1492 /* Wait until AF flag is set */
1493 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
1494 {
1495 return HAL_ERROR;
1496 }
1497
1498 /* Clear AF flag */
1499 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
1500
1501 /* Disable Address Acknowledge */
1502 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1503
1504 hi2c->State = HAL_I2C_STATE_READY;
1505 hi2c->Mode = HAL_I2C_MODE_NONE;
1506
1507 /* Process Unlocked */
1508 __HAL_UNLOCK(hi2c);
1509
1510 return HAL_OK;
1511 }
1512 else
1513 {
1514 return HAL_BUSY;
1515 }
1516 }
1517
1518 /**
1519 * @brief Receive in slave mode an amount of data in blocking mode
1520 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1521 * the configuration information for the specified I2C.
1522 * @param pData Pointer to data buffer
1523 * @param Size Amount of data to be sent
1524 * @param Timeout Timeout duration
1525 * @retval HAL status
1526 */
HAL_I2C_Slave_Receive(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1527 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1528 {
1529 /* Init tickstart for timeout management*/
1530 uint32_t tickstart = HAL_GetTick();
1531
1532 if (hi2c->State == HAL_I2C_STATE_READY)
1533 {
1534 if ((pData == NULL) || (Size == (uint16_t)0))
1535 {
1536 return HAL_ERROR;
1537 }
1538
1539 /* Process Locked */
1540 __HAL_LOCK(hi2c);
1541
1542 /* Check if the I2C is already enabled */
1543 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1544 {
1545 /* Enable I2C peripheral */
1546 __HAL_I2C_ENABLE(hi2c);
1547 }
1548
1549 /* Disable Pos */
1550 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1551
1552 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1553 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1554 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1555
1556 /* Prepare transfer parameters */
1557 hi2c->pBuffPtr = pData;
1558 hi2c->XferCount = Size;
1559 hi2c->XferSize = hi2c->XferCount;
1560 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1561
1562 /* Enable Address Acknowledge */
1563 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1564
1565 /* Wait until ADDR flag is set */
1566 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1567 {
1568 return HAL_ERROR;
1569 }
1570
1571 /* Clear ADDR flag */
1572 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1573
1574 while (hi2c->XferSize > 0U)
1575 {
1576 /* Wait until RXNE flag is set */
1577 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1578 {
1579 /* Disable Address Acknowledge */
1580 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1581
1582 return HAL_ERROR;
1583 }
1584
1585 /* Read data from DR */
1586 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1587
1588 /* Increment Buffer pointer */
1589 hi2c->pBuffPtr++;
1590
1591 /* Update counter */
1592 hi2c->XferSize--;
1593 hi2c->XferCount--;
1594
1595 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
1596 {
1597 /* Read data from DR */
1598 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1599
1600 /* Increment Buffer pointer */
1601 hi2c->pBuffPtr++;
1602
1603 /* Update counter */
1604 hi2c->XferSize--;
1605 hi2c->XferCount--;
1606 }
1607 }
1608
1609 /* Wait until STOP flag is set */
1610 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1611 {
1612 /* Disable Address Acknowledge */
1613 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1614
1615 return HAL_ERROR;
1616 }
1617
1618 /* Clear STOP flag */
1619 __HAL_I2C_CLEAR_STOPFLAG(hi2c);
1620
1621 /* Disable Address Acknowledge */
1622 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1623
1624 hi2c->State = HAL_I2C_STATE_READY;
1625 hi2c->Mode = HAL_I2C_MODE_NONE;
1626
1627 /* Process Unlocked */
1628 __HAL_UNLOCK(hi2c);
1629
1630 return HAL_OK;
1631 }
1632 else
1633 {
1634 return HAL_BUSY;
1635 }
1636 }
1637
1638 /**
1639 * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
1640 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1641 * the configuration information for the specified I2C.
1642 * @param DevAddress Target device address: The device 7 bits address value
1643 * in datasheet must be shifted to the left before calling the interface
1644 * @param pData Pointer to data buffer
1645 * @param Size Amount of data to be sent
1646 * @retval HAL status
1647 */
HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1648 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1649 {
1650 __IO uint32_t count = 0U;
1651
1652 if (hi2c->State == HAL_I2C_STATE_READY)
1653 {
1654 /* Wait until BUSY flag is reset */
1655 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
1656 do
1657 {
1658 count--;
1659 if (count == 0U)
1660 {
1661 hi2c->PreviousState = I2C_STATE_NONE;
1662 hi2c->State = HAL_I2C_STATE_READY;
1663 hi2c->Mode = HAL_I2C_MODE_NONE;
1664 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
1665
1666 /* Process Unlocked */
1667 __HAL_UNLOCK(hi2c);
1668
1669 return HAL_ERROR;
1670 }
1671 }
1672 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1673
1674 /* Process Locked */
1675 __HAL_LOCK(hi2c);
1676
1677 /* Check if the I2C is already enabled */
1678 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1679 {
1680 /* Enable I2C peripheral */
1681 __HAL_I2C_ENABLE(hi2c);
1682 }
1683
1684 /* Disable Pos */
1685 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1686
1687 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1688 hi2c->Mode = HAL_I2C_MODE_MASTER;
1689 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1690
1691 /* Prepare transfer parameters */
1692 hi2c->pBuffPtr = pData;
1693 hi2c->XferCount = Size;
1694 hi2c->XferSize = hi2c->XferCount;
1695 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1696 hi2c->Devaddress = DevAddress;
1697
1698 /* Process Unlocked */
1699 __HAL_UNLOCK(hi2c);
1700
1701 /* Note : The I2C interrupts must be enabled after unlocking current process
1702 to avoid the risk of I2C interrupt handle execution before current
1703 process unlock */
1704 /* Enable EVT, BUF and ERR interrupt */
1705 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1706
1707 /* Generate Start */
1708 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
1709
1710 return HAL_OK;
1711 }
1712 else
1713 {
1714 return HAL_BUSY;
1715 }
1716 }
1717
1718 /**
1719 * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
1720 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1721 * the configuration information for the specified I2C.
1722 * @param DevAddress Target device address: The device 7 bits address value
1723 * in datasheet must be shifted to the left before calling the interface
1724 * @param pData Pointer to data buffer
1725 * @param Size Amount of data to be sent
1726 * @retval HAL status
1727 */
HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1728 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1729 {
1730 __IO uint32_t count = 0U;
1731
1732 if (hi2c->State == HAL_I2C_STATE_READY)
1733 {
1734 /* Wait until BUSY flag is reset */
1735 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
1736 do
1737 {
1738 count--;
1739 if (count == 0U)
1740 {
1741 hi2c->PreviousState = I2C_STATE_NONE;
1742 hi2c->State = HAL_I2C_STATE_READY;
1743 hi2c->Mode = HAL_I2C_MODE_NONE;
1744 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
1745
1746 /* Process Unlocked */
1747 __HAL_UNLOCK(hi2c);
1748
1749 return HAL_ERROR;
1750 }
1751 }
1752 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1753
1754 /* Process Locked */
1755 __HAL_LOCK(hi2c);
1756
1757 /* Check if the I2C is already enabled */
1758 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1759 {
1760 /* Enable I2C peripheral */
1761 __HAL_I2C_ENABLE(hi2c);
1762 }
1763
1764 /* Disable Pos */
1765 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1766
1767 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1768 hi2c->Mode = HAL_I2C_MODE_MASTER;
1769 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1770
1771 /* Prepare transfer parameters */
1772 hi2c->pBuffPtr = pData;
1773 hi2c->XferCount = Size;
1774 hi2c->XferSize = hi2c->XferCount;
1775 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1776 hi2c->Devaddress = DevAddress;
1777
1778
1779 /* Process Unlocked */
1780 __HAL_UNLOCK(hi2c);
1781
1782 /* Note : The I2C interrupts must be enabled after unlocking current process
1783 to avoid the risk of I2C interrupt handle execution before current
1784 process unlock */
1785
1786 /* Enable EVT, BUF and ERR interrupt */
1787 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1788
1789 /* Enable Acknowledge */
1790 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1791
1792 /* Generate Start */
1793 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
1794
1795 return HAL_OK;
1796 }
1797 else
1798 {
1799 return HAL_BUSY;
1800 }
1801 }
1802
1803 /**
1804 * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
1805 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1806 * the configuration information for the specified I2C.
1807 * @param pData Pointer to data buffer
1808 * @param Size Amount of data to be sent
1809 * @retval HAL status
1810 */
HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1811 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1812 {
1813
1814 if (hi2c->State == HAL_I2C_STATE_READY)
1815 {
1816 if ((pData == NULL) || (Size == 0U))
1817 {
1818 return HAL_ERROR;
1819 }
1820
1821 /* Process Locked */
1822 __HAL_LOCK(hi2c);
1823
1824 /* Check if the I2C is already enabled */
1825 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1826 {
1827 /* Enable I2C peripheral */
1828 __HAL_I2C_ENABLE(hi2c);
1829 }
1830
1831 /* Disable Pos */
1832 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1833
1834 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1835 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1836 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1837
1838 /* Prepare transfer parameters */
1839 hi2c->pBuffPtr = pData;
1840 hi2c->XferCount = Size;
1841 hi2c->XferSize = hi2c->XferCount;
1842 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1843
1844 /* Enable Address Acknowledge */
1845 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1846
1847 /* Process Unlocked */
1848 __HAL_UNLOCK(hi2c);
1849
1850 /* Note : The I2C interrupts must be enabled after unlocking current process
1851 to avoid the risk of I2C interrupt handle execution before current
1852 process unlock */
1853
1854 /* Enable EVT, BUF and ERR interrupt */
1855 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1856
1857 return HAL_OK;
1858 }
1859 else
1860 {
1861 return HAL_BUSY;
1862 }
1863 }
1864
1865 /**
1866 * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
1867 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1868 * the configuration information for the specified I2C.
1869 * @param pData Pointer to data buffer
1870 * @param Size Amount of data to be sent
1871 * @retval HAL status
1872 */
HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1873 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1874 {
1875
1876 if (hi2c->State == HAL_I2C_STATE_READY)
1877 {
1878 if ((pData == NULL) || (Size == 0U))
1879 {
1880 return HAL_ERROR;
1881 }
1882
1883 /* Process Locked */
1884 __HAL_LOCK(hi2c);
1885
1886 /* Check if the I2C is already enabled */
1887 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1888 {
1889 /* Enable I2C peripheral */
1890 __HAL_I2C_ENABLE(hi2c);
1891 }
1892
1893 /* Disable Pos */
1894 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1895
1896 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1897 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1898 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1899
1900 /* Prepare transfer parameters */
1901 hi2c->pBuffPtr = pData;
1902 hi2c->XferCount = Size;
1903 hi2c->XferSize = hi2c->XferCount;
1904 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1905
1906 /* Enable Address Acknowledge */
1907 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1908
1909 /* Process Unlocked */
1910 __HAL_UNLOCK(hi2c);
1911
1912 /* Note : The I2C interrupts must be enabled after unlocking current process
1913 to avoid the risk of I2C interrupt handle execution before current
1914 process unlock */
1915
1916 /* Enable EVT, BUF and ERR interrupt */
1917 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1918
1919 return HAL_OK;
1920 }
1921 else
1922 {
1923 return HAL_BUSY;
1924 }
1925 }
1926
1927 /**
1928 * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
1929 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1930 * the configuration information for the specified I2C.
1931 * @param DevAddress Target device address: The device 7 bits address value
1932 * in datasheet must be shifted to the left before calling the interface
1933 * @param pData Pointer to data buffer
1934 * @param Size Amount of data to be sent
1935 * @retval HAL status
1936 */
HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1937 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1938 {
1939 __IO uint32_t count = 0U;
1940 HAL_StatusTypeDef dmaxferstatus;
1941
1942 if (hi2c->State == HAL_I2C_STATE_READY)
1943 {
1944 /* Wait until BUSY flag is reset */
1945 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
1946 do
1947 {
1948 count--;
1949 if (count == 0U)
1950 {
1951 hi2c->PreviousState = I2C_STATE_NONE;
1952 hi2c->State = HAL_I2C_STATE_READY;
1953 hi2c->Mode = HAL_I2C_MODE_NONE;
1954 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
1955
1956 /* Process Unlocked */
1957 __HAL_UNLOCK(hi2c);
1958
1959 return HAL_ERROR;
1960 }
1961 }
1962 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1963
1964 /* Process Locked */
1965 __HAL_LOCK(hi2c);
1966
1967 /* Check if the I2C is already enabled */
1968 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1969 {
1970 /* Enable I2C peripheral */
1971 __HAL_I2C_ENABLE(hi2c);
1972 }
1973
1974 /* Disable Pos */
1975 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1976
1977 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1978 hi2c->Mode = HAL_I2C_MODE_MASTER;
1979 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1980
1981 /* Prepare transfer parameters */
1982 hi2c->pBuffPtr = pData;
1983 hi2c->XferCount = Size;
1984 hi2c->XferSize = hi2c->XferCount;
1985 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1986 hi2c->Devaddress = DevAddress;
1987
1988 if (hi2c->XferSize > 0U)
1989 {
1990 if (hi2c->hdmatx != NULL)
1991 {
1992 /* Set the I2C DMA transfer complete callback */
1993 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
1994
1995 /* Set the DMA error callback */
1996 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
1997
1998 /* Set the unused DMA callbacks to NULL */
1999 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2000 hi2c->hdmatx->XferM1CpltCallback = NULL;
2001 hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
2002 hi2c->hdmatx->XferAbortCallback = NULL;
2003
2004 /* Enable the DMA stream */
2005 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
2006 }
2007 else
2008 {
2009 /* Update I2C state */
2010 hi2c->State = HAL_I2C_STATE_READY;
2011 hi2c->Mode = HAL_I2C_MODE_NONE;
2012
2013 /* Update I2C error code */
2014 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2015
2016 /* Process Unlocked */
2017 __HAL_UNLOCK(hi2c);
2018
2019 return HAL_ERROR;
2020 }
2021
2022 if (dmaxferstatus == HAL_OK)
2023 {
2024 /* Process Unlocked */
2025 __HAL_UNLOCK(hi2c);
2026
2027 /* Note : The I2C interrupts must be enabled after unlocking current process
2028 to avoid the risk of I2C interrupt handle execution before current
2029 process unlock */
2030
2031 /* Enable EVT and ERR interrupt */
2032 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2033
2034 /* Enable DMA Request */
2035 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
2036
2037 /* Enable Acknowledge */
2038 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2039
2040 /* Generate Start */
2041 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2042 }
2043 else
2044 {
2045 /* Update I2C state */
2046 hi2c->State = HAL_I2C_STATE_READY;
2047 hi2c->Mode = HAL_I2C_MODE_NONE;
2048
2049 /* Update I2C error code */
2050 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2051
2052 /* Process Unlocked */
2053 __HAL_UNLOCK(hi2c);
2054
2055 return HAL_ERROR;
2056 }
2057 }
2058 else
2059 {
2060 /* Enable Acknowledge */
2061 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2062
2063 /* Generate Start */
2064 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2065
2066 /* Process Unlocked */
2067 __HAL_UNLOCK(hi2c);
2068
2069 /* Note : The I2C interrupts must be enabled after unlocking current process
2070 to avoid the risk of I2C interrupt handle execution before current
2071 process unlock */
2072
2073 /* Enable EVT, BUF and ERR interrupt */
2074 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2075 }
2076
2077 return HAL_OK;
2078 }
2079 else
2080 {
2081 return HAL_BUSY;
2082 }
2083 }
2084
2085 /**
2086 * @brief Receive in master mode an amount of data in non-blocking mode with DMA
2087 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2088 * the configuration information for the specified I2C.
2089 * @param DevAddress Target device address: The device 7 bits address value
2090 * in datasheet must be shifted to the left before calling the interface
2091 * @param pData Pointer to data buffer
2092 * @param Size Amount of data to be sent
2093 * @retval HAL status
2094 */
HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)2095 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
2096 {
2097 __IO uint32_t count = 0U;
2098 HAL_StatusTypeDef dmaxferstatus;
2099
2100 if (hi2c->State == HAL_I2C_STATE_READY)
2101 {
2102 /* Wait until BUSY flag is reset */
2103 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
2104 do
2105 {
2106 count--;
2107 if (count == 0U)
2108 {
2109 hi2c->PreviousState = I2C_STATE_NONE;
2110 hi2c->State = HAL_I2C_STATE_READY;
2111 hi2c->Mode = HAL_I2C_MODE_NONE;
2112 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
2113
2114 /* Process Unlocked */
2115 __HAL_UNLOCK(hi2c);
2116
2117 return HAL_ERROR;
2118 }
2119 }
2120 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2121
2122 /* Process Locked */
2123 __HAL_LOCK(hi2c);
2124
2125 /* Check if the I2C is already enabled */
2126 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2127 {
2128 /* Enable I2C peripheral */
2129 __HAL_I2C_ENABLE(hi2c);
2130 }
2131
2132 /* Disable Pos */
2133 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2134
2135 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2136 hi2c->Mode = HAL_I2C_MODE_MASTER;
2137 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2138
2139 /* Prepare transfer parameters */
2140 hi2c->pBuffPtr = pData;
2141 hi2c->XferCount = Size;
2142 hi2c->XferSize = hi2c->XferCount;
2143 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2144 hi2c->Devaddress = DevAddress;
2145
2146 if (hi2c->XferSize > 0U)
2147 {
2148 if (hi2c->hdmarx != NULL)
2149 {
2150 /* Set the I2C DMA transfer complete callback */
2151 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
2152
2153 /* Set the DMA error callback */
2154 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2155
2156 /* Set the unused DMA callbacks to NULL */
2157 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2158 hi2c->hdmarx->XferM1CpltCallback = NULL;
2159 hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
2160 hi2c->hdmarx->XferAbortCallback = NULL;
2161
2162 /* Enable the DMA stream */
2163 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
2164 }
2165 else
2166 {
2167 /* Update I2C state */
2168 hi2c->State = HAL_I2C_STATE_READY;
2169 hi2c->Mode = HAL_I2C_MODE_NONE;
2170
2171 /* Update I2C error code */
2172 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2173
2174 /* Process Unlocked */
2175 __HAL_UNLOCK(hi2c);
2176
2177 return HAL_ERROR;
2178 }
2179
2180 if (dmaxferstatus == HAL_OK)
2181 {
2182 /* Enable Acknowledge */
2183 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2184
2185 /* Generate Start */
2186 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2187
2188 /* Process Unlocked */
2189 __HAL_UNLOCK(hi2c);
2190
2191 /* Note : The I2C interrupts must be enabled after unlocking current process
2192 to avoid the risk of I2C interrupt handle execution before current
2193 process unlock */
2194
2195 /* Enable EVT and ERR interrupt */
2196 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2197
2198 /* Enable DMA Request */
2199 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
2200 }
2201 else
2202 {
2203 /* Update I2C state */
2204 hi2c->State = HAL_I2C_STATE_READY;
2205 hi2c->Mode = HAL_I2C_MODE_NONE;
2206
2207 /* Update I2C error code */
2208 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2209
2210 /* Process Unlocked */
2211 __HAL_UNLOCK(hi2c);
2212
2213 return HAL_ERROR;
2214 }
2215 }
2216 else
2217 {
2218 /* Process Unlocked */
2219 __HAL_UNLOCK(hi2c);
2220
2221 /* Note : The I2C interrupts must be enabled after unlocking current process
2222 to avoid the risk of I2C interrupt handle execution before current
2223 process unlock */
2224
2225 /* Enable EVT, BUF and ERR interrupt */
2226 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2227
2228 /* Enable Acknowledge */
2229 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2230
2231 /* Generate Start */
2232 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2233 }
2234
2235 return HAL_OK;
2236 }
2237 else
2238 {
2239 return HAL_BUSY;
2240 }
2241 }
2242
2243 /**
2244 * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
2245 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2246 * the configuration information for the specified I2C.
2247 * @param pData Pointer to data buffer
2248 * @param Size Amount of data to be sent
2249 * @retval HAL status
2250 */
HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2251 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2252 {
2253 HAL_StatusTypeDef dmaxferstatus;
2254
2255 if (hi2c->State == HAL_I2C_STATE_READY)
2256 {
2257 if ((pData == NULL) || (Size == 0U))
2258 {
2259 return HAL_ERROR;
2260 }
2261
2262 /* Process Locked */
2263 __HAL_LOCK(hi2c);
2264
2265 /* Check if the I2C is already enabled */
2266 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2267 {
2268 /* Enable I2C peripheral */
2269 __HAL_I2C_ENABLE(hi2c);
2270 }
2271
2272 /* Disable Pos */
2273 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2274
2275 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2276 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2277 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2278
2279 /* Prepare transfer parameters */
2280 hi2c->pBuffPtr = pData;
2281 hi2c->XferCount = Size;
2282 hi2c->XferSize = hi2c->XferCount;
2283 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2284
2285 if (hi2c->hdmatx != NULL)
2286 {
2287 /* Set the I2C DMA transfer complete callback */
2288 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
2289
2290 /* Set the DMA error callback */
2291 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2292
2293 /* Set the unused DMA callbacks to NULL */
2294 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2295 hi2c->hdmatx->XferM1CpltCallback = NULL;
2296 hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
2297 hi2c->hdmatx->XferAbortCallback = NULL;
2298
2299 /* Enable the DMA stream */
2300 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
2301 }
2302 else
2303 {
2304 /* Update I2C state */
2305 hi2c->State = HAL_I2C_STATE_LISTEN;
2306 hi2c->Mode = HAL_I2C_MODE_NONE;
2307
2308 /* Update I2C error code */
2309 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2310
2311 /* Process Unlocked */
2312 __HAL_UNLOCK(hi2c);
2313
2314 return HAL_ERROR;
2315 }
2316
2317 if (dmaxferstatus == HAL_OK)
2318 {
2319 /* Enable Address Acknowledge */
2320 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2321
2322 /* Process Unlocked */
2323 __HAL_UNLOCK(hi2c);
2324
2325 /* Note : The I2C interrupts must be enabled after unlocking current process
2326 to avoid the risk of I2C interrupt handle execution before current
2327 process unlock */
2328 /* Enable EVT and ERR interrupt */
2329 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2330
2331 /* Enable DMA Request */
2332 hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
2333
2334 return HAL_OK;
2335 }
2336 else
2337 {
2338 /* Update I2C state */
2339 hi2c->State = HAL_I2C_STATE_READY;
2340 hi2c->Mode = HAL_I2C_MODE_NONE;
2341
2342 /* Update I2C error code */
2343 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2344
2345 /* Process Unlocked */
2346 __HAL_UNLOCK(hi2c);
2347
2348 return HAL_ERROR;
2349 }
2350 }
2351 else
2352 {
2353 return HAL_BUSY;
2354 }
2355 }
2356
2357 /**
2358 * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
2359 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2360 * the configuration information for the specified I2C.
2361 * @param pData Pointer to data buffer
2362 * @param Size Amount of data to be sent
2363 * @retval HAL status
2364 */
HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2365 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2366 {
2367 HAL_StatusTypeDef dmaxferstatus;
2368
2369 if (hi2c->State == HAL_I2C_STATE_READY)
2370 {
2371 if ((pData == NULL) || (Size == 0U))
2372 {
2373 return HAL_ERROR;
2374 }
2375
2376 /* Process Locked */
2377 __HAL_LOCK(hi2c);
2378
2379 /* Check if the I2C is already enabled */
2380 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2381 {
2382 /* Enable I2C peripheral */
2383 __HAL_I2C_ENABLE(hi2c);
2384 }
2385
2386 /* Disable Pos */
2387 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2388
2389 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2390 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2391 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2392
2393 /* Prepare transfer parameters */
2394 hi2c->pBuffPtr = pData;
2395 hi2c->XferCount = Size;
2396 hi2c->XferSize = hi2c->XferCount;
2397 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2398
2399 if (hi2c->hdmarx != NULL)
2400 {
2401 /* Set the I2C DMA transfer complete callback */
2402 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
2403
2404 /* Set the DMA error callback */
2405 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2406
2407 /* Set the unused DMA callbacks to NULL */
2408 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2409 hi2c->hdmarx->XferM1CpltCallback = NULL;
2410 hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
2411 hi2c->hdmarx->XferAbortCallback = NULL;
2412
2413 /* Enable the DMA stream */
2414 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
2415 }
2416 else
2417 {
2418 /* Update I2C state */
2419 hi2c->State = HAL_I2C_STATE_LISTEN;
2420 hi2c->Mode = HAL_I2C_MODE_NONE;
2421
2422 /* Update I2C error code */
2423 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2424
2425 /* Process Unlocked */
2426 __HAL_UNLOCK(hi2c);
2427
2428 return HAL_ERROR;
2429 }
2430
2431 if (dmaxferstatus == HAL_OK)
2432 {
2433 /* Enable Address Acknowledge */
2434 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2435
2436 /* Process Unlocked */
2437 __HAL_UNLOCK(hi2c);
2438
2439 /* Note : The I2C interrupts must be enabled after unlocking current process
2440 to avoid the risk of I2C interrupt handle execution before current
2441 process unlock */
2442 /* Enable EVT and ERR interrupt */
2443 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2444
2445 /* Enable DMA Request */
2446 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
2447
2448 return HAL_OK;
2449 }
2450 else
2451 {
2452 /* Update I2C state */
2453 hi2c->State = HAL_I2C_STATE_READY;
2454 hi2c->Mode = HAL_I2C_MODE_NONE;
2455
2456 /* Update I2C error code */
2457 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2458
2459 /* Process Unlocked */
2460 __HAL_UNLOCK(hi2c);
2461
2462 return HAL_ERROR;
2463 }
2464 }
2465 else
2466 {
2467 return HAL_BUSY;
2468 }
2469 }
2470
2471 /**
2472 * @brief Write an amount of data in blocking mode to a specific memory address
2473 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2474 * the configuration information for the specified I2C.
2475 * @param DevAddress Target device address: The device 7 bits address value
2476 * in datasheet must be shifted to the left before calling the interface
2477 * @param MemAddress Internal memory address
2478 * @param MemAddSize Size of internal memory address
2479 * @param pData Pointer to data buffer
2480 * @param Size Amount of data to be sent
2481 * @param Timeout Timeout duration
2482 * @retval HAL status
2483 */
HAL_I2C_Mem_Write(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2484 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2485 {
2486 /* Init tickstart for timeout management*/
2487 uint32_t tickstart = HAL_GetTick();
2488
2489 /* Check the parameters */
2490 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2491
2492 if (hi2c->State == HAL_I2C_STATE_READY)
2493 {
2494 /* Wait until BUSY flag is reset */
2495 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
2496 {
2497 return HAL_BUSY;
2498 }
2499
2500 /* Process Locked */
2501 __HAL_LOCK(hi2c);
2502
2503 /* Check if the I2C is already enabled */
2504 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2505 {
2506 /* Enable I2C peripheral */
2507 __HAL_I2C_ENABLE(hi2c);
2508 }
2509
2510 /* Disable Pos */
2511 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2512
2513 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2514 hi2c->Mode = HAL_I2C_MODE_MEM;
2515 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2516
2517 /* Prepare transfer parameters */
2518 hi2c->pBuffPtr = pData;
2519 hi2c->XferCount = Size;
2520 hi2c->XferSize = hi2c->XferCount;
2521 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2522
2523 /* Send Slave Address and Memory Address */
2524 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2525 {
2526 return HAL_ERROR;
2527 }
2528
2529 while (hi2c->XferSize > 0U)
2530 {
2531 /* Wait until TXE flag is set */
2532 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2533 {
2534 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2535 {
2536 /* Generate Stop */
2537 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2538 }
2539 return HAL_ERROR;
2540 }
2541
2542 /* Write data to DR */
2543 hi2c->Instance->DR = *hi2c->pBuffPtr;
2544
2545 /* Increment Buffer pointer */
2546 hi2c->pBuffPtr++;
2547
2548 /* Update counter */
2549 hi2c->XferSize--;
2550 hi2c->XferCount--;
2551
2552 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
2553 {
2554 /* Write data to DR */
2555 hi2c->Instance->DR = *hi2c->pBuffPtr;
2556
2557 /* Increment Buffer pointer */
2558 hi2c->pBuffPtr++;
2559
2560 /* Update counter */
2561 hi2c->XferSize--;
2562 hi2c->XferCount--;
2563 }
2564 }
2565
2566 /* Wait until BTF flag is set */
2567 if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2568 {
2569 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2570 {
2571 /* Generate Stop */
2572 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2573 }
2574 return HAL_ERROR;
2575 }
2576
2577 /* Generate Stop */
2578 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2579
2580 hi2c->State = HAL_I2C_STATE_READY;
2581 hi2c->Mode = HAL_I2C_MODE_NONE;
2582
2583 /* Process Unlocked */
2584 __HAL_UNLOCK(hi2c);
2585
2586 return HAL_OK;
2587 }
2588 else
2589 {
2590 return HAL_BUSY;
2591 }
2592 }
2593
2594 /**
2595 * @brief Read an amount of data in blocking mode from a specific memory address
2596 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2597 * the configuration information for the specified I2C.
2598 * @param DevAddress Target device address: The device 7 bits address value
2599 * in datasheet must be shifted to the left before calling the interface
2600 * @param MemAddress Internal memory address
2601 * @param MemAddSize Size of internal memory address
2602 * @param pData Pointer to data buffer
2603 * @param Size Amount of data to be sent
2604 * @param Timeout Timeout duration
2605 * @retval HAL status
2606 */
HAL_I2C_Mem_Read(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2607 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2608 {
2609 /* Init tickstart for timeout management*/
2610 uint32_t tickstart = HAL_GetTick();
2611
2612 /* Check the parameters */
2613 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2614
2615 if (hi2c->State == HAL_I2C_STATE_READY)
2616 {
2617 /* Wait until BUSY flag is reset */
2618 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
2619 {
2620 return HAL_BUSY;
2621 }
2622
2623 /* Process Locked */
2624 __HAL_LOCK(hi2c);
2625
2626 /* Check if the I2C is already enabled */
2627 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2628 {
2629 /* Enable I2C peripheral */
2630 __HAL_I2C_ENABLE(hi2c);
2631 }
2632
2633 /* Disable Pos */
2634 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2635
2636 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2637 hi2c->Mode = HAL_I2C_MODE_MEM;
2638 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2639
2640 /* Prepare transfer parameters */
2641 hi2c->pBuffPtr = pData;
2642 hi2c->XferCount = Size;
2643 hi2c->XferSize = hi2c->XferCount;
2644 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2645
2646 /* Send Slave Address and Memory Address */
2647 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2648 {
2649 return HAL_ERROR;
2650 }
2651
2652 if (hi2c->XferSize == 0U)
2653 {
2654 /* Clear ADDR flag */
2655 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2656
2657 /* Generate Stop */
2658 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2659 }
2660 else if (hi2c->XferSize == 1U)
2661 {
2662 /* Disable Acknowledge */
2663 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2664
2665 /* Clear ADDR flag */
2666 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2667
2668 /* Generate Stop */
2669 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2670 }
2671 else if (hi2c->XferSize == 2U)
2672 {
2673 /* Disable Acknowledge */
2674 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2675
2676 /* Enable Pos */
2677 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2678
2679 /* Clear ADDR flag */
2680 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2681 }
2682 else
2683 {
2684 /* Clear ADDR flag */
2685 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2686 }
2687
2688 while (hi2c->XferSize > 0U)
2689 {
2690 if (hi2c->XferSize <= 3U)
2691 {
2692 /* One byte */
2693 if (hi2c->XferSize == 1U)
2694 {
2695 /* Wait until RXNE flag is set */
2696 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2697 {
2698 return HAL_ERROR;
2699 }
2700
2701 /* Read data from DR */
2702 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2703
2704 /* Increment Buffer pointer */
2705 hi2c->pBuffPtr++;
2706
2707 /* Update counter */
2708 hi2c->XferSize--;
2709 hi2c->XferCount--;
2710 }
2711 /* Two bytes */
2712 else if (hi2c->XferSize == 2U)
2713 {
2714 /* Wait until BTF flag is set */
2715 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2716 {
2717 return HAL_ERROR;
2718 }
2719
2720 /* Generate Stop */
2721 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2722
2723 /* Read data from DR */
2724 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2725
2726 /* Increment Buffer pointer */
2727 hi2c->pBuffPtr++;
2728
2729 /* Update counter */
2730 hi2c->XferSize--;
2731 hi2c->XferCount--;
2732
2733 /* Read data from DR */
2734 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2735
2736 /* Increment Buffer pointer */
2737 hi2c->pBuffPtr++;
2738
2739 /* Update counter */
2740 hi2c->XferSize--;
2741 hi2c->XferCount--;
2742 }
2743 /* 3 Last bytes */
2744 else
2745 {
2746 /* Wait until BTF flag is set */
2747 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2748 {
2749 return HAL_ERROR;
2750 }
2751
2752 /* Disable Acknowledge */
2753 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2754
2755 /* Read data from DR */
2756 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2757
2758 /* Increment Buffer pointer */
2759 hi2c->pBuffPtr++;
2760
2761 /* Update counter */
2762 hi2c->XferSize--;
2763 hi2c->XferCount--;
2764
2765 /* Wait until BTF flag is set */
2766 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2767 {
2768 return HAL_ERROR;
2769 }
2770
2771 /* Generate Stop */
2772 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2773
2774 /* Read data from DR */
2775 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2776
2777 /* Increment Buffer pointer */
2778 hi2c->pBuffPtr++;
2779
2780 /* Update counter */
2781 hi2c->XferSize--;
2782 hi2c->XferCount--;
2783
2784 /* Read data from DR */
2785 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2786
2787 /* Increment Buffer pointer */
2788 hi2c->pBuffPtr++;
2789
2790 /* Update counter */
2791 hi2c->XferSize--;
2792 hi2c->XferCount--;
2793 }
2794 }
2795 else
2796 {
2797 /* Wait until RXNE flag is set */
2798 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2799 {
2800 return HAL_ERROR;
2801 }
2802
2803 /* Read data from DR */
2804 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2805
2806 /* Increment Buffer pointer */
2807 hi2c->pBuffPtr++;
2808
2809 /* Update counter */
2810 hi2c->XferSize--;
2811 hi2c->XferCount--;
2812
2813 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
2814 {
2815 /* Read data from DR */
2816 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2817
2818 /* Increment Buffer pointer */
2819 hi2c->pBuffPtr++;
2820
2821 /* Update counter */
2822 hi2c->XferSize--;
2823 hi2c->XferCount--;
2824 }
2825 }
2826 }
2827
2828 hi2c->State = HAL_I2C_STATE_READY;
2829 hi2c->Mode = HAL_I2C_MODE_NONE;
2830
2831 /* Process Unlocked */
2832 __HAL_UNLOCK(hi2c);
2833
2834 return HAL_OK;
2835 }
2836 else
2837 {
2838 return HAL_BUSY;
2839 }
2840 }
2841
2842 /**
2843 * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
2844 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2845 * the configuration information for the specified I2C.
2846 * @param DevAddress Target device address: The device 7 bits address value
2847 * in datasheet must be shifted to the left before calling the interface
2848 * @param MemAddress Internal memory address
2849 * @param MemAddSize Size of internal memory address
2850 * @param pData Pointer to data buffer
2851 * @param Size Amount of data to be sent
2852 * @retval HAL status
2853 */
HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2854 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2855 {
2856 __IO uint32_t count = 0U;
2857
2858 /* Check the parameters */
2859 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2860
2861 if (hi2c->State == HAL_I2C_STATE_READY)
2862 {
2863 /* Wait until BUSY flag is reset */
2864 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
2865 do
2866 {
2867 count--;
2868 if (count == 0U)
2869 {
2870 hi2c->PreviousState = I2C_STATE_NONE;
2871 hi2c->State = HAL_I2C_STATE_READY;
2872 hi2c->Mode = HAL_I2C_MODE_NONE;
2873 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
2874
2875 /* Process Unlocked */
2876 __HAL_UNLOCK(hi2c);
2877
2878 return HAL_ERROR;
2879 }
2880 }
2881 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2882
2883 /* Process Locked */
2884 __HAL_LOCK(hi2c);
2885
2886 /* Check if the I2C is already enabled */
2887 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2888 {
2889 /* Enable I2C peripheral */
2890 __HAL_I2C_ENABLE(hi2c);
2891 }
2892
2893 /* Disable Pos */
2894 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2895
2896 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2897 hi2c->Mode = HAL_I2C_MODE_MEM;
2898 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2899
2900 /* Prepare transfer parameters */
2901 hi2c->pBuffPtr = pData;
2902 hi2c->XferCount = Size;
2903 hi2c->XferSize = hi2c->XferCount;
2904 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2905 hi2c->Devaddress = DevAddress;
2906 hi2c->Memaddress = MemAddress;
2907 hi2c->MemaddSize = MemAddSize;
2908 hi2c->EventCount = 0U;
2909
2910 /* Generate Start */
2911 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2912
2913 /* Process Unlocked */
2914 __HAL_UNLOCK(hi2c);
2915
2916 /* Note : The I2C interrupts must be enabled after unlocking current process
2917 to avoid the risk of I2C interrupt handle execution before current
2918 process unlock */
2919
2920 /* Enable EVT, BUF and ERR interrupt */
2921 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2922
2923 return HAL_OK;
2924 }
2925 else
2926 {
2927 return HAL_BUSY;
2928 }
2929 }
2930
2931 /**
2932 * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
2933 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2934 * the configuration information for the specified I2C.
2935 * @param DevAddress Target device address
2936 * @param MemAddress Internal memory address
2937 * @param MemAddSize Size of internal memory address
2938 * @param pData Pointer to data buffer
2939 * @param Size Amount of data to be sent
2940 * @retval HAL status
2941 */
HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2942 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2943 {
2944 __IO uint32_t count = 0U;
2945
2946 /* Check the parameters */
2947 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2948
2949 if (hi2c->State == HAL_I2C_STATE_READY)
2950 {
2951 /* Wait until BUSY flag is reset */
2952 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
2953 do
2954 {
2955 count--;
2956 if (count == 0U)
2957 {
2958 hi2c->PreviousState = I2C_STATE_NONE;
2959 hi2c->State = HAL_I2C_STATE_READY;
2960 hi2c->Mode = HAL_I2C_MODE_NONE;
2961 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
2962
2963 /* Process Unlocked */
2964 __HAL_UNLOCK(hi2c);
2965
2966 return HAL_ERROR;
2967 }
2968 }
2969 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2970
2971 /* Process Locked */
2972 __HAL_LOCK(hi2c);
2973
2974 /* Check if the I2C is already enabled */
2975 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2976 {
2977 /* Enable I2C peripheral */
2978 __HAL_I2C_ENABLE(hi2c);
2979 }
2980
2981 /* Disable Pos */
2982 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2983
2984 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2985 hi2c->Mode = HAL_I2C_MODE_MEM;
2986 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2987
2988 /* Prepare transfer parameters */
2989 hi2c->pBuffPtr = pData;
2990 hi2c->XferCount = Size;
2991 hi2c->XferSize = hi2c->XferCount;
2992 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2993 hi2c->Devaddress = DevAddress;
2994 hi2c->Memaddress = MemAddress;
2995 hi2c->MemaddSize = MemAddSize;
2996 hi2c->EventCount = 0U;
2997
2998 /* Enable Acknowledge */
2999 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3000
3001 /* Generate Start */
3002 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3003
3004 /* Process Unlocked */
3005 __HAL_UNLOCK(hi2c);
3006
3007 if (hi2c->XferSize > 0U)
3008 {
3009 /* Note : The I2C interrupts must be enabled after unlocking current process
3010 to avoid the risk of I2C interrupt handle execution before current
3011 process unlock */
3012
3013 /* Enable EVT, BUF and ERR interrupt */
3014 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3015 }
3016 return HAL_OK;
3017 }
3018 else
3019 {
3020 return HAL_BUSY;
3021 }
3022 }
3023
3024 /**
3025 * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
3026 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3027 * the configuration information for the specified I2C.
3028 * @param DevAddress Target device address: The device 7 bits address value
3029 * in datasheet must be shifted to the left before calling the interface
3030 * @param MemAddress Internal memory address
3031 * @param MemAddSize Size of internal memory address
3032 * @param pData Pointer to data buffer
3033 * @param Size Amount of data to be sent
3034 * @retval HAL status
3035 */
HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3036 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3037 {
3038 __IO uint32_t count = 0U;
3039 HAL_StatusTypeDef dmaxferstatus;
3040
3041 /* Init tickstart for timeout management*/
3042 uint32_t tickstart = HAL_GetTick();
3043
3044 /* Check the parameters */
3045 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3046
3047 if (hi2c->State == HAL_I2C_STATE_READY)
3048 {
3049 /* Wait until BUSY flag is reset */
3050 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3051 do
3052 {
3053 count--;
3054 if (count == 0U)
3055 {
3056 hi2c->PreviousState = I2C_STATE_NONE;
3057 hi2c->State = HAL_I2C_STATE_READY;
3058 hi2c->Mode = HAL_I2C_MODE_NONE;
3059 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3060
3061 /* Process Unlocked */
3062 __HAL_UNLOCK(hi2c);
3063
3064 return HAL_ERROR;
3065 }
3066 }
3067 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3068
3069 /* Process Locked */
3070 __HAL_LOCK(hi2c);
3071
3072 /* Check if the I2C is already enabled */
3073 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3074 {
3075 /* Enable I2C peripheral */
3076 __HAL_I2C_ENABLE(hi2c);
3077 }
3078
3079 /* Disable Pos */
3080 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3081
3082 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3083 hi2c->Mode = HAL_I2C_MODE_MEM;
3084 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3085
3086 /* Prepare transfer parameters */
3087 hi2c->pBuffPtr = pData;
3088 hi2c->XferCount = Size;
3089 hi2c->XferSize = hi2c->XferCount;
3090 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3091 hi2c->Devaddress = DevAddress;
3092 hi2c->Memaddress = MemAddress;
3093 hi2c->MemaddSize = MemAddSize;
3094 hi2c->EventCount = 0U;
3095
3096 if (hi2c->XferSize > 0U)
3097 {
3098 if (hi2c->hdmatx != NULL)
3099 {
3100 /* Set the I2C DMA transfer complete callback */
3101 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
3102
3103 /* Set the DMA error callback */
3104 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3105
3106 /* Set the unused DMA callbacks to NULL */
3107 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3108 hi2c->hdmatx->XferM1CpltCallback = NULL;
3109 hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
3110 hi2c->hdmatx->XferAbortCallback = NULL;
3111
3112 /* Enable the DMA stream */
3113 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
3114 }
3115 else
3116 {
3117 /* Update I2C state */
3118 hi2c->State = HAL_I2C_STATE_READY;
3119 hi2c->Mode = HAL_I2C_MODE_NONE;
3120
3121 /* Update I2C error code */
3122 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3123
3124 /* Process Unlocked */
3125 __HAL_UNLOCK(hi2c);
3126
3127 return HAL_ERROR;
3128 }
3129
3130 if (dmaxferstatus == HAL_OK)
3131 {
3132 /* Send Slave Address and Memory Address */
3133 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3134 {
3135 /* Abort the ongoing DMA */
3136 dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmatx);
3137
3138 /* Prevent unused argument(s) compilation and MISRA warning */
3139 UNUSED(dmaxferstatus);
3140
3141 /* Set the unused I2C DMA transfer complete callback to NULL */
3142 hi2c->hdmatx->XferCpltCallback = NULL;
3143
3144 /* Disable Acknowledge */
3145 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3146
3147 hi2c->XferSize = 0U;
3148 hi2c->XferCount = 0U;
3149
3150 /* Disable I2C peripheral to prevent dummy data in buffer */
3151 __HAL_I2C_DISABLE(hi2c);
3152
3153 return HAL_ERROR;
3154 }
3155
3156 /* Clear ADDR flag */
3157 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3158
3159 /* Process Unlocked */
3160 __HAL_UNLOCK(hi2c);
3161
3162 /* Note : The I2C interrupts must be enabled after unlocking current process
3163 to avoid the risk of I2C interrupt handle execution before current
3164 process unlock */
3165 /* Enable ERR interrupt */
3166 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
3167
3168 /* Enable DMA Request */
3169 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
3170
3171 return HAL_OK;
3172 }
3173 else
3174 {
3175 /* Update I2C state */
3176 hi2c->State = HAL_I2C_STATE_READY;
3177 hi2c->Mode = HAL_I2C_MODE_NONE;
3178
3179 /* Update I2C error code */
3180 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3181
3182 /* Process Unlocked */
3183 __HAL_UNLOCK(hi2c);
3184
3185 return HAL_ERROR;
3186 }
3187 }
3188 else
3189 {
3190 /* Update I2C state */
3191 hi2c->State = HAL_I2C_STATE_READY;
3192 hi2c->Mode = HAL_I2C_MODE_NONE;
3193
3194 /* Update I2C error code */
3195 hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
3196
3197 /* Process Unlocked */
3198 __HAL_UNLOCK(hi2c);
3199
3200 return HAL_ERROR;
3201 }
3202 }
3203 else
3204 {
3205 return HAL_BUSY;
3206 }
3207 }
3208
3209 /**
3210 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
3211 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3212 * the configuration information for the specified I2C.
3213 * @param DevAddress Target device address: The device 7 bits address value
3214 * in datasheet must be shifted to the left before calling the interface
3215 * @param MemAddress Internal memory address
3216 * @param MemAddSize Size of internal memory address
3217 * @param pData Pointer to data buffer
3218 * @param Size Amount of data to be read
3219 * @retval HAL status
3220 */
HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3221 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3222 {
3223 /* Init tickstart for timeout management*/
3224 uint32_t tickstart = HAL_GetTick();
3225 __IO uint32_t count = 0U;
3226 HAL_StatusTypeDef dmaxferstatus;
3227
3228 /* Check the parameters */
3229 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3230
3231 if (hi2c->State == HAL_I2C_STATE_READY)
3232 {
3233 /* Wait until BUSY flag is reset */
3234 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3235 do
3236 {
3237 count--;
3238 if (count == 0U)
3239 {
3240 hi2c->PreviousState = I2C_STATE_NONE;
3241 hi2c->State = HAL_I2C_STATE_READY;
3242 hi2c->Mode = HAL_I2C_MODE_NONE;
3243 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3244
3245 /* Process Unlocked */
3246 __HAL_UNLOCK(hi2c);
3247
3248 return HAL_ERROR;
3249 }
3250 }
3251 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3252
3253 /* Process Locked */
3254 __HAL_LOCK(hi2c);
3255
3256 /* Check if the I2C is already enabled */
3257 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3258 {
3259 /* Enable I2C peripheral */
3260 __HAL_I2C_ENABLE(hi2c);
3261 }
3262
3263 /* Disable Pos */
3264 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3265
3266 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3267 hi2c->Mode = HAL_I2C_MODE_MEM;
3268 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3269
3270 /* Prepare transfer parameters */
3271 hi2c->pBuffPtr = pData;
3272 hi2c->XferCount = Size;
3273 hi2c->XferSize = hi2c->XferCount;
3274 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3275 hi2c->Devaddress = DevAddress;
3276 hi2c->Memaddress = MemAddress;
3277 hi2c->MemaddSize = MemAddSize;
3278 hi2c->EventCount = 0U;
3279
3280 if (hi2c->XferSize > 0U)
3281 {
3282 if (hi2c->hdmarx != NULL)
3283 {
3284 /* Set the I2C DMA transfer complete callback */
3285 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
3286
3287 /* Set the DMA error callback */
3288 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3289
3290 /* Set the unused DMA callbacks to NULL */
3291 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3292 hi2c->hdmarx->XferM1CpltCallback = NULL;
3293 hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
3294 hi2c->hdmarx->XferAbortCallback = NULL;
3295
3296 /* Enable the DMA stream */
3297 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
3298 }
3299 else
3300 {
3301 /* Update I2C state */
3302 hi2c->State = HAL_I2C_STATE_READY;
3303 hi2c->Mode = HAL_I2C_MODE_NONE;
3304
3305 /* Update I2C error code */
3306 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3307
3308 /* Process Unlocked */
3309 __HAL_UNLOCK(hi2c);
3310
3311 return HAL_ERROR;
3312 }
3313
3314 if (dmaxferstatus == HAL_OK)
3315 {
3316 /* Send Slave Address and Memory Address */
3317 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3318 {
3319 /* Abort the ongoing DMA */
3320 dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmarx);
3321
3322 /* Prevent unused argument(s) compilation and MISRA warning */
3323 UNUSED(dmaxferstatus);
3324
3325 /* Set the unused I2C DMA transfer complete callback to NULL */
3326 hi2c->hdmarx->XferCpltCallback = NULL;
3327
3328 /* Disable Acknowledge */
3329 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3330
3331 hi2c->XferSize = 0U;
3332 hi2c->XferCount = 0U;
3333
3334 /* Disable I2C peripheral to prevent dummy data in buffer */
3335 __HAL_I2C_DISABLE(hi2c);
3336
3337 return HAL_ERROR;
3338 }
3339
3340 if (hi2c->XferSize == 1U)
3341 {
3342 /* Disable Acknowledge */
3343 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3344 }
3345 else
3346 {
3347 /* Enable Last DMA bit */
3348 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
3349 }
3350
3351 /* Clear ADDR flag */
3352 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3353
3354 /* Process Unlocked */
3355 __HAL_UNLOCK(hi2c);
3356
3357 /* Note : The I2C interrupts must be enabled after unlocking current process
3358 to avoid the risk of I2C interrupt handle execution before current
3359 process unlock */
3360 /* Enable ERR interrupt */
3361 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
3362
3363 /* Enable DMA Request */
3364 hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
3365 }
3366 else
3367 {
3368 /* Update I2C state */
3369 hi2c->State = HAL_I2C_STATE_READY;
3370 hi2c->Mode = HAL_I2C_MODE_NONE;
3371
3372 /* Update I2C error code */
3373 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3374
3375 /* Process Unlocked */
3376 __HAL_UNLOCK(hi2c);
3377
3378 return HAL_ERROR;
3379 }
3380 }
3381 else
3382 {
3383 /* Send Slave Address and Memory Address */
3384 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3385 {
3386 return HAL_ERROR;
3387 }
3388
3389 /* Clear ADDR flag */
3390 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3391
3392 /* Generate Stop */
3393 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3394
3395 hi2c->State = HAL_I2C_STATE_READY;
3396
3397 /* Process Unlocked */
3398 __HAL_UNLOCK(hi2c);
3399 }
3400
3401 return HAL_OK;
3402 }
3403 else
3404 {
3405 return HAL_BUSY;
3406 }
3407 }
3408
3409 /**
3410 * @brief Checks if target device is ready for communication.
3411 * @note This function is used with Memory devices
3412 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3413 * the configuration information for the specified I2C.
3414 * @param DevAddress Target device address: The device 7 bits address value
3415 * in datasheet must be shifted to the left before calling the interface
3416 * @param Trials Number of trials
3417 * @param Timeout Timeout duration
3418 * @retval HAL status
3419 */
HAL_I2C_IsDeviceReady(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Trials,uint32_t Timeout)3420 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
3421 {
3422 /* Get tick */
3423 uint32_t tickstart = HAL_GetTick();
3424 uint32_t I2C_Trials = 1U;
3425 FlagStatus tmp1;
3426 FlagStatus tmp2;
3427
3428 if (hi2c->State == HAL_I2C_STATE_READY)
3429 {
3430 /* Wait until BUSY flag is reset */
3431 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3432 {
3433 return HAL_BUSY;
3434 }
3435
3436 /* Process Locked */
3437 __HAL_LOCK(hi2c);
3438
3439 /* Check if the I2C is already enabled */
3440 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3441 {
3442 /* Enable I2C peripheral */
3443 __HAL_I2C_ENABLE(hi2c);
3444 }
3445
3446 /* Disable Pos */
3447 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3448
3449 hi2c->State = HAL_I2C_STATE_BUSY;
3450 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3451 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3452
3453 do
3454 {
3455 /* Generate Start */
3456 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3457
3458 /* Wait until SB flag is set */
3459 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
3460 {
3461 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
3462 {
3463 hi2c->ErrorCode = HAL_I2C_WRONG_START;
3464 }
3465 return HAL_TIMEOUT;
3466 }
3467
3468 /* Send slave address */
3469 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
3470
3471 /* Wait until ADDR or AF flag are set */
3472 /* Get tick */
3473 tickstart = HAL_GetTick();
3474
3475 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
3476 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3477 while ((hi2c->State != HAL_I2C_STATE_TIMEOUT) && (tmp1 == RESET) && (tmp2 == RESET))
3478 {
3479 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3480 {
3481 hi2c->State = HAL_I2C_STATE_TIMEOUT;
3482 }
3483 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
3484 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3485 }
3486
3487 hi2c->State = HAL_I2C_STATE_READY;
3488
3489 /* Check if the ADDR flag has been set */
3490 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
3491 {
3492 /* Generate Stop */
3493 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3494
3495 /* Clear ADDR Flag */
3496 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3497
3498 /* Wait until BUSY flag is reset */
3499 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3500 {
3501 return HAL_ERROR;
3502 }
3503
3504 hi2c->State = HAL_I2C_STATE_READY;
3505
3506 /* Process Unlocked */
3507 __HAL_UNLOCK(hi2c);
3508
3509 return HAL_OK;
3510 }
3511 else
3512 {
3513 /* Generate Stop */
3514 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3515
3516 /* Clear AF Flag */
3517 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3518
3519 /* Wait until BUSY flag is reset */
3520 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3521 {
3522 return HAL_ERROR;
3523 }
3524 }
3525
3526 /* Increment Trials */
3527 I2C_Trials++;
3528 }
3529 while (I2C_Trials < Trials);
3530
3531 hi2c->State = HAL_I2C_STATE_READY;
3532
3533 /* Process Unlocked */
3534 __HAL_UNLOCK(hi2c);
3535
3536 return HAL_ERROR;
3537 }
3538 else
3539 {
3540 return HAL_BUSY;
3541 }
3542 }
3543
3544 /**
3545 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
3546 * @note This interface allow to manage repeated start condition when a direction change during transfer
3547 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3548 * the configuration information for the specified I2C.
3549 * @param DevAddress Target device address: The device 7 bits address value
3550 * in datasheet must be shifted to the left before calling the interface
3551 * @param pData Pointer to data buffer
3552 * @param Size Amount of data to be sent
3553 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3554 * @retval HAL status
3555 */
HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3556 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3557 {
3558 __IO uint32_t Prev_State = 0x00U;
3559 __IO uint32_t count = 0x00U;
3560
3561 /* Check the parameters */
3562 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3563
3564 if (hi2c->State == HAL_I2C_STATE_READY)
3565 {
3566 /* Check Busy Flag only if FIRST call of Master interface */
3567 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3568 {
3569 /* Wait until BUSY flag is reset */
3570 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3571 do
3572 {
3573 count--;
3574 if (count == 0U)
3575 {
3576 hi2c->PreviousState = I2C_STATE_NONE;
3577 hi2c->State = HAL_I2C_STATE_READY;
3578 hi2c->Mode = HAL_I2C_MODE_NONE;
3579 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3580
3581 /* Process Unlocked */
3582 __HAL_UNLOCK(hi2c);
3583
3584 return HAL_ERROR;
3585 }
3586 }
3587 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3588 }
3589
3590 /* Process Locked */
3591 __HAL_LOCK(hi2c);
3592
3593 /* Check if the I2C is already enabled */
3594 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3595 {
3596 /* Enable I2C peripheral */
3597 __HAL_I2C_ENABLE(hi2c);
3598 }
3599
3600 /* Disable Pos */
3601 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3602
3603 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3604 hi2c->Mode = HAL_I2C_MODE_MASTER;
3605 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3606
3607 /* Prepare transfer parameters */
3608 hi2c->pBuffPtr = pData;
3609 hi2c->XferCount = Size;
3610 hi2c->XferSize = hi2c->XferCount;
3611 hi2c->XferOptions = XferOptions;
3612 hi2c->Devaddress = DevAddress;
3613
3614 Prev_State = hi2c->PreviousState;
3615
3616 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3617 /* Mean Previous state is same as current state */
3618 if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3619 {
3620 /* Generate Start */
3621 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3622 }
3623
3624 /* Process Unlocked */
3625 __HAL_UNLOCK(hi2c);
3626
3627 /* Note : The I2C interrupts must be enabled after unlocking current process
3628 to avoid the risk of I2C interrupt handle execution before current
3629 process unlock */
3630
3631 /* Enable EVT, BUF and ERR interrupt */
3632 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3633
3634 return HAL_OK;
3635 }
3636 else
3637 {
3638 return HAL_BUSY;
3639 }
3640 }
3641
3642 /**
3643 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
3644 * @note This interface allow to manage repeated start condition when a direction change during transfer
3645 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3646 * the configuration information for the specified I2C.
3647 * @param DevAddress Target device address: The device 7 bits address value
3648 * in datasheet must be shifted to the left before calling the interface
3649 * @param pData Pointer to data buffer
3650 * @param Size Amount of data to be sent
3651 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3652 * @retval HAL status
3653 */
HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3654 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3655 {
3656 __IO uint32_t Prev_State = 0x00U;
3657 __IO uint32_t count = 0x00U;
3658 HAL_StatusTypeDef dmaxferstatus;
3659
3660 /* Check the parameters */
3661 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3662
3663 if (hi2c->State == HAL_I2C_STATE_READY)
3664 {
3665 /* Check Busy Flag only if FIRST call of Master interface */
3666 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3667 {
3668 /* Wait until BUSY flag is reset */
3669 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3670 do
3671 {
3672 count--;
3673 if (count == 0U)
3674 {
3675 hi2c->PreviousState = I2C_STATE_NONE;
3676 hi2c->State = HAL_I2C_STATE_READY;
3677 hi2c->Mode = HAL_I2C_MODE_NONE;
3678 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3679
3680 /* Process Unlocked */
3681 __HAL_UNLOCK(hi2c);
3682
3683 return HAL_ERROR;
3684 }
3685 }
3686 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3687 }
3688
3689 /* Process Locked */
3690 __HAL_LOCK(hi2c);
3691
3692 /* Check if the I2C is already enabled */
3693 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3694 {
3695 /* Enable I2C peripheral */
3696 __HAL_I2C_ENABLE(hi2c);
3697 }
3698
3699 /* Disable Pos */
3700 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3701
3702 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3703 hi2c->Mode = HAL_I2C_MODE_MASTER;
3704 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3705
3706 /* Prepare transfer parameters */
3707 hi2c->pBuffPtr = pData;
3708 hi2c->XferCount = Size;
3709 hi2c->XferSize = hi2c->XferCount;
3710 hi2c->XferOptions = XferOptions;
3711 hi2c->Devaddress = DevAddress;
3712
3713 Prev_State = hi2c->PreviousState;
3714
3715 if (hi2c->XferSize > 0U)
3716 {
3717 if (hi2c->hdmatx != NULL)
3718 {
3719 /* Set the I2C DMA transfer complete callback */
3720 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
3721
3722 /* Set the DMA error callback */
3723 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3724
3725 /* Set the unused DMA callbacks to NULL */
3726 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3727 hi2c->hdmatx->XferAbortCallback = NULL;
3728
3729 /* Enable the DMA stream */
3730 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
3731 }
3732 else
3733 {
3734 /* Update I2C state */
3735 hi2c->State = HAL_I2C_STATE_READY;
3736 hi2c->Mode = HAL_I2C_MODE_NONE;
3737
3738 /* Update I2C error code */
3739 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3740
3741 /* Process Unlocked */
3742 __HAL_UNLOCK(hi2c);
3743
3744 return HAL_ERROR;
3745 }
3746
3747 if (dmaxferstatus == HAL_OK)
3748 {
3749 /* Enable Acknowledge */
3750 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3751
3752 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3753 /* Mean Previous state is same as current state */
3754 if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3755 {
3756 /* Generate Start */
3757 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3758 }
3759
3760 /* Process Unlocked */
3761 __HAL_UNLOCK(hi2c);
3762
3763 /* Note : The I2C interrupts must be enabled after unlocking current process
3764 to avoid the risk of I2C interrupt handle execution before current
3765 process unlock */
3766
3767 /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */
3768 /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */
3769 if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
3770 {
3771 /* Enable DMA Request */
3772 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
3773 }
3774
3775 /* Enable EVT and ERR interrupt */
3776 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
3777 }
3778 else
3779 {
3780 /* Update I2C state */
3781 hi2c->State = HAL_I2C_STATE_READY;
3782 hi2c->Mode = HAL_I2C_MODE_NONE;
3783
3784 /* Update I2C error code */
3785 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3786
3787 /* Process Unlocked */
3788 __HAL_UNLOCK(hi2c);
3789
3790 return HAL_ERROR;
3791 }
3792 }
3793 else
3794 {
3795 /* Enable Acknowledge */
3796 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3797
3798 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3799 /* Mean Previous state is same as current state */
3800 if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3801 {
3802 /* Generate Start */
3803 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3804 }
3805
3806 /* Process Unlocked */
3807 __HAL_UNLOCK(hi2c);
3808
3809 /* Note : The I2C interrupts must be enabled after unlocking current process
3810 to avoid the risk of I2C interrupt handle execution before current
3811 process unlock */
3812
3813 /* Enable EVT, BUF and ERR interrupt */
3814 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3815 }
3816
3817 return HAL_OK;
3818 }
3819 else
3820 {
3821 return HAL_BUSY;
3822 }
3823 }
3824
3825 /**
3826 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
3827 * @note This interface allow to manage repeated start condition when a direction change during transfer
3828 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3829 * the configuration information for the specified I2C.
3830 * @param DevAddress Target device address: The device 7 bits address value
3831 * in datasheet must be shifted to the left before calling the interface
3832 * @param pData Pointer to data buffer
3833 * @param Size Amount of data to be sent
3834 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3835 * @retval HAL status
3836 */
HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3837 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3838 {
3839 __IO uint32_t Prev_State = 0x00U;
3840 __IO uint32_t count = 0U;
3841 uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3842
3843 /* Check the parameters */
3844 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3845
3846 if (hi2c->State == HAL_I2C_STATE_READY)
3847 {
3848 /* Check Busy Flag only if FIRST call of Master interface */
3849 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3850 {
3851 /* Wait until BUSY flag is reset */
3852 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3853 do
3854 {
3855 count--;
3856 if (count == 0U)
3857 {
3858 hi2c->PreviousState = I2C_STATE_NONE;
3859 hi2c->State = HAL_I2C_STATE_READY;
3860 hi2c->Mode = HAL_I2C_MODE_NONE;
3861 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3862
3863 /* Process Unlocked */
3864 __HAL_UNLOCK(hi2c);
3865
3866 return HAL_ERROR;
3867 }
3868 }
3869 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3870 }
3871
3872 /* Process Locked */
3873 __HAL_LOCK(hi2c);
3874
3875 /* Check if the I2C is already enabled */
3876 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3877 {
3878 /* Enable I2C peripheral */
3879 __HAL_I2C_ENABLE(hi2c);
3880 }
3881
3882 /* Disable Pos */
3883 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3884
3885 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3886 hi2c->Mode = HAL_I2C_MODE_MASTER;
3887 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3888
3889 /* Prepare transfer parameters */
3890 hi2c->pBuffPtr = pData;
3891 hi2c->XferCount = Size;
3892 hi2c->XferSize = hi2c->XferCount;
3893 hi2c->XferOptions = XferOptions;
3894 hi2c->Devaddress = DevAddress;
3895
3896 Prev_State = hi2c->PreviousState;
3897
3898 if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
3899 {
3900 if (Prev_State == I2C_STATE_MASTER_BUSY_RX)
3901 {
3902 /* Disable Acknowledge */
3903 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3904
3905 /* Enable Pos */
3906 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3907
3908 /* Remove Enabling of IT_BUF, mean RXNE treatment, treat the 2 bytes through BTF */
3909 enableIT &= ~I2C_IT_BUF;
3910 }
3911 else
3912 {
3913 /* Enable Acknowledge */
3914 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3915 }
3916 }
3917 else
3918 {
3919 /* Enable Acknowledge */
3920 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3921 }
3922
3923 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3924 /* Mean Previous state is same as current state */
3925 if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3926 {
3927 /* Generate Start */
3928 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3929 }
3930
3931 /* Process Unlocked */
3932 __HAL_UNLOCK(hi2c);
3933
3934 /* Note : The I2C interrupts must be enabled after unlocking current process
3935 to avoid the risk of I2C interrupt handle execution before current
3936 process unlock */
3937
3938 /* Enable interrupts */
3939 __HAL_I2C_ENABLE_IT(hi2c, enableIT);
3940
3941 return HAL_OK;
3942 }
3943 else
3944 {
3945 return HAL_BUSY;
3946 }
3947 }
3948
3949 /**
3950 * @brief Sequential receive in master mode an amount of data in non-blocking mode with DMA
3951 * @note This interface allow to manage repeated start condition when a direction change during transfer
3952 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3953 * the configuration information for the specified I2C.
3954 * @param DevAddress Target device address: The device 7 bits address value
3955 * in datasheet must be shifted to the left before calling the interface
3956 * @param pData Pointer to data buffer
3957 * @param Size Amount of data to be sent
3958 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3959 * @retval HAL status
3960 */
HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3961 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3962 {
3963 __IO uint32_t Prev_State = 0x00U;
3964 __IO uint32_t count = 0U;
3965 uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3966 HAL_StatusTypeDef dmaxferstatus;
3967
3968 /* Check the parameters */
3969 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3970
3971 if (hi2c->State == HAL_I2C_STATE_READY)
3972 {
3973 /* Check Busy Flag only if FIRST call of Master interface */
3974 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3975 {
3976 /* Wait until BUSY flag is reset */
3977 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3978 do
3979 {
3980 count--;
3981 if (count == 0U)
3982 {
3983 hi2c->PreviousState = I2C_STATE_NONE;
3984 hi2c->State = HAL_I2C_STATE_READY;
3985 hi2c->Mode = HAL_I2C_MODE_NONE;
3986 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3987
3988 /* Process Unlocked */
3989 __HAL_UNLOCK(hi2c);
3990
3991 return HAL_ERROR;
3992 }
3993 }
3994 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3995 }
3996
3997 /* Process Locked */
3998 __HAL_LOCK(hi2c);
3999
4000 /* Check if the I2C is already enabled */
4001 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4002 {
4003 /* Enable I2C peripheral */
4004 __HAL_I2C_ENABLE(hi2c);
4005 }
4006
4007 /* Disable Pos */
4008 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4009
4010 /* Clear Last DMA bit */
4011 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
4012
4013 hi2c->State = HAL_I2C_STATE_BUSY_RX;
4014 hi2c->Mode = HAL_I2C_MODE_MASTER;
4015 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4016
4017 /* Prepare transfer parameters */
4018 hi2c->pBuffPtr = pData;
4019 hi2c->XferCount = Size;
4020 hi2c->XferSize = hi2c->XferCount;
4021 hi2c->XferOptions = XferOptions;
4022 hi2c->Devaddress = DevAddress;
4023
4024 Prev_State = hi2c->PreviousState;
4025
4026 if (hi2c->XferSize > 0U)
4027 {
4028 if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
4029 {
4030 if (Prev_State == I2C_STATE_MASTER_BUSY_RX)
4031 {
4032 /* Disable Acknowledge */
4033 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4034
4035 /* Enable Pos */
4036 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4037
4038 /* Enable Last DMA bit */
4039 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
4040 }
4041 else
4042 {
4043 /* Enable Acknowledge */
4044 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4045 }
4046 }
4047 else
4048 {
4049 /* Enable Acknowledge */
4050 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4051
4052 if ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
4053 {
4054 /* Enable Last DMA bit */
4055 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
4056 }
4057 }
4058 if (hi2c->hdmarx != NULL)
4059 {
4060 /* Set the I2C DMA transfer complete callback */
4061 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
4062
4063 /* Set the DMA error callback */
4064 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4065
4066 /* Set the unused DMA callbacks to NULL */
4067 hi2c->hdmarx->XferHalfCpltCallback = NULL;
4068 hi2c->hdmarx->XferAbortCallback = NULL;
4069
4070 /* Enable the DMA stream */
4071 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
4072 }
4073 else
4074 {
4075 /* Update I2C state */
4076 hi2c->State = HAL_I2C_STATE_READY;
4077 hi2c->Mode = HAL_I2C_MODE_NONE;
4078
4079 /* Update I2C error code */
4080 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4081
4082 /* Process Unlocked */
4083 __HAL_UNLOCK(hi2c);
4084
4085 return HAL_ERROR;
4086 }
4087 if (dmaxferstatus == HAL_OK)
4088 {
4089 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
4090 /* Mean Previous state is same as current state */
4091 if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
4092 {
4093 /* Generate Start */
4094 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
4095
4096 /* Update interrupt for only EVT and ERR */
4097 enableIT = (I2C_IT_EVT | I2C_IT_ERR);
4098 }
4099 else
4100 {
4101 /* Update interrupt for only ERR */
4102 enableIT = I2C_IT_ERR;
4103 }
4104
4105 /* Process Unlocked */
4106 __HAL_UNLOCK(hi2c);
4107
4108 /* Note : The I2C interrupts must be enabled after unlocking current process
4109 to avoid the risk of I2C interrupt handle execution before current
4110 process unlock */
4111
4112 /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */
4113 /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */
4114 if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
4115 {
4116 /* Enable DMA Request */
4117 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4118 }
4119
4120 /* Enable EVT and ERR interrupt */
4121 __HAL_I2C_ENABLE_IT(hi2c, enableIT);
4122 }
4123 else
4124 {
4125 /* Update I2C state */
4126 hi2c->State = HAL_I2C_STATE_READY;
4127 hi2c->Mode = HAL_I2C_MODE_NONE;
4128
4129 /* Update I2C error code */
4130 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4131
4132 /* Process Unlocked */
4133 __HAL_UNLOCK(hi2c);
4134
4135 return HAL_ERROR;
4136 }
4137 }
4138 else
4139 {
4140 /* Enable Acknowledge */
4141 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4142
4143 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
4144 /* Mean Previous state is same as current state */
4145 if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
4146 {
4147 /* Generate Start */
4148 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
4149 }
4150
4151 /* Process Unlocked */
4152 __HAL_UNLOCK(hi2c);
4153
4154 /* Note : The I2C interrupts must be enabled after unlocking current process
4155 to avoid the risk of I2C interrupt handle execution before current
4156 process unlock */
4157
4158 /* Enable interrupts */
4159 __HAL_I2C_ENABLE_IT(hi2c, enableIT);
4160 }
4161 return HAL_OK;
4162 }
4163 else
4164 {
4165 return HAL_BUSY;
4166 }
4167 }
4168
4169 /**
4170 * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with Interrupt
4171 * @note This interface allow to manage repeated start condition when a direction change during transfer
4172 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4173 * the configuration information for the specified I2C.
4174 * @param pData Pointer to data buffer
4175 * @param Size Amount of data to be sent
4176 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4177 * @retval HAL status
4178 */
HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4179 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4180 {
4181 /* Check the parameters */
4182 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4183
4184 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4185 {
4186 if ((pData == NULL) || (Size == 0U))
4187 {
4188 return HAL_ERROR;
4189 }
4190
4191 /* Process Locked */
4192 __HAL_LOCK(hi2c);
4193
4194 /* Check if the I2C is already enabled */
4195 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4196 {
4197 /* Enable I2C peripheral */
4198 __HAL_I2C_ENABLE(hi2c);
4199 }
4200
4201 /* Disable Pos */
4202 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4203
4204 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4205 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4206 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4207
4208 /* Prepare transfer parameters */
4209 hi2c->pBuffPtr = pData;
4210 hi2c->XferCount = Size;
4211 hi2c->XferSize = hi2c->XferCount;
4212 hi2c->XferOptions = XferOptions;
4213
4214 /* Clear ADDR flag */
4215 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4216
4217 /* Process Unlocked */
4218 __HAL_UNLOCK(hi2c);
4219
4220 /* Note : The I2C interrupts must be enabled after unlocking current process
4221 to avoid the risk of I2C interrupt handle execution before current
4222 process unlock */
4223
4224 /* Enable EVT, BUF and ERR interrupt */
4225 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4226
4227 return HAL_OK;
4228 }
4229 else
4230 {
4231 return HAL_BUSY;
4232 }
4233 }
4234
4235 /**
4236 * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with DMA
4237 * @note This interface allow to manage repeated start condition when a direction change during transfer
4238 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4239 * the configuration information for the specified I2C.
4240 * @param pData Pointer to data buffer
4241 * @param Size Amount of data to be sent
4242 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4243 * @retval HAL status
4244 */
HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4245 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4246 {
4247 HAL_StatusTypeDef dmaxferstatus;
4248
4249 /* Check the parameters */
4250 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4251
4252 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4253 {
4254 if ((pData == NULL) || (Size == 0U))
4255 {
4256 return HAL_ERROR;
4257 }
4258
4259 /* Process Locked */
4260 __HAL_LOCK(hi2c);
4261
4262 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4263 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4264
4265 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4266 /* and then toggle the HAL slave RX state to TX state */
4267 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4268 {
4269 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4270 {
4271 /* Abort DMA Xfer if any */
4272 if (hi2c->hdmarx != NULL)
4273 {
4274 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4275
4276 /* Set the I2C DMA Abort callback :
4277 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4278 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4279
4280 /* Abort DMA RX */
4281 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4282 {
4283 /* Call Directly XferAbortCallback function in case of error */
4284 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4285 }
4286 }
4287 }
4288 }
4289 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4290 {
4291 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4292 {
4293 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4294
4295 /* Abort DMA Xfer if any */
4296 if (hi2c->hdmatx != NULL)
4297 {
4298 /* Set the I2C DMA Abort callback :
4299 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4300 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4301
4302 /* Abort DMA TX */
4303 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4304 {
4305 /* Call Directly XferAbortCallback function in case of error */
4306 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4307 }
4308 }
4309 }
4310 }
4311 else
4312 {
4313 /* Nothing to do */
4314 }
4315
4316 /* Check if the I2C is already enabled */
4317 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4318 {
4319 /* Enable I2C peripheral */
4320 __HAL_I2C_ENABLE(hi2c);
4321 }
4322
4323 /* Disable Pos */
4324 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4325
4326 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4327 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4328 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4329
4330 /* Prepare transfer parameters */
4331 hi2c->pBuffPtr = pData;
4332 hi2c->XferCount = Size;
4333 hi2c->XferSize = hi2c->XferCount;
4334 hi2c->XferOptions = XferOptions;
4335
4336 if (hi2c->hdmatx != NULL)
4337 {
4338 /* Set the I2C DMA transfer complete callback */
4339 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
4340
4341 /* Set the DMA error callback */
4342 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
4343
4344 /* Set the unused DMA callbacks to NULL */
4345 hi2c->hdmatx->XferHalfCpltCallback = NULL;
4346 hi2c->hdmatx->XferAbortCallback = NULL;
4347
4348 /* Enable the DMA stream */
4349 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
4350 }
4351 else
4352 {
4353 /* Update I2C state */
4354 hi2c->State = HAL_I2C_STATE_LISTEN;
4355 hi2c->Mode = HAL_I2C_MODE_NONE;
4356
4357 /* Update I2C error code */
4358 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4359
4360 /* Process Unlocked */
4361 __HAL_UNLOCK(hi2c);
4362
4363 return HAL_ERROR;
4364 }
4365
4366 if (dmaxferstatus == HAL_OK)
4367 {
4368 /* Enable Address Acknowledge */
4369 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4370
4371 /* Clear ADDR flag */
4372 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4373
4374 /* Process Unlocked */
4375 __HAL_UNLOCK(hi2c);
4376
4377 /* Note : The I2C interrupts must be enabled after unlocking current process
4378 to avoid the risk of I2C interrupt handle execution before current
4379 process unlock */
4380 /* Enable EVT and ERR interrupt */
4381 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4382
4383 /* Enable DMA Request */
4384 hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
4385
4386 return HAL_OK;
4387 }
4388 else
4389 {
4390 /* Update I2C state */
4391 hi2c->State = HAL_I2C_STATE_READY;
4392 hi2c->Mode = HAL_I2C_MODE_NONE;
4393
4394 /* Update I2C error code */
4395 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4396
4397 /* Process Unlocked */
4398 __HAL_UNLOCK(hi2c);
4399
4400 return HAL_ERROR;
4401 }
4402 }
4403 else
4404 {
4405 return HAL_BUSY;
4406 }
4407 }
4408
4409 /**
4410 * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt
4411 * @note This interface allow to manage repeated start condition when a direction change during transfer
4412 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4413 * the configuration information for the specified I2C.
4414 * @param pData Pointer to data buffer
4415 * @param Size Amount of data to be sent
4416 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4417 * @retval HAL status
4418 */
HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4419 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4420 {
4421 /* Check the parameters */
4422 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4423
4424 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4425 {
4426 if ((pData == NULL) || (Size == 0U))
4427 {
4428 return HAL_ERROR;
4429 }
4430
4431 /* Process Locked */
4432 __HAL_LOCK(hi2c);
4433
4434 /* Check if the I2C is already enabled */
4435 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4436 {
4437 /* Enable I2C peripheral */
4438 __HAL_I2C_ENABLE(hi2c);
4439 }
4440
4441 /* Disable Pos */
4442 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4443
4444 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4445 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4446 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4447
4448 /* Prepare transfer parameters */
4449 hi2c->pBuffPtr = pData;
4450 hi2c->XferCount = Size;
4451 hi2c->XferSize = hi2c->XferCount;
4452 hi2c->XferOptions = XferOptions;
4453
4454 /* Clear ADDR flag */
4455 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4456
4457 /* Process Unlocked */
4458 __HAL_UNLOCK(hi2c);
4459
4460 /* Note : The I2C interrupts must be enabled after unlocking current process
4461 to avoid the risk of I2C interrupt handle execution before current
4462 process unlock */
4463
4464 /* Enable EVT, BUF and ERR interrupt */
4465 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4466
4467 return HAL_OK;
4468 }
4469 else
4470 {
4471 return HAL_BUSY;
4472 }
4473 }
4474
4475 /**
4476 * @brief Sequential receive in slave mode an amount of data in non-blocking mode with DMA
4477 * @note This interface allow to manage repeated start condition when a direction change during transfer
4478 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4479 * the configuration information for the specified I2C.
4480 * @param pData Pointer to data buffer
4481 * @param Size Amount of data to be sent
4482 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4483 * @retval HAL status
4484 */
HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4485 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4486 {
4487 HAL_StatusTypeDef dmaxferstatus;
4488
4489 /* Check the parameters */
4490 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4491
4492 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4493 {
4494 if ((pData == NULL) || (Size == 0U))
4495 {
4496 return HAL_ERROR;
4497 }
4498
4499 /* Process Locked */
4500 __HAL_LOCK(hi2c);
4501
4502 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4503 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4504
4505 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4506 /* and then toggle the HAL slave RX state to TX state */
4507 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4508 {
4509 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4510 {
4511 /* Abort DMA Xfer if any */
4512 if (hi2c->hdmarx != NULL)
4513 {
4514 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4515
4516 /* Set the I2C DMA Abort callback :
4517 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4518 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4519
4520 /* Abort DMA RX */
4521 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4522 {
4523 /* Call Directly XferAbortCallback function in case of error */
4524 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4525 }
4526 }
4527 }
4528 }
4529 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4530 {
4531 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4532 {
4533 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4534
4535 /* Abort DMA Xfer if any */
4536 if (hi2c->hdmatx != NULL)
4537 {
4538 /* Set the I2C DMA Abort callback :
4539 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4540 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4541
4542 /* Abort DMA TX */
4543 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4544 {
4545 /* Call Directly XferAbortCallback function in case of error */
4546 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4547 }
4548 }
4549 }
4550 }
4551 else
4552 {
4553 /* Nothing to do */
4554 }
4555
4556 /* Check if the I2C is already enabled */
4557 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4558 {
4559 /* Enable I2C peripheral */
4560 __HAL_I2C_ENABLE(hi2c);
4561 }
4562
4563 /* Disable Pos */
4564 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4565
4566 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4567 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4568 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4569
4570 /* Prepare transfer parameters */
4571 hi2c->pBuffPtr = pData;
4572 hi2c->XferCount = Size;
4573 hi2c->XferSize = hi2c->XferCount;
4574 hi2c->XferOptions = XferOptions;
4575
4576 if (hi2c->hdmarx != NULL)
4577 {
4578 /* Set the I2C DMA transfer complete callback */
4579 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
4580
4581 /* Set the DMA error callback */
4582 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4583
4584 /* Set the unused DMA callbacks to NULL */
4585 hi2c->hdmarx->XferHalfCpltCallback = NULL;
4586 hi2c->hdmarx->XferAbortCallback = NULL;
4587
4588 /* Enable the DMA stream */
4589 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
4590 }
4591 else
4592 {
4593 /* Update I2C state */
4594 hi2c->State = HAL_I2C_STATE_LISTEN;
4595 hi2c->Mode = HAL_I2C_MODE_NONE;
4596
4597 /* Update I2C error code */
4598 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4599
4600 /* Process Unlocked */
4601 __HAL_UNLOCK(hi2c);
4602
4603 return HAL_ERROR;
4604 }
4605
4606 if (dmaxferstatus == HAL_OK)
4607 {
4608 /* Enable Address Acknowledge */
4609 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4610
4611 /* Clear ADDR flag */
4612 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4613
4614 /* Process Unlocked */
4615 __HAL_UNLOCK(hi2c);
4616
4617 /* Enable DMA Request */
4618 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4619
4620 /* Note : The I2C interrupts must be enabled after unlocking current process
4621 to avoid the risk of I2C interrupt handle execution before current
4622 process unlock */
4623 /* Enable EVT and ERR interrupt */
4624 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4625
4626 return HAL_OK;
4627 }
4628 else
4629 {
4630 /* Update I2C state */
4631 hi2c->State = HAL_I2C_STATE_READY;
4632 hi2c->Mode = HAL_I2C_MODE_NONE;
4633
4634 /* Update I2C error code */
4635 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4636
4637 /* Process Unlocked */
4638 __HAL_UNLOCK(hi2c);
4639
4640 return HAL_ERROR;
4641 }
4642 }
4643 else
4644 {
4645 return HAL_BUSY;
4646 }
4647 }
4648
4649 /**
4650 * @brief Enable the Address listen mode with Interrupt.
4651 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4652 * the configuration information for the specified I2C.
4653 * @retval HAL status
4654 */
HAL_I2C_EnableListen_IT(I2C_HandleTypeDef * hi2c)4655 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
4656 {
4657 if (hi2c->State == HAL_I2C_STATE_READY)
4658 {
4659 hi2c->State = HAL_I2C_STATE_LISTEN;
4660
4661 /* Check if the I2C is already enabled */
4662 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4663 {
4664 /* Enable I2C peripheral */
4665 __HAL_I2C_ENABLE(hi2c);
4666 }
4667
4668 /* Enable Address Acknowledge */
4669 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4670
4671 /* Enable EVT and ERR interrupt */
4672 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4673
4674 return HAL_OK;
4675 }
4676 else
4677 {
4678 return HAL_BUSY;
4679 }
4680 }
4681
4682 /**
4683 * @brief Disable the Address listen mode with Interrupt.
4684 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4685 * the configuration information for the specified I2C.
4686 * @retval HAL status
4687 */
HAL_I2C_DisableListen_IT(I2C_HandleTypeDef * hi2c)4688 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
4689 {
4690 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4691 uint32_t tmp;
4692
4693 /* Disable Address listen mode only if a transfer is not ongoing */
4694 if (hi2c->State == HAL_I2C_STATE_LISTEN)
4695 {
4696 tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
4697 hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
4698 hi2c->State = HAL_I2C_STATE_READY;
4699 hi2c->Mode = HAL_I2C_MODE_NONE;
4700
4701 /* Disable Address Acknowledge */
4702 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4703
4704 /* Disable EVT and ERR interrupt */
4705 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4706
4707 return HAL_OK;
4708 }
4709 else
4710 {
4711 return HAL_BUSY;
4712 }
4713 }
4714
4715 /**
4716 * @brief Abort a master I2C IT or DMA process communication with Interrupt.
4717 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4718 * the configuration information for the specified I2C.
4719 * @param DevAddress Target device address: The device 7 bits address value
4720 * in datasheet must be shifted to the left before calling the interface
4721 * @retval HAL status
4722 */
HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress)4723 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
4724 {
4725 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
4726 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
4727
4728 /* Prevent unused argument(s) compilation warning */
4729 UNUSED(DevAddress);
4730
4731 /* Abort Master transfer during Receive or Transmit process */
4732 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && (CurrentMode == HAL_I2C_MODE_MASTER))
4733 {
4734 /* Process Locked */
4735 __HAL_LOCK(hi2c);
4736
4737 hi2c->PreviousState = I2C_STATE_NONE;
4738 hi2c->State = HAL_I2C_STATE_ABORT;
4739
4740 /* Disable Acknowledge */
4741 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4742
4743 /* Generate Stop */
4744 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
4745
4746 hi2c->XferCount = 0U;
4747
4748 /* Disable EVT, BUF and ERR interrupt */
4749 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4750
4751 /* Process Unlocked */
4752 __HAL_UNLOCK(hi2c);
4753
4754 /* Call the corresponding callback to inform upper layer of End of Transfer */
4755 I2C_ITError(hi2c);
4756
4757 return HAL_OK;
4758 }
4759 else
4760 {
4761 /* Wrong usage of abort function */
4762 /* This function should be used only in case of abort monitored by master device */
4763 /* Or periphal is not in busy state, mean there is no active sequence to be abort */
4764 return HAL_ERROR;
4765 }
4766 }
4767
4768 /**
4769 * @}
4770 */
4771
4772 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
4773 * @{
4774 */
4775
4776 /**
4777 * @brief This function handles I2C event interrupt request.
4778 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4779 * the configuration information for the specified I2C.
4780 * @retval None
4781 */
HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef * hi2c)4782 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
4783 {
4784 uint32_t sr1itflags;
4785 uint32_t sr2itflags = 0U;
4786 uint32_t itsources = READ_REG(hi2c->Instance->CR2);
4787 uint32_t CurrentXferOptions = hi2c->XferOptions;
4788 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
4789 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
4790
4791 /* Master or Memory mode selected */
4792 if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
4793 {
4794 sr2itflags = READ_REG(hi2c->Instance->SR2);
4795 sr1itflags = READ_REG(hi2c->Instance->SR1);
4796
4797 /* Exit IRQ event until Start Bit detected in case of Other frame requested */
4798 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) == RESET) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(CurrentXferOptions) == 1U))
4799 {
4800 return;
4801 }
4802
4803 /* SB Set ----------------------------------------------------------------*/
4804 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4805 {
4806 /* Convert OTHER_xxx XferOptions if any */
4807 I2C_ConvertOtherXferOptions(hi2c);
4808
4809 I2C_Master_SB(hi2c);
4810 }
4811 /* ADD10 Set -------------------------------------------------------------*/
4812 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADD10) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4813 {
4814 I2C_Master_ADD10(hi2c);
4815 }
4816 /* ADDR Set --------------------------------------------------------------*/
4817 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4818 {
4819 I2C_Master_ADDR(hi2c);
4820 }
4821 /* I2C in mode Transmitter -----------------------------------------------*/
4822 else if (I2C_CHECK_FLAG(sr2itflags, I2C_FLAG_TRA) != RESET)
4823 {
4824 /* Do not check buffer and BTF flag if a Xfer DMA is on going */
4825 if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN)
4826 {
4827 /* TXE set and BTF reset -----------------------------------------------*/
4828 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4829 {
4830 I2C_MasterTransmit_TXE(hi2c);
4831 }
4832 /* BTF set -------------------------------------------------------------*/
4833 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4834 {
4835 if (CurrentState == HAL_I2C_STATE_BUSY_TX)
4836 {
4837 I2C_MasterTransmit_BTF(hi2c);
4838 }
4839 else /* HAL_I2C_MODE_MEM */
4840 {
4841 if (CurrentMode == HAL_I2C_MODE_MEM)
4842 {
4843 I2C_MemoryTransmit_TXE_BTF(hi2c);
4844 }
4845 }
4846 }
4847 else
4848 {
4849 /* Do nothing */
4850 }
4851 }
4852 }
4853 /* I2C in mode Receiver --------------------------------------------------*/
4854 else
4855 {
4856 /* Do not check buffer and BTF flag if a Xfer DMA is on going */
4857 if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN)
4858 {
4859 /* RXNE set and BTF reset -----------------------------------------------*/
4860 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4861 {
4862 I2C_MasterReceive_RXNE(hi2c);
4863 }
4864 /* BTF set -------------------------------------------------------------*/
4865 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4866 {
4867 I2C_MasterReceive_BTF(hi2c);
4868 }
4869 else
4870 {
4871 /* Do nothing */
4872 }
4873 }
4874 }
4875 }
4876 /* Slave mode selected */
4877 else
4878 {
4879 /* If an error is detected, read only SR1 register to prevent */
4880 /* a clear of ADDR flags by reading SR2 after reading SR1 in Error treatment */
4881 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
4882 {
4883 sr1itflags = READ_REG(hi2c->Instance->SR1);
4884 }
4885 else
4886 {
4887 sr2itflags = READ_REG(hi2c->Instance->SR2);
4888 sr1itflags = READ_REG(hi2c->Instance->SR1);
4889 }
4890
4891 /* ADDR set --------------------------------------------------------------*/
4892 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4893 {
4894 /* Now time to read SR2, this will clear ADDR flag automatically */
4895 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
4896 {
4897 sr2itflags = READ_REG(hi2c->Instance->SR2);
4898 }
4899 I2C_Slave_ADDR(hi2c, sr2itflags);
4900 }
4901 /* STOPF set --------------------------------------------------------------*/
4902 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4903 {
4904 I2C_Slave_STOPF(hi2c);
4905 }
4906 /* I2C in mode Transmitter -----------------------------------------------*/
4907 else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
4908 {
4909 /* TXE set and BTF reset -----------------------------------------------*/
4910 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4911 {
4912 I2C_SlaveTransmit_TXE(hi2c);
4913 }
4914 /* BTF set -------------------------------------------------------------*/
4915 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4916 {
4917 I2C_SlaveTransmit_BTF(hi2c);
4918 }
4919 else
4920 {
4921 /* Do nothing */
4922 }
4923 }
4924 /* I2C in mode Receiver --------------------------------------------------*/
4925 else
4926 {
4927 /* RXNE set and BTF reset ----------------------------------------------*/
4928 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4929 {
4930 I2C_SlaveReceive_RXNE(hi2c);
4931 }
4932 /* BTF set -------------------------------------------------------------*/
4933 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4934 {
4935 I2C_SlaveReceive_BTF(hi2c);
4936 }
4937 else
4938 {
4939 /* Do nothing */
4940 }
4941 }
4942 }
4943 }
4944
4945 /**
4946 * @brief This function handles I2C error interrupt request.
4947 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4948 * the configuration information for the specified I2C.
4949 * @retval None
4950 */
HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef * hi2c)4951 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
4952 {
4953 HAL_I2C_ModeTypeDef tmp1;
4954 uint32_t tmp2;
4955 HAL_I2C_StateTypeDef tmp3;
4956 uint32_t tmp4;
4957 uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
4958 uint32_t itsources = READ_REG(hi2c->Instance->CR2);
4959 uint32_t error = HAL_I2C_ERROR_NONE;
4960 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
4961
4962 /* I2C Bus error interrupt occurred ----------------------------------------*/
4963 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
4964 {
4965 error |= HAL_I2C_ERROR_BERR;
4966
4967 /* Clear BERR flag */
4968 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
4969 }
4970
4971 /* I2C Arbitration Lost error interrupt occurred ---------------------------*/
4972 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
4973 {
4974 error |= HAL_I2C_ERROR_ARLO;
4975
4976 /* Clear ARLO flag */
4977 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
4978 }
4979
4980 /* I2C Acknowledge failure error interrupt occurred ------------------------*/
4981 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
4982 {
4983 tmp1 = CurrentMode;
4984 tmp2 = hi2c->XferCount;
4985 tmp3 = hi2c->State;
4986 tmp4 = hi2c->PreviousState;
4987 if ((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \
4988 ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \
4989 ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX))))
4990 {
4991 I2C_Slave_AF(hi2c);
4992 }
4993 else
4994 {
4995 /* Clear AF flag */
4996 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4997
4998 error |= HAL_I2C_ERROR_AF;
4999
5000 /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
5001 if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
5002 {
5003 /* Generate Stop */
5004 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5005 }
5006 }
5007 }
5008
5009 /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
5010 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
5011 {
5012 error |= HAL_I2C_ERROR_OVR;
5013 /* Clear OVR flag */
5014 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
5015 }
5016
5017 /* Call the Error Callback in case of Error detected -----------------------*/
5018 if (error != HAL_I2C_ERROR_NONE)
5019 {
5020 hi2c->ErrorCode |= error;
5021 I2C_ITError(hi2c);
5022 }
5023 }
5024
5025 /**
5026 * @brief Master Tx Transfer completed callback.
5027 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5028 * the configuration information for the specified I2C.
5029 * @retval None
5030 */
HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef * hi2c)5031 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
5032 {
5033 /* Prevent unused argument(s) compilation warning */
5034 UNUSED(hi2c);
5035
5036 /* NOTE : This function should not be modified, when the callback is needed,
5037 the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
5038 */
5039 }
5040
5041 /**
5042 * @brief Master Rx Transfer completed callback.
5043 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5044 * the configuration information for the specified I2C.
5045 * @retval None
5046 */
HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef * hi2c)5047 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
5048 {
5049 /* Prevent unused argument(s) compilation warning */
5050 UNUSED(hi2c);
5051
5052 /* NOTE : This function should not be modified, when the callback is needed,
5053 the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
5054 */
5055 }
5056
5057 /** @brief Slave Tx Transfer completed callback.
5058 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5059 * the configuration information for the specified I2C.
5060 * @retval None
5061 */
HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef * hi2c)5062 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
5063 {
5064 /* Prevent unused argument(s) compilation warning */
5065 UNUSED(hi2c);
5066
5067 /* NOTE : This function should not be modified, when the callback is needed,
5068 the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
5069 */
5070 }
5071
5072 /**
5073 * @brief Slave Rx Transfer completed callback.
5074 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5075 * the configuration information for the specified I2C.
5076 * @retval None
5077 */
HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef * hi2c)5078 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
5079 {
5080 /* Prevent unused argument(s) compilation warning */
5081 UNUSED(hi2c);
5082
5083 /* NOTE : This function should not be modified, when the callback is needed,
5084 the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
5085 */
5086 }
5087
5088 /**
5089 * @brief Slave Address Match callback.
5090 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5091 * the configuration information for the specified I2C.
5092 * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferDirection_definition
5093 * @param AddrMatchCode Address Match Code
5094 * @retval None
5095 */
HAL_I2C_AddrCallback(I2C_HandleTypeDef * hi2c,uint8_t TransferDirection,uint16_t AddrMatchCode)5096 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
5097 {
5098 /* Prevent unused argument(s) compilation warning */
5099 UNUSED(hi2c);
5100 UNUSED(TransferDirection);
5101 UNUSED(AddrMatchCode);
5102
5103 /* NOTE : This function should not be modified, when the callback is needed,
5104 the HAL_I2C_AddrCallback() could be implemented in the user file
5105 */
5106 }
5107
5108 /**
5109 * @brief Listen Complete callback.
5110 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5111 * the configuration information for the specified I2C.
5112 * @retval None
5113 */
HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef * hi2c)5114 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
5115 {
5116 /* Prevent unused argument(s) compilation warning */
5117 UNUSED(hi2c);
5118
5119 /* NOTE : This function should not be modified, when the callback is needed,
5120 the HAL_I2C_ListenCpltCallback() could be implemented in the user file
5121 */
5122 }
5123
5124 /**
5125 * @brief Memory Tx Transfer completed callback.
5126 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5127 * the configuration information for the specified I2C.
5128 * @retval None
5129 */
HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef * hi2c)5130 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
5131 {
5132 /* Prevent unused argument(s) compilation warning */
5133 UNUSED(hi2c);
5134
5135 /* NOTE : This function should not be modified, when the callback is needed,
5136 the HAL_I2C_MemTxCpltCallback could be implemented in the user file
5137 */
5138 }
5139
5140 /**
5141 * @brief Memory Rx Transfer completed callback.
5142 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5143 * the configuration information for the specified I2C.
5144 * @retval None
5145 */
HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef * hi2c)5146 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
5147 {
5148 /* Prevent unused argument(s) compilation warning */
5149 UNUSED(hi2c);
5150
5151 /* NOTE : This function should not be modified, when the callback is needed,
5152 the HAL_I2C_MemRxCpltCallback could be implemented in the user file
5153 */
5154 }
5155
5156 /**
5157 * @brief I2C error callback.
5158 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5159 * the configuration information for the specified I2C.
5160 * @retval None
5161 */
HAL_I2C_ErrorCallback(I2C_HandleTypeDef * hi2c)5162 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
5163 {
5164 /* Prevent unused argument(s) compilation warning */
5165 UNUSED(hi2c);
5166
5167 /* NOTE : This function should not be modified, when the callback is needed,
5168 the HAL_I2C_ErrorCallback could be implemented in the user file
5169 */
5170 }
5171
5172 /**
5173 * @brief I2C abort callback.
5174 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5175 * the configuration information for the specified I2C.
5176 * @retval None
5177 */
HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef * hi2c)5178 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
5179 {
5180 /* Prevent unused argument(s) compilation warning */
5181 UNUSED(hi2c);
5182
5183 /* NOTE : This function should not be modified, when the callback is needed,
5184 the HAL_I2C_AbortCpltCallback could be implemented in the user file
5185 */
5186 }
5187
5188 /**
5189 * @}
5190 */
5191
5192 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
5193 * @brief Peripheral State, Mode and Error functions
5194 *
5195 @verbatim
5196 ===============================================================================
5197 ##### Peripheral State, Mode and Error functions #####
5198 ===============================================================================
5199 [..]
5200 This subsection permit to get in run-time the status of the peripheral
5201 and the data flow.
5202
5203 @endverbatim
5204 * @{
5205 */
5206
5207 /**
5208 * @brief Return the I2C handle state.
5209 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5210 * the configuration information for the specified I2C.
5211 * @retval HAL state
5212 */
HAL_I2C_GetState(I2C_HandleTypeDef * hi2c)5213 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
5214 {
5215 /* Return I2C handle state */
5216 return hi2c->State;
5217 }
5218
5219 /**
5220 * @brief Returns the I2C Master, Slave, Memory or no mode.
5221 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5222 * the configuration information for I2C module
5223 * @retval HAL mode
5224 */
HAL_I2C_GetMode(I2C_HandleTypeDef * hi2c)5225 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
5226 {
5227 return hi2c->Mode;
5228 }
5229
5230 /**
5231 * @brief Return the I2C error code.
5232 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5233 * the configuration information for the specified I2C.
5234 * @retval I2C Error Code
5235 */
HAL_I2C_GetError(I2C_HandleTypeDef * hi2c)5236 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
5237 {
5238 return hi2c->ErrorCode;
5239 }
5240
5241 /**
5242 * @}
5243 */
5244
5245 /**
5246 * @}
5247 */
5248
5249 /** @addtogroup I2C_Private_Functions
5250 * @{
5251 */
5252
5253 /**
5254 * @brief Handle TXE flag for Master
5255 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5256 * the configuration information for I2C module
5257 * @retval None
5258 */
I2C_MasterTransmit_TXE(I2C_HandleTypeDef * hi2c)5259 static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
5260 {
5261 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5262 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
5263 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
5264 uint32_t CurrentXferOptions = hi2c->XferOptions;
5265
5266 if ((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
5267 {
5268 /* Call TxCpltCallback() directly if no stop mode is set */
5269 if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
5270 {
5271 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5272
5273 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5274 hi2c->Mode = HAL_I2C_MODE_NONE;
5275 hi2c->State = HAL_I2C_STATE_READY;
5276
5277 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5278 hi2c->MasterTxCpltCallback(hi2c);
5279 #else
5280 HAL_I2C_MasterTxCpltCallback(hi2c);
5281 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5282 }
5283 else /* Generate Stop condition then Call TxCpltCallback() */
5284 {
5285 /* Disable EVT, BUF and ERR interrupt */
5286 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5287
5288 /* Generate Stop */
5289 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5290
5291 hi2c->PreviousState = I2C_STATE_NONE;
5292 hi2c->State = HAL_I2C_STATE_READY;
5293
5294 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5295 {
5296 hi2c->Mode = HAL_I2C_MODE_NONE;
5297 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5298 hi2c->MemTxCpltCallback(hi2c);
5299 #else
5300 HAL_I2C_MemTxCpltCallback(hi2c);
5301 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5302 }
5303 else
5304 {
5305 hi2c->Mode = HAL_I2C_MODE_NONE;
5306 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5307 hi2c->MasterTxCpltCallback(hi2c);
5308 #else
5309 HAL_I2C_MasterTxCpltCallback(hi2c);
5310 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5311 }
5312 }
5313 }
5314 else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || \
5315 ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX)))
5316 {
5317 if (hi2c->XferCount == 0U)
5318 {
5319 /* Disable BUF interrupt */
5320 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5321 }
5322 else
5323 {
5324 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5325 {
5326 I2C_MemoryTransmit_TXE_BTF(hi2c);
5327 }
5328 else
5329 {
5330 /* Write data to DR */
5331 hi2c->Instance->DR = *hi2c->pBuffPtr;
5332
5333 /* Increment Buffer pointer */
5334 hi2c->pBuffPtr++;
5335
5336 /* Update counter */
5337 hi2c->XferCount--;
5338 }
5339 }
5340 }
5341 else
5342 {
5343 /* Do nothing */
5344 }
5345 }
5346
5347 /**
5348 * @brief Handle BTF flag for Master transmitter
5349 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5350 * the configuration information for I2C module
5351 * @retval None
5352 */
I2C_MasterTransmit_BTF(I2C_HandleTypeDef * hi2c)5353 static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
5354 {
5355 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5356 uint32_t CurrentXferOptions = hi2c->XferOptions;
5357
5358 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5359 {
5360 if (hi2c->XferCount != 0U)
5361 {
5362 /* Write data to DR */
5363 hi2c->Instance->DR = *hi2c->pBuffPtr;
5364
5365 /* Increment Buffer pointer */
5366 hi2c->pBuffPtr++;
5367
5368 /* Update counter */
5369 hi2c->XferCount--;
5370 }
5371 else
5372 {
5373 /* Call TxCpltCallback() directly if no stop mode is set */
5374 if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
5375 {
5376 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5377
5378 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5379 hi2c->Mode = HAL_I2C_MODE_NONE;
5380 hi2c->State = HAL_I2C_STATE_READY;
5381
5382 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5383 hi2c->MasterTxCpltCallback(hi2c);
5384 #else
5385 HAL_I2C_MasterTxCpltCallback(hi2c);
5386 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5387 }
5388 else /* Generate Stop condition then Call TxCpltCallback() */
5389 {
5390 /* Disable EVT, BUF and ERR interrupt */
5391 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5392
5393 /* Generate Stop */
5394 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5395
5396 hi2c->PreviousState = I2C_STATE_NONE;
5397 hi2c->State = HAL_I2C_STATE_READY;
5398 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5399 {
5400 hi2c->Mode = HAL_I2C_MODE_NONE;
5401 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5402 hi2c->MemTxCpltCallback(hi2c);
5403 #else
5404 HAL_I2C_MemTxCpltCallback(hi2c);
5405 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5406 }
5407 else
5408 {
5409 hi2c->Mode = HAL_I2C_MODE_NONE;
5410
5411 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5412 hi2c->MasterTxCpltCallback(hi2c);
5413 #else
5414 HAL_I2C_MasterTxCpltCallback(hi2c);
5415 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5416 }
5417 }
5418 }
5419 }
5420 else
5421 {
5422 /* Do nothing */
5423 }
5424 }
5425
5426 /**
5427 * @brief Handle TXE and BTF flag for Memory transmitter
5428 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5429 * the configuration information for I2C module
5430 * @retval None
5431 */
I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef * hi2c)5432 static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c)
5433 {
5434 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5435 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
5436
5437 if (hi2c->EventCount == 0U)
5438 {
5439 /* If Memory address size is 8Bit */
5440 if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
5441 {
5442 /* Send Memory Address */
5443 hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
5444
5445 hi2c->EventCount += 2U;
5446 }
5447 /* If Memory address size is 16Bit */
5448 else
5449 {
5450 /* Send MSB of Memory Address */
5451 hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
5452
5453 hi2c->EventCount++;
5454 }
5455 }
5456 else if (hi2c->EventCount == 1U)
5457 {
5458 /* Send LSB of Memory Address */
5459 hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
5460
5461 hi2c->EventCount++;
5462 }
5463 else if (hi2c->EventCount == 2U)
5464 {
5465 if (CurrentState == HAL_I2C_STATE_BUSY_RX)
5466 {
5467 /* Generate Restart */
5468 hi2c->Instance->CR1 |= I2C_CR1_START;
5469
5470 hi2c->EventCount++;
5471 }
5472 else if ((hi2c->XferCount > 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
5473 {
5474 /* Write data to DR */
5475 hi2c->Instance->DR = *hi2c->pBuffPtr;
5476
5477 /* Increment Buffer pointer */
5478 hi2c->pBuffPtr++;
5479
5480 /* Update counter */
5481 hi2c->XferCount--;
5482 }
5483 else if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
5484 {
5485 /* Generate Stop condition then Call TxCpltCallback() */
5486 /* Disable EVT, BUF and ERR interrupt */
5487 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5488
5489 /* Generate Stop */
5490 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5491
5492 hi2c->PreviousState = I2C_STATE_NONE;
5493 hi2c->State = HAL_I2C_STATE_READY;
5494 hi2c->Mode = HAL_I2C_MODE_NONE;
5495 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5496 hi2c->MemTxCpltCallback(hi2c);
5497 #else
5498 HAL_I2C_MemTxCpltCallback(hi2c);
5499 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5500 }
5501 else
5502 {
5503 /* Do nothing */
5504 }
5505 }
5506 else
5507 {
5508 /* Do nothing */
5509 }
5510 }
5511
5512 /**
5513 * @brief Handle RXNE flag for Master
5514 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5515 * the configuration information for I2C module
5516 * @retval None
5517 */
I2C_MasterReceive_RXNE(I2C_HandleTypeDef * hi2c)5518 static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
5519 {
5520 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5521 {
5522 uint32_t tmp;
5523
5524 tmp = hi2c->XferCount;
5525 if (tmp > 3U)
5526 {
5527 /* Read data from DR */
5528 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5529
5530 /* Increment Buffer pointer */
5531 hi2c->pBuffPtr++;
5532
5533 /* Update counter */
5534 hi2c->XferCount--;
5535
5536 if (hi2c->XferCount == (uint16_t)3)
5537 {
5538 /* Disable BUF interrupt, this help to treat correctly the last 4 bytes
5539 on BTF subroutine */
5540 /* Disable BUF interrupt */
5541 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5542 }
5543 }
5544 else if ((hi2c->XferOptions != I2C_FIRST_AND_NEXT_FRAME) && ((tmp == 1U) || (tmp == 0U)))
5545 {
5546 if (I2C_WaitOnSTOPRequestThroughIT(hi2c) == HAL_OK)
5547 {
5548 /* Disable Acknowledge */
5549 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5550
5551 /* Disable EVT, BUF and ERR interrupt */
5552 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5553
5554 /* Read data from DR */
5555 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5556
5557 /* Increment Buffer pointer */
5558 hi2c->pBuffPtr++;
5559
5560 /* Update counter */
5561 hi2c->XferCount--;
5562
5563 hi2c->State = HAL_I2C_STATE_READY;
5564
5565 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5566 {
5567 hi2c->Mode = HAL_I2C_MODE_NONE;
5568 hi2c->PreviousState = I2C_STATE_NONE;
5569
5570 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5571 hi2c->MemRxCpltCallback(hi2c);
5572 #else
5573 HAL_I2C_MemRxCpltCallback(hi2c);
5574 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5575 }
5576 else
5577 {
5578 hi2c->Mode = HAL_I2C_MODE_NONE;
5579 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
5580
5581 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5582 hi2c->MasterRxCpltCallback(hi2c);
5583 #else
5584 HAL_I2C_MasterRxCpltCallback(hi2c);
5585 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5586 }
5587 }
5588 else
5589 {
5590 /* Disable EVT, BUF and ERR interrupt */
5591 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5592
5593 /* Read data from DR */
5594 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5595
5596 /* Increment Buffer pointer */
5597 hi2c->pBuffPtr++;
5598
5599 /* Update counter */
5600 hi2c->XferCount--;
5601
5602 hi2c->State = HAL_I2C_STATE_READY;
5603 hi2c->Mode = HAL_I2C_MODE_NONE;
5604
5605 /* Call user error callback */
5606 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5607 hi2c->ErrorCallback(hi2c);
5608 #else
5609 HAL_I2C_ErrorCallback(hi2c);
5610 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5611 }
5612 }
5613 else
5614 {
5615 /* Do nothing */
5616 }
5617 }
5618 }
5619
5620 /**
5621 * @brief Handle BTF flag for Master receiver
5622 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5623 * the configuration information for I2C module
5624 * @retval None
5625 */
I2C_MasterReceive_BTF(I2C_HandleTypeDef * hi2c)5626 static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
5627 {
5628 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5629 uint32_t CurrentXferOptions = hi2c->XferOptions;
5630
5631 if (hi2c->XferCount == 4U)
5632 {
5633 /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
5634 on BTF subroutine if there is a reception delay between N-1 and N byte */
5635 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5636
5637 /* Read data from DR */
5638 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5639
5640 /* Increment Buffer pointer */
5641 hi2c->pBuffPtr++;
5642
5643 /* Update counter */
5644 hi2c->XferCount--;
5645 }
5646 else if (hi2c->XferCount == 3U)
5647 {
5648 /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
5649 on BTF subroutine if there is a reception delay between N-1 and N byte */
5650 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5651
5652 if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME))
5653 {
5654 /* Disable Acknowledge */
5655 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5656 }
5657
5658 /* Read data from DR */
5659 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5660
5661 /* Increment Buffer pointer */
5662 hi2c->pBuffPtr++;
5663
5664 /* Update counter */
5665 hi2c->XferCount--;
5666 }
5667 else if (hi2c->XferCount == 2U)
5668 {
5669 /* Prepare next transfer or stop current transfer */
5670 if ((CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP))
5671 {
5672 /* Disable Acknowledge */
5673 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5674 }
5675 else if ((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_NEXT_FRAME))
5676 {
5677 /* Enable Acknowledge */
5678 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5679 }
5680 else if (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)
5681 {
5682 /* Generate Stop */
5683 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5684 }
5685 else
5686 {
5687 /* Do nothing */
5688 }
5689
5690 /* Read data from DR */
5691 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5692
5693 /* Increment Buffer pointer */
5694 hi2c->pBuffPtr++;
5695
5696 /* Update counter */
5697 hi2c->XferCount--;
5698
5699 /* Read data from DR */
5700 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5701
5702 /* Increment Buffer pointer */
5703 hi2c->pBuffPtr++;
5704
5705 /* Update counter */
5706 hi2c->XferCount--;
5707
5708 /* Disable EVT and ERR interrupt */
5709 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
5710
5711 hi2c->State = HAL_I2C_STATE_READY;
5712 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5713 {
5714 hi2c->Mode = HAL_I2C_MODE_NONE;
5715 hi2c->PreviousState = I2C_STATE_NONE;
5716 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5717 hi2c->MemRxCpltCallback(hi2c);
5718 #else
5719 HAL_I2C_MemRxCpltCallback(hi2c);
5720 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5721 }
5722 else
5723 {
5724 hi2c->Mode = HAL_I2C_MODE_NONE;
5725 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
5726 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5727 hi2c->MasterRxCpltCallback(hi2c);
5728 #else
5729 HAL_I2C_MasterRxCpltCallback(hi2c);
5730 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5731 }
5732 }
5733 else
5734 {
5735 /* Read data from DR */
5736 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5737
5738 /* Increment Buffer pointer */
5739 hi2c->pBuffPtr++;
5740
5741 /* Update counter */
5742 hi2c->XferCount--;
5743 }
5744 }
5745
5746 /**
5747 * @brief Handle SB flag for Master
5748 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5749 * the configuration information for I2C module
5750 * @retval None
5751 */
I2C_Master_SB(I2C_HandleTypeDef * hi2c)5752 static void I2C_Master_SB(I2C_HandleTypeDef *hi2c)
5753 {
5754 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5755 {
5756 if (hi2c->EventCount == 0U)
5757 {
5758 /* Send slave address */
5759 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
5760 }
5761 else
5762 {
5763 hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
5764 }
5765 }
5766 else
5767 {
5768 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
5769 {
5770 /* Send slave 7 Bits address */
5771 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5772 {
5773 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
5774 }
5775 else
5776 {
5777 hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
5778 }
5779
5780 if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL))
5781 || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL)))
5782 {
5783 /* Enable DMA Request */
5784 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
5785 }
5786 }
5787 else
5788 {
5789 if (hi2c->EventCount == 0U)
5790 {
5791 /* Send header of slave address */
5792 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress);
5793 }
5794 else if (hi2c->EventCount == 1U)
5795 {
5796 /* Send header of slave address */
5797 hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress);
5798 }
5799 else
5800 {
5801 /* Do nothing */
5802 }
5803 }
5804 }
5805 }
5806
5807 /**
5808 * @brief Handle ADD10 flag for Master
5809 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5810 * the configuration information for I2C module
5811 * @retval None
5812 */
I2C_Master_ADD10(I2C_HandleTypeDef * hi2c)5813 static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)
5814 {
5815 /* Send slave address */
5816 hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);
5817
5818 if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL))
5819 || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL)))
5820 {
5821 /* Enable DMA Request */
5822 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
5823 }
5824 }
5825
5826 /**
5827 * @brief Handle ADDR flag for Master
5828 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5829 * the configuration information for I2C module
5830 * @retval None
5831 */
I2C_Master_ADDR(I2C_HandleTypeDef * hi2c)5832 static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
5833 {
5834 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
5835 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
5836 uint32_t CurrentXferOptions = hi2c->XferOptions;
5837 uint32_t Prev_State = hi2c->PreviousState;
5838
5839 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5840 {
5841 if ((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM))
5842 {
5843 /* Clear ADDR flag */
5844 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5845 }
5846 else if ((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT))
5847 {
5848 /* Clear ADDR flag */
5849 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5850
5851 /* Generate Restart */
5852 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
5853
5854 hi2c->EventCount++;
5855 }
5856 else
5857 {
5858 if (hi2c->XferCount == 0U)
5859 {
5860 /* Clear ADDR flag */
5861 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5862
5863 /* Generate Stop */
5864 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5865 }
5866 else if (hi2c->XferCount == 1U)
5867 {
5868 if (CurrentXferOptions == I2C_NO_OPTION_FRAME)
5869 {
5870 /* Disable Acknowledge */
5871 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5872
5873 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
5874 {
5875 /* Disable Acknowledge */
5876 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5877
5878 /* Clear ADDR flag */
5879 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5880 }
5881 else
5882 {
5883 /* Clear ADDR flag */
5884 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5885
5886 /* Generate Stop */
5887 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5888 }
5889 }
5890 /* Prepare next transfer or stop current transfer */
5891 else if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \
5892 && ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (CurrentXferOptions == I2C_FIRST_FRAME)))
5893 {
5894 if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP))
5895 {
5896 /* Disable Acknowledge */
5897 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5898 }
5899 else
5900 {
5901 /* Enable Acknowledge */
5902 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5903 }
5904
5905 /* Clear ADDR flag */
5906 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5907 }
5908 else
5909 {
5910 /* Disable Acknowledge */
5911 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5912
5913 /* Clear ADDR flag */
5914 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5915
5916 /* Generate Stop */
5917 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5918 }
5919 }
5920 else if (hi2c->XferCount == 2U)
5921 {
5922 if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP))
5923 {
5924 /* Disable Acknowledge */
5925 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5926
5927 /* Enable Pos */
5928 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
5929 }
5930 else
5931 {
5932 /* Enable Acknowledge */
5933 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5934 }
5935
5936 if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME)))
5937 {
5938 /* Enable Last DMA bit */
5939 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
5940 }
5941
5942 /* Clear ADDR flag */
5943 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5944 }
5945 else
5946 {
5947 /* Enable Acknowledge */
5948 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5949
5950 if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME)))
5951 {
5952 /* Enable Last DMA bit */
5953 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
5954 }
5955
5956 /* Clear ADDR flag */
5957 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5958 }
5959
5960 /* Reset Event counter */
5961 hi2c->EventCount = 0U;
5962 }
5963 }
5964 else
5965 {
5966 /* Clear ADDR flag */
5967 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5968 }
5969 }
5970
5971 /**
5972 * @brief Handle TXE flag for Slave
5973 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5974 * the configuration information for I2C module
5975 * @retval None
5976 */
I2C_SlaveTransmit_TXE(I2C_HandleTypeDef * hi2c)5977 static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
5978 {
5979 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5980 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
5981
5982 if (hi2c->XferCount != 0U)
5983 {
5984 /* Write data to DR */
5985 hi2c->Instance->DR = *hi2c->pBuffPtr;
5986
5987 /* Increment Buffer pointer */
5988 hi2c->pBuffPtr++;
5989
5990 /* Update counter */
5991 hi2c->XferCount--;
5992
5993 if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
5994 {
5995 /* Last Byte is received, disable Interrupt */
5996 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5997
5998 /* Set state at HAL_I2C_STATE_LISTEN */
5999 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6000 hi2c->State = HAL_I2C_STATE_LISTEN;
6001
6002 /* Call the corresponding callback to inform upper layer of End of Transfer */
6003 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6004 hi2c->SlaveTxCpltCallback(hi2c);
6005 #else
6006 HAL_I2C_SlaveTxCpltCallback(hi2c);
6007 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6008 }
6009 }
6010 }
6011
6012 /**
6013 * @brief Handle BTF flag for Slave transmitter
6014 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6015 * the configuration information for I2C module
6016 * @retval None
6017 */
I2C_SlaveTransmit_BTF(I2C_HandleTypeDef * hi2c)6018 static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
6019 {
6020 if (hi2c->XferCount != 0U)
6021 {
6022 /* Write data to DR */
6023 hi2c->Instance->DR = *hi2c->pBuffPtr;
6024
6025 /* Increment Buffer pointer */
6026 hi2c->pBuffPtr++;
6027
6028 /* Update counter */
6029 hi2c->XferCount--;
6030 }
6031 }
6032
6033 /**
6034 * @brief Handle RXNE flag for Slave
6035 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6036 * the configuration information for I2C module
6037 * @retval None
6038 */
I2C_SlaveReceive_RXNE(I2C_HandleTypeDef * hi2c)6039 static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
6040 {
6041 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
6042 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6043
6044 if (hi2c->XferCount != 0U)
6045 {
6046 /* Read data from DR */
6047 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6048
6049 /* Increment Buffer pointer */
6050 hi2c->pBuffPtr++;
6051
6052 /* Update counter */
6053 hi2c->XferCount--;
6054
6055 if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
6056 {
6057 /* Last Byte is received, disable Interrupt */
6058 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
6059
6060 /* Set state at HAL_I2C_STATE_LISTEN */
6061 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6062 hi2c->State = HAL_I2C_STATE_LISTEN;
6063
6064 /* Call the corresponding callback to inform upper layer of End of Transfer */
6065 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6066 hi2c->SlaveRxCpltCallback(hi2c);
6067 #else
6068 HAL_I2C_SlaveRxCpltCallback(hi2c);
6069 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6070 }
6071 }
6072 }
6073
6074 /**
6075 * @brief Handle BTF flag for Slave receiver
6076 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6077 * the configuration information for I2C module
6078 * @retval None
6079 */
I2C_SlaveReceive_BTF(I2C_HandleTypeDef * hi2c)6080 static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
6081 {
6082 if (hi2c->XferCount != 0U)
6083 {
6084 /* Read data from DR */
6085 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6086
6087 /* Increment Buffer pointer */
6088 hi2c->pBuffPtr++;
6089
6090 /* Update counter */
6091 hi2c->XferCount--;
6092 }
6093 }
6094
6095 /**
6096 * @brief Handle ADD flag for Slave
6097 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6098 * the configuration information for I2C module
6099 * @param IT2Flags Interrupt2 flags to handle.
6100 * @retval None
6101 */
I2C_Slave_ADDR(I2C_HandleTypeDef * hi2c,uint32_t IT2Flags)6102 static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags)
6103 {
6104 uint8_t TransferDirection = I2C_DIRECTION_RECEIVE;
6105 uint16_t SlaveAddrCode;
6106
6107 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
6108 {
6109 /* Disable BUF interrupt, BUF enabling is manage through slave specific interface */
6110 __HAL_I2C_DISABLE_IT(hi2c, (I2C_IT_BUF));
6111
6112 /* Transfer Direction requested by Master */
6113 if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_TRA) == RESET)
6114 {
6115 TransferDirection = I2C_DIRECTION_TRANSMIT;
6116 }
6117
6118 if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_DUALF) == RESET)
6119 {
6120 SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress1;
6121 }
6122 else
6123 {
6124 SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress2;
6125 }
6126
6127 /* Process Unlocked */
6128 __HAL_UNLOCK(hi2c);
6129
6130 /* Call Slave Addr callback */
6131 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6132 hi2c->AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
6133 #else
6134 HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
6135 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6136 }
6137 else
6138 {
6139 /* Clear ADDR flag */
6140 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6141
6142 /* Process Unlocked */
6143 __HAL_UNLOCK(hi2c);
6144 }
6145 }
6146
6147 /**
6148 * @brief Handle STOPF flag for Slave
6149 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6150 * the configuration information for I2C module
6151 * @retval None
6152 */
I2C_Slave_STOPF(I2C_HandleTypeDef * hi2c)6153 static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
6154 {
6155 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6156 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6157
6158 /* Disable EVT, BUF and ERR interrupt */
6159 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6160
6161 /* Clear STOPF flag */
6162 __HAL_I2C_CLEAR_STOPFLAG(hi2c);
6163
6164 /* Disable Acknowledge */
6165 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6166
6167 /* If a DMA is ongoing, Update handle size context */
6168 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
6169 {
6170 if ((CurrentState == HAL_I2C_STATE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
6171 {
6172 hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmarx));
6173
6174 if (hi2c->XferCount != 0U)
6175 {
6176 /* Set ErrorCode corresponding to a Non-Acknowledge */
6177 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6178 }
6179
6180 /* Disable, stop the current DMA */
6181 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
6182
6183 /* Abort DMA Xfer if any */
6184 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
6185 {
6186 /* Set the I2C DMA Abort callback :
6187 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6188 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6189
6190 /* Abort DMA RX */
6191 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6192 {
6193 /* Call Directly XferAbortCallback function in case of error */
6194 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6195 }
6196 }
6197 }
6198 else
6199 {
6200 hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmatx));
6201
6202 if (hi2c->XferCount != 0U)
6203 {
6204 /* Set ErrorCode corresponding to a Non-Acknowledge */
6205 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6206 }
6207
6208 /* Disable, stop the current DMA */
6209 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
6210
6211 /* Abort DMA Xfer if any */
6212 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
6213 {
6214 /* Set the I2C DMA Abort callback :
6215 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6216 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6217
6218 /* Abort DMA TX */
6219 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6220 {
6221 /* Call Directly XferAbortCallback function in case of error */
6222 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6223 }
6224 }
6225 }
6226 }
6227
6228 /* All data are not transferred, so set error code accordingly */
6229 if (hi2c->XferCount != 0U)
6230 {
6231 /* Store Last receive data if any */
6232 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
6233 {
6234 /* Read data from DR */
6235 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6236
6237 /* Increment Buffer pointer */
6238 hi2c->pBuffPtr++;
6239
6240 /* Update counter */
6241 hi2c->XferCount--;
6242 }
6243
6244 /* Store Last receive data if any */
6245 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6246 {
6247 /* Read data from DR */
6248 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6249
6250 /* Increment Buffer pointer */
6251 hi2c->pBuffPtr++;
6252
6253 /* Update counter */
6254 hi2c->XferCount--;
6255 }
6256
6257 if (hi2c->XferCount != 0U)
6258 {
6259 /* Set ErrorCode corresponding to a Non-Acknowledge */
6260 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6261 }
6262 }
6263
6264 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
6265 {
6266 /* Call the corresponding callback to inform upper layer of End of Transfer */
6267 I2C_ITError(hi2c);
6268 }
6269 else
6270 {
6271 if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)
6272 {
6273 /* Set state at HAL_I2C_STATE_LISTEN */
6274 hi2c->PreviousState = I2C_STATE_NONE;
6275 hi2c->State = HAL_I2C_STATE_LISTEN;
6276
6277 /* Call the corresponding callback to inform upper layer of End of Transfer */
6278 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6279 hi2c->SlaveRxCpltCallback(hi2c);
6280 #else
6281 HAL_I2C_SlaveRxCpltCallback(hi2c);
6282 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6283 }
6284
6285 if (hi2c->State == HAL_I2C_STATE_LISTEN)
6286 {
6287 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6288 hi2c->PreviousState = I2C_STATE_NONE;
6289 hi2c->State = HAL_I2C_STATE_READY;
6290 hi2c->Mode = HAL_I2C_MODE_NONE;
6291
6292 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6293 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6294 hi2c->ListenCpltCallback(hi2c);
6295 #else
6296 HAL_I2C_ListenCpltCallback(hi2c);
6297 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6298 }
6299 else
6300 {
6301 if ((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX))
6302 {
6303 hi2c->PreviousState = I2C_STATE_NONE;
6304 hi2c->State = HAL_I2C_STATE_READY;
6305 hi2c->Mode = HAL_I2C_MODE_NONE;
6306
6307 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6308 hi2c->SlaveRxCpltCallback(hi2c);
6309 #else
6310 HAL_I2C_SlaveRxCpltCallback(hi2c);
6311 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6312 }
6313 }
6314 }
6315 }
6316
6317 /**
6318 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6319 * the configuration information for I2C module
6320 * @retval None
6321 */
I2C_Slave_AF(I2C_HandleTypeDef * hi2c)6322 static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
6323 {
6324 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
6325 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6326 uint32_t CurrentXferOptions = hi2c->XferOptions;
6327
6328 if (((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \
6329 (CurrentState == HAL_I2C_STATE_LISTEN))
6330 {
6331 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6332
6333 /* Disable EVT, BUF and ERR interrupt */
6334 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6335
6336 /* Clear AF flag */
6337 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6338
6339 /* Disable Acknowledge */
6340 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6341
6342 hi2c->PreviousState = I2C_STATE_NONE;
6343 hi2c->State = HAL_I2C_STATE_READY;
6344 hi2c->Mode = HAL_I2C_MODE_NONE;
6345
6346 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6347 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6348 hi2c->ListenCpltCallback(hi2c);
6349 #else
6350 HAL_I2C_ListenCpltCallback(hi2c);
6351 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6352 }
6353 else if (CurrentState == HAL_I2C_STATE_BUSY_TX)
6354 {
6355 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6356 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6357 hi2c->State = HAL_I2C_STATE_READY;
6358 hi2c->Mode = HAL_I2C_MODE_NONE;
6359
6360 /* Disable EVT, BUF and ERR interrupt */
6361 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6362
6363 /* Clear AF flag */
6364 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6365
6366 /* Disable Acknowledge */
6367 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6368
6369 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6370 hi2c->SlaveTxCpltCallback(hi2c);
6371 #else
6372 HAL_I2C_SlaveTxCpltCallback(hi2c);
6373 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6374 }
6375 else
6376 {
6377 /* Clear AF flag only */
6378 /* State Listen, but XferOptions == FIRST or NEXT */
6379 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6380 }
6381 }
6382
6383 /**
6384 * @brief I2C interrupts error process
6385 * @param hi2c I2C handle.
6386 * @retval None
6387 */
I2C_ITError(I2C_HandleTypeDef * hi2c)6388 static void I2C_ITError(I2C_HandleTypeDef *hi2c)
6389 {
6390 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6391 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6392 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
6393 uint32_t CurrentError;
6394
6395 if (((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) && (CurrentState == HAL_I2C_STATE_BUSY_RX))
6396 {
6397 /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
6398 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
6399 }
6400
6401 if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
6402 {
6403 /* keep HAL_I2C_STATE_LISTEN */
6404 hi2c->PreviousState = I2C_STATE_NONE;
6405 hi2c->State = HAL_I2C_STATE_LISTEN;
6406 }
6407 else
6408 {
6409 /* If state is an abort treatment on going, don't change state */
6410 /* This change will be do later */
6411 if ((READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) && (CurrentState != HAL_I2C_STATE_ABORT))
6412 {
6413 hi2c->State = HAL_I2C_STATE_READY;
6414 hi2c->Mode = HAL_I2C_MODE_NONE;
6415 }
6416 hi2c->PreviousState = I2C_STATE_NONE;
6417 }
6418
6419 /* Abort DMA transfer */
6420 if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
6421 {
6422 hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
6423
6424 if (hi2c->hdmatx->State != HAL_DMA_STATE_READY)
6425 {
6426 /* Set the DMA Abort callback :
6427 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6428 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6429
6430 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6431 {
6432 /* Disable I2C peripheral to prevent dummy data in buffer */
6433 __HAL_I2C_DISABLE(hi2c);
6434
6435 hi2c->State = HAL_I2C_STATE_READY;
6436
6437 /* Call Directly XferAbortCallback function in case of error */
6438 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6439 }
6440 }
6441 else
6442 {
6443 /* Set the DMA Abort callback :
6444 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6445 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6446
6447 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6448 {
6449 /* Store Last receive data if any */
6450 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6451 {
6452 /* Read data from DR */
6453 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6454
6455 /* Increment Buffer pointer */
6456 hi2c->pBuffPtr++;
6457 }
6458
6459 /* Disable I2C peripheral to prevent dummy data in buffer */
6460 __HAL_I2C_DISABLE(hi2c);
6461
6462 hi2c->State = HAL_I2C_STATE_READY;
6463
6464 /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
6465 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6466 }
6467 }
6468 }
6469 else if (hi2c->State == HAL_I2C_STATE_ABORT)
6470 {
6471 hi2c->State = HAL_I2C_STATE_READY;
6472 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
6473
6474 /* Store Last receive data if any */
6475 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6476 {
6477 /* Read data from DR */
6478 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6479
6480 /* Increment Buffer pointer */
6481 hi2c->pBuffPtr++;
6482 }
6483
6484 /* Disable I2C peripheral to prevent dummy data in buffer */
6485 __HAL_I2C_DISABLE(hi2c);
6486
6487 /* Call the corresponding callback to inform upper layer of End of Transfer */
6488 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6489 hi2c->AbortCpltCallback(hi2c);
6490 #else
6491 HAL_I2C_AbortCpltCallback(hi2c);
6492 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6493 }
6494 else
6495 {
6496 /* Store Last receive data if any */
6497 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6498 {
6499 /* Read data from DR */
6500 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6501
6502 /* Increment Buffer pointer */
6503 hi2c->pBuffPtr++;
6504 }
6505
6506 /* Call user error callback */
6507 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6508 hi2c->ErrorCallback(hi2c);
6509 #else
6510 HAL_I2C_ErrorCallback(hi2c);
6511 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6512 }
6513
6514 /* STOP Flag is not set after a NACK reception, BusError, ArbitrationLost, OverRun */
6515 CurrentError = hi2c->ErrorCode;
6516
6517 if (((CurrentError & HAL_I2C_ERROR_BERR) == HAL_I2C_ERROR_BERR) || \
6518 ((CurrentError & HAL_I2C_ERROR_ARLO) == HAL_I2C_ERROR_ARLO) || \
6519 ((CurrentError & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) || \
6520 ((CurrentError & HAL_I2C_ERROR_OVR) == HAL_I2C_ERROR_OVR))
6521 {
6522 /* Disable EVT, BUF and ERR interrupt */
6523 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6524 }
6525
6526 /* So may inform upper layer that listen phase is stopped */
6527 /* during NACK error treatment */
6528 CurrentState = hi2c->State;
6529 if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN))
6530 {
6531 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6532 hi2c->PreviousState = I2C_STATE_NONE;
6533 hi2c->State = HAL_I2C_STATE_READY;
6534 hi2c->Mode = HAL_I2C_MODE_NONE;
6535
6536 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6537 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6538 hi2c->ListenCpltCallback(hi2c);
6539 #else
6540 HAL_I2C_ListenCpltCallback(hi2c);
6541 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6542 }
6543 }
6544
6545 /**
6546 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6547 * the configuration information for I2C module
6548 * @param DevAddress Target device address: The device 7 bits address value
6549 * in datasheet must be shifted to the left before calling the interface
6550 * @param Timeout Timeout duration
6551 * @param Tickstart Tick start value
6552 * @retval HAL status
6553 */
I2C_MasterRequestWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Timeout,uint32_t Tickstart)6554 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
6555 {
6556 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6557 uint32_t CurrentXferOptions = hi2c->XferOptions;
6558
6559 /* Generate Start condition if first transfer */
6560 if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
6561 {
6562 /* Generate Start */
6563 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6564 }
6565 else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
6566 {
6567 /* Generate ReStart */
6568 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6569 }
6570 else
6571 {
6572 /* Do nothing */
6573 }
6574
6575 /* Wait until SB flag is set */
6576 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6577 {
6578 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6579 {
6580 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6581 }
6582 return HAL_TIMEOUT;
6583 }
6584
6585 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
6586 {
6587 /* Send slave address */
6588 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
6589 }
6590 else
6591 {
6592 /* Send header of slave address */
6593 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
6594
6595 /* Wait until ADD10 flag is set */
6596 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
6597 {
6598 return HAL_ERROR;
6599 }
6600
6601 /* Send slave address */
6602 hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
6603 }
6604
6605 /* Wait until ADDR flag is set */
6606 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6607 {
6608 return HAL_ERROR;
6609 }
6610
6611 return HAL_OK;
6612 }
6613
6614 /**
6615 * @brief Master sends target device address for read request.
6616 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6617 * the configuration information for I2C module
6618 * @param DevAddress Target device address: The device 7 bits address value
6619 * in datasheet must be shifted to the left before calling the interface
6620 * @param Timeout Timeout duration
6621 * @param Tickstart Tick start value
6622 * @retval HAL status
6623 */
I2C_MasterRequestRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Timeout,uint32_t Tickstart)6624 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
6625 {
6626 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6627 uint32_t CurrentXferOptions = hi2c->XferOptions;
6628
6629 /* Enable Acknowledge */
6630 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6631
6632 /* Generate Start condition if first transfer */
6633 if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
6634 {
6635 /* Generate Start */
6636 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6637 }
6638 else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
6639 {
6640 /* Generate ReStart */
6641 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6642 }
6643 else
6644 {
6645 /* Do nothing */
6646 }
6647
6648 /* Wait until SB flag is set */
6649 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6650 {
6651 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6652 {
6653 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6654 }
6655 return HAL_TIMEOUT;
6656 }
6657
6658 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
6659 {
6660 /* Send slave address */
6661 hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
6662 }
6663 else
6664 {
6665 /* Send header of slave address */
6666 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
6667
6668 /* Wait until ADD10 flag is set */
6669 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
6670 {
6671 return HAL_ERROR;
6672 }
6673
6674 /* Send slave address */
6675 hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
6676
6677 /* Wait until ADDR flag is set */
6678 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6679 {
6680 return HAL_ERROR;
6681 }
6682
6683 /* Clear ADDR flag */
6684 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6685
6686 /* Generate Restart */
6687 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6688
6689 /* Wait until SB flag is set */
6690 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6691 {
6692 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6693 {
6694 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6695 }
6696 return HAL_TIMEOUT;
6697 }
6698
6699 /* Send header of slave address */
6700 hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
6701 }
6702
6703 /* Wait until ADDR flag is set */
6704 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6705 {
6706 return HAL_ERROR;
6707 }
6708
6709 return HAL_OK;
6710 }
6711
6712 /**
6713 * @brief Master sends target device address followed by internal memory address for write request.
6714 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6715 * the configuration information for I2C module
6716 * @param DevAddress Target device address: The device 7 bits address value
6717 * in datasheet must be shifted to the left before calling the interface
6718 * @param MemAddress Internal memory address
6719 * @param MemAddSize Size of internal memory address
6720 * @param Timeout Timeout duration
6721 * @param Tickstart Tick start value
6722 * @retval HAL status
6723 */
I2C_RequestMemoryWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)6724 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
6725 {
6726 /* Generate Start */
6727 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6728
6729 /* Wait until SB flag is set */
6730 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6731 {
6732 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6733 {
6734 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6735 }
6736 return HAL_TIMEOUT;
6737 }
6738
6739 /* Send slave address */
6740 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
6741
6742 /* Wait until ADDR flag is set */
6743 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6744 {
6745 return HAL_ERROR;
6746 }
6747
6748 /* Clear ADDR flag */
6749 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6750
6751 /* Wait until TXE flag is set */
6752 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6753 {
6754 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6755 {
6756 /* Generate Stop */
6757 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6758 }
6759 return HAL_ERROR;
6760 }
6761
6762 /* If Memory address size is 8Bit */
6763 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
6764 {
6765 /* Send Memory Address */
6766 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6767 }
6768 /* If Memory address size is 16Bit */
6769 else
6770 {
6771 /* Send MSB of Memory Address */
6772 hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
6773
6774 /* Wait until TXE flag is set */
6775 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6776 {
6777 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6778 {
6779 /* Generate Stop */
6780 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6781 }
6782 return HAL_ERROR;
6783 }
6784
6785 /* Send LSB of Memory Address */
6786 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6787 }
6788
6789 return HAL_OK;
6790 }
6791
6792 /**
6793 * @brief Master sends target device address followed by internal memory address for read request.
6794 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6795 * the configuration information for I2C module
6796 * @param DevAddress Target device address: The device 7 bits address value
6797 * in datasheet must be shifted to the left before calling the interface
6798 * @param MemAddress Internal memory address
6799 * @param MemAddSize Size of internal memory address
6800 * @param Timeout Timeout duration
6801 * @param Tickstart Tick start value
6802 * @retval HAL status
6803 */
I2C_RequestMemoryRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)6804 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
6805 {
6806 /* Enable Acknowledge */
6807 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6808
6809 /* Generate Start */
6810 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6811
6812 /* Wait until SB flag is set */
6813 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6814 {
6815 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6816 {
6817 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6818 }
6819 return HAL_TIMEOUT;
6820 }
6821
6822 /* Send slave address */
6823 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
6824
6825 /* Wait until ADDR flag is set */
6826 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6827 {
6828 return HAL_ERROR;
6829 }
6830
6831 /* Clear ADDR flag */
6832 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6833
6834 /* Wait until TXE flag is set */
6835 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6836 {
6837 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6838 {
6839 /* Generate Stop */
6840 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6841 }
6842 return HAL_ERROR;
6843 }
6844
6845 /* If Memory address size is 8Bit */
6846 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
6847 {
6848 /* Send Memory Address */
6849 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6850 }
6851 /* If Memory address size is 16Bit */
6852 else
6853 {
6854 /* Send MSB of Memory Address */
6855 hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
6856
6857 /* Wait until TXE flag is set */
6858 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6859 {
6860 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6861 {
6862 /* Generate Stop */
6863 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6864 }
6865 return HAL_ERROR;
6866 }
6867
6868 /* Send LSB of Memory Address */
6869 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6870 }
6871
6872 /* Wait until TXE flag is set */
6873 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6874 {
6875 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6876 {
6877 /* Generate Stop */
6878 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6879 }
6880 return HAL_ERROR;
6881 }
6882
6883 /* Generate Restart */
6884 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6885
6886 /* Wait until SB flag is set */
6887 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6888 {
6889 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6890 {
6891 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6892 }
6893 return HAL_TIMEOUT;
6894 }
6895
6896 /* Send slave address */
6897 hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
6898
6899 /* Wait until ADDR flag is set */
6900 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6901 {
6902 return HAL_ERROR;
6903 }
6904
6905 return HAL_OK;
6906 }
6907
6908 /**
6909 * @brief DMA I2C process complete callback.
6910 * @param hdma DMA handle
6911 * @retval None
6912 */
I2C_DMAXferCplt(DMA_HandleTypeDef * hdma)6913 static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
6914 {
6915 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
6916
6917 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6918 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6919 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
6920 uint32_t CurrentXferOptions = hi2c->XferOptions;
6921
6922 /* Disable EVT and ERR interrupt */
6923 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
6924
6925 /* Clear Complete callback */
6926 if (hi2c->hdmatx != NULL)
6927 {
6928 hi2c->hdmatx->XferCpltCallback = NULL;
6929 }
6930 if (hi2c->hdmarx != NULL)
6931 {
6932 hi2c->hdmarx->XferCpltCallback = NULL;
6933 }
6934
6935 if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE)))
6936 {
6937 /* Disable DMA Request */
6938 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
6939
6940 hi2c->XferCount = 0U;
6941
6942 if (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)
6943 {
6944 /* Set state at HAL_I2C_STATE_LISTEN */
6945 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6946 hi2c->State = HAL_I2C_STATE_LISTEN;
6947
6948 /* Call the corresponding callback to inform upper layer of End of Transfer */
6949 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6950 hi2c->SlaveTxCpltCallback(hi2c);
6951 #else
6952 HAL_I2C_SlaveTxCpltCallback(hi2c);
6953 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6954 }
6955 else if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)
6956 {
6957 /* Set state at HAL_I2C_STATE_LISTEN */
6958 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6959 hi2c->State = HAL_I2C_STATE_LISTEN;
6960
6961 /* Call the corresponding callback to inform upper layer of End of Transfer */
6962 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6963 hi2c->SlaveRxCpltCallback(hi2c);
6964 #else
6965 HAL_I2C_SlaveRxCpltCallback(hi2c);
6966 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6967 }
6968 else
6969 {
6970 /* Do nothing */
6971 }
6972
6973 /* Enable EVT and ERR interrupt to treat end of transfer in IRQ handler */
6974 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
6975 }
6976 /* Check current Mode, in case of treatment DMA handler have been preempted by a prior interrupt */
6977 else if (hi2c->Mode != HAL_I2C_MODE_NONE)
6978 {
6979 if (hi2c->XferCount == (uint16_t)1)
6980 {
6981 /* Disable Acknowledge */
6982 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6983 }
6984
6985 /* Disable EVT and ERR interrupt */
6986 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
6987
6988 /* Prepare next transfer or stop current transfer */
6989 if ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_OTHER_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME))
6990 {
6991 /* Generate Stop */
6992 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6993 }
6994
6995 /* Disable Last DMA */
6996 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
6997
6998 /* Disable DMA Request */
6999 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
7000
7001 hi2c->XferCount = 0U;
7002
7003 /* Check if Errors has been detected during transfer */
7004 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
7005 {
7006 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7007 hi2c->ErrorCallback(hi2c);
7008 #else
7009 HAL_I2C_ErrorCallback(hi2c);
7010 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7011 }
7012 else
7013 {
7014 hi2c->State = HAL_I2C_STATE_READY;
7015
7016 if (hi2c->Mode == HAL_I2C_MODE_MEM)
7017 {
7018 hi2c->Mode = HAL_I2C_MODE_NONE;
7019 hi2c->PreviousState = I2C_STATE_NONE;
7020
7021 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7022 hi2c->MemRxCpltCallback(hi2c);
7023 #else
7024 HAL_I2C_MemRxCpltCallback(hi2c);
7025 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7026 }
7027 else
7028 {
7029 hi2c->Mode = HAL_I2C_MODE_NONE;
7030 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
7031
7032 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7033 hi2c->MasterRxCpltCallback(hi2c);
7034 #else
7035 HAL_I2C_MasterRxCpltCallback(hi2c);
7036 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7037 }
7038 }
7039 }
7040 else
7041 {
7042 /* Do nothing */
7043 }
7044 }
7045
7046 /**
7047 * @brief DMA I2C communication error callback.
7048 * @param hdma DMA handle
7049 * @retval None
7050 */
I2C_DMAError(DMA_HandleTypeDef * hdma)7051 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
7052 {
7053 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
7054
7055 /* Clear Complete callback */
7056 if (hi2c->hdmatx != NULL)
7057 {
7058 hi2c->hdmatx->XferCpltCallback = NULL;
7059 }
7060 if (hi2c->hdmarx != NULL)
7061 {
7062 hi2c->hdmarx->XferCpltCallback = NULL;
7063 }
7064
7065 /* Ignore DMA FIFO error */
7066 if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
7067 {
7068 /* Disable Acknowledge */
7069 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
7070
7071 hi2c->XferCount = 0U;
7072
7073 hi2c->State = HAL_I2C_STATE_READY;
7074 hi2c->Mode = HAL_I2C_MODE_NONE;
7075
7076 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
7077
7078 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7079 hi2c->ErrorCallback(hi2c);
7080 #else
7081 HAL_I2C_ErrorCallback(hi2c);
7082 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7083 }
7084 }
7085
7086 /**
7087 * @brief DMA I2C communication abort callback
7088 * (To be called at end of DMA Abort procedure).
7089 * @param hdma DMA handle.
7090 * @retval None
7091 */
I2C_DMAAbort(DMA_HandleTypeDef * hdma)7092 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
7093 {
7094 __IO uint32_t count = 0U;
7095 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
7096
7097 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
7098 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
7099
7100 /* During abort treatment, check that there is no pending STOP request */
7101 /* Wait until STOP flag is reset */
7102 count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U);
7103 do
7104 {
7105 if (count == 0U)
7106 {
7107 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7108 break;
7109 }
7110 count--;
7111 }
7112 while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP);
7113
7114 /* Clear Complete callback */
7115 if (hi2c->hdmatx != NULL)
7116 {
7117 hi2c->hdmatx->XferCpltCallback = NULL;
7118 }
7119 if (hi2c->hdmarx != NULL)
7120 {
7121 hi2c->hdmarx->XferCpltCallback = NULL;
7122 }
7123
7124 /* Disable Acknowledge */
7125 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
7126
7127 hi2c->XferCount = 0U;
7128
7129 /* Reset XferAbortCallback */
7130 if (hi2c->hdmatx != NULL)
7131 {
7132 hi2c->hdmatx->XferAbortCallback = NULL;
7133 }
7134 if (hi2c->hdmarx != NULL)
7135 {
7136 hi2c->hdmarx->XferAbortCallback = NULL;
7137 }
7138
7139 /* Disable I2C peripheral to prevent dummy data in buffer */
7140 __HAL_I2C_DISABLE(hi2c);
7141
7142 /* Check if come from abort from user */
7143 if (hi2c->State == HAL_I2C_STATE_ABORT)
7144 {
7145 hi2c->State = HAL_I2C_STATE_READY;
7146 hi2c->Mode = HAL_I2C_MODE_NONE;
7147 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
7148
7149 /* Call the corresponding callback to inform upper layer of End of Transfer */
7150 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7151 hi2c->AbortCpltCallback(hi2c);
7152 #else
7153 HAL_I2C_AbortCpltCallback(hi2c);
7154 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7155 }
7156 else
7157 {
7158 if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
7159 {
7160 /* Renable I2C peripheral */
7161 __HAL_I2C_ENABLE(hi2c);
7162
7163 /* Enable Acknowledge */
7164 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
7165
7166 /* keep HAL_I2C_STATE_LISTEN */
7167 hi2c->PreviousState = I2C_STATE_NONE;
7168 hi2c->State = HAL_I2C_STATE_LISTEN;
7169 }
7170 else
7171 {
7172 hi2c->State = HAL_I2C_STATE_READY;
7173 hi2c->Mode = HAL_I2C_MODE_NONE;
7174 }
7175
7176 /* Call the corresponding callback to inform upper layer of End of Transfer */
7177 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7178 hi2c->ErrorCallback(hi2c);
7179 #else
7180 HAL_I2C_ErrorCallback(hi2c);
7181 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7182 }
7183 }
7184
7185 /**
7186 * @brief This function handles I2C Communication Timeout.
7187 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7188 * the configuration information for I2C module
7189 * @param Flag specifies the I2C flag to check.
7190 * @param Status The new Flag status (SET or RESET).
7191 * @param Timeout Timeout duration
7192 * @param Tickstart Tick start value
7193 * @retval HAL status
7194 */
I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,FlagStatus Status,uint32_t Timeout,uint32_t Tickstart)7195 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
7196 {
7197 /* Wait until flag is set */
7198 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
7199 {
7200 /* Check for the Timeout */
7201 if (Timeout != HAL_MAX_DELAY)
7202 {
7203 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7204 {
7205 hi2c->PreviousState = I2C_STATE_NONE;
7206 hi2c->State = HAL_I2C_STATE_READY;
7207 hi2c->Mode = HAL_I2C_MODE_NONE;
7208 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7209
7210 /* Process Unlocked */
7211 __HAL_UNLOCK(hi2c);
7212
7213 return HAL_ERROR;
7214 }
7215 }
7216 }
7217 return HAL_OK;
7218 }
7219
7220 /**
7221 * @brief This function handles I2C Communication Timeout for Master addressing phase.
7222 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7223 * the configuration information for I2C module
7224 * @param Flag specifies the I2C flag to check.
7225 * @param Timeout Timeout duration
7226 * @param Tickstart Tick start value
7227 * @retval HAL status
7228 */
I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,uint32_t Timeout,uint32_t Tickstart)7229 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
7230 {
7231 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
7232 {
7233 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
7234 {
7235 /* Generate Stop */
7236 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
7237
7238 /* Clear AF Flag */
7239 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7240
7241 hi2c->PreviousState = I2C_STATE_NONE;
7242 hi2c->State = HAL_I2C_STATE_READY;
7243 hi2c->Mode = HAL_I2C_MODE_NONE;
7244 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
7245
7246 /* Process Unlocked */
7247 __HAL_UNLOCK(hi2c);
7248
7249 return HAL_ERROR;
7250 }
7251
7252 /* Check for the Timeout */
7253 if (Timeout != HAL_MAX_DELAY)
7254 {
7255 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7256 {
7257 hi2c->PreviousState = I2C_STATE_NONE;
7258 hi2c->State = HAL_I2C_STATE_READY;
7259 hi2c->Mode = HAL_I2C_MODE_NONE;
7260 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7261
7262 /* Process Unlocked */
7263 __HAL_UNLOCK(hi2c);
7264
7265 return HAL_ERROR;
7266 }
7267 }
7268 }
7269 return HAL_OK;
7270 }
7271
7272 /**
7273 * @brief This function handles I2C Communication Timeout for specific usage of TXE flag.
7274 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7275 * the configuration information for the specified I2C.
7276 * @param Timeout Timeout duration
7277 * @param Tickstart Tick start value
7278 * @retval HAL status
7279 */
I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7280 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7281 {
7282 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
7283 {
7284 /* Check if a NACK is detected */
7285 if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
7286 {
7287 return HAL_ERROR;
7288 }
7289
7290 /* Check for the Timeout */
7291 if (Timeout != HAL_MAX_DELAY)
7292 {
7293 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7294 {
7295 hi2c->PreviousState = I2C_STATE_NONE;
7296 hi2c->State = HAL_I2C_STATE_READY;
7297 hi2c->Mode = HAL_I2C_MODE_NONE;
7298 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7299
7300 /* Process Unlocked */
7301 __HAL_UNLOCK(hi2c);
7302
7303 return HAL_ERROR;
7304 }
7305 }
7306 }
7307 return HAL_OK;
7308 }
7309
7310 /**
7311 * @brief This function handles I2C Communication Timeout for specific usage of BTF flag.
7312 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7313 * the configuration information for the specified I2C.
7314 * @param Timeout Timeout duration
7315 * @param Tickstart Tick start value
7316 * @retval HAL status
7317 */
I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7318 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7319 {
7320 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
7321 {
7322 /* Check if a NACK is detected */
7323 if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
7324 {
7325 return HAL_ERROR;
7326 }
7327
7328 /* Check for the Timeout */
7329 if (Timeout != HAL_MAX_DELAY)
7330 {
7331 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7332 {
7333 hi2c->PreviousState = I2C_STATE_NONE;
7334 hi2c->State = HAL_I2C_STATE_READY;
7335 hi2c->Mode = HAL_I2C_MODE_NONE;
7336 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7337
7338 /* Process Unlocked */
7339 __HAL_UNLOCK(hi2c);
7340
7341 return HAL_ERROR;
7342 }
7343 }
7344 }
7345 return HAL_OK;
7346 }
7347
7348 /**
7349 * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
7350 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7351 * the configuration information for the specified I2C.
7352 * @param Timeout Timeout duration
7353 * @param Tickstart Tick start value
7354 * @retval HAL status
7355 */
I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7356 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7357 {
7358 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
7359 {
7360 /* Check if a NACK is detected */
7361 if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
7362 {
7363 return HAL_ERROR;
7364 }
7365
7366 /* Check for the Timeout */
7367 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7368 {
7369 hi2c->PreviousState = I2C_STATE_NONE;
7370 hi2c->State = HAL_I2C_STATE_READY;
7371 hi2c->Mode = HAL_I2C_MODE_NONE;
7372 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7373
7374 /* Process Unlocked */
7375 __HAL_UNLOCK(hi2c);
7376
7377 return HAL_ERROR;
7378 }
7379 }
7380 return HAL_OK;
7381 }
7382
7383 /**
7384 * @brief This function handles I2C Communication Timeout for specific usage of STOP request through Interrupt.
7385 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7386 * the configuration information for the specified I2C.
7387 * @retval HAL status
7388 */
I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef * hi2c)7389 static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c)
7390 {
7391 __IO uint32_t count = 0U;
7392
7393 /* Wait until STOP flag is reset */
7394 count = I2C_TIMEOUT_STOP_FLAG * (SystemCoreClock / 25U / 1000U);
7395 do
7396 {
7397 count--;
7398 if (count == 0U)
7399 {
7400 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7401
7402 return HAL_ERROR;
7403 }
7404 }
7405 while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP);
7406
7407 return HAL_OK;
7408 }
7409
7410 /**
7411 * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
7412 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7413 * the configuration information for the specified I2C.
7414 * @param Timeout Timeout duration
7415 * @param Tickstart Tick start value
7416 * @retval HAL status
7417 */
I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7418 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7419 {
7420
7421 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
7422 {
7423 /* Check if a STOPF is detected */
7424 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
7425 {
7426 /* Clear STOP Flag */
7427 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
7428
7429 hi2c->PreviousState = I2C_STATE_NONE;
7430 hi2c->State = HAL_I2C_STATE_READY;
7431 hi2c->Mode = HAL_I2C_MODE_NONE;
7432 hi2c->ErrorCode |= HAL_I2C_ERROR_NONE;
7433
7434 /* Process Unlocked */
7435 __HAL_UNLOCK(hi2c);
7436
7437 return HAL_ERROR;
7438 }
7439
7440 /* Check for the Timeout */
7441 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7442 {
7443 hi2c->PreviousState = I2C_STATE_NONE;
7444 hi2c->State = HAL_I2C_STATE_READY;
7445 hi2c->Mode = HAL_I2C_MODE_NONE;
7446 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7447
7448 /* Process Unlocked */
7449 __HAL_UNLOCK(hi2c);
7450
7451 return HAL_ERROR;
7452 }
7453 }
7454 return HAL_OK;
7455 }
7456
7457 /**
7458 * @brief This function handles Acknowledge failed detection during an I2C Communication.
7459 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7460 * the configuration information for the specified I2C.
7461 * @retval HAL status
7462 */
I2C_IsAcknowledgeFailed(I2C_HandleTypeDef * hi2c)7463 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
7464 {
7465 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
7466 {
7467 /* Clear NACKF Flag */
7468 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7469
7470 hi2c->PreviousState = I2C_STATE_NONE;
7471 hi2c->State = HAL_I2C_STATE_READY;
7472 hi2c->Mode = HAL_I2C_MODE_NONE;
7473 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
7474
7475 /* Process Unlocked */
7476 __HAL_UNLOCK(hi2c);
7477
7478 return HAL_ERROR;
7479 }
7480 return HAL_OK;
7481 }
7482
7483 /**
7484 * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
7485 * @param hi2c I2C handle.
7486 * @retval None
7487 */
I2C_ConvertOtherXferOptions(I2C_HandleTypeDef * hi2c)7488 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
7489 {
7490 /* if user set XferOptions to I2C_OTHER_FRAME */
7491 /* it request implicitly to generate a restart condition */
7492 /* set XferOptions to I2C_FIRST_FRAME */
7493 if (hi2c->XferOptions == I2C_OTHER_FRAME)
7494 {
7495 hi2c->XferOptions = I2C_FIRST_FRAME;
7496 }
7497 /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
7498 /* it request implicitly to generate a restart condition */
7499 /* then generate a stop condition at the end of transfer */
7500 /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
7501 else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
7502 {
7503 hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
7504 }
7505 else
7506 {
7507 /* Nothing to do */
7508 }
7509 }
7510
7511 /**
7512 * @}
7513 */
7514
7515 #endif /* HAL_I2C_MODULE_ENABLED */
7516 /**
7517 * @}
7518 */
7519
7520 /**
7521 * @}
7522 */
7523
7524 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
7525