1 // Copyright (C) 2022 Beken Corporation 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #ifndef __ARCH_INTERRUPT_H__ 16 #define __ARCH_INTERRUPT_H__ 17 18 19 #include "mcu_ip.h" 20 #include "core_v5.h" 21 #include <common/bk_include.h> 22 #include <common/bk_err.h> 23 #include <driver/hal/hal_int_types.h> 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 #define USE_PLIC (1) 30 31 /* 32 * Define 'NDS_PLIC_BASE' and 'NDS_PLIC_SW_BASE' before include platform 33 * intrinsic header file to active PLIC/PLIC_SW related intrinsic functions. 34 */ 35 #define NDS_PLIC_BASE PLIC_BASE 36 #define NDS_PLIC_SW_BASE PLIC_SW_BASE 37 38 /* 39 * CPU Machine timer control 40 */ 41 #define HAL_MTIMER_INITIAL() 42 #define HAL_MTIME_ENABLE() set_csr(NDS_MIE, MIP_MTIP) 43 #define HAL_MTIME_DISABLE() clear_csr(NDS_MIE, MIP_MTIP); 44 45 /* 46 * CPU Machine SWI control 47 * 48 * Machine SWI (MSIP) is connected to PLIC_SW source 1. 49 */ 50 #define HAL_MSWI_INITIAL() \ 51 { \ 52 __nds__plic_sw_set_priority(1, 1); \ 53 __nds__plic_sw_enable_interrupt(1); \ 54 } 55 #define HAL_MSWI_ENABLE() set_csr(NDS_MIE, MIP_MSIP) 56 #define HAL_MSWI_DISABLE() clear_csr(NDS_MIE, MIP_MTIP) 57 #define HAL_MSWI_PENDING() __nds__plic_sw_set_pending(1) 58 #define HAL_MSWI_CLEAR() __nds__plic_sw_claim_interrupt() 59 60 /* 61 * Platform defined interrupt controller access 62 * 63 * This uses the vectored PLIC scheme. 64 */ 65 #define HAL_MEIP_ENABLE() set_csr(NDS_MIE, MIP_MEIP) 66 #define HAL_MEIP_DISABLE() clear_csr(NDS_MIE, MIP_MEIP) 67 #define HAL_INTERRUPT_ENABLE(vector) __nds__plic_enable_interrupt(vector) 68 #define HAL_INTERRUPT_DISABLE(vector) __nds__plic_disable_interrupt(vector) 69 #define HAL_INTERRUPT_THRESHOLD(threshold) __nds__plic_set_threshold(threshold) 70 #define HAL_INTERRUPT_SET_LEVEL(vector, level) __nds__plic_set_priority(vector, level) 71 72 /* 73 * Vectored based inline interrupt attach and detach control 74 */ 75 extern int __vectors[]; 76 extern void default_irq_entry(void); 77 78 #define HAL_INLINE_INTERRUPT_ATTACH(vector, isr) { __vectors[vector] = (int)isr; } 79 #define HAL_INLINE_INTERRUPT_DETACH(vector, isr) { if ( __vectors[vector] == (int)isr ) __vectors[vector] = (int)default_irq_entry; } 80 81 /* 82 * Inline nested interrupt entry/exit macros 83 */ 84 /* Save/Restore macro */ 85 #define SAVE_CSR(r) long __##r = read_csr(r); 86 #define RESTORE_CSR(r) write_csr(r, __##r); 87 88 #if SUPPORT_PFT_ARCH 89 #define SAVE_MXSTATUS() SAVE_CSR(NDS_MXSTATUS) 90 #define RESTORE_MXSTATUS() RESTORE_CSR(NDS_MXSTATUS) 91 #else 92 #define SAVE_MXSTATUS() 93 #define RESTORE_MXSTATUS() 94 #endif 95 96 #ifdef __riscv_flen 97 #define SAVE_FCSR() int __fcsr = read_fcsr(); 98 #define RESTORE_FCSR() write_fcsr(__fcsr); 99 #else 100 #define SAVE_FCSR() 101 #define RESTORE_FCSR() 102 #endif 103 104 #ifdef __riscv_dsp 105 #define SAVE_UCODE() SAVE_CSR(NDS_UCODE) 106 #define RESTORE_UCODE() RESTORE_CSR(NDS_UCODE) 107 #else 108 #define SAVE_UCODE() 109 #define RESTORE_UCODE() 110 #endif 111 112 /* Nested IRQ entry macro : Save CSRs and enable global interrupt. */ 113 #define NESTED_IRQ_ENTER() \ 114 SAVE_CSR(NDS_MEPC) \ 115 SAVE_CSR(NDS_MSTATUS) \ 116 SAVE_MXSTATUS() \ 117 SAVE_FCSR() \ 118 SAVE_UCODE() \ 119 set_csr(NDS_MSTATUS, MSTATUS_MIE); 120 121 /* Nested IRQ exit macro : Restore CSRs */ 122 #define NESTED_IRQ_EXIT() \ 123 clear_csr(NDS_MSTATUS, MSTATUS_MIE); \ 124 RESTORE_CSR(NDS_MSTATUS) \ 125 RESTORE_CSR(NDS_MEPC) \ 126 RESTORE_MXSTATUS() \ 127 RESTORE_FCSR() \ 128 RESTORE_UCODE() 129 130 131 /*Define INT ID */ 132 typedef enum { 133 INT_ID_NULL0_INT = 0, 134 INT_ID_EIP130_0_IRQ , 135 INT_ID_EIP130_0_SEC_IRQ , 136 INT_ID_TIMER , 137 INT_ID_UART0 , 138 INT_ID_PWM , 139 INT_ID_I2C , 140 INT_ID_SPI , 141 INT_ID_SADC , 142 INT_ID_IRDA , 143 INT_ID_SDIO , 144 INT_ID_GDMA , 145 INT_ID_LA , 146 INT_ID_TIMER1 , 147 INT_ID_I2C1 , 148 INT_ID_UART1 , 149 INT_ID_UART2 , 150 INT_ID_SPI1 , 151 INT_ID_CAN , 152 INT_ID_USB , 153 INT_ID_QSPI , 154 INT_ID_FFT , 155 INT_ID_SBC , 156 INT_ID_AUD , 157 INT_ID_I2S , 158 INT_ID_JPEGENC , 159 INT_ID_JPEGDEC , 160 INT_ID_LCD , 161 INT_ID_NULL1_INT , 162 INT_ID_INT_PHY , 163 INT_ID_MAC_TX_RX_TIMER_N , 164 INT_ID_MAC_TX_RX_MISC_N , 165 INT_ID_MAC_RX_TRIGGER_N , 166 INT_ID_MAC_TX_TRIGGER_N , 167 INT_ID_MAC_PORT_TRIGGER_N , 168 INT_ID_MAC_GEN_N , 169 INT_ID_HSU_IRQ , 170 INT_ID_INT_MAC_WAKEUP , 171 INT_ID_NULL2_INT , 172 INT_ID_DM , 173 INT_ID_BLE , 174 INT_ID_BT , 175 INT_ID_NULL3_INT , 176 INT_ID_NULL4_INT , 177 INT_ID_NULL5_INT , 178 INT_ID_NULL6_INT , 179 INT_ID_NULL7_INT , 180 INT_ID_NULL8_INT , 181 INT_ID_MBOX0 , 182 INT_ID_MBOX1 , 183 INT_ID_BMC64 , 184 INT_ID_NULL9_INT , 185 INT_ID_TOUCHED , 186 INT_ID_USBPLUG , 187 INT_ID_RTC , 188 INT_ID_GPIO , 189 INT_ID_MAX 190 } arch_int_src_t; 191 192 193 typedef void (*interrupt_handle_p)(); 194 195 196 bk_err_t arch_isr_entry_init(void); 197 void arch_interrupt_set_priority(arch_int_src_t int_number, uint32_t int_priority); 198 void arch_interrupt_register_int(arch_int_src_t int_number, int_group_isr_t isr_callback); 199 void arch_interrupt_unregister_int(arch_int_src_t int_number); 200 unsigned int arch_get_interrupt_nest_cnt(void); 201 unsigned int arch_is_enter_exception(void); 202 void mext_interrupt(void); 203 bool mtimer_is_timeout(); 204 uint64_t arch_get_plic_pending_status(void); 205 206 #endif /* __ARCH_INTERRUPT_H__ */ 207 208