1 /* 2 * Copyright (c) 2022 Unionman Technology Co., Ltd. 3 * 4 * HDF is dual licensed: you can use it either under the terms of 5 * the GPL, or the BSD license, at your option. 6 * See the LICENSE file in the root of this repository for complete details. 7 */ 8 9 #ifndef MESON_AXG_FIFO_H 10 #define MESON_AXG_FIFO_H 11 12 #include <linux/regmap.h> 13 14 #ifdef __cplusplus 15 #if __cplusplus 16 extern "C" { 17 #endif 18 #endif /* __cplusplus */ 19 20 struct clk; 21 struct platform_device; 22 struct reg_field; 23 struct regmap; 24 struct regmap_field; 25 struct reset_control; 26 27 #define AXG_FIFO_CH_MAX 128 28 #define AXG_FIFO_RATES (SNDRV_PCM_RATE_5512 | \ 29 SNDRV_PCM_RATE_8000_192000) 30 #define AXG_FIFO_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 31 SNDRV_PCM_FMTBIT_S16_LE | \ 32 SNDRV_PCM_FMTBIT_S20_LE | \ 33 SNDRV_PCM_FMTBIT_S24_LE | \ 34 SNDRV_PCM_FMTBIT_S32_LE | \ 35 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE) 36 37 #define AXG_FIFO_BURST 8 38 39 #define FIFO_INT_ADDR_FINISH BIT(0) 40 #define FIFO_INT_ADDR_INT BIT(1) 41 #define FIFO_INT_COUNT_REPEAT BIT(2) 42 #define FIFO_INT_COUNT_ONCE BIT(3) 43 #define FIFO_INT_FIFO_ZERO BIT(4) 44 #define FIFO_INT_FIFO_DEPTH BIT(5) 45 #define FIFO_INT_MASK GENMASK(7, 0) 46 47 #define FIFO_CTRL0 0x00 48 #define CTRL0_DMA_EN BIT(31) 49 #define CTRL0_INT_EN(x) ((x) << 16) 50 #define CTRL0_SEL_MASK GENMASK(2, 0) 51 #define CTRL0_SEL_SHIFT 0 52 #define FIFO_CTRL1 0x04 53 #define CTRL1_INT_CLR(x) ((x) << 0) 54 #define CTRL1_STATUS2_SEL_MASK GENMASK(11, 8) 55 #define CTRL1_STATUS2_SEL(x) ((x) << 8) 56 #define STATUS2_SEL_DDR_READ 0 57 #define CTRL1_FRDDR_DEPTH_MASK GENMASK(31, 24) 58 #define CTRL1_FRDDR_DEPTH(x) ((x) << 24) 59 #define FIFO_START_ADDR 0x08 60 #define FIFO_FINISH_ADDR 0x0c 61 #define FIFO_INT_ADDR 0x10 62 #define FIFO_STATUS1 0x14 63 #define STATUS1_INT_STS(x) ((x) << 0) 64 #define FIFO_STATUS2 0x18 65 #define FIFO_INIT_ADDR 0x24 66 #define FIFO_CTRL2 0x28 67 68 struct axg_fifo { 69 const char *name_prefix; /* such as FRDDR_B, TODDR_B */ 70 struct device *dev; 71 struct regmap *map; 72 struct clk *pclk; 73 struct reset_control *arb; 74 struct regmap_field *field_threshold; 75 unsigned int depth; 76 int irq; 77 dma_addr_t dma_addr; /* physical bus address (no cached) */ 78 unsigned char *dma_vaddr; /* virtual pointer */ 79 size_t dma_area; /* size of DMA area */ 80 size_t dma_cir_size; /* size of DMA circle buffer */ 81 int is_frddr; /* 1 for from-ddr, 0 for to-ddr */ 82 int is_g12a; /* 1 for g12a, 0 for axg */ 83 bool pcm_opened; 84 bool dai_startup; 85 86 struct list_head list; 87 }; 88 89 struct axg_fifo_match_data { 90 struct reg_field field_threshold; 91 int is_frddr; /* 1 for from-ddr, 0 for to-ddr */ 92 int is_g12a; /* 1 for g12a, 0 for axg */ 93 }; 94 95 int meson_axg_fifo_probe(struct platform_device *pdev); 96 97 // name_prefix: such as FRDDR_B, TODDR_B... 98 struct axg_fifo *meson_axg_fifo_get(const char *name_prefix); 99 100 int meson_axg_fifo_update_bits(struct axg_fifo *fifo, 101 unsigned int reg, unsigned int mask, unsigned int val); 102 103 int meson_axg_fifo_pcm_open(struct axg_fifo *fifo); 104 105 int meson_axg_fifo_pcm_close(struct axg_fifo *fifo); 106 107 int meson_axg_fifo_dai_hw_params(struct axg_fifo *fifo, 108 unsigned int bit_width, unsigned int phys_width); 109 110 int meson_axg_fifo_pcm_hw_params(struct axg_fifo *fifo, 111 unsigned int period, unsigned int cir_buf_size); 112 113 int meson_axg_fifo_pcm_hw_free(struct axg_fifo *fifo); 114 115 int meson_axg_fifo_pcm_prepare(struct axg_fifo *fifo); 116 117 uint32_t meson_axg_fifo_pcm_pointer(struct axg_fifo *fifo); 118 119 int meson_axg_fifo_pcm_enable(struct axg_fifo *fifo, bool enable); 120 121 #ifdef __cplusplus 122 #if __cplusplus 123 } 124 #endif 125 #endif /* __cplusplus */ 126 127 #endif /* MESON_AXG_FIFO_H */ 128