1 // Copyright (C) 2022 Beken Corporation 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 #define ICU_FAILURE (1) 22 #define ICU_SUCCESS (0) 23 24 #define ICU_DEV_NAME "icu" 25 26 #define ICU_CMD_MAGIC (0xe220000) 27 enum 28 { 29 CMD_ICU_CLKGATING_DISABLE = ICU_CMD_MAGIC + 1, 30 CMD_ICU_CLKGATING_ENABLE, 31 CMD_ICU_INT_DISABLE, 32 CMD_ICU_INT_ENABLE, 33 CMD_ICU_FIQ_DISABLE, 34 CMD_ICU_FIQ_ENABLE, 35 CMD_ICU_GLOBAL_INT_DISABLE, 36 CMD_ICU_GLOBAL_INT_ENABLE, 37 CMD_GET_INTR_STATUS, 38 CMD_CLR_INTR_STATUS, 39 CMD_GET_FIQ_REG_STATUS, 40 CMD_CLR_FIQ_REG_STATUS, 41 CMD_GET_INTR_RAW_STATUS, 42 CMD_CLR_INTR_RAW_STATUS, 43 CMD_CLK_PWR_DOWN, 44 CMD_CLK_PWR_UP, 45 CMD_FUNC_CLK_PWR_DOWN, 46 CMD_FUNC_CLK_PWR_UP, 47 CMD_CONF_PWM_PCLK, 48 CMD_CONF_PWM_LPOCLK, 49 CMD_TL410_CLK_PWR_DOWN, 50 CMD_TL410_CLK_PWR_UP, 51 CMD_CONF_PCLK_26M, 52 CMD_CONF_PCLK_DCO, 53 CMD_SET_JTAG_MODE, 54 CMD_GET_JTAG_MODE, 55 CMD_ARM_WAKEUP_DISABLE, 56 CMD_ARM_WAKEUP_ENABLE, 57 CMD_GET_ARM_WAKEUP, 58 CMD_QSPI_CLK_SEL 59 }; 60 61 /*CMD_CONF_PCLK*/ 62 #define PCLK_POSI (0) 63 #if (CONFIG_SOC_BK7271) 64 #define PCLK_POSI_UART1 (1 << 0) 65 #define PCLK_POSI_UART2 (1 << 1) 66 #define PCLK_POSI_UART3 (1 << 2) 67 #define PCLK_POSI_IRDA (1 << 3) 68 #define PCLK_POSI_FM_I2C (1 << 4) 69 #define PCLK_POSI_I2C1 (1 << 5) 70 #define PCLK_POSI_I2C2 (1 << 6) 71 #define PCLK_POSI_SPI1 (1 << 7) 72 #define PCLK_POSI_SPI2 (1 << 8) 73 #define PCLK_POSI_SPI3 (1 << 9) 74 #define PCLK_POSI_PWMS (1 << 10) 75 #define PCLK_POSI_SDIO (1 << 11) 76 #define PCLK_POSI_EFUSE (1 << 12) 77 #define PCLK_POSI_CEC (1 << 13) 78 #else 79 #define PCLK_POSI_UART1 (1 << 0) 80 #define PCLK_POSI_UART2 (1 << 1) 81 #define PCLK_POSI_I2C1 (1 << 2) 82 #define PCLK_POSI_IRDA (1 << 3) 83 #define PCLK_POSI_I2C2 (1 << 4) 84 #define PCLK_POSI_SARADC (1 << 5) 85 #define PCLK_POSI_SPI (1 << 6) 86 #define PCLK_POSI_PWMS (1 << 7) 87 #define PCLK_POSI_SDIO (1 << 8) 88 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX) || (CONFIG_SOC_BK7236) 89 #define PCLK_POSI_EFUSE (1 << 9) 90 #else 91 #define PCLK_POSI_SARADC_AUD (1 << 9) 92 #endif 93 #endif 94 95 #define PCLK_POSI_QSPI_DCO (0 << 16) 96 #define PCLK_POSI_QSPI_26M (1 << 16) 97 #define PCLK_POSI_QSPI_120M (2 << 16) 98 99 /*CMD_CONF_PWM_PCLK, CMD_CONF_PWM_LPOCLK*/ 100 #define PWM_MUX_POSI (0) 101 #define PWM_MUX_LPO (1) 102 #define PWM_MUX_PCLK (0) 103 // *param = channel_id 104 105 /*CMD_CLK_PWR_DOWN CMD_CLK_PWR_UP*/ 106 #define PWD_QSPI_CLK_BIT (1 << 23) 107 108 #if (CONFIG_SOC_BK7271) 109 #define PWD_CEC_CLK_BIT (1 << 19) 110 #define PWD_SARADC_CLK_BIT (1 << 18) 111 #define PWD_PWM3_CLK_BIT (1 << 17) 112 #define PWD_PWM2_CLK_BIT (1 << 16) 113 #define PWD_PWM1_CLK_BIT (1 << 15) 114 #define PWD_PWM0_CLK_BIT (1 << 14) 115 #define PWD_TIMER_32K_CLK_BIT (1 << 13) 116 #define PWD_TIMER_26M_CLK_BIT (1 << 12) 117 #define PWD_IRDA_CLK_BIT (1 << 11) 118 #define PWD_SPI3_CLK_BIT (1 << 10) 119 #define PWD_SPI2_CLK_BIT (1 << 9) 120 #define PWD_SPI1_CLK_BIT (1 << 8) 121 #define PWD_SDIO_CLK_BIT (1 << 6) 122 #define PWD_I2C2_CLK_BIT (1 << 5) 123 #define PWD_I2C1_CLK_BIT (1 << 4) 124 #define PWD_FM_I2C_CLK_BIT (1 << 3) 125 #define PWD_UART3_CLK_BIT (1 << 2) 126 #define PWD_UART2_CLK_BIT (1 << 1) 127 #define PWD_UART1_CLK_BIT (1 << 0) 128 129 #define PWD_JEPG_CLK_BIT (1 << 3) 130 #define PWD_ARM_WATCHDOG_CLK_BIT (1 << 0) 131 #else 132 #define PWD_JEPG_CLK_BIT (1 << 22) 133 #if (!CONFIG_SOC_BK7231) 134 #define PWD_TIMER_32K_CLK_BIT (1 << 21) 135 #define PWD_TIMER_26M_CLK_BIT (1 << 20) 136 #endif 137 138 #define PWD_QSPI_CLK_BIT (1 << 23) 139 #define PWD_FFT_CLK_BIT (1 << 19) 140 #define PWD_USB_CLK_BIT (1 << 18) 141 #define PWD_SDIO_CLK_BIT (1 << 17) 142 #define PWD_TL410_WATCHDOG_BIT (1 << 16) 143 #define PWD_AUDIO_CLK_BIT (1 << 15) 144 #define PWD_PWM5_CLK_BIT (1 << 14) 145 #define PWD_PWM4_CLK_BIT (1 << 13) 146 #define PWD_PWM3_CLK_BIT (1 << 12) 147 #define PWD_PWM2_CLK_BIT (1 << 11) 148 #define PWD_PWM1_CLK_BIT (1 << 10) 149 #define PWD_PWM0_CLK_BIT (1 << 9) 150 #define PWD_ARM_WATCHDOG_CLK_BIT (1 << 8) 151 #define PWD_SARADC_CLK_BIT (1 << 7) 152 #define PWD_SPI_CLK_BIT (1 << 6) 153 #define PWD_I2C2_CLK_BIT (1 << 5) 154 #define PWD_I2S_PCM_CLK_BIT (1 << 4) 155 #define PWD_IRDA_CLK_BIT (1 << 3) 156 #define PWD_I2C1_CLK_BIT (1 << 2) 157 #define PWD_UART2_CLK_BIT (1 << 1) 158 #define PWD_UART1_CLK_BIT (1 << 0) 159 #endif 160 161 /* CMD_ICU_CLKGATING_DISABLE CMD_ICU_CLKGATING_ENABLE*/ 162 #define CLKGATE_MAC_AHB_BIT (1 << 16) 163 #define CLKGATE_FFT_AHB_BIT (1 << 15) 164 #define CLKGATE_USB_AHB_BIT (1 << 14) 165 #define CLKGATE_SDIO_AHB_BIT (1 << 13) 166 #define CLKGATE_SARADC_APB_BIT (1 << 12) 167 #define CLKGATE_AUDIO_APB_BIT (1 << 11) 168 #define CLKGATE_PWM_APB_BIT (1 << 10) 169 #define CLKGATE_WATCHDOG_APB_BIT (1 << 9) 170 #define CLKGATE_GPIO_APB_BIT (1 << 8) 171 #define CLKGATE_SPI_APB_BIT (1 << 7) 172 #define CLKGATE_I2C2_APB_BIT (1 << 6) 173 #define CLKGATE_I2S_PCM_APB_BIT (1 << 5) 174 #define CLKGATE_IRDA_APB_BIT (1 << 4) 175 #define CLKGATE_I2C1_APB_BIT (1 << 3) 176 #define CLKGATE_UART2_APB_BIT (1 << 2) 177 #define CLKGATE_UART1_APB_BIT (1 << 1) 178 #define CLKGATE_ICU_APB_BIT (1 << 0) 179 180 /* CMD ICU_TL410_CLK_PWD*/ 181 #define PWD_TL410_CLK_BIT (1 << 0) 182 #define PWD_BLE_CLK_BIT (1 << 1) 183 184 /* ICU_R_JTAG_SELECT */ 185 #define JTAG_ARM_MODE 0 186 #if (CONFIG_SOC_BK7271) 187 #define JTAG_BT_MODE 1 188 #define JTAG_TL410_MODE 2 189 #else 190 #define JTAG_TL410_MODE 1 191 #endif 192 193 #if (CONFIG_SOC_BK7271) 194 #define FIQ_MAC_WAKEUP_BIT (1 << 31) /* IRQ actually, compatible with legacy name */ 195 #define FIQ_MAC_GENERAL_BIT (1 << 30) 196 #define FIQ_MAC_PROT_TRIGGER_BIT (1 << 29) 197 #define FIQ_MAC_TX_TRIGGER_BIT (1 << 28) 198 #define FIQ_MAC_RX_TRIGGER_BIT (1 << 27) 199 #define FIQ_MAC_TX_RX_MISC_BIT (1 << 26) 200 #define FIQ_MAC_TX_RX_TIMER_BIT (1 << 25) 201 #define FIQ_MODEM_BIT (1 << 24) 202 #define FIQ_SECURITY_BIT (1 << 23) /* IRQ actually, compatible with legacy name */ 203 #define IRQ_MAILBOX2_BIT (1 << 22) 204 #define IRQ_MAILBOX1_BIT (1 << 21) 205 #define IRQ_GDMA_BIT (1 << 20) 206 #define FIQ_SDIO_DMA_BIT (1 << 19) /* IRQ actually, compatible with legacy name */ 207 #define IRQ_USB2_BIT (1 << 18) 208 #define IRQ_QSPI_BIT (1 << 17) 209 #define IRQ_SARADC_BIT (1 << 16) 210 #define IRQ_PWM2_BIT (1 << 15) 211 #define IRQ_PWM_BIT (1 << 14) 212 #define IRQ_TIMER_BIT (1 << 13) 213 #define IRQ_IRDA_BIT (1 << 12) 214 #define IRQ_GPIO_BIT (1 << 11) 215 #define IRQ_SPI3_BIT (1 << 10) 216 #define IRQ_SPI2_BIT (1 << 9) 217 #define IRQ_SPI1_BIT (1 << 8) 218 #define IRQ_USB1_BIT (1 << 7) 219 #define IRQ_SDIO_BIT (1 << 6) 220 #define IRQ_I2C2_BIT (1 << 5) 221 #define IRQ_I2C1_BIT (1 << 4) 222 #define IRQ_FM_I2C_BIT (1 << 3) 223 #define IRQ_UART3_BIT (1 << 2) 224 #define IRQ_UART2_BIT (1 << 1) 225 #define IRQ_UART1_BIT (1 << 0) 226 227 #define FIQ_JPEG_DECODER_BIT (1 << 7) 228 #define FIQ_CEC_BIT (1 << 6) 229 #define FIQ_TOUCH_BIT (1 << 5) 230 #define FIQ_RTC_BIT (1 << 4) 231 #define FIQ_DSP_WATCHDOG_BIT (1 << 3) 232 #define FIQ_BT_WATCHDOG_BIT (1 << 2) 233 #define FIQ_USB_PLUG_INOUT_BIT (1 << 1) 234 #define FIQ_DPLL_UNLOCK_BIT (1 << 0) 235 #else 236 /*CMD_ICU_INT_DISABLE CMD_ICU_INT_ENABLE*/ 237 #if (!CONFIG_SOC_BK7236A) && (!CONFIG_SOC_BK7236) 238 #define FIQ_JPEG_DECODER_BIT (1 << 29) 239 #endif 240 #define FIQ_DPLL_UNLOCK_BIT (1 << 28) 241 #define FIQ_SPI_DMA_BIT (1 << 27) 242 #define FIQ_MAC_WAKEUP_BIT (1 << 26) 243 #if (CONFIG_SOC_BK7251) 244 #define FIQ_SECURITY_BIT (1 << 25) 245 #define FIQ_USB_PLUG_INOUT_BIT (1 << 24) 246 #else 247 #define FIQ_MAILBOX1_BIT (1 << 25) 248 #define FIQ_MAILBOX0_BIT (1 << 24) 249 #endif // (CONFIG_SOC_BK7251) 250 #define FIQ_PSRAM_BIT (1 << 31) 251 #define FIQ_SDIO_DMA_BIT (1 << 23) 252 #define FIQ_MAC_GENERAL_BIT (1 << 22) 253 #define FIQ_MAC_PROT_TRIGGER_BIT (1 << 21) 254 #define FIQ_MAC_TX_TRIGGER_BIT (1 << 20) 255 #define FIQ_MAC_RX_TRIGGER_BIT (1 << 19) 256 #define FIQ_MAC_TX_RX_MISC_BIT (1 << 18) 257 #define FIQ_MAC_TX_RX_TIMER_BIT (1 << 17) 258 #define FIQ_MODEM_BIT (1 << 16) 259 #define IRQ_GDMA_BIT (1 << 15) 260 #define IRQ_FFT_BIT (1 << 14) 261 #define IRQ_USB_BIT (1 << 13) 262 #define IRQ_SDIO_BIT (1 << 12) 263 #define IRQ_SARADC_BIT (1 << 11) 264 #if (!CONFIG_SOC_BK7236A) && (!CONFIG_SOC_BK7236) 265 #define IRQ_AUDIO_BIT (1 << 10) 266 #else 267 #define IRQ_JPEG_DECODER_BIT (1 << 10) 268 #endif 269 #define IRQ_PWM_BIT (1 << 9) 270 #define IRQ_TL410_WATCHDOG_BIT (1 << 8) 271 #define IRQ_GPIO_BIT (1 << 7) 272 #define IRQ_SPI_BIT (1 << 6) 273 #define IRQ_I2C2_BIT (1 << 5) 274 #define IRQ_I2S_PCM_BIT (1 << 4) 275 #define IRQ_IRDA_BIT (1 << 3) 276 #define IRQ_I2C1_BIT (1 << 2) 277 #define IRQ_UART2_BIT (1 << 1) 278 #define IRQ_UART1_BIT (1 << 0) 279 #endif 280 281 /* CMD_ICU_GLOBAL_INT_DISABLE CMD_ICU_GLOBAL_INT_ENABLE*/ 282 #define GINTR_FIQ_BIT (1 << 1) 283 #define GINTR_IRQ_BIT (1 << 0) 284 285 /* CMD_ARM_WAKEUP */ 286 #if (CONFIG_SOC_BK7231) 287 #define TL410_WATCHDOG_ARM_WAKEUP_EN_BIT (1 << 8) 288 #elif (CONFIG_SOC_BK7271) 289 #define TIMER_ARM_WAKEUP_EN_BIT (1 << 13) 290 #else 291 #define TIMER_ARM_WAKEUP_EN_BIT (1 << 8) 292 #endif 293 #define BLE_ARM_WAKEUP_EN_BIT (1 << 30) 294 295 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX) || (CONFIG_SOC_BK7236) 296 #define BTDM_ARM_WAKEUP_EN_BIT (1 << 29) 297 #endif 298 299 #if (CONFIG_SOC_BK7271) 300 #define MAC_ARM_WAKEUP_EN_BIT (1 << 31) 301 #define GPIO_ARM_WAKEUP_EN_BIT (1 << 11) 302 #else 303 #define MAC_ARM_WAKEUP_EN_BIT (1 << 26) 304 #define GPIO_ARM_WAKEUP_EN_BIT (1 << 7) 305 #endif 306 307 #define AUDIO_ARM_WAKEUP_EN_BIT (1 << 10) 308 #define PWM_ARM_WAKEUP_EN_BIT (1 << 9) 309 #define UART2_ARM_WAKEUP_EN_BIT (1 << 1) 310 #define UART1_ARM_WAKEUP_EN_BIT (1 << 0) 311 312 /******************************************************************************* 313 * Function Declarations 314 *******************************************************************************/ 315 void icu_init(void); 316 void icu_exit(void); 317 UINT32 icu_ctrl(UINT32 cmd, void *param); 318 319 320 /**< wdt related APIs */ 321 void icu_pwr_up_wdt(void); 322 void icu_pwr_down_wdt(void); 323 324 #ifdef __cplusplus 325 } 326 #endif 327