1 // Copyright (C) 2022 Beken Corporation 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 #include <common/bk_typedef.h> 22 23 #if (CONFIG_SOC_BK7271) 24 #include "pmu.h" 25 #endif 26 27 #define SCTRL_DEV_NAME "sys_ctrl" 28 29 #define SCTRL_FAILURE ((UINT32)-1) 30 #define SCTRL_SUCCESS (0) 31 32 #define SCTRL_CMD_MAGIC (0xC123000) 33 enum 34 { 35 CMD_GET_CHIP_ID = SCTRL_CMD_MAGIC + 1, 36 CMD_GET_DEVICE_ID = SCTRL_CMD_MAGIC + 2, 37 CMD_GET_SCTRL_CONTROL, 38 CMD_SET_SCTRL_CONTROL, 39 40 CMD_SCTRL_MCLK_SELECT, 41 CMD_SCTRL_MCLK_DIVISION, 42 CMD_SCTRL_MCLK_MUX_GET, 43 CMD_SCTRL_MCLK_DIV_GET, 44 45 CMD_SCTRL_RESET_SET, 46 CMD_SCTRL_RESET_CLR, 47 CMD_SCTRL_MODEM_CORE_RESET, 48 CMD_SCTRL_MPIF_CLK_INVERT, 49 CMD_SCTRL_MODEM_SUBCHIP_RESET, 50 CMD_SCTRL_MAC_SUBSYS_RESET, 51 CMD_SCTRL_USB_SUBSYS_RESET, 52 CMD_SCTRL_DSP_SUBSYS_RESET, 53 CMD_SCTRL_BLK_ENABLE, 54 CMD_SCTRL_BLK_DISABLE, 55 56 CMD_SCTRL_DSP_POWERDOWN, 57 CMD_SCTRL_DSP_POWERUP, 58 CMD_SCTRL_USB_POWERDOWN, 59 CMD_SCTRL_USB_POWERUP, 60 CMD_SCTRL_MAC_POWERDOWN, 61 CMD_SCTRL_MAC_POWERUP, 62 CMD_SCTRL_MODEM_POWERDOWN, 63 CMD_SCTRL_MODEM_POWERUP, 64 CMD_SCTRL_BLE_POWERDOWN, 65 CMD_SCTRL_BLE_POWERUP, 66 67 #if (CONFIG_SOC_BK7271) 68 CMD_SCTRL_LBUS_POWERDOWN, 69 CMD_SCTRL_LBUS_POWERUP, 70 CMD_SCTRL_BT_POWERDOWN, 71 CMD_SCTRL_BT_POWERUP, 72 #endif 73 74 CMD_SCTRL_CALI_DPLL, 75 76 CMD_SCTRL_BIAS_REG_SET, 77 CMD_SCTRL_BIAS_REG_CLEAN, 78 CMD_SCTRL_BIAS_REG_READ, 79 CMD_SCTRL_BIAS_REG_WRITE, 80 CMD_SCTRL_BIAS_GET_CALI_OUT, 81 82 CMD_SCTRL_ANALOG_CTRL4_SET, 83 CMD_SCTRL_ANALOG_CTRL4_CLEAN, 84 #if (CONFIG_SOC_BK7271) 85 CMD_SCTRL_ANALOG_CTRL9_REAL_SET, 86 CMD_SCTRL_ANALOG_CTRL9_REAL_CLEAN, 87 #endif 88 89 CMD_SCTRL_SET_FLASH_DCO, 90 CMD_SCTRL_SET_FLASH_DPLL, 91 CMD_SCTRL_NORMAL_SLEEP, 92 CMD_SCTRL_NORMAL_WAKEUP, 93 CMD_SCTRL_RTOS_IDLE_SLEEP, 94 CMD_SCTRL_RTOS_IDLE_WAKEUP, 95 CMD_SCTRL_RTOS_DEEP_SLEEP, 96 97 #if (!CONFIG_SOC_BK7231) 98 CMD_SCTRL_SET_XTALH_CTUNE, 99 CMD_SCTRL_GET_XTALH_CTUNE, 100 CMD_BLE_RF_BIT_SET, 101 CMD_BLE_RF_BIT_CLR, 102 CMD_BLE_RF_BIT_GET, 103 104 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX) 105 CMD_BLE_RF_PTA_EN, 106 CMD_BLE_RF_PTA_DIS, 107 #endif 108 109 CMD_EFUSE_WRITE_BYTE, 110 CMD_EFUSE_READ_BYTE, 111 CMD_GET_SCTRL_RETETION, 112 CMD_SET_SCTRL_RETETION, 113 #endif // (!CONFIG_SOC_BK7231) 114 115 #if (!CONFIG_SOC_BK7231) && (!CONFIG_SOC_BK7231N) && (!CONFIG_SOC_BK7236A) && (!CONFIG_SOC_BK7256XX) 116 CMD_QSPI_VDDRAM_VOLTAGE, 117 CMD_QSPI_IO_VOLTAGE, 118 #endif // (!CONFIG_SOC_BK7231) 119 120 CMD_SCTRL_SET_ANALOG0, 121 CMD_SCTRL_SET_ANALOG1, 122 CMD_SCTRL_SET_ANALOG2, 123 CMD_SCTRL_SET_ANALOG3, 124 CMD_SCTRL_SET_ANALOG4, 125 CMD_SCTRL_SET_ANALOG5, 126 CMD_SCTRL_SET_ANALOG6, 127 CMD_SCTRL_SET_ANALOG7, 128 CMD_SCTRL_SET_ANALOG8, 129 CMD_SCTRL_SET_ANALOG9, 130 CMD_SCTRL_SET_ANALOG10, 131 CMD_SCTRL_GET_ANALOG0, 132 CMD_SCTRL_GET_ANALOG1, 133 CMD_SCTRL_GET_ANALOG2, 134 CMD_SCTRL_GET_ANALOG3, 135 CMD_SCTRL_GET_ANALOG4, 136 CMD_SCTRL_GET_ANALOG5, 137 CMD_SCTRL_GET_ANALOG6, 138 CMD_SCTRL_GET_ANALOG7, 139 CMD_SCTRL_GET_ANALOG8, 140 CMD_SCTRL_GET_ANALOG9, 141 CMD_SCTRL_GET_ANALOG10, 142 143 #if (CONFIG_SOC_BK7251) || (CONFIG_SOC_BK7271) 144 CMD_SCTRL_OPEN_DAC_ANALOG, 145 CMD_SCTRL_CLOSE_DAC_ANALOG, 146 CMD_SCTRL_OPEN_ADC_MIC_ANALOG, 147 CMD_SCTRL_CLOSE_ADC_MIC_ANALOG, 148 CMD_SCTRL_ENALBLE_ADC_LINE_IN, 149 CMD_SCTRL_DISALBLE_ADC_LINE_IN, 150 CMD_SCTRL_SET_DAC_VOLUME_ANALOG, 151 CMD_SCTRL_SET_LINEIN_VOLUME_ANALOG, 152 CMD_SCTRL_SET_VOLUME_PORT, 153 CMD_SCTRL_SET_AUD_DAC_MUTE, 154 CMD_SCTRL_AUDIO_PLL, 155 CMD_SCTRL_USB_CHARGE_CAL, 156 CMD_SCTRL_USB_CHARGE_START, 157 CMD_SCTRL_USB_CHARGE_STOP, 158 159 CMD_SCTRL_UNCONDITIONAL_MAC_DOWN, 160 CMD_SCTRL_UNCONDITIONAL_MAC_UP, 161 162 #endif // (CONFIG_SOC_BK7251) || (CONFIG_SOC_BK7271) 163 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7256XX) 164 CMD_SCTRL_FIX_DPLL_DIV, 165 #endif 166 167 CMD_SCTRL_MODEM_AHB_CLOCK_DISABLE, 168 CMD_SCTRL_MODEM_AHB_CLOCK_ENABLE, 169 CMD_SCTRL_MODEM_CLOCK480M_DISABLE, 170 CMD_SCTRL_MODEM_CLOCK480M_ENABLE, 171 CMD_SCTRL_MAC_AHB_CLOCK_DISABLE, 172 CMD_SCTRL_MAC_AHB_CLOCK_ENABLE, 173 CMD_SCTRL_MAC_CLOCK480M_DISABLE, 174 CMD_SCTRL_MAC_CLOCK480M_ENABLE, 175 CMD_SCTRL_SET_LOW_PWR_CLK, 176 CMD_SCTRL_SET_GADC_SEL, 177 CMD_SCTRL_SET_VDD_VALUE, 178 CMD_SCTRL_GET_VDD_VALUE, 179 CMD_SCTRL_BLOCK_EN_MUX_SET, 180 181 #if (CONFIG_SOC_BK7271) 182 CMD_SCTRL_OVERCLOCK, 183 #endif 184 }; 185 186 /*PSRAM_VDDPAD_VOLT */ 187 #define PSRAM_VDD_1_8V (0x0) 188 #define PSRAM_VDD_2_5V (0x1) 189 #define PSRAM_VDD_3_3V (0x2) 190 #define PSRAM_VDD_3_3V_DEF (0x3) 191 192 #define QSPI_IO_1_8V (0x0) 193 #define QSPI_IO_2_5V (0x1) 194 #define QSPI_IO_3_3V (0x2) 195 #define QSPI_IO_3V_DEF (0x3) 196 197 /*CMD_SCTRL_MCLK_SELECT*/ 198 #define MCLK_SELECT_DCO (0x0) 199 #define MCLK_SELECT_26M_XTAL (0x1) 200 #define MCLK_SELECT_DPLL (0x2) 201 #define MCLK_SELECT_LPO (0x3) 202 203 /*CMD_SCTRL_MCLK_DIVISION*/ 204 #define MCLK_DIV_0 (0) 205 #define MCLK_DIV_1 (1) 206 #define MCLK_DIV_2 (2) 207 #define MCLK_DIV_3 (3) 208 #define MCLK_DIV_4 (4) 209 #define MCLK_DIV_5 (5) 210 #define MCLK_DIV_6 (6) 211 #define MCLK_DIV_7 (7) 212 #define MCLK_DIV_8 (8) 213 #define MCLK_DIV_9 (9) 214 #define MCLK_DIV_10 (10) 215 #define MCLK_DIV_11 (11) 216 #define MCLK_DIV_12 (12) 217 #define MCLK_DIV_13 (13) 218 #define MCLK_DIV_14 (14) 219 #define MCLK_DIV_15 (15) 220 221 222 /*CMD_SCTRL_BLK_ENABLE CMD_SCTRL_BLK_DISABLE*/ 223 #if (!CONFIG_SOC_BK7271) 224 #if (CONFIG_SOC_BK7231) 225 #define BLK_BIT_LINEIN (1 << 19) 226 #define BLK_BIT_MIC_R_CHANNEL (1 << 18) 227 #define BLK_BIT_MIC_L_CHANNEL (1 << 17) 228 #define BLK_BIT_AUDIO_R_CHANNEL (1 << 16) 229 #define BLK_BIT_AUDIO_L_CHANNEL (1 << 15) 230 #define BLK_BIT_USB (1 << 14) 231 #elif (CONFIG_SOC_BK7231U) 232 #define BLK_BIT_NC (1 << 19) 233 #define BLK_BIT_MIC_QSPI_RAM_OR_FLASH (1 << 18) 234 #define BLK_BIT_MIC_PGA (1 << 17) 235 #define BLK_BIT_AUDIO_PLL (1 << 16) 236 #define BLK_BIT_AUDIO_RANDOM_GENERATOR (1 << 15) 237 #define BLK_BIT_USB (1 << 14) 238 #elif (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX) 239 #define BLK_BIT_AUDIO_RANDOM_GENERATOR (1 << 15) 240 #elif (CONFIG_SOC_BK7251) 241 #define BLK_BIT_NC (1 << 19) 242 #define BLK_BIT_MIC_QSPI_RAM_OR_FLASH (1 << 18) 243 #define BLK_BIT_AUDIO (1 << 17) 244 #define BLK_BIT_AUDIO_PLL (1 << 16) 245 #define BLK_BIT_AUDIO_RANDOM_GENERATOR (1 << 15) 246 #define BLK_BIT_USB (1 << 14) 247 #endif // (CONFIG_SOC_BK7231) 248 #define BLK_BIT_SARADC (1 << 13) 249 #define BLK_BIT_TEMPRATURE_SENSOR (1 << 12) 250 #define BLK_BIT_26M_XTAL_LOW_POWER (1 << 11) 251 #define BLK_BIT_XTAL2RF (1 << 10) 252 #define BLK_BIT_IO_LDO_LOW_POWER (1 << 09) 253 #define BLK_BIT_ANALOG_SYS_LDO (1 << 08) 254 #define BLK_BIT_DIGITAL_CORE_LDO_LOW_POWER (1 << 07) 255 #define BLK_BIT_DIGITAL_CORE (1 << 06) 256 #define BLK_BIT_DPLL_480M (1 << 05) 257 #define BLK_BIT_32K_XTAL (1 << 04) 258 #define BLK_BIT_26M_XTAL (1 << 03) 259 #define BLK_BIT_ROSC32K (1 << 02) 260 #define BLK_BIT_DCO (1 << 01) 261 #define BLK_BIT_FLASH (1 << 00) 262 #endif 263 264 /* CMD_SCTRL_RESET _SET/_CLR*/ 265 #define PARAM_MODEM_CORE_RESET_BIT (1 << 6) 266 #define PARAM_TL410_EXT_WAIT_BIT (1 << 5) 267 #define PARAM_USB_SUBSYS_RESET_BIT (1 << 4) 268 #define PARAM_TL410_BOOT_BIT (1 << 3) 269 #define PARAM_MAC_SUBSYS_RESET_BIT (1 << 2) 270 #define PARAM_DSP_SUBSYS_RESET_BIT (1 << 1) 271 #define PARAM_MODEM_SUBCHIP_RESET_BIT (1 << 0) 272 273 /* CMD_GET_SCTRL_CONTROL CMD_SET_SCTRL_CONTROL*/ 274 #define MCLK_MODE_DCO (0x0) 275 #define MCLK_MODE_26M_XTAL (0x1) 276 #define MCLK_MODE_DPLL (0x2) 277 #define MCLK_MODE_LPO (0x3) 278 279 /*CMD_SCTRL_BIAS_REG_SET CMD_SCTRL_BIAS_REG_CLEAN*/ 280 #if (CONFIG_SOC_BK7271) 281 #define PARAM_BIAS_CAL_OUT_POSI (12) 282 #define PARAM_BIAS_CAL_OUT_MASK (0x1F) 283 #define PARAM_LDO_VAL_MANUAL_POSI (16) 284 #define PARAM_LDO_VAL_MANUAL_MASK (0x1F) 285 #define PARAM_BIAS_CAL_MANUAL_BIT (1 << 22) 286 #define PARAM_BIAS_CAL_TRIGGER_BIT (1 << 21) 287 #else 288 #define PARAM_BIAS_CAL_OUT_POSI (16) 289 #define PARAM_BIAS_CAL_OUT_MASK (0x1F) 290 #define PARAM_LDO_VAL_MANUAL_POSI (8) 291 #define PARAM_LDO_VAL_MANUAL_MASK (0x1F) 292 #define PARAM_BIAS_CAL_MANUAL_BIT (1 << 4) 293 #define PARAM_BIAS_CAL_TRIGGER_BIT (1 << 0) 294 #endif 295 296 /*CMD_SCTRL_ANALOG_CTRL4_SET CMD_SCTRL_ANALOG_CTRL4_CLEAN*/ 297 #define PARAM_VSEL_SYS_LDO_POSI (27) 298 #define PARAM_VSEL_SYS_LDO_MASK (0x3) 299 #define PARAM_SARADC_BT_TXSEL_BIT (1 << 5) 300 #define PARAM_SARADC_VREF_SEL_BIT (1 << 4) 301 302 #if (CONFIG_SOC_BK7231U) 303 #define DEFAULT_TXID_XTAL (0x19) 304 #elif (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7236) 305 #if (CONFIG_XTAL_FREQ_40M) 306 #define DEFAULT_TXID_XTAL (0x70) 307 #else 308 #define DEFAULT_TXID_XTAL (0x10)//(0x37) 309 #endif 310 #elif (CONFIG_SOC_BK7251) || (CONFIG_SOC_BK7271) 311 #define DEFAULT_TXID_XTAL (0x10) 312 #endif // (CONFIG_SOC_BK7231U) 313 314 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX) 315 #define PARAM_XTALH_CTUNE_MASK (0x7F) 316 317 #define PARAM_AUD_DAC_GAIN_MASK (0x1F) 318 #elif (!CONFIG_SOC_BK7231) 319 #define PARAM_XTALH_CTUNE_MASK (0x3F) 320 321 #define PARAM_AUD_DAC_GAIN_MASK (0x1F) 322 #endif // (!CONFIG_SOC_BK7231) 323 324 /*CMD_SCTRL_SET_LOW_PWR_CLK*/ 325 #define LPO_SELECT_ROSC (0x0) 326 #define LPO_SELECT_32K_XTAL (0x1) 327 #define LPO_SELECT_32K_DIV (0x2) 328 329 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX) 330 #define SW_RETENTION_WDT_FLAG (1 << 16) 331 #define SW_RETENTION_WDT_FLAG_POS (16) 332 #define SW_RETENTION_VAL_MASK (0XFFFF) 333 #define SW_RETENTION_VAL_POS (0) 334 #endif 335 336 337 typedef union 338 { 339 UINT32 val; 340 struct 341 { 342 UINT32 mclk_mux: 2; 343 UINT32 resv0: 2; 344 UINT32 mclk_div: 4; 345 UINT32 flash_26m_select: 1; 346 UINT32 hclk_div2_en: 1; 347 UINT32 modem_clk480m_pwd: 1; 348 UINT32 mac_clk480m_pwd: 1; 349 UINT32 mpif_clk_inv: 1; 350 UINT32 sdio_clk_inv: 1; 351 UINT32 resv1: 18; 352 } bits; 353 } SYS_CTRL_U; 354 355 typedef struct efuse_oper_st 356 { 357 UINT8 addr; 358 UINT8 data; 359 } EFUSE_OPER_ST, *EFUSE_OPER_PTR; 360 361 typedef enum 362 { 363 INTERNAL_HW_MODE = 0, 364 INTERNAL_SW_MODE = 1, 365 EXTERNAL_HW_MODE = 2, 366 EXTERNAL_SW_MODE = 3, 367 } CHARGE_TYPE; 368 369 typedef enum 370 { 371 STEP_STOP = 0, 372 STEP_START = 1, 373 STEP_TRICKLE = 2, 374 STEP_EXTER_CC = 3, 375 STEP_INTER_CC = 4, 376 STEP_INTER_CV = 5, 377 378 } CHARGE_STEP; 379 380 typedef enum { 381 RESET_SOURCE_POWERON = 0x0, 382 RESET_SOURCE_REBOOT = 0x1, 383 RESET_SOURCE_WATCHDOG = 0x2, 384 385 RESET_SOURCE_DEEPPS_GPIO = 0x3, 386 RESET_SOURCE_DEEPPS_RTC = 0x4, 387 388 RESET_SOURCE_CRASH_ILLEGAL_JUMP = 0x5, 389 RESET_SOURCE_CRASH_UNDEFINED = 0x6, 390 RESET_SOURCE_CRASH_PREFETCH_ABORT = 0x7, 391 RESET_SOURCE_CRASH_DATA_ABORT = 0x8, 392 RESET_SOURCE_CRASH_UNUSED = 0x9, 393 394 RESET_SOURCE_DEEPPS_USB = 0xa, 395 RESET_SOURCE_UNKNOWN = 0xb, 396 } RESET_SOURCE_STATUS; 397 398 typedef struct charge_oper_st 399 { 400 CHARGE_TYPE type; 401 CHARGE_STEP step; 402 UINT32 elect; 403 UINT8 cal[3]; 404 } CHARGE_OPER_ST, *CHARGE_OPER_PTR; 405 406 #define CHARGE_ANALOG_CTRL3_CAL_DEFAULT_VALUE (0x180004A0) 407 #define CHARGE_ANALOG_CTRL3_CHARGE_DEFAULT_VALUE (0x180704A0) 408 #define CHARGE_ANALOG_CTRL4_CAL_DEFAULT_VALUE (0xC2400520) 409 #define CHARGE_ANALOG_CTRL4_CHARGE_DEFAULT_VALUE (0xC2401520) 410 411 412 #define AUDIO_DAC_VOL_DIFF_MODE (0) 413 #define AUDIO_DAC_VOL_SINGLE_MODE (1) 414 415 #define AUDIO_DAC_ANALOG_UNMUTE (0) 416 #define AUDIO_DAC_ANALOG_MUTE (1) 417 418 #define EFUSE_ENCRYPT_WORD_ADDR (0) 419 #define EFUSE_ENCRYPT_WORD_LEN (16) 420 #define EFUSE_CHARGE_CAL_ADDR (16) 421 #define EFUSE_CHARGE_CAL_LEN (4) 422 #define EFUSE_UID_ADDR (20) 423 #define EFUSE_UID_LEN (4) 424 #define EFUSE_MAC_START_ADDR (24) 425 #define EFUSE_MAC_LEN (6) 426 #define EFUSE_USER_AREA_ADDR (30) 427 #define EFUSE_USER_AREA_LEN (1) 428 #define EFUSE_CTRL_ADDR (31) 429 #define EFUSE_USER_AREA_LEN (1) 430 #define EFUSE_INIT_VAL (0x0) 431 432 #define EFUSE_CTRL_JTAG_DISABLE (1 << 7) 433 #define EFUSE_CTRL_FLASH_DOWNLOAD_DISABLE (1 << 6) 434 #define EFUSE_CTRL_ENCRYPT_EN (1 << 5) 435 #define EFUSE_CTRL_ENCRYPT_DISABLE_READ (1 << 4) 436 #define EFUSE_CTRL_ENCRYPT_DISABLE_WRITE (1 << 3) 437 #define EFUSE_CTRL_UID_DISABLE_WRITE (1 << 2) 438 #define EFUSE_CTRL_MAC_DISABLE_WRITE (1 << 1) 439 #define EFUSE_CTRL_ALL_AREA_DISABLE_WRITE (1 << 0) 440 441 typedef void (*sctrl_cal_bias_cb_t)(void); 442 typedef void (*sctrl_wifi_phy_wakeup_rf_reinit_cb_t)(void); 443 typedef void (*sctrl_wifi_phy_wakeup_wifi_reinit_cb_t)(void); 444 445 /******************************************************************************* 446 * Function Declarations 447 *******************************************************************************/ 448 extern void sctrl_init(void); 449 extern void sctrl_exit(void); 450 extern void sctrl_normal_exit_sleep(void); 451 extern void sctrl_normal_enter_sleep(UINT32 peri_clk); 452 extern void sctrl_mcu_exit(void); 453 extern void sctrl_mcu_init(void); 454 extern void sctrl_mcu_sleep(UINT32 ); 455 extern UINT32 sctrl_mcu_wakeup(void); 456 extern void sctrl_ps_dump(); 457 extern void sctrl_flash_select_dco(void); 458 extern UINT32 charger_is_full(void); 459 extern UINT32 usb_power_is_pluged(void); 460 RESET_SOURCE_STATUS sctrl_get_deep_sleep_wake_soure(void); 461 extern void rf_ps_enable_set(void); 462 extern void rf_ps_enable_clear(void); 463 extern int rf_ps_enabled(void); 464 extern UINT32 sctrl_get_deep_sleep_gpio_floating_map(void); 465 extern int bk_misc_wakeup_get_gpio_num(void); 466 extern int bk_init_deep_wakeup_gpio_status(void); 467 extern UINT32 sctrl_get_deep_sleep_gpio_last_floating_map(void); 468 extern void sctrl_set_deep_sleep_gpio_last_floating_map(UINT32); 469 extern void sctrl_set_deep_sleep_gpio_floating_map(UINT32); 470 extern void sctrl_register_cal_bias_callback(sctrl_cal_bias_cb_t cb); 471 extern void sctrl_register_wifi_phy_wakeup_rf_reinit_callback(sctrl_wifi_phy_wakeup_rf_reinit_cb_t cb); 472 extern void sctrl_register_wifi_phy_wakeup_wifi_reinit_callback(sctrl_wifi_phy_wakeup_wifi_reinit_cb_t cb); 473 474 #ifdef __cplusplus 475 } 476 #endif 477 478