1/* 2 * Copyright (c) 2021 Chipsea Technologies (Shenzhen) Corp., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 .syntax unified 16 .arch armv7-m 17 18/* Memory Model 19 The HEAP starts at the end of the DATA section and grows upward. 20 21 The STACK starts at the end of the RAM and grows downward. 22 23 The HEAP and stack STACK are only checked at compile time: 24 (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE 25 26 This is just a check for the bare minimum for the Heap+Stack area before 27 aborting compilation, it is not the run time limit: 28 Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100 29 */ 30 .section .stack 31 .align 3 32#ifdef __STACK_SIZE 33 .equ Stack_Size, __STACK_SIZE 34#else 35 .equ Stack_Size, 0x800 36#endif 37 .globl __StackTop 38 .globl __StackLimit 39__StackLimit: 40 .space Stack_Size 41 .size __StackLimit, . - __StackLimit 42__StackTop: 43 .size __StackTop, . - __StackTop 44 45 .section .heap 46 .align 3 47#ifdef __HEAP_SIZE 48 .equ Heap_Size, __HEAP_SIZE 49#else 50 .equ Heap_Size, 0x10000 51#endif 52 .globl __HeapBase 53 .globl __HeapLimit 54__HeapBase: 55 .space Heap_Size 56 .size __HeapBase, . - __HeapBase 57__HeapLimit: 58 .size __HeapLimit, . - __HeapLimit 59 60 .section .isr_vector 61 .align 2 62 .globl __isr_vector 63__isr_vector: 64 .long __StackTop /* Top of Stack */ 65 .long Reset_Handler /* Reset Handler */ 66 .long NMI_Handler /* NMI Handler */ 67 .long HardFault_Handler /* Hard Fault Handler */ 68 .long MemManage_Handler /* MPU Fault Handler */ 69 .long BusFault_Handler /* Bus Fault Handler */ 70 .long UsageFault_Handler /* Usage Fault Handler */ 71 .long 0 /* Reserved */ 72 .long 0 /* Reserved */ 73 .long 0 /* Reserved */ 74 .long 0 /* Reserved */ 75 .long SVC_Handler /* SVCall Handler */ 76 .long DebugMon_Handler /* Debug Monitor Handler */ 77 .long 0 /* Reserved */ 78 .long PendSV_Handler /* PendSV Handler */ 79 .long SysTick_Handler /* SysTick Handler */ 80 81 /* External interrupts */ 82 .long BTAON_IRQHandler /* 16: BT AON */ 83 .long WCNAON_IRQHandler /* 17: WCN AON */ 84 .long WGEN_IRQHandler /* 18: WGEN */ 85 .long WPROTTRIG_IRQHandler /* 19: WPROTTRIG */ 86 .long WTXTRIG_IRQHandler /* 20: WTXTRIG */ 87 .long WRXTRIG_IRQHandler /* 21: WRXTRIG */ 88 .long WTXRXMISC_IRQHandler /* 22: WTXRXMISC */ 89 .long WTXRXTIM_IRQHandler /* 23: WTXRXTIM */ 90 .long WPHY_IRQHandler /* 24: WPHY */ 91 .long BLE_IRQHandler /* 25: BLE */ 92 .long BT_IRQHandler /* 26: BT */ 93 .long BTDM_IRQHandler /* 27: BTDM */ 94 .long FREQ_IRQHandler /* 28: FREQ */ 95 .long DMACOMB_IRQHandler /* 29: DMA Comb */ 96 .long SDIO_IRQHandler /* 30: SDIO */ 97 .long USBDMA_IRQHandler /* 31: USB DMA */ 98 .long UART0_IRQHandler /* 32: UART0 */ 99 .long UART1_IRQHandler /* 33: UART1 */ 100 .long UART2_IRQHandler /* 34: UART2 */ 101 .long MCU2WCN0_IRQHandler /* 35: MCU2WCN */ 102 .long MCU2WCN1_IRQHandler /* 36: MCU2WCN */ 103 .long WCN2MCU0_IRQHandler /* 37: WCN2MCU */ 104 .long WCN2MCU1_IRQHandler /* 38: WCN2MCU */ 105 .long MCU2WCN0_G1_IRQHandler /* 39: MCU2WCN G1 */ 106 .long MCU2WCN1_G1_IRQHandler /* 40: MCU2WCN G1 */ 107 .long WCN2MCU0_G1_IRQHandler /* 41: WCN2MCU G1 */ 108 .long WCN2MCU1_G1_IRQHandler /* 42: WCN2MCU G1 */ 109 .long TIMER20_IRQHandler /* 43: Timer */ 110 .long TIMER21_IRQHandler /* 44: Timer */ 111 .long TIMER22_IRQHandler /* 45: Timer */ 112 .long WDT3_IRQHandler /* 46: WDT */ 113 .long ASDMA_CMN_IRQHandler /* 47: ASDMA Common */ 114 .long ASDMA_GE_SW_IRQHandler /* 48: ASDMA Generic SW */ 115 .long ASDMA_AUDIO_IRQHandler /* 49: ASDMA Audio Channel */ 116 .long ASDMA_GE_HW_IRQHandler /* 50: ASDMA Generic HW */ 117 .long ASDMA_DMAC_IRQHandler /* 51: ASDMA Dmac */ 118 .long AUD_PROC_IRQHandler /* 52: Audio Process */ 119 .long DMA00_IRQHandler /* 53: DMA */ 120 .long DMA01_IRQHandler /* 54: DMA */ 121 .long DMA02_IRQHandler /* 55: DMA */ 122 .long DMA03_IRQHandler /* 56: DMA */ 123 .long DMA04_IRQHandler /* 57: DMA */ 124 .long DMA05_IRQHandler /* 58: DMA */ 125 .long DMA06_IRQHandler /* 59: DMA */ 126 .long DMA07_IRQHandler /* 60: DMA */ 127 .long DMA08_IRQHandler /* 61: DMA */ 128 .long DMA09_IRQHandler /* 62: DMA */ 129 .long DMA10_IRQHandler /* 63: DMA */ 130 .long DMA11_IRQHandler /* 64: DMA */ 131 .long DMA12_IRQHandler /* 65: DMA */ 132 .long DMA13_IRQHandler /* 66: DMA */ 133 .long MCU2WCN2_IRQHandler /* 67: MCU2WCN */ 134 .long MCU2WCN3_IRQHandler /* 68: MCU2WCN */ 135 .long WCN2MCU2_IRQHandler /* 69: WCN2MCU */ 136 .long WCN2MCU3_IRQHandler /* 70: WCN2MCU */ 137 .long MCU2WCN2_G1_IRQHandler /* 71: MCU2WCN G1 */ 138 .long MCU2WCN3_G1_IRQHandler /* 72: MCU2WCN G1 */ 139 .long WCN2MCU2_G1_IRQHandler /* 73: WCN2MCU G1 */ 140 .long WCN2MCU3_G1_IRQHandler /* 74: WCN2MCU G1 */ 141 .long TIMER00_IRQHandler /* 75: Timer */ 142 .long TIMER01_IRQHandler /* 76: Timer */ 143 .long TIMER02_IRQHandler /* 77: Timer */ 144 .long TIMER10_IRQHandler /* 78: Timer */ 145 .long TIMER11_IRQHandler /* 79: Timer */ 146 .long TIMER12_IRQHandler /* 80: Timer */ 147 .long GPIO_IRQHandler /* 81: GPIO */ 148 .long WDT0_IRQHandler /* 82: WDT */ 149 .long WDT1_IRQHandler /* 83: WDT */ 150 .long WDT2_IRQHandler /* 84: WDT */ 151 .long SPI0_IRQHandler /* 85: SPI */ 152 .long TRNG_IRQHandler /* 86: TRNG */ 153 .long I2CM_IRQHandler /* 87: I2CM */ 154 .long I2CS_IRQHandler /* 88: I2CS */ 155 .long CACHE0_IRQHandler /* 89: CACHE */ 156 .long CACHE1_IRQHandler /* 90: CACHE */ 157 .long PSRAM_IRQHandler /* 91: PSRAM */ 158 .long SDMMC_IRQHandler /* 92: SDMMC */ 159 .long PSIM_IRQHandler /* 93: PSIM */ 160 .long PWRCTRL_IRQHandler /* 94: PWRCTRL */ 161 .long PMIC_IRQHandler /* 95: PMIC */ 162 163 164 .size __isr_vector, . - __isr_vector 165 166 .text 167 .thumb 168 .align 2 169 .globl Image_Info 170Image_Info: 171 .long 0x474D4946 /* Magic number, "FIMG" */ 172 .long __image_end__ /* End address of flash image */ 173 .long 0xFFFFFFFF 174 .long 0xFFFFFFFF 175 .size Image_Info, . - Image_Info 176 177 .text 178 .thumb 179 .thumb_func 180 .align 2 181 .globl Reset_Handler 182 .type Reset_Handler, %function 183Reset_Handler: 184/* Loop to copy data from read only memory to RAM. The ranges 185 * of copy from/to are specified by following symbols evaluated in 186 * linker script. 187 * _etext: End of code section, i.e., begin of data sections to copy from. 188 * __data_start__/__data_end__: RAM address range that data should be 189 * copied to. Both must be aligned to 4 bytes boundary. */ 190 191 ldr r0, =__StackTop 192 msr msp, r0 193 194 ldr r1, =__etext 195 ldr r2, =__data_start__ 196 ldr r3, =__data_end__ 197 198.Liram_to_dram_loop: 199 cmp r2, r3 200 ittt lt 201 ldrlt r0, [r1], #4 202 strlt r0, [r2], #4 203 blt .Liram_to_dram_loop 204 205/* bss clear start */ 206 mov r1, #0 207 ldr r2, =__bss_start__ 208 ldr r3, =__bss_end__ 209 210.Lclear_bss_loop: 211 cmp r2, r3 212 itt lt 213 strlt r1, [r2], #4 214 blt .Lclear_bss_loop 215/* bss clear end */ 216 217#ifdef CFG_USB_MEM 218 ldr r1, =__etext_plus_data_end__ 219 ldr r2, =__usb_data_start__ 220 ldr r3, =__usb_data_end__ 221 222.Liram_to_usb_dram_loop: 223 cmp r2, r3 224 ittt lt 225 ldrlt r0, [r1], #4 226 strlt r0, [r2], #4 227 blt .Liram_to_usb_dram_loop 228 229/* usb bss clear start */ 230 mov r1, #0 231 ldr r2, =__usb_bss_start__ 232 ldr r3, =__usb_bss_end__ 233 234.Lclear_usb_bss_loop: 235 cmp r2, r3 236 itt lt 237 strlt r1, [r2], #4 238 blt .Lclear_usb_bss_loop 239/* usb bss clear end */ 240#endif /* CFG_USB_MEM */ 241 ldr r0, =NVIC_Vectors_Init 242 blx r0 243 ldr r0, =SystemInit 244 blx r0 245 ldr r0, =rw_main 246 bx r0 247 248 .pool 249 .size Reset_Handler, . - Reset_Handler 250 251 .text 252/* Macro to define default handlers. Default handler 253 * will be weak symbol and just dead loops. They can be 254 * overwritten by other handlers */ 255 .macro def_default_handler handler_name 256 .align 1 257 .thumb_func 258 .weak \handler_name 259 .type \handler_name, %function 260\handler_name : 261 b . 262 .size \handler_name, . - \handler_name 263 .endm 264 265 def_default_handler NMI_Handler 266 def_default_handler HardFault_Handler 267 def_default_handler MemManage_Handler 268 def_default_handler BusFault_Handler 269 def_default_handler UsageFault_Handler 270 def_default_handler SVC_Handler 271 def_default_handler DebugMon_Handler 272 def_default_handler PendSV_Handler 273 def_default_handler SysTick_Handler 274 def_default_handler Default_Handler 275 276 .macro def_irq_default_handler handler_name 277 .weak \handler_name 278 .set \handler_name, Default_Handler 279 .endm 280 281 def_irq_default_handler BTAON_IRQHandler 282 def_irq_default_handler WCNAON_IRQHandler 283 def_irq_default_handler WGEN_IRQHandler 284 def_irq_default_handler WPROTTRIG_IRQHandler 285 def_irq_default_handler WTXTRIG_IRQHandler 286 def_irq_default_handler WRXTRIG_IRQHandler 287 def_irq_default_handler WTXRXMISC_IRQHandler 288 def_irq_default_handler WTXRXTIM_IRQHandler 289 def_irq_default_handler WPHY_IRQHandler 290 def_irq_default_handler BLE_IRQHandler 291 def_irq_default_handler BT_IRQHandler 292 def_irq_default_handler BTDM_IRQHandler 293 def_irq_default_handler FREQ_IRQHandler 294 def_irq_default_handler DMACOMB_IRQHandler 295 def_irq_default_handler SDIO_IRQHandler 296 def_irq_default_handler USBDMA_IRQHandler 297 def_irq_default_handler UART0_IRQHandler 298 def_irq_default_handler UART1_IRQHandler 299 def_irq_default_handler UART2_IRQHandler 300 def_irq_default_handler MCU2WCN0_IRQHandler 301 def_irq_default_handler MCU2WCN1_IRQHandler 302 def_irq_default_handler WCN2MCU0_IRQHandler 303 def_irq_default_handler WCN2MCU1_IRQHandler 304 def_irq_default_handler MCU2WCN0_G1_IRQHandler 305 def_irq_default_handler MCU2WCN1_G1_IRQHandler 306 def_irq_default_handler WCN2MCU0_G1_IRQHandler 307 def_irq_default_handler WCN2MCU1_G1_IRQHandler 308 def_irq_default_handler TIMER20_IRQHandler 309 def_irq_default_handler TIMER21_IRQHandler 310 def_irq_default_handler TIMER22_IRQHandler 311 def_irq_default_handler WDT3_IRQHandler 312 def_irq_default_handler ASDMA_CMN_IRQHandler 313 def_irq_default_handler ASDMA_GE_SW_IRQHandler 314 def_irq_default_handler ASDMA_AUDIO_IRQHandler 315 def_irq_default_handler ASDMA_GE_HW_IRQHandler 316 def_irq_default_handler ASDMA_DMAC_IRQHandler 317 def_irq_default_handler AUD_PROC_IRQHandler 318 def_irq_default_handler DMA00_IRQHandler 319 def_irq_default_handler DMA01_IRQHandler 320 def_irq_default_handler DMA02_IRQHandler 321 def_irq_default_handler DMA03_IRQHandler 322 def_irq_default_handler DMA04_IRQHandler 323 def_irq_default_handler DMA05_IRQHandler 324 def_irq_default_handler DMA06_IRQHandler 325 def_irq_default_handler DMA07_IRQHandler 326 def_irq_default_handler DMA08_IRQHandler 327 def_irq_default_handler DMA09_IRQHandler 328 def_irq_default_handler DMA10_IRQHandler 329 def_irq_default_handler DMA11_IRQHandler 330 def_irq_default_handler DMA12_IRQHandler 331 def_irq_default_handler DMA13_IRQHandler 332 def_irq_default_handler MCU2WCN2_IRQHandler 333 def_irq_default_handler MCU2WCN3_IRQHandler 334 def_irq_default_handler WCN2MCU2_IRQHandler 335 def_irq_default_handler WCN2MCU3_IRQHandler 336 def_irq_default_handler MCU2WCN2_G1_IRQHandler 337 def_irq_default_handler MCU2WCN3_G1_IRQHandler 338 def_irq_default_handler WCN2MCU2_G1_IRQHandler 339 def_irq_default_handler WCN2MCU3_G1_IRQHandler 340 def_irq_default_handler TIMER00_IRQHandler 341 def_irq_default_handler TIMER01_IRQHandler 342 def_irq_default_handler TIMER02_IRQHandler 343 def_irq_default_handler TIMER10_IRQHandler 344 def_irq_default_handler TIMER11_IRQHandler 345 def_irq_default_handler TIMER12_IRQHandler 346 def_irq_default_handler GPIO_IRQHandler 347 def_irq_default_handler WDT0_IRQHandler 348 def_irq_default_handler WDT1_IRQHandler 349 def_irq_default_handler WDT2_IRQHandler 350 def_irq_default_handler SPI0_IRQHandler 351 def_irq_default_handler TRNG_IRQHandler 352 def_irq_default_handler I2CM_IRQHandler 353 def_irq_default_handler I2CS_IRQHandler 354 def_irq_default_handler CACHE0_IRQHandler 355 def_irq_default_handler CACHE1_IRQHandler 356 def_irq_default_handler PSRAM_IRQHandler 357 def_irq_default_handler SDMMC_IRQHandler 358 def_irq_default_handler PSIM_IRQHandler 359 def_irq_default_handler PWRCTRL_IRQHandler 360 def_irq_default_handler PMIC_IRQHandler 361 362 .end 363