1 // Copyright 2017 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 #include "sdkconfig.h"
15 #include "soc/soc.h"
16 #include "soc/rtc.h"
17 #include "soc/efuse_periph.h"
18 #include "soc/rtc_cntl_reg.h"
19
20 #define CPU_RESET_REASON RTC_SW_CPU_RESET
21
22 #ifdef CONFIG_IDF_TARGET_ESP32
23 #include "soc/dport_reg.h"
24 #include "esp32/rom/rtc.h"
25 #undef CPU_RESET_REASON
26 #define CPU_RESET_REASON SW_CPU_RESET
27 #elif CONFIG_IDF_TARGET_ESP32S2
28 #include "esp32s2/rom/rtc.h"
29 #elif CONFIG_IDF_TARGET_ESP32S3
30 #include "esp32s3/rom/rtc.h"
31 #elif CONFIG_IDF_TARGET_ESP32C3
32 #include "esp32c3/rom/rtc.h"
33 #endif
34 #include "esp_rom_uart.h"
35
bootloader_clock_configure(void)36 __attribute__((weak)) void bootloader_clock_configure(void)
37 {
38 // ROM bootloader may have put a lot of text into UART0 FIFO.
39 // Wait for it to be printed.
40 // This is not needed on power on reset, when ROM bootloader is running at
41 // 40 MHz. But in case of TG WDT reset, CPU may still be running at >80 MHZ,
42 // and will be done with the bootloader much earlier than UART FIFO is empty.
43 esp_rom_uart_tx_wait_idle(0);
44
45 /* Set CPU to 80MHz. Keep other clocks unmodified. */
46 int cpu_freq_mhz = 80;
47
48 #if CONFIG_IDF_TARGET_ESP32
49 /* On ESP32 rev 0, switching to 80/160 MHz if clock was previously set to
50 * 240 MHz may cause the chip to lock up (see section 3.5 of the errata
51 * document). For rev. 0, switch to 240 instead if it has been enabled
52 * previously.
53 */
54 uint32_t chip_ver_reg = REG_READ(EFUSE_BLK0_RDATA3_REG);
55 if ((chip_ver_reg & EFUSE_RD_CHIP_VER_REV1_M) == 0 &&
56 DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL) == DPORT_CPUPERIOD_SEL_240) {
57 cpu_freq_mhz = 240;
58 }
59 #endif
60
61 if (rtc_clk_apb_freq_get() < APB_CLK_FREQ || rtc_get_reset_reason(0) != CPU_RESET_REASON) {
62 rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT();
63 #if CONFIG_IDF_TARGET_ESP32
64 clk_cfg.xtal_freq = CONFIG_ESP32_XTAL_FREQ;
65 #endif
66 /* ESP32-S2 doesn't have XTAL_FREQ choice, always 40MHz */
67 clk_cfg.cpu_freq_mhz = cpu_freq_mhz;
68 clk_cfg.slow_freq = rtc_clk_slow_freq_get();
69 clk_cfg.fast_freq = rtc_clk_fast_freq_get();
70 rtc_clk_init(clk_cfg);
71 }
72
73 /* As a slight optimization, if 32k XTAL was enabled in sdkconfig, we enable
74 * it here. Usually it needs some time to start up, so we amortize at least
75 * part of the start up time by enabling 32k XTAL early.
76 * App startup code will wait until the oscillator has started up.
77 */
78 #if CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
79 if (!rtc_clk_32k_enabled()) {
80 rtc_clk_32k_bootstrap(CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES);
81 }
82 #endif // CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
83
84 REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
85 REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
86 }
87