1 // Copyright 2018 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 #include <stdbool.h>
15 #include <assert.h>
16 #include "string.h"
17 #include "sdkconfig.h"
18 #include "esp_err.h"
19 #include "esp_log.h"
20 #include "esp_rom_gpio.h"
21 #include "esp_rom_efuse.h"
22 #include "esp32/rom/spi_flash.h"
23 #include "soc/gpio_periph.h"
24 #include "soc/efuse_reg.h"
25 #include "soc/spi_reg.h"
26 #include "soc/soc_caps.h"
27 #include "soc/soc_pins.h"
28 #include "hal/gpio_hal.h"
29 #include "flash_qio_mode.h"
30 #include "bootloader_common.h"
31 #include "bootloader_flash_config.h"
32
bootloader_flash_update_id(void)33 void bootloader_flash_update_id(void)
34 {
35 g_rom_flashchip.device_id = bootloader_read_flash_id();
36 }
37
bootloader_flash_update_size(uint32_t size)38 void bootloader_flash_update_size(uint32_t size)
39 {
40 g_rom_flashchip.chip_size = size;
41 }
42
bootloader_flash_cs_timing_config(void)43 void IRAM_ATTR bootloader_flash_cs_timing_config(void)
44 {
45 SET_PERI_REG_MASK(SPI_USER_REG(0), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
46 SET_PERI_REG_BITS(SPI_CTRL2_REG(0), SPI_HOLD_TIME_V, 1, SPI_HOLD_TIME_S);
47 SET_PERI_REG_BITS(SPI_CTRL2_REG(0), SPI_SETUP_TIME_V, 0, SPI_SETUP_TIME_S);
48 SET_PERI_REG_MASK(SPI_USER_REG(1), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
49 SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_HOLD_TIME_V, 1, SPI_HOLD_TIME_S);
50 SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_SETUP_TIME_V, 0, SPI_SETUP_TIME_S);
51 }
52
bootloader_flash_clock_config(const esp_image_header_t * pfhdr)53 void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t* pfhdr)
54 {
55 uint32_t spi_clk_div = 0;
56 switch (pfhdr->spi_speed) {
57 case ESP_IMAGE_SPI_SPEED_80M:
58 spi_clk_div = 1;
59 break;
60 case ESP_IMAGE_SPI_SPEED_40M:
61 spi_clk_div = 2;
62 break;
63 case ESP_IMAGE_SPI_SPEED_26M:
64 spi_clk_div = 3;
65 break;
66 case ESP_IMAGE_SPI_SPEED_20M:
67 spi_clk_div = 4;
68 break;
69 default:
70 break;
71 }
72 esp_rom_spiflash_config_clk(spi_clk_div, 0);
73 esp_rom_spiflash_config_clk(spi_clk_div, 1);
74 }
75
bootloader_flash_gpio_config(const esp_image_header_t * pfhdr)76 void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr)
77 {
78 uint32_t drv = 2;
79 if (pfhdr->spi_speed == ESP_IMAGE_SPI_SPEED_80M) {
80 drv = 3;
81 }
82
83 uint32_t pkg_ver = bootloader_common_get_chip_ver_pkg();
84
85 if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 ||
86 pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 ||
87 pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 ||
88 pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) {
89 // For ESP32D2WD or ESP32-PICO series,the SPI pins are already configured
90 // flash clock signal should come from IO MUX.
91 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
92 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
93 } else {
94 const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
95 if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
96 esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_CS, SPICS0_OUT_IDX, 0, 0);
97 esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_OUT_IDX, 0, 0);
98 esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_IN_IDX, 0);
99 esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_MOSI, SPID_OUT_IDX, 0, 0);
100 esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_MOSI, SPID_IN_IDX, 0);
101 esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_WP, SPIWP_OUT_IDX, 0, 0);
102 esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_WP, SPIWP_IN_IDX, 0);
103 esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_HD, SPIHD_OUT_IDX, 0, 0);
104 esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_HD, SPIHD_IN_IDX, 0);
105 //select pin function gpio
106 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
107 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);
108 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA2_U, PIN_FUNC_GPIO);
109 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA3_U, PIN_FUNC_GPIO);
110 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CMD_U, PIN_FUNC_GPIO);
111 // flash clock signal should come from IO MUX.
112 // set drive ability for clock
113 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
114 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
115
116 uint32_t flash_id = g_rom_flashchip.device_id;
117 if (flash_id == FLASH_ID_GD25LQ32C) {
118 // Set drive ability for 1.8v flash in 80Mhz.
119 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA0_U, FUN_DRV, 3, FUN_DRV_S);
120 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA1_U, FUN_DRV, 3, FUN_DRV_S);
121 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA2_U, FUN_DRV, 3, FUN_DRV_S);
122 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA3_U, FUN_DRV, 3, FUN_DRV_S);
123 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CMD_U, FUN_DRV, 3, FUN_DRV_S);
124 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, 3, FUN_DRV_S);
125 }
126 }
127 }
128 }
129
bootloader_flash_dummy_config(const esp_image_header_t * pfhdr)130 void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t* pfhdr)
131 {
132 int spi_cache_dummy = 0;
133 uint32_t modebit = READ_PERI_REG(SPI_CTRL_REG(0));
134 if (modebit & SPI_FASTRD_MODE) {
135 if (modebit & SPI_FREAD_QIO) { //SPI mode is QIO
136 spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN;
137 } else if (modebit & SPI_FREAD_DIO) { //SPI mode is DIO
138 spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN;
139 SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN_V, SPI0_R_DIO_ADDR_BITSLEN, SPI_USR_ADDR_BITLEN_S);
140 } else if(modebit & (SPI_FREAD_QUAD | SPI_FREAD_DUAL)) { //SPI mode is QOUT or DIO
141 spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
142 }
143 }
144
145 extern uint8_t g_rom_spiflash_dummy_len_plus[];
146 switch (pfhdr->spi_speed) {
147 case ESP_IMAGE_SPI_SPEED_80M:
148 g_rom_spiflash_dummy_len_plus[0] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M;
149 g_rom_spiflash_dummy_len_plus[1] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M;
150 break;
151 case ESP_IMAGE_SPI_SPEED_40M:
152 g_rom_spiflash_dummy_len_plus[0] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M;
153 g_rom_spiflash_dummy_len_plus[1] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M;
154 break;
155 case ESP_IMAGE_SPI_SPEED_26M:
156 case ESP_IMAGE_SPI_SPEED_20M:
157 g_rom_spiflash_dummy_len_plus[0] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M;
158 g_rom_spiflash_dummy_len_plus[1] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M;
159 break;
160 default:
161 break;
162 }
163
164 SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + g_rom_spiflash_dummy_len_plus[0],
165 SPI_USR_DUMMY_CYCLELEN_S);
166 }
167
168 #define ESP32_D2WD_WP_GPIO 7 /* ESP32-D2WD & ESP32-PICO-D4 has this GPIO wired to WP pin of flash */
169 #define ESP32_PICO_V3_GPIO 18 /* ESP32-PICO-V3* use this GPIO for WP pin of flash */
170
bootloader_flash_get_wp_pin(void)171 int bootloader_flash_get_wp_pin(void)
172 {
173 #if CONFIG_BOOTLOADER_SPI_CUSTOM_WP_PIN
174 return CONFIG_BOOTLOADER_SPI_WP_PIN; // can be set for bootloader when QIO or QOUT config in use
175 #elif CONFIG_SPIRAM_CUSTOM_SPIWP_SD3_PIN
176 return CONFIG_SPIRAM_SPIWP_SD3_PIN; // can be set for app when DIO or DOUT config used for PSRAM only
177 #else
178 // no custom value, find it based on the package eFuse value
179 uint8_t chip_ver;
180 uint32_t pkg_ver = bootloader_common_get_chip_ver_pkg();
181 switch(pkg_ver) {
182 case EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH:
183 case EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5:
184 return ESP32_D2WD_WP_GPIO;
185 case EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4:
186 /* Same package IDs are used for ESP32-PICO-V3 and ESP32-PICO-D4, silicon version differentiates */
187 chip_ver = bootloader_common_get_chip_revision();
188 return (chip_ver < 3) ? ESP32_D2WD_WP_GPIO : ESP32_PICO_V3_GPIO;
189 case EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302:
190 return ESP32_PICO_V3_GPIO;
191 default:
192 return SPI_WP_GPIO_NUM;
193 }
194 #endif
195 }
196