1 /*
2 * Copyright (c) 2021 Chipsea Technologies (Shenzhen) Corp., Ltd. All rights reserved.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15 #include "plf.h"
16 #include "system.h"
17 #include "bt_hci.h"
18 #include "bt_cs8800_drv_config.h"
19 #include "dbg.h"
20
21 #define CSBT_FW_DEFAULT_START_ADDR 0x80000
22 #define CSBT_FW_RAM_START_ADDR 0x100000
23
24 static uint32_t bt_fw_start_addr = CSBT_FW_DEFAULT_START_ADDR;
25 uint32_t bt_fw_patch_addr = 0;
26 static uint32_t bt_hci_ram_base[BT_HCI_CH_NUM] = {0,};
27 static struct csbt_patch_init_desc patch_init_desc;
28
29 /*
30 * set bt fw addr
31 * @param addr : if value is 0 or this function is not used, it will use default fw addr;
32 */
bt_common_set_defalut_fw_addr(uint32_t addr)33 void bt_common_set_defalut_fw_addr(uint32_t addr)
34 {
35 if(addr && addr != bt_fw_start_addr){
36 bt_fw_start_addr = addr;
37 TRACE("fw_start_addr = 0x%x\n",bt_fw_start_addr);
38 }
39 }
40
bt_common_get_defalut_fw_addr(void)41 uint32_t bt_common_get_defalut_fw_addr(void)
42 {
43 return bt_fw_start_addr;
44 }
45
46 /*
47 * set bt hci ipc ram base
48 * @param ram_base[BT_HCI_CH_NUM] : if value is 0 or this function is not used, it will use default ipc ram base;
49 */
bt_common_set_default_ram_base(uint32_t * ram_base)50 void bt_common_set_default_ram_base(uint32_t *ram_base)
51 {
52 for(uint8_t i = 0; i < BT_HCI_CH_NUM; i++){
53 if (ram_base[i]) {
54 bt_hci_ram_base[i] = ram_base[i];
55 TRACE("hci_ram_base %x = 0x%x\n",i,bt_hci_ram_base[i]);
56 }
57 }
58 }
59
bt_common_get_default_ram_base(void)60 uint32_t *bt_common_get_default_ram_base(void)
61 {
62 return &bt_hci_ram_base[0];
63 }
64
bt_common_get_patch_init_desc(void)65 struct csbt_patch_init_desc *bt_common_get_patch_init_desc(void)
66 {
67 struct csbt_patch_init_desc *desc;
68
69 #ifdef CFG_BTDM_RAM_VER
70 //TODO
71 desc = NULL;
72 #else
73 uint8_t rom_ver;
74 #if (CFG_ROM_VER == 255)
75 rom_ver = ChipRomVerGet();
76 #else
77 rom_ver = CFG_ROM_VER;
78 #endif
79
80 switch (rom_ver) {
81 case 0x02: {
82 desc = &patch_init_desc;
83 desc->chip_id = CSBT_CHIP_ID_U02;
84 desc->adid_size = CSBT_ADID_SIZE_U02;
85 desc->adid_ram_base_addr = (uint8_t *)CSBT_ADID_RAM_BASE_ADDR_U02;
86 desc->adid_rom_base_addr = (uint8_t *)CSBT_ADID_ROM_BASE_ADDR_U02;
87 desc->patch_base_addr = (uint8_t *)CSBT_PATCH_BASE_ADDR_U02;
88 desc->patch_data_ptr = (uint8_t *)CSBT_PATCH_DATA_PTR_U02;
89 desc->patch_data_size = CSBT_PATCH_DATA_SIZE_U02;
90 desc->patch_table_ptr = (uint8_t *)CSBT_PATCH_TABLE_PTR_U02;
91 desc->patch_table_size = CSBT_PATCH_TABLE_SIZE_U02;
92 desc->head = NULL;
93 break;
94 }
95 case 0x03: {
96 desc = &patch_init_desc;
97 desc->chip_id = CSBT_CHIP_ID_U03;
98 desc->adid_size = CSBT_ADID_SIZE_U03;
99 desc->adid_ram_base_addr = (uint8_t *)CSBT_ADID_RAM_BASE_ADDR_U03;
100 desc->adid_rom_base_addr = (uint8_t *)CSBT_ADID_ROM_BASE_ADDR_U03;
101 desc->patch_base_addr = (uint8_t *)CSBT_PATCH_BASE_ADDR_U03;
102 desc->patch_data_ptr = (uint8_t *)CSBT_PATCH_DATA_PTR_U03;
103 desc->patch_data_size = CSBT_PATCH_DATA_SIZE_U03;
104 desc->patch_table_ptr = (uint8_t *)CSBT_PATCH_TABLE_PTR_U03;
105 desc->patch_table_size = CSBT_PATCH_TABLE_SIZE_U03;
106 desc->head = NULL;
107 break;
108 }
109 case 0x04: {
110 desc = &patch_init_desc;
111 desc->chip_id = CSBT_CHIP_ID_U04;
112 desc->adid_size = CSBT_ADID_SIZE_U04;
113 desc->adid_ram_base_addr = (uint8_t *)CSBT_ADID_RAM_BASE_ADDR_U04;
114 desc->adid_rom_base_addr = (uint8_t *)CSBT_ADID_ROM_BASE_ADDR_U04;
115 desc->patch_base_addr = (uint8_t *)CSBT_PATCH_BASE_ADDR_U04;
116 desc->patch_data_ptr = (uint8_t *)CSBT_PATCH_DATA_PTR_U04;
117 desc->patch_data_size = CSBT_PATCH_DATA_SIZE_U04;
118 desc->patch_table_ptr = (uint8_t *)CSBT_PATCH_TABLE_PTR_U04;
119 desc->patch_table_size = CSBT_PATCH_TABLE_SIZE_U04;
120 desc->head = NULL;
121 break;
122 }
123 default:
124 desc = NULL;
125 break;
126 }
127 #endif
128
129 return desc;
130 }
131
132 /*
133 * bt_common_change_fw_load_in_ram
134 * only used for debug fw in ram addr ,fw in rom will mask this function.
135 */
bt_common_change_fw_load_in_ram(void)136 void bt_common_change_fw_load_in_ram(void)
137 {
138 uint32_t mb_base[BT_HCI_CH_NUM] = {(0x00170000 + 0x10000 - 0x100)};
139 bt_common_set_default_ram_base(&mb_base[0]);
140 bt_common_set_defalut_fw_addr(CSBT_FW_RAM_START_ADDR);
141 }
142
143
144