1 /*
2 * Copyright (c) 2021 Chipsea Technologies (Shenzhen) Corp., Ltd. All rights reserved.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15 /*chipsea_ohos proguard begin*/
16 #include "cs_proguard.h"
17 /*chipsea_ohos proguard end*/
18 #include "al_rtos.h"
19 #include "cs_target_config.h"
20 #include "bt_cs8800_drvif.h"
21 #ifndef CFG_BLE_ONLY
22 #include "bt_task.h"
23 #include "bt_task_msg.h"
24 #include "cs_adp_api.h"
25 #include "app_bt_queue.h"
26 #else
27 #include "ble_task.h"
28 #include "ble_task_msg.h"
29 #include "cs_ble_adp_api.h"
30 #endif
31 #include "dma_api.h"
32 #include "ce_api.h"
33 #include "reg_sysctrl.h"
34 #include <string.h>
35 #include "stdlib.h"
36 #if AON_SUPPORT == 1
37 #include "cs_bt_aon_sram.h"
38 #endif
39 #include "sysctrl_api.h"
40 #if (PLF_BT_STACK || PLF_BLE_STACK) && (PLF_WIFI_STACK && !defined(CFG_HOSTIF))
41 #include "wb_coex.h"
42 #endif
43 #include "reg_access_wrapper.h"
44 #include "reg_iomux.h"
45 #include "reg_ipc_comreg.h"
46 #include "reg_ipc_app.h"
47 #include "sleep_api.h"
48 #include "bt_patch_table.h"
49 #include "compiler.h"
50 #include "system.h"
51
52 extern void bt_drv_poweron(uint8_t en);
53
54
55 /************************************************************
56 bt driver default param config
57
58 ************************************************************/
59 static uint8_t table_index = 0;
60 uint32_t fw_mem_wr_table[][2] =
61 {
62 //disble uart1 irq in fw
63 //{0xe000e180,0x00020000},
64 };
65
66 #define GWB_AGC 0
67 #define GEN_ACI 0
68
69 static uint16_t mdm_table_index = 0;
70
71 const uint32_t rf_mdm_regs_table_bt_only[][2] =
72 {
73 #if (PLF_HW_ASIC == 1)
74 //@ btrf
75 #if (PLF_WIFI_STACK == 0)
76 {0x40580104, 0x000923FB},//for product bt only
77 #else
78 {0x40580104, 0x000933FB},//for product bt+wifi
79 #endif
80 {0x4062201C, 0x0008D000},
81 {0x40622028, 0x48912020},//dvdd=1.18v
82 {0x40622014, 0x00018983},
83 {0x40622054, 0x00008F34},
84 {0x40620748, 0x021A01A0},
85 {0x40620728, 0x00010020},
86 {0x40620738, 0x04800FD4},
87 {0x4062073C, 0x00C80064},
88 {0x4062202C, 0x000CB220},
89 {0x4062200C, 0xE9AD2B45},
90 #if (APP_SUPPORT_TWS == 1)
91 // dpll for rx = 208m, (tws slave must use this config)
92 {0x40622030, 0x143C30D2},
93 #else
94 // dpll for rx = 52m
95 {0x40622030, 0x140C30D2},
96 #endif
97 //{0x40622000, 0x00000000},//default value
98 {0x40622034, 0x00001602},
99 {0x40620754, 0x214220FD},
100 {0x40620758, 0x0007F01E},
101 {0x4062071C, 0x00000A33},
102 {0x40622018, 0x00124124},
103 {0x4062000C, 0x04040000},
104 //@ btrf tx
105 {0x40620090, 0x00069082},
106 {0x40621034, 0x02003080},
107 {0x40621014, 0x0445117A},
108 {0x40622024, 0x00001100},
109 {0x40622004, 0x0001A9C0},
110
111 //@ pwr up time
112 {0x4060048C, 0x00500834},
113 {0x40600110, 0x027E0058},
114 {0x40600880, 0x00500834},
115 {0x40600884, 0x00500834},
116 {0x40600888, 0x00500834},
117 {0x4060088C, 0x00000834},
118
119 #if GWB_AGC
120 //@ wb agc
121 {0x40620518, 0x3090880A},
122 {0x40620514, 0xA80C1A10},
123 {0x40620510, 0x1466FF0A},
124 {0x406205B8, 0x00000000},
125 {0x4062050C, 0x0A202013},
126
127 {0x406205A0, 0x12140505},
128 {0x406205A4, 0x42302E24},
129 #else
130 //@ nb agc
131 {0x40620518, 0x3692880A},// rsten_srrc
132 {0x40620514, 0xA80C1A10},// dagc=0
133 {0x4062052C, 0x9C0C1403},// dagc=3, lr
134 {0x4062050C, 0x20202013},
135 {0x406205A0, 0x14150C00},
136 {0x406205A4, 0x362D3624},
137 {0x406205F0, 0x0000FF00},
138 #endif
139 //@ cm agc
140 {0x40620508, 0x54553132},
141 {0x40620530, 0x13171200},
142 {0x40620534, 0x00000074},
143 {0x406205B0, 0x00005355},
144 //@ dc
145 {0x4062051C, 0x964B5766},
146 #if GEN_ACI
147 {0x40621878, 0x00000002},
148 {0x4062157C, 0x00000040},
149 {0x40621580, 0x00000040},
150 {0x40621560, 0x051B1200},
151 {0x40621564, 0x051B2200},
152 {0x40621560, 0x09145640},
153 {0x40621564, 0x051B1201},
154 #endif
155 #endif
156 };
157
158 const uint32_t rf_mdm_regs_table_bt_combo[][2] =
159 {
160 #if (PLF_HW_ASIC == 1)
161 //@ btrf
162 #if (PLF_WIFI_STACK == 0)
163 {0x40580104, 0x000923FB},//for product bt only
164 #else
165 {0x40580104, 0x000933FB},//for product bt+wifi
166 #endif
167 {0x40344020, 0x00000B77},
168 {0x40344024, 0x006EC594},
169 {0x40344028, 0x00009402},
170 {0x4034402C, 0x56201884},
171 {0x40344030, 0x1A2E5168},
172
173 //@ pwr up time
174 {0x4060048C, 0x00500834},
175 {0x40600110, 0x027E0058},
176 {0x40600880, 0x00500834},
177 {0x40600884, 0x00500834},
178 {0x40600888, 0x00500834},
179 {0x4060088C, 0x00000834},
180
181 #if GWB_AGC
182 //@ wb agc
183 {0x40620518, 0x3090880A},
184 {0x40620514, 0xA80C1A10},
185 {0x40620510, 0x1466FF0A},
186 {0x406205B8, 0x00000000},
187 {0x4062050C, 0x0A202013},
188
189 {0x40620508, 0x54553032},
190 {0x406205A0, 0x1810120F},
191 {0x406205A4, 0x372E2F2E},
192 {0x406205F0, 0x00000077},
193 #else
194 //@ nb agc
195 {0x40620518, 0x3692880A},// rsten_srrc
196 {0x40620514, 0xA80C1A10},// dagc=0
197 {0x4062052C, 0x9C0C1403},// dagc=3, lr
198 {0x4062050C, 0x20202013},
199 {0x40620508, 0x54553132},
200 {0x406205A0, 0x0F171600},
201 {0x406205A4, 0x36283636},
202 {0x406205F0, 0x0000FF00},
203 #endif
204 //@ cm agc
205 {0x40620530, 0x13171A00},
206 {0x40620534, 0x00000076},
207 {0x406205B0, 0x00005355},
208 //@ dc
209 {0x4062051C, 0x964B5766},
210 //@ 26m cic
211 {0x40620090, 0x00050032},
212 //@ srrc rolloff = 0.305
213 {0x40621010, 0x12000143},
214 #if GEN_ACI
215 {0x40621878, 0x00000002},
216 {0x4062157C, 0x00000040},
217 {0x40621580, 0x00000040},
218 {0x40621560, 0x051B1200},
219 {0x40621564, 0x051B2200},
220 {0x40621560, 0x09145640},
221 {0x40621564, 0x051B1201},
222 #endif
223 #endif
224 };
225 #if 0//def CFG_WIFI_BT_COMBO
226 const BtDrvRfModeEnum bt_rf_mode = DRV_RF_MODE_BTWIFI_COMBO;
227 const bt_drv_rf_calib_req_cmd rf_calib_req = {DRV_RF_MODE_BTWIFI_COMBO, 0x0000, {0x04, {0x03,0x42,0x26,0x00}}};
228 #else
229 const BtDrvRfModeEnum bt_rf_mode = DRV_RF_MODE_BT_ONLY;
230 const bt_drv_rf_calib_req_cmd rf_calib_req = {DRV_RF_MODE_BT_ONLY, 0x0000, {0x08, {0x03,0x42,0x26,0x00,0x0f,0x30,0x02,0x00}}};
231 #endif
232 const uint16_t page_timeout_default_value = 0x2000;
233 const uint8_t local_feature[8] = {0xbf,0xee,0xcd,0xfa,0xd8,0x3f,0x7b,0x87};
234 #ifdef CFG_BTDM_RAM_VER
235 #if PLF_PMIC
236 #define AON_BT_PWR_ON_DLY1 (1 + 5)//+5 for safe(not necessary)
237 #define AON_BT_PWR_ON_DLY2 (10 + 48 + 5)//+48 for dp_open_delay, +5 for safe
238 #define AON_BT_PWR_ON_DLY3 (12 + 48 + 8 + 5)//+8 for more dp_open_delay than AON_BT_PWR_ON_DLY2, +5 for safe
239 #define AON_BT_PWR_ON_DLY_AON (11 + 48 + 8 + 5)//+8 for more dp_open_delay than AON_BT_PWR_ON_DLY2, +5 for safe
240 #else
241 #define AON_BT_PWR_ON_DLY1 (1)
242 #define AON_BT_PWR_ON_DLY2 (10)
243 #define AON_BT_PWR_ON_DLY3 (12)
244 #define AON_BT_PWR_ON_DLY_AON (11)
245 #endif
246 const bt_drv_wr_aon_param wr_aon_param =
247 {
248 0x18D700, 0x18F700, 64, 40, 400, 400, 3, 2,
249 3, 2, 40, 512, 20, 21, 20, 32,
250 8, 0, 0, 20000, 0x101, 0x20067302, AON_BT_PWR_ON_DLY1, AON_BT_PWR_ON_DLY2,
251 AON_BT_PWR_ON_DLY3, AON_BT_PWR_ON_DLY_AON, 32, 360, 420, 100, 100, 8,
252 24, 40, 140, 0, 64, 20000, 50
253 };
254 #else
255 #if PLF_PMIC
256 #define AON_BT_PWR_ON_DLY1_U02 (1 + 5)//+5 for safe(not necessary)
257 #define AON_BT_PWR_ON_DLY2_U02 (10 + 48 + 5)//+48 for dp_open_delay, +5 for safe
258 #define AON_BT_PWR_ON_DLY3_U02 (12 + 48 + 8 + 5)//+8 for more dp_open_delay than AON_BT_PWR_ON_DLY2, +5 for safe
259 #define AON_BT_PWR_ON_DLY_AON_U02 (11 + 48 + 8 + 5)//+8 for more dp_open_delay than AON_BT_PWR_ON_DLY2, +5 for safe
260 #define AON_BT_PWR_ON_DLY1_U03 (1 + 5)//+5 for safe(not necessary)
261 #define AON_BT_PWR_ON_DLY2_U03 (10 + 48 + 5)//+48 for dp_open_delay, +5 for safe
262 #define AON_BT_PWR_ON_DLY3_U03 (12 + 48 + 8 + 5)//+8 for more dp_open_delay than AON_BT_PWR_ON_DLY2, +5 for safe
263 #define AON_BT_PWR_ON_DLY_AON_U03 (11 + 48 + 8 + 5)//+8 for more dp_open_delay than AON_BT_PWR_ON_DLY2, +5 for safe
264
265 #define AON_BT_PWR_ON_DLY1x(v) MCAT(AON_BT_PWR_ON_DLY1_U0, v)
266 #define AON_BT_PWR_ON_DLY1 AON_BT_PWR_ON_DLY1x(CFG_ROM_VER)
267 #define AON_BT_PWR_ON_DLY2x(v) MCAT(AON_BT_PWR_ON_DLY2_U0, v)
268 #define AON_BT_PWR_ON_DLY2 AON_BT_PWR_ON_DLY2x(CFG_ROM_VER)
269 #define AON_BT_PWR_ON_DLY3x(v) MCAT(AON_BT_PWR_ON_DLY3_U0, v)
270 #define AON_BT_PWR_ON_DLY3 AON_BT_PWR_ON_DLY3x(CFG_ROM_VER)
271 #define AON_BT_PWR_ON_DLY_AONx(v) MCAT(AON_BT_PWR_ON_DLY_AON_U0, v)
272 #define AON_BT_PWR_ON_DLY_AON AON_BT_PWR_ON_DLY_AONx(CFG_ROM_VER)
273 #else
274 #define AON_BT_PWR_ON_DLY1 (1)
275 #define AON_BT_PWR_ON_DLY1x(v) AON_BT_PWR_ON_DLY1
276 #define AON_BT_PWR_ON_DLY2 (10)
277 #define AON_BT_PWR_ON_DLY2x(v) AON_BT_PWR_ON_DLY2
278 #define AON_BT_PWR_ON_DLY3 (12)
279 #define AON_BT_PWR_ON_DLY2x(v) AON_BT_PWR_ON_DLY3
280 #define AON_BT_PWR_ON_DLY_AON (11)
281 #define AON_BT_PWR_ON_DLY_AONx(v) AON_BT_PWR_ON_DLY_AON
282 #endif
283
284 const bt_drv_wr_aon_param VAR_WITH_VERx(wr_aon_param, 2) =
285 {
286 0x16D700, 0x16F680, 64, 40, 400, 400, 3, 2,
287 3, 2, 40, 512, 20, 21, 20, 32,
288 8, -2, 0, 20000, 0x101, 0x20067302, AON_BT_PWR_ON_DLY1x(2), AON_BT_PWR_ON_DLY2x(2),
289 AON_BT_PWR_ON_DLY3x(2), AON_BT_PWR_ON_DLY_AONx(2), 32, 360, 420, 100, 100, 8,
290 24, 40, 140, 0, 64, 20000, 50
291 };
292
293 const bt_drv_wr_aon_param VAR_WITH_VERx(wr_aon_param, 3) =
294 {
295 0x16D700, 0x16F680, 64, 40, 400, 400, 3, 2,
296 3, 2, 40, 512, 20, 21, 20, 32,
297 8, -2, 0, 20000, 0x101, 0x20067302, AON_BT_PWR_ON_DLY1x(3), AON_BT_PWR_ON_DLY2x(3),
298 AON_BT_PWR_ON_DLY3x(3), AON_BT_PWR_ON_DLY_AONx(3), 32, 360, 420, 100, 100, 8,
299 24, 40, 140, 0, 64, 20000, 50
300 };
301 #endif
302
303 const bt_drv_wr_aon_param *wr_aon_param_ptr;
304 uint32_t aon_debug_level;
305
306 /*
307 *
308 * BT_LP_LEVEL_ACTIVE = 0x00,//BT CORE active, CPUSYS active, VCORE active
309 * BT_LP_LEVEL_CLOCK_GATE1 = 0x01,//BT CORE clock gate, CPUSYS active, VCORE active
310 * BT_LP_LEVEL_CLOCK_GATE2 = 0x02,//BT CORE clock gate, CPUSYS clock gate, VCORE active
311 * BT_LP_LEVEL_CLOCK_GATE3 = 0x03,//BT CORE clock gate, CPUSYS clock gate, VCORE clock_gate
312 * BT_LP_LEVEL_POWER_OFF1 = 0x04,//BT CORE power off, CPUSYS active, VCORE active
313 * BT_LP_LEVEL_POWER_OFF2 = 0x05,//BT CORE power off, CPUSYS clock gate, VCORE active
314 * BT_LP_LEVEL_POWER_OFF3 = 0x06,//BT CORE power off, CPUSYS power off, VCORE active
315 * BT_LP_LEVEL_HIBERNATE = 0x07,//BT CORE power off, CPUSYS power off, VCORE power off
316 * BT_LP_LEVEL_NUM = 0x08,
317 */
318 #if APP_SLEEP_LEVEL == 0
319 uint8_t bt_lp_level = BT_LP_LEVEL_ACTIVE;
320 #elif APP_SLEEP_LEVEL == 1
321 uint8_t bt_lp_level = BT_LP_LEVEL_CLOCK_GATE2;
322 #elif APP_SLEEP_LEVEL == 2
323 uint8_t bt_lp_level = BT_LP_LEVEL_POWER_OFF3;
324 #elif APP_SLEEP_LEVEL == 3
325 uint8_t bt_lp_level = BT_LP_LEVEL_HIBERNATE;
326 #else
327 uint8_t bt_lp_level = BT_LP_LEVEL_ACTIVE;
328 #endif
329
330 uint8_t pwr_ctrl_slave = 1;
331
332 uint8_t bt_sleep_debug_level = 0xFF;
333
334 /************************************************************/
335
336 //bt default param set
337
bt_drv_fw_mem_table_isneeded_get(void)338 bool bt_drv_fw_mem_table_isneeded_get(void)
339 {
340 bool ret = false;
341 uint32_t remain_size = 0;
342 remain_size = sizeof(fw_mem_wr_table)/sizeof(fw_mem_wr_table[0]) - table_index;
343 if(remain_size)
344 ret = true;
345 return ret;
346 }
347
348
bt_drv_fw_mem_table_entry_get(uint32_t * addr,uint32_t * val)349 bool bt_drv_fw_mem_table_entry_get(uint32_t *addr, uint32_t *val)
350 {
351 bool ret = false;
352 if (sizeof(fw_mem_wr_table) == 0 || table_index > (sizeof(fw_mem_wr_table)/sizeof(fw_mem_wr_table[0])-1))
353 return ret;
354 *addr = fw_mem_wr_table[table_index][0];
355 *val = fw_mem_wr_table[table_index][1];
356 table_index++;
357 ret = true;
358 return ret;
359 }
360
361
362
bt_drv_rf_mdm_regs_table_isneeded_get(void)363 bool bt_drv_rf_mdm_regs_table_isneeded_get(void)
364 {
365 bool ret = false;
366 uint32_t remain_size = 0;
367
368 if (bt_rf_mode == DRV_RF_MODE_BT_ONLY) {
369 remain_size = sizeof(rf_mdm_regs_table_bt_only)/sizeof(rf_mdm_regs_table_bt_only[0]) - mdm_table_index;
370 } else if ((bt_rf_mode == DRV_RF_MODE_BT_COMBO) || (bt_rf_mode == DRV_RF_MODE_BTWIFI_COMBO)) {
371 remain_size = sizeof(rf_mdm_regs_table_bt_combo)/sizeof(rf_mdm_regs_table_bt_combo[0]) - mdm_table_index;
372 }
373
374 if(remain_size)
375 ret = true;
376
377 return ret;
378 }
379
bt_drv_rf_mdm_regs_table_entry_get(uint32_t * addr,uint32_t * val)380 bool bt_drv_rf_mdm_regs_table_entry_get(uint32_t *addr, uint32_t *val)
381 {
382 bool ret = false;
383
384 if (bt_rf_mode == DRV_RF_MODE_BT_ONLY) {
385 if (sizeof(rf_mdm_regs_table_bt_only) == 0 || mdm_table_index > (sizeof(rf_mdm_regs_table_bt_only)/sizeof(rf_mdm_regs_table_bt_only[0])-1))
386 return ret;
387 *addr = rf_mdm_regs_table_bt_only[mdm_table_index][0];
388 *val = rf_mdm_regs_table_bt_only[mdm_table_index][1];
389 } else if ((bt_rf_mode == DRV_RF_MODE_BT_COMBO) || (bt_rf_mode == DRV_RF_MODE_BTWIFI_COMBO)) {
390 if (sizeof(rf_mdm_regs_table_bt_combo) == 0 || mdm_table_index > (sizeof(rf_mdm_regs_table_bt_combo)/sizeof(rf_mdm_regs_table_bt_combo[0])-1))
391 return ret;
392 *addr = rf_mdm_regs_table_bt_combo[mdm_table_index][0];
393 *val = rf_mdm_regs_table_bt_combo[mdm_table_index][1];
394 } else {
395 return ret;
396 }
397
398 mdm_table_index++;
399
400 ret = true;
401
402 return ret;
403 }
404
405
cs_bt_start(void)406 void cs_bt_start(void)
407 {
408 if (!bt_get_fw_init_complete()) {
409 #ifdef CFG_BTDM_RAM_VER
410 wr_aon_param_ptr = &wr_aon_param;
411 #else
412 #if (CFG_ROM_VER == 255)
413 uint8_t chip_id = ChipIdGet(0);
414 if (chip_id == 0x03) {
415 wr_aon_param_ptr = &VAR_WITH_VERx(wr_aon_param, 2);
416 } else if (chip_id == 0x07) {
417 wr_aon_param_ptr = &VAR_WITH_VERx(wr_aon_param, 3);
418 }
419 #else
420 wr_aon_param_ptr = &VAR_WITH_VER(wr_aon_param);
421 #endif
422 bt_patch_prepare();
423 #endif
424 aon_debug_level = wr_aon_param_ptr->aon_debug_level;
425 bt_drv_poweron(BT_POWERON);
426 }
427 }
428 /************************************************************
429 *
430 * bt driver api which is diffrent for bt or (ble only) mode.
431 *
432 ************************************************************/
bt_drv_ecc_key_complete_notify(void)433 void bt_drv_ecc_key_complete_notify(void)
434 {
435 #ifndef CFG_BLE_ONLY
436 app_bt_generate_key_complete();
437 #else
438 cs_adp_send_generate_key_ble_only();
439 #endif
440 }
441
bt_drv_task_notify(bool isr)442 void bt_drv_task_notify(bool isr)
443 {
444 #ifndef CFG_BLE_ONLY
445 bt_task_queue_notify(isr);
446 #else
447 ble_task_queue_notify(isr);
448 #endif
449 }
450
451 /************************************************************
452 *
453 * bt driver send hci cmd directly
454 *
455 ************************************************************/
bt_drv_send_data(const uint8_t * buff,uint8_t len)456 void bt_drv_send_data(const uint8_t *buff,uint8_t len)
457 {
458 #ifndef CFG_BLE_ONLY
459 cs_adp_send_hci_data_direct(buff, len);
460 #else
461 cs_adp_send_hci_data_direct_ble_only(buff, len);
462 #endif
463 }
464
bt_drv_lp_level_set(uint8_t level)465 void bt_drv_lp_level_set(uint8_t level)
466 {
467 #ifndef CFG_BLE_ONLY
468 app_bt_set_lp_level(level);
469 #else
470 app_ble_lp_level_msg_send(level);
471 #endif
472 }
473
474 const uint8_t hci_dbg_evt_filter[] =
475 {
476 0x01,0x05, 0x0c, 0x03, 0x02, 0x00, 0x02
477 };//auto accept connect
478
479 const uint8_t hci_dbg_enable_dut[] =
480 {
481 0x01,0x03, 0x18, 0x00
482 };
483 const uint8_t hci_dbg_enable_allscan[] =
484 {
485 0x01, 0x1a, 0x0c, 0x01, 0x03
486 };
487 const uint8_t hci_dbg_enable_pagescan[] =
488 {
489 0x01, 0x1a, 0x0c, 0x01, 0x02
490 };
491
492 const uint8_t hci_dbg_enable_inquiryscan[] =
493 {
494 0x01, 0x1a, 0x0c, 0x01, 0x01
495 };
496
497 const uint8_t hci_dbg_enable_noscan[] =
498 {
499 0x01, 0x1a, 0x0c, 0x01, 0x00
500 };
501
bt_drv_enable_dut(void)502 void bt_drv_enable_dut(void)
503 {
504 bt_drv_send_data(hci_dbg_evt_filter, sizeof(hci_dbg_evt_filter));
505 bt_drv_send_data(hci_dbg_enable_allscan, sizeof(hci_dbg_enable_allscan));
506 bt_drv_send_data(hci_dbg_enable_dut, sizeof(hci_dbg_enable_dut));
507 }
508
bt_drv_scan_en(uint32_t scan_en)509 void bt_drv_scan_en(uint32_t scan_en)
510 {
511 if (scan_en == 0) {
512 bt_drv_send_data(hci_dbg_enable_noscan, sizeof(hci_dbg_enable_noscan));
513 } else if (scan_en == 1) {
514 bt_drv_send_data(hci_dbg_enable_inquiryscan, sizeof(hci_dbg_enable_inquiryscan));
515 } else if (scan_en == 2) {
516 bt_drv_send_data(hci_dbg_enable_pagescan, sizeof(hci_dbg_enable_pagescan));
517 } else if (scan_en == 3) {
518 bt_drv_send_data(hci_dbg_enable_allscan, sizeof(hci_dbg_enable_allscan));
519 }
520 }
521