1 /*
2 * Copyright (c) 2021 Chipsea Technologies (Shenzhen) Corp., Ltd. All rights reserved.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15 #ifndef __BT_CS8800_DRIVER_H__
16 #define __BT_CS8800_DRIVER_H__
17 #include "compiler.h"
18 #include "reg_access_wrapper.h"
19
20 #define BT_POWERON 1
21 #define BT_POWEROFF 0
22
23
24 /// 8 bit access types
25 #define _8_Bit 8
26 /// 16 bit access types
27 #define _16_Bit 16
28 /// 32 bit access types
29 #define _32_Bit 32
30
31 #ifndef RWIP_TIME_T
32 #define RWIP_TIME_T
33 typedef struct
34 {
35 /// Integer part of the time (in half-slot)
36 uint32_t hs;
37 /// Fractional part of the time (in half-us) (range: 0-624)
38 uint32_t hus;
39 } rwip_time_t;
40
41 typedef struct
42 {
43 /// Integer part of the time (in half-slot)
44 uint32_t clk_off_hs;
45 /// Fractional part of the time (in half-us) (range: 0-624)
46 uint32_t clk_off_hus;
47 } TWS_BT_CLK_INFO_Type;
48 #endif
49
50 #define CLK_ADD_2(clock_a, clock_b) ((uint32_t)(((clock_a) + (clock_b)) & RWIP_MAX_CLOCK_TIME))
51 #define CLK_SUB(clock_a, clock_b) ((uint32_t)(((clock_a) - (clock_b)) & RWIP_MAX_CLOCK_TIME))
52 #define RWIP_MAX_CLOCK_TIME ((1L<<28) - 1)
53
54
55 typedef enum {
56 DRV_RF_MODE_NULL = 0x00,
57 DRV_RF_MODE_BT_ONLY = 0x01,
58 DRV_RF_MODE_BT_COMBO = 0x02,
59 DRV_RF_MODE_BTWIFI_COMBO = 0x03,
60 DRV_RF_MODE_NUM = 0x04
61 }BtDrvRfModeEnum;
62
63 enum {
64 BT_LP_LEVEL_POWER_OFF = 0x00,//BT CORE power off, CPUSYS power off, VCORE power off
65 BT_LP_LEVEL_CLOCK_GATE = 0x01,//BT CORE clock gate, CPUSYS clock gate, VCORE clock_gate
66 };
67
68 enum {
69 BT_LP_LEVEL_ACTIVE = 0x00,//BT CORE active, CPUSYS active, VCORE active
70 BT_LP_LEVEL_CLOCK_GATE1 = 0x01,//BT CORE clock gate, CPUSYS active, VCORE active
71 BT_LP_LEVEL_CLOCK_GATE2 = 0x02,//BT CORE clock gate, CPUSYS clock gate, VCORE active
72 BT_LP_LEVEL_CLOCK_GATE3 = 0x03,//BT CORE clock gate, CPUSYS clock gate, VCORE clock_gate
73 BT_LP_LEVEL_POWER_OFF1 = 0x04,//BT CORE power off, CPUSYS active, VCORE active
74 BT_LP_LEVEL_POWER_OFF2 = 0x05,//BT CORE power off, CPUSYS clock gate, VCORE active
75 BT_LP_LEVEL_POWER_OFF3 = 0x06,//BT CORE power off, CPUSYS power off, VCORE active
76 BT_LP_LEVEL_HIBERNATE = 0x07,//BT CORE power off, CPUSYS power off, VCORE power off
77 BT_LP_LEVEL_NUM = 0x08,
78 };
79
80 enum {
81 BT_PRV_SLP_TIMER = (0x01UL << 0),
82 BT_STACK_SLP_DISALLOW = (0x01UL << 1),
83 BLE_STACK_SLP_DISALLOW = (0x01UL << 2),
84 };
85
86 typedef struct
87 {
88 /// Em save start address
89 uint32_t em_save_start_addr;
90 /// Em save end address
91 uint32_t em_save_end_addr;
92 /// Minimum time that allow power off (in hs)
93 int32_t aon_min_power_off_duration;
94 /// Maximum aon params
95 uint16_t aon_max_nb_params;
96 /// RF config const time on cpus side (in hus)
97 int16_t aon_rf_config_time_cpus;
98 /// RF config const time on aon side (in hus)
99 int16_t aon_rf_config_time_aon;
100 /// Maximum active acl link supported by aon
101 uint16_t aon_max_nb_active_acl;
102 /// Maximum ble activity supported by aon
103 uint16_t aon_ble_activity_max;
104 /// Maximum bt rxdesc field supported by aon
105 uint16_t aon_max_bt_rxdesc_field;
106 /// Maximum ble rxdesc field supported by aon
107 uint16_t aon_max_ble_rxdesc_field;
108 /// Maximum regs supported by aon
109 uint16_t aon_max_nb_regs;
110 /// Maximum length of ke_env supported by aon
111 uint16_t aon_max_ke_env_len;
112 /// Maximum elements of sch_arb_env supported by aon
113 uint16_t aon_max_nb_sch_arb_elt;
114 /// Maximun elements of sch_plan_env supported by aon
115 uint16_t aon_max_nb_sch_plan_elt;
116 /// Maximun elements of sch_alarm_env supported by aon
117 uint16_t aon_max_nb_sch_alarm_elt;
118 /// Minimum advertising interval in slots(625 us) supported by aon
119 uint32_t aon_min_ble_adv_intv;
120 /// Minimum connection interval in 2-slots(1.25 ms) supported by aon
121 uint32_t aon_min_ble_con_intv;
122 /// Extra sleep duration for cpus(in hs), may be negative
123 int32_t aon_extra_sleep_duration_cpus;
124 /// Extra sleep duration for aon cpu(in hs), may be negative
125 int32_t aon_extra_sleep_duration_aon;
126 /// Minimum time that allow host to power off (in us)
127 int32_t aon_min_power_off_duration_cpup;
128 /// aon debug level for cpus
129 uint32_t aon_debug_level;
130 /// aon debug level for aon cpu
131 uint32_t aon_debug_level_aon;
132 /// Power on delay of bt core on when cpu_sys alive on cpus side(in lp cycles)
133 uint16_t aon_bt_pwr_on_dly1;
134 /// Power on delay of bt core when cpu_sys clock gate on cpus side(in lp cycles)
135 uint16_t aon_bt_pwr_on_dly2;
136 /// Power on delay of bt core when cpu_sys power off on cpus side(in lp cycles)
137 uint16_t aon_bt_pwr_on_dly3;
138 /// Power on delay of bt core on aon side(in lp cycles)
139 uint16_t aon_bt_pwr_on_dly_aon;
140 /// Time to cancel sch arbiter elements in advance when switching to cpus (in hus)
141 uint16_t aon_sch_arb_cancel_in_advance_time;
142 /// Duration of sleep and wake-up algorithm (depends on CPU speed) expressed in half us on cpus side
143 /// should also contian deep_sleep_on rising edge to finecnt halt (max 4 lp cycles) and finecnt resume to dm_slp_irq (0.5 lp cycles)
144 uint16_t aon_sleep_algo_dur_cpus;
145 /// Duration of sleep and wake-up algorithm (depends on CPU speed) expressed in half us on aon side
146 /// should also contian deep_sleep_on rising edge to finecnt halt (max 4 lp cycles) and finecnt resume to dm_slp_irq (0.5 lp cycles)
147 uint16_t aon_sleep_algo_dur_aon;
148 /// Threshold that treat fractional part of restore time (in hus) as 1hs on cpus side
149 uint16_t aon_restore_time_ceil_cpus;
150 /// Threshold that treat fractional part of restore time (in hus) as 1hs on aon side
151 uint16_t aon_restore_time_ceil_aon;
152 /// Minimum time that allow deep sleep on cpus side (in hs)
153 uint16_t aon_min_sleep_duration_cpus;
154 /// Minimum time that allow deep sleep on aon side (in hs)
155 uint16_t aon_min_sleep_duration_aon;
156 /// Difference of restore time and save time on cpus side (in hus)
157 int16_t aon_restore_save_time_diff_cpus;
158 /// Difference of restore time and save time on aon side (in hus)
159 int16_t aon_restore_save_time_diff_aon;
160 /// Difference of restore time on aon side and save time on cpus side (in hus)
161 int16_t aon_restore_save_time_diff_cpus_aon;
162 /// Minimum time that allow clock gate (in hs)
163 int32_t aon_min_clock_gate_duration;
164 /// Minimum time that allow host to clock gate (in us)
165 int32_t aon_min_clock_gate_duration_cpup;
166 /// Maximum rf & mdm regs supported by aon
167 uint16_t aon_max_nb_rf_mdm_regs;
168 }bt_drv_wr_aon_param;
169
170 /// Buffer structure
171 struct bt_buffer_tag
172 {
173 /// length of buffer
174 uint8_t length;
175 /// data of 128 bytes length
176 uint8_t data[128];
177 };
178
179 typedef struct
180 {
181 uint8_t calib_type;
182 uint16_t offset;
183 struct bt_buffer_tag buf;
184 }bt_drv_rf_calib_req_cmd;
185
186 ///HCI Debug wr rf mdm regs command parameters - vendor specific
187 typedef struct
188 {
189 /// offset
190 uint16_t offset;
191 // reserved
192 uint8_t reserved;
193 /// length
194 uint8_t length;
195 /// data (addr<32bits> value<32bits> addr<32bits> value<32bits> ...)
196 uint8_t data[248];
197 }hci_dbg_wr_rf_mdm_regs_cmd;
198
199 #define RF_MDM_REGS_MAX_DATA_SIZE 30// (248/8 = 31)-1
200
201
202 /**
203 * @brief CLKNCNTRAW register definition
204 * <pre>
205 * Bits Field Name Reset Value
206 * ----- ------------------ -----------
207 * 27:00 CLKNCNTRAW 0x0
208 * </pre>
209 */
210 #define IP_CLKNCNTRAW_ADDR 0x40600048
211 #define IP_CLKNCNTRAW_OFFSET 0x00000048
212 #define IP_CLKNCNTRAW_INDEX 0x00000012
213 #define IP_CLKNCNTRAW_RESET 0x00000000
214
ip_clkncntraw_get(void)215 __INLINE uint32_t ip_clkncntraw_get(void)
216 {
217 return IP_REG_READ(IP_CLKNCNTRAW_ADDR);
218 }
219 /**
220 * @brief FINECNTRAW register definition
221 * <pre>
222 * Bits Field Name Reset Value
223 * ----- ------------------ -----------
224 * 09:00 FINECNTRAW 0x0
225 * </pre>
226 */
227 #define IP_FINECNTRAW_ADDR 0x4060004C
228 #define IP_FINECNTRAW_OFFSET 0x0000004C
229 #define IP_FINECNTRAW_INDEX 0x00000013
230 #define IP_FINECNTRAW_RESET 0x00000000
231
ip_finecntraw_get(void)232 __INLINE uint32_t ip_finecntraw_get(void)
233 {
234 return IP_REG_READ(IP_FINECNTRAW_ADDR);
235 }
236
237 #endif
238