1 // Copyright (C) 2022 Beken Corporation 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 #include <components/log.h> 18 #include "clock_hal.h" 19 20 #if (CONFIG_SOC_BK7256XX) //bk7256 to do 21 #include "sys_hal.h" 22 23 #define clk_set_uart_clk_26m(id) sys_hal_uart_select_clock(id,UART_SCLK_XTAL_26M) 24 25 #define clk_set_spi_clk_26m(id) //sys_hal_set_clksel_spi(SPI_CLK_SRC_XTAL) 26 #define clk_set_spi_clk_dco(id) //sys_hal_set_clksel_spi(SPI_CLK_SRC_UNKNOW)//spi don't support DCO clock source 27 28 #define clk_enable_saradc_audio_pll() //do nothing 29 #define clk_disable_saradc_audio_pll() //do nothing 30 #define clk_set_saradc_clk_26m() sys_hal_set_cksel_sadc(0) 31 #define clk_set_saradc_clk_dco() sys_hal_set_cksel_sadc(1) 32 33 #define clk_set_pwms_clk_26m() sys_hal_set_cksel_pwm(1) 34 #define clk_set_pwms_clk_dco() //pwm don't support DCO clock source 35 #define clk_enable_pwm_clk_lpo(chan) //pwm don't support lpo clock source 36 #define clk_disable_pwm_clk_lpo(chan) //pwm don't support lpo clock source 37 38 #define clk_set_qspi_clk_26m() //do nothing 39 #define clk_set_qspi_clk_dco() //do nothing 40 #define clk_set_qspi_clk_120m() //do nothing 41 #define clk_set_qspi_clk_80m() //do nothing 42 43 #define clk_get_uart_clk(id) sys_hal_uart_select_clock_get(id) 44 #else 45 #include "icu_driver.h" 46 47 extern icu_driver_t s_icu; 48 49 /**< clock source division APIs: 26M XTAL division only for gpio output clock*/ 50 #define clk_set_dco_1_div() clock_hal_set_dco_1_div(&s_icu.hal) 51 #define clk_set_dco_2_div() clock_hal_set_dco_2_div(&s_icu.hal) 52 #define clk_set_dco_4_div() clock_hal_set_dco_4_div(&s_icu.hal) 53 #define clk_set_dco_8_div() clock_hal_set_dco_8_div(&s_icu.hal) 54 55 56 #define clk_set_26m_1_div() clock_hal_set_26m_1_div(&s_icu.hal) 57 #define clk_set_26m_2_div() clock_hal_set_26m_2_div(&s_icu.hal) 58 #define clk_set_26m_4_div() clock_hal_set_26m_4_div(&s_icu.hal) 59 #define clk_set_26m_8_div() clock_hal_set_26m_8_div(&s_icu.hal) 60 61 #define clk_set_uart_clk_26m(id) clock_hal_uart_set_clk_26m(&s_icu.hal, id) 62 #define clk_set_uart_clk_dco(id) clock_hal_uart_set_clk_dco(&s_icu.hal, id) 63 64 #define clk_set_i2c_clk_26m(id) clock_hal_i2c_set_clk_26m(&s_icu.hal, id) 65 #define clk_set_i2c_clk_dco(id) clock_hal_i2c_set_clk_dco(&s_icu.hal, id) 66 67 #define clk_set_irda_clk_26m() clock_hal_irda_set_clk_26m(&s_icu.hal) 68 #define clk_set_irda_clk_dco() clock_hal_irda_set_clk_dco(&s_icu.hal) 69 70 #define clk_set_spi_clk_26m(id) clock_hal_spi_set_clk_26m(&s_icu.hal, id) 71 #define clk_set_spi_clk_dco(id) clock_hal_spi_set_clk_dco(&s_icu.hal, id) 72 73 #define clk_enable_saradc_audio_pll() clock_hal_saradc_enable_audio_pll(&s_icu.hal) 74 #define clk_disable_saradc_audio_pll() clock_hal_saradc_disable_audio_pll(&s_icu.hal) 75 #define clk_set_saradc_clk_26m() clock_hal_saradc_set_clk_26m(&s_icu.hal) 76 #define clk_set_saradc_clk_dco() clock_hal_saradc_set_clk_dco(&s_icu.hal) 77 78 #define clk_set_pwms_clk_26m() clock_hal_pwms_set_clk_26m(&s_icu.hal) 79 #define clk_set_pwms_clk_dco() clock_hal_pwms_set_clk_dco(&s_icu.hal) 80 #define clk_enable_pwm_clk_lpo(chan) clock_hal_enable_pwm_lpo_clk(&s_icu.hal, chan) 81 #define clk_disable_pwm_clk_lpo(chan) clock_hal_disable_pwm_lpo_clk(&s_icu.hal, chan) 82 83 #define clk_set_sdio_clk_26m() clock_hal_sdio_set_clk_26m(&s_icu.hal) 84 #define clk_set_sdio_clk_dco() clock_hal_sdio_set_clk_dco(&s_icu.hal) 85 86 #define clk_set_qspi_clk_26m() clock_hal_qspi_set_clk_26m(&s_icu.hal) 87 #define clk_set_qspi_clk_dco() clock_hal_qspi_set_clk_dco(&s_icu.hal) 88 #define clk_set_qspi_clk_120m() clock_hal_qspi_set_clk_120m(&s_icu.hal) 89 #define clk_set_qspi_clk_80m() clock_hal_qspi_set_clk_80m(&s_icu.hal) 90 91 #define clk_set_efuse_clk_26m() clock_hal_efuse_set_clk_26m(&s_icu.hal) 92 #define clk_set_efuse_clk_dco() clock_hal_efuse_set_clk_dco(&s_icu.hal) 93 94 #define clk_set_cec_clk_26m() clock_hal_cec_set_clk_26m(&s_icu.hal) 95 #define clk_set_cec_clk_dco() clock_hal_cec_set_clk_dco(&s_icu.hal) 96 97 #define clk_set_i2s_1_div() clock_hal_set_i2s_1_div(&s_icu.hal) 98 #define clk_set_i2s_2_div() clock_hal_set_i2s_2_div(&s_icu.hal) 99 #define clk_set_i2s_4_div() clock_hal_set_i2s_4_div(&s_icu.hal) 100 #define clk_set_i2s_8_div() clock_hal_set_i2s_8_div(&s_icu.hal) 101 #define clk_set_i2s_16_div() clock_hal_set_i2s_16_div(&s_icu.hal) 102 #define clk_set_i2s_32_div() clock_hal_set_i2s_32_div(&s_icu.hal) 103 104 #define clk_get_uart_clk(id) clock_hal_get_uart_clk(&s_icu.hal, id) 105 106 #if CONFIG_SOC_BK7236A 107 #define clock_jpeg_set_96m clock_hal_jpeg_set_96m(&s_icu.hal) 108 #define clock_jpeg_set_120m clock_hal_jpeg_set_120m(&s_icu.hal) 109 #define clock_jpeg_set_160m clock_hal_jpeg_set_160m(&s_icu.hal) 110 #define clock_jpeg_set_240m clock_hal_jpeg_set_240m(&s_icu.hal) 111 #endif 112 113 #endif 114 115